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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Nate DeSimone > -----Original Message----- > From: Luo, Heng > Sent: Sunday, January 31, 2021 5:36 PM > To: devel@edk2.groups.io > Cc: Chaganty, Rangasai V ; Desimone, > Nathaniel L > Subject: [PATCH 03/40] TigerlakeSiliconPkg/Include: Add Pins, Register an= d > other include headers >=20 > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3171 >=20 > Adds the following header files: > * Include/Pins > * Include/Register > * Include/*.h >=20 > Cc: Sai Chaganty > Cc: Nate DeSimone > Signed-off-by: Heng Luo > --- > Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock.h | 53 > +++++++++++++++++++++++++++++++++++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Include/CpuPcieHob.h | 38 > ++++++++++++++++++++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Include/DmaRemappingTable.h | 75 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Include/DxeHdaNhlt.h | 138 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Include/Hda.h | 57 > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Include/MePolicyCommon.h | 24 > ++++++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Include/PcieRegs.h | 155 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Include/Pins/GpioPinsVer2Lp.h | 110 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Include/Register/FlashRegs.h | 72 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Include/Register/GpioRegs.h | 121 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++ > Silicon/Intel/TigerlakeSiliconPkg/Include/Register/GpioRegsVer2.h | 226 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Include/Register/PchDmi14Regs.h | 16 > ++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Include/Register/PchDmiRegs.h | 36 > ++++++++++++++++++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Include/Register/PchPcieRpRegs.h | 93 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Include/Register/PmcRegs.h | 258 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Include/Register/RtcRegs.h | 45 > +++++++++++++++++++++++++++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Include/Register/SataRegs.h | 56 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Include/Register/SerialIoRegs.h | 47 > +++++++++++++++++++++++++++++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Include/Register/UsbRegs.h | 51 > +++++++++++++++++++++++++++++++++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Include/SerialIoDevices.h | 213 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Include/SiConfigHob.h | 17 > +++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Include/SiPolicyStruct.h | 64 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++ > 22 files changed, 1965 insertions(+) >=20 > diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock.h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock.h > new file mode 100644 > index 0000000000..ad34e4ea42 > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock.h > @@ -0,0 +1,53 @@ > +/** @file >=20 > + Header file for Config Block Lib implementation >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +#ifndef _CONFIG_BLOCK_H_ >=20 > +#define _CONFIG_BLOCK_H_ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +#pragma pack (push,1) >=20 > + >=20 > +/// >=20 > +/// Config Block Header >=20 > +/// >=20 > +typedef struct _CONFIG_BLOCK_HEADER { >=20 > + EFI_HOB_GUID_TYPE GuidHob; ///< Offset 0-23 GUID > extension HOB header >=20 > + UINT8 Revision; ///< Offset 24 Revi= sion of this config > block >=20 > + UINT8 Attributes; ///< Offset 25 The = main revision for > config block >=20 > + UINT8 Reserved[2]; ///< Offset 26-27 Rese= rved for future > use >=20 > +} CONFIG_BLOCK_HEADER; >=20 > + >=20 > +/// >=20 > +/// Config Block >=20 > +/// >=20 > +typedef struct _CONFIG_BLOCK { >=20 > + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Head= er of > config block >=20 > + // >=20 > + // Config Block Data >=20 > + // >=20 > +} CONFIG_BLOCK; >=20 > + >=20 > +/// >=20 > +/// Config Block Table Header >=20 > +/// >=20 > +typedef struct _CONFIG_BLOCK_TABLE_STRUCT { >=20 > + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 GUID > number for main entry of config block >=20 > + UINT8 Rsvd0[2]; ///< Offset 28-29 Rese= rved for future use >=20 > + UINT16 NumberOfBlocks; ///< Offset 30-31 Numb= er of config > blocks (N) >=20 > + UINT32 AvailableSize; ///< Offset 32-35 Curr= ent config block > table size >=20 > +/// >=20 > +/// Individual Config Block Structures are added here in memory as part = of > AddConfigBlock() >=20 > +/// >=20 > +} CONFIG_BLOCK_TABLE_HEADER; >=20 > +#pragma pack (pop) >=20 > + >=20 > +#endif // _CONFIG_BLOCK_H_ >=20 > + >=20 > diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/CpuPcieHob.h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/CpuPcieHob.h > new file mode 100644 > index 0000000000..23a408e8dc > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/CpuPcieHob.h > @@ -0,0 +1,38 @@ > +/** @file >=20 > + The GUID definition for CpuPcieHob >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _CPU_PCIE_HOB_H_ >=20 > +#define _CPU_PCIE_HOB_H_ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +extern EFI_GUID gCpuPcieHobGuid; >=20 > +#pragma pack (push,1) >=20 > + >=20 > +/** >=20 > + The CPU_PCIE_HOB block describes the expected configuration of the > CpuPcie controllers >=20 > +**/ >=20 > +typedef struct { >=20 > + /// >=20 > + /// These members describe the configuration of each CPU PCIe root por= t. >=20 > + /// >=20 > + EFI_HOB_GUID_TYPE EfiHobGuidType; = ///< Offset 0 - 23: > GUID Hob type structure for gCpuPcieHobGuid >=20 > + CPU_PCIE_ROOT_PORT_CONFIG > RootPort[CPU_PCIE_MAX_ROOT_PORTS]; >=20 > + UINT8 L1SubStates[CPU_PCIE_MAX_ROOT_PORTS]; ///= < The > L1 Substates configuration of the root port >=20 > + >=20 > + UINT32 DekelFwVersionMinor; = ///< Dekel Firmware > Minor Version >=20 > + UINT32 DekelFwVersionMajor; = ///< Dekel Firmware > Major Version >=20 > + BOOLEAN InitPcieAspmAfterOprom; = ///< 1=3Dinitialize > PCIe ASPM after Oprom; 0=3Dbefore (This will be set basing on policy) >=20 > + UINT32 RpEnabledMask; = ///< Rootport enabled > mask based on DEVEN register >=20 > + UINT32 RpEnMaskFromDevEn; = ///< Rootport > enabled mask based on Device Id >=20 > + UINT8 DisableClkReqMsg[CPU_PCIE_MAX_ROOT_PORTS]; > ///< 1=3DClkReqMsg disabled, 0=3DClkReqMsg enabled >=20 > + UINT8 SlotSelection; = ///< 1=3DM2 slot, 0=3DCEMx4 slot >=20 > + BOOLEAN ComplianceTest; = ///< Compliance Test > based on policy >=20 > +} CPU_PCIE_HOB; >=20 > +#pragma pack (pop) >=20 > +#endif >=20 > diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/DmaRemappingTable.= h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/DmaRemappingTable.h > new file mode 100644 > index 0000000000..5b058c7a45 > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/DmaRemappingTable.h > @@ -0,0 +1,75 @@ > +/** @file >=20 > + This code defines ACPI DMA Remapping table related definitions. >=20 > + See the System Agent BIOS specification for definition of the table. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _DMA_REMAPPING_TABLE_H_ >=20 > +#define _DMA_REMAPPING_TABLE_H_ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +#pragma pack(1) >=20 > +/// >=20 > +/// DMAR table signature >=20 > +/// >=20 > +#define EFI_ACPI_VTD_DMAR_TABLE_SIGNATURE 0x52414D44 ///< > "DMAR" >=20 > +#define EFI_ACPI_DMAR_TABLE_REVISION 2 >=20 > +#define EFI_ACPI_DRHD_ENGINE_HEADER_LENGTH 0x10 >=20 > +#define EFI_ACPI_RMRR_HEADER_LENGTH 0x18 >=20 > +#define MAX_PCI_DEPTH 5 >=20 > + >=20 > +typedef struct { >=20 > + EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER > DeviceScopeStructureHeader; >=20 > + EFI_ACPI_DMAR_PCI_PATH PciPath; // device, fu= nction >=20 > +} EFI_ACPI_DEV_SCOPE_STRUCTURE; >=20 > + >=20 > +typedef struct { >=20 > + EFI_ACPI_DMAR_DRHD_HEADER DrhdHeader; >=20 > + EFI_ACPI_DEV_SCOPE_STRUCTURE DeviceScope[1]; >=20 > +} EFI_ACPI_DRHD_ENGINE1_STRUCT; >=20 > + >=20 > +typedef struct { >=20 > + EFI_ACPI_DMAR_DRHD_HEADER DrhdHeader; >=20 > + // >=20 > + // @todo use PCD >=20 > + // >=20 > + EFI_ACPI_DEV_SCOPE_STRUCTURE DeviceScope[2]; >=20 > +} EFI_ACPI_DRHD_ENGINE3_STRUCT; >=20 > + >=20 > +typedef struct { >=20 > + EFI_ACPI_DMAR_RMRR_HEADER RmrrHeader; >=20 > + EFI_ACPI_DEV_SCOPE_STRUCTURE DeviceScope[2]; >=20 > +} EFI_ACPI_RMRR_USB_STRUC; >=20 > + >=20 > +typedef struct { >=20 > + EFI_ACPI_DMAR_RMRR_HEADER RmrrHeader; >=20 > + EFI_ACPI_DEV_SCOPE_STRUCTURE DeviceScope[1]; // IGD >=20 > +} EFI_ACPI_RMRR_IGD_STRUC; >=20 > + >=20 > +typedef struct { >=20 > + EFI_ACPI_DMAR_RMRR_HEADER RmrrHeader; >=20 > + EFI_ACPI_DEV_SCOPE_STRUCTURE DeviceScope[1]; // IGD - DiSM >=20 > +} EFI_ACPI_RMRR_IGD_DISM_STRUC; >=20 > + >=20 > +typedef struct { >=20 > + EFI_ACPI_DMAR_ANDD_HEADER AnddHeader; >=20 > + UINT8 AcpiObjectName[20]; >=20 > +} EFI_ACPI_ANDD_STRUC; >=20 > + >=20 > +typedef struct { >=20 > + EFI_ACPI_DMAR_HEADER DmarHeader; >=20 > + EFI_ACPI_DRHD_ENGINE1_STRUCT DrhdEngine1; >=20 > + EFI_ACPI_DRHD_ENGINE3_STRUCT DrhdEngine3; >=20 > + EFI_ACPI_RMRR_IGD_STRUC RmrrIgd; >=20 > + EFI_ACPI_RMRR_IGD_DISM_STRUC RmrrIgdDism; >=20 > +} EFI_ACPI_DMAR_TABLE; >=20 > + >=20 > +#pragma pack() >=20 > + >=20 > +#endif >=20 > diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/DxeHdaNhlt.h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/DxeHdaNhlt.h > new file mode 100644 > index 0000000000..edb3855b68 > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/DxeHdaNhlt.h > @@ -0,0 +1,138 @@ > +/** @file >=20 > + Header file for DxePchHdaNhltLib - NHLT structure definitions. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +#ifndef _DXE_HDA_NHLT_H_ >=20 > +#define _DXE_HDA_NHLT_H_ >=20 > + >=20 > +#include >=20 > + >=20 > +// >=20 > +// ACPI support protocol instance signature definition. >=20 > +// >=20 > +#define NHLT_ACPI_TABLE_SIGNATURE SIGNATURE_32 ('N', 'H', 'L', 'T') >=20 > + >=20 > +// MSFT defined structures >=20 > +#define SPEAKER_FRONT_LEFT 0x1 >=20 > +#define SPEAKER_FRONT_RIGHT 0x2 >=20 > +#define SPEAKER_FRONT_CENTER 0x4 >=20 > +#define SPEAKER_BACK_LEFT 0x10 >=20 > +#define SPEAKER_BACK_RIGHT 0x20 >=20 > + >=20 > +#define KSAUDIO_SPEAKER_MONO (SPEAKER_FRONT_CENTER) >=20 > +#define KSAUDIO_SPEAKER_STEREO (SPEAKER_FRONT_LEFT | > SPEAKER_FRONT_RIGHT) >=20 > +#define KSAUDIO_SPEAKER_QUAD (SPEAKER_FRONT_LEFT | > SPEAKER_FRONT_RIGHT | SPEAKER_BACK_LEFT | SPEAKER_BACK_RIGHT) >=20 > + >=20 > +#define WAVE_FORMAT_EXTENSIBLE 0xFFFE /* Microsoft */ >=20 > +#define KSDATAFORMAT_SUBTYPE_PCM \ >=20 > + {0x00000001, 0x0000, 0x0010, {0x80, 0x00, 0x00, 0xaa, 0x00, 0x38= , 0x9b, > 0x71}} >=20 > + >=20 > +#pragma pack (push, 1) >=20 > + >=20 > +typedef struct { >=20 > + UINT16 wFormatTag; >=20 > + UINT16 nChannels; >=20 > + UINT32 nSamplesPerSec; >=20 > + UINT32 nAvgBytesPerSec; >=20 > + UINT16 nBlockAlign; >=20 > + UINT16 wBitsPerSample; >=20 > + UINT16 cbSize; >=20 > +} WAVEFORMATEX; >=20 > + >=20 > +typedef struct { >=20 > + WAVEFORMATEX Format; >=20 > + union { >=20 > + UINT16 wValidBitsPerSample; >=20 > + UINT16 wSamplesPerBlock; >=20 > + UINT16 wReserved; >=20 > + } Samples; >=20 > + UINT32 dwChannelMask; >=20 > + GUID SubFormat; >=20 > +} WAVEFORMATEXTENSIBLE; >=20 > + >=20 > +// >=20 > +// List of supported link type. >=20 > +// >=20 > +enum NHLT_LINK_TYPE >=20 > +{ >=20 > + HdaNhltLinkHd =3D 0, >=20 > + HdaNhltLinkDsp =3D 1, >=20 > + HdaNhltLinkDmic =3D 2, >=20 > + HdaNhltLinkSsp =3D 3, >=20 > + HdaNhltLinkInvalid >=20 > +}; >=20 > + >=20 > +// >=20 > +// List of supported device type. >=20 > +// >=20 > +enum NHLT_SSP_DEVICE_TYPE >=20 > +{ >=20 > + HdaNhltSspDeviceBt =3D 0, >=20 > + HdaNhltSspDeviceI2s =3D 4, >=20 > + HdaNhltSspDeviceInvalid >=20 > +}; >=20 > + >=20 > +enum NHLT_PDM_DEVICE_TYPE >=20 > +{ >=20 > + HdaNhltPdmDeviceDmic =3D 0, >=20 > + HdaNhltPdmDeviceInvalid >=20 > +}; >=20 > + >=20 > +typedef struct { >=20 > + UINT32 CapabilitiesSize; >=20 > + UINT8 Capabilities[1]; >=20 > +} SPECIFIC_CONFIG; >=20 > + >=20 > +typedef struct { >=20 > + WAVEFORMATEXTENSIBLE Format; >=20 > + SPECIFIC_CONFIG FormatConfiguration; >=20 > +} FORMAT_CONFIG; >=20 > + >=20 > +typedef struct { >=20 > + UINT8 FormatsCount; >=20 > + FORMAT_CONFIG FormatsConfiguration[1]; >=20 > +} FORMATS_CONFIG; >=20 > + >=20 > +typedef struct { >=20 > + UINT8 DeviceId[16]; >=20 > + UINT8 DeviceInstanceId; >=20 > + UINT8 DevicePortId; >=20 > +} DEVICE_INFO; >=20 > + >=20 > +typedef struct { >=20 > + UINT8 DeviceInfoCount; >=20 > + DEVICE_INFO DeviceInformation[1]; >=20 > +} DEVICES_INFO; >=20 > + >=20 > +typedef struct { >=20 > + UINT32 EndpointDescriptorLength; >=20 > + UINT8 LinkType; >=20 > + UINT8 InstanceId; >=20 > + UINT16 HwVendorId; >=20 > + UINT16 HwDeviceId; >=20 > + UINT16 HwRevisionId; >=20 > + UINT32 HwSubsystemId; >=20 > + UINT8 DeviceType; >=20 > + UINT8 Direction; >=20 > + UINT8 VirtualBusId; >=20 > + SPECIFIC_CONFIG EndpointConfig; >=20 > + FORMATS_CONFIG FormatsConfig; >=20 > + DEVICES_INFO DevicesInformation; >=20 > +} ENDPOINT_DESCRIPTOR; >=20 > + >=20 > +// >=20 > +// High Level Table structure >=20 > +// >=20 > +typedef struct { >=20 > + EFI_ACPI_DESCRIPTION_HEADER Header; //{'N', 'H', 'L', 'T'} >=20 > + UINT8 EndpointCount; // Actual number of endpo= ints >=20 > + ENDPOINT_DESCRIPTOR EndpointDescriptors[1]; >=20 > + SPECIFIC_CONFIG OedConfiguration; >=20 > +} NHLT_ACPI_TABLE; >=20 > + >=20 > +#pragma pack (pop) >=20 > + >=20 > +#endif // _DXE_PCH_HDA_NHLT_H_ >=20 > diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Hda.h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/Hda.h > new file mode 100644 > index 0000000000..ab3f2c9cd0 > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Hda.h > @@ -0,0 +1,57 @@ > +/** @file >=20 > + Header file for HD Audio configuration. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +#ifndef _HDA_H_ >=20 > +#define _HDA_H_ >=20 > + >=20 > +typedef enum { >=20 > + HdaVc0 =3D 0, >=20 > + HdaVc1 =3D 1 >=20 > +} HDAUDIO_VC_TYPE; >=20 > + >=20 > +typedef enum { >=20 > + HdaDmicDisabled =3D 0, >=20 > + HdaDmic2chArray =3D 1, >=20 > + HdaDmic4chArray =3D 2, >=20 > + HdaDmic1chArray =3D 3 >=20 > +} HDAUDIO_DMIC_TYPE; >=20 > + >=20 > +typedef enum { >=20 > + HdaLinkFreq6MHz =3D 0, >=20 > + HdaLinkFreq12MHz =3D 1, >=20 > + HdaLinkFreq24MHz =3D 2, >=20 > + HdaLinkFreq48MHz =3D 3, >=20 > + HdaLinkFreq96MHz =3D 4, >=20 > + HdaLinkFreqInvalid >=20 > +} HDAUDIO_LINK_FREQUENCY; >=20 > + >=20 > +typedef enum { >=20 > + HdaIDispMode2T =3D 0, >=20 > + HdaIDispMode1T =3D 1, >=20 > + HdaIDispMode4T =3D 2, >=20 > + HdaIDispMode8T =3D 3, >=20 > + HdaIDispMode16T =3D 4, >=20 > + HdaIDispTModeInvalid >=20 > +} HDAUDIO_IDISP_TMODE; >=20 > + >=20 > +typedef enum { >=20 > + HdaLink =3D 0, >=20 > + HdaIDispLink =3D 1, >=20 > + HdaDmic =3D 2, >=20 > + HdaSsp =3D 3, >=20 > + HdaSndw =3D 4, >=20 > + HdaLinkUnsupported >=20 > +} HDAUDIO_LINK_TYPE; >=20 > + >=20 > +typedef enum { >=20 > + HdaDmicClockSelectBoth =3D 0, >=20 > + HdaDmicClockSelectClkA =3D 1, >=20 > + HdaDmicClockSelectClkB =3D 2, >=20 > + HdaDmicClockSelectInvalid >=20 > +} HDAUDIO_DMIC_CLOCK_SELECT; >=20 > + >=20 > +#endif >=20 > diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/MePolicyCommon.h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/MePolicyCommon.h > new file mode 100644 > index 0000000000..023ba12daa > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/MePolicyCommon.h > @@ -0,0 +1,24 @@ > +/** @file >=20 > + Definition for ME common policy >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _ME_POLICY_COMMON_H_ >=20 > +#define _ME_POLICY_COMMON_H_ >=20 > + >=20 > +#include >=20 > + >=20 > +#include >=20 > + >=20 > +#ifndef PLATFORM_POR >=20 > +#define PLATFORM_POR 0 >=20 > +#endif >=20 > +#ifndef FORCE_ENABLE >=20 > +#define FORCE_ENABLE 1 >=20 > +#endif >=20 > +#ifndef FORCE_DISABLE >=20 > +#define FORCE_DISABLE 2 >=20 > +#endif >=20 > + >=20 > +#endif // _ME_POLICY_COMMON_H_ >=20 > diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/PcieRegs.h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/PcieRegs.h > new file mode 100644 > index 0000000000..d98019d1b4 > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/PcieRegs.h > @@ -0,0 +1,155 @@ > +/** @file >=20 > + Register names for PCIE standard register >=20 > + >=20 > + Conventions: >=20 > + >=20 > + - Prefixes: >=20 > + Definitions beginning with "R_" are registers >=20 > + Definitions beginning with "B_" are bits within registers >=20 > + Definitions beginning with "V_" are meaningful values within the bit= s >=20 > + Definitions beginning with "S_" are register sizes >=20 > + Definitions beginning with "N_" are the bit position >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _PCIE_REGS_H_ >=20 > +#define _PCIE_REGS_H_ >=20 > + >=20 > +#include >=20 > + >=20 > +// >=20 > +// PCI type 0 Header >=20 > +// >=20 > +#define R_PCI_BCC_OFFSET 0x0B >=20 > + >=20 > +// >=20 > +// PCI type 1 Header >=20 > +// >=20 > +#define R_PCI_BRIDGE_BNUM 0x18 ///< Bus Number R= egister >=20 > +#define B_PCI_BRIDGE_BNUM_SBBN 0x00FF0000 ///< > Subordinate Bus Number >=20 > +#define B_PCI_BRIDGE_BNUM_SCBN 0x0000FF00 ///< Second= ary > Bus Number >=20 > + >=20 > +// >=20 > +// PCI Express Capability List Register (CAPID:10h) >=20 > +// >=20 > +#define R_PCIE_XCAP_OFFSET 0x02 ///< PCI Express = Capabilities > Register (Offset 02h) >=20 > +#define B_PCIE_XCAP_DT (BIT7 | BIT6 | BIT5 | = BIT4) ///< > Device/Port Type >=20 > +#define N_PCIE_XCAP_DT 4 >=20 > + >=20 > +#define R_PCIE_DCAP_OFFSET 0x04 ///< Device Capab= ilities > Register (Offset 04h) >=20 > +#define B_PCIE_DCAP_RBER BIT15 ///< Role-Based = Error > Reporting >=20 > +#define B_PCIE_DCAP_E1AL (BIT11 | BIT10 | BIT9)= ///< > Endpoint L1 Acceptable Latency >=20 > +#define N_PCIE_DCAP_E1AL 9 >=20 > +#define B_PCIE_DCAP_E0AL (BIT8 | BIT7 | BIT6) /= //< Endpoint > L0s Acceptable Latency >=20 > +#define N_PCIE_DCAP_E0AL 6 >=20 > +#define B_PCIE_DCAP_MPS (BIT2 | BIT1 | BIT0) /= //< > Max_Payload_Size Supported >=20 > + >=20 > +#define R_PCIE_DCTL_OFFSET 0x08 ///< Device Contr= ol Register > (Offset 08h) >=20 > +#define B_PCIE_DCTL_MPS (BIT7 | BIT6 | BIT5) /= //< > Max_Payload_Size >=20 > +#define N_PCIE_DCTL_MPS 5 >=20 > + >=20 > +#define R_PCIE_LCAP_OFFSET 0x0C ///< Link Capabil= ities > Register (Offset 0Ch) >=20 > +#define B_PCIE_LCAP_CPM BIT18 ///< Clock Power > Management >=20 > +#define B_PCIE_LCAP_EL1 (BIT17 | BIT16 | BIT15= ) ///< L1 Exit > Latency >=20 > +#define N_PCIE_LCAP_EL1 15 >=20 > +#define B_PCIE_LCAP_EL0 (BIT14 | BIT13 | BIT12= ) ///< L0s Exit > Latency >=20 > +#define N_PCIE_LCAP_EL0 12 >=20 > +#define B_PCIE_LCAP_APMS_L0S BIT10 >=20 > +#define B_PCIE_LCAP_APMS_L1 BIT11 >=20 > +#define B_PCIE_LCAP_MLS (BIT3 | BIT2 | BIT1 | = BIT0) ///< Max > Link Speed >=20 > +#define V_PCIE_LCAP_MLS_GEN3 3 >=20 > +#define V_PCIE_LCAP_MLS_GEN4 4 >=20 > + >=20 > +#define R_PCIE_LCTL_OFFSET 0x10 ///< Link Control= Register > (Offset 10h) >=20 > +#define B_PCIE_LCTL_ECPM BIT8 ///< Enable Clock= Power > Management >=20 > +#define B_PCIE_LCTL_CCC BIT6 ///< Common Clock > Configuration >=20 > +#define B_PCIE_LCTL_RL BIT5 ///< Retrain Link >=20 > +#define B_PCIE_LCTL_ASPM (BIT1 | BIT0) ///< Act= ive State > Power Management (ASPM) Control >=20 > +#define V_PCIE_LCTL_ASPM_L0S 1 >=20 > +#define V_PCIE_LCTL_ASPM_L1 2 >=20 > +#define V_PCIE_LCTL_ASPM_L0S_L1 3 >=20 > + >=20 > +#define R_PCIE_LSTS_OFFSET 0x12 ///< Link Status = Register > (Offset 12h) >=20 > +#define B_PCIE_LSTS_LA BIT13 ///< Data Link L= ayer Link Active >=20 > +#define B_PCIE_LSTS_SCC BIT12 ///< Slot Clock = Configuration >=20 > +#define B_PCIE_LSTS_LT BIT11 ///< Link Traini= ng >=20 > +#define B_PCIE_LSTS_NLW 0x03F0 ///< Negotiated= Link Width >=20 > +#define N_PCIE_LSTS_NLW 4 >=20 > +#define B_PCIE_LSTS_CLS 0x000F ///< Current Li= nk Speed >=20 > + >=20 > +#define R_PCIE_SLCAP_OFFSET 0x14 ///< Slot Capabil= ities > Register (Offset 14h) >=20 > +#define B_PCIE_SLCAP_HPC BIT6 ///< Hot-Pl= ug Capable >=20 > + >=20 > +#define R_PCIE_SLSTS_OFFSET 0x1A ///< Slot Status = Register > (Offset 1Ah) >=20 > +#define B_PCIE_SLSTS_PDS BIT6 ///< Presence Det= ect State >=20 > + >=20 > +#define R_PCIE_DCAP2_OFFSET 0x24 ///< Device Capab= ilities 2 > Register (Offset 24h) >=20 > +#define B_PCIE_DCAP2_LTRMS BIT11 ///< LTR Mechani= sm > Supported >=20 > + >=20 > +#define R_PCIE_DCTL2_OFFSET 0x28 ///< Device Contr= ol 2 > Register (Offset 28h) >=20 > +#define B_PCIE_DCTL2_LTREN BIT10 ///< LTR Mechani= sm Enable >=20 > + >=20 > +#define B_PCIE_LCTL2_TLS (BIT3 | BIT2 | BIT1 | = BIT0) ///< > Target Link Speed >=20 > + >=20 > +// >=20 > +// Latency Tolerance Reporting Extended Capability Registers (CAPID:0018= h) >=20 > +// >=20 > +#define R_PCIE_LTRECH_CID 0x0018 >=20 > + >=20 > +#define R_PCIE_LTRECH_MSLR_OFFSET 0x04 >=20 > +#define N_PCIE_LTRECH_MSLR_VALUE 0 >=20 > +#define N_PCIE_LTRECH_MSLR_SCALE 10 >=20 > + >=20 > +#define R_PCIE_LTRECH_MNSLR_OFFSET 0x06 >=20 > +#define N_PCIE_LTRECH_MNSLR_VALUE 0 >=20 > +#define N_PCIE_LTRECH_MNSLR_SCALE 10 >=20 > + >=20 > +// >=20 > +// Secondary PCI Express Extended Capability Header (CAPID:0019h) >=20 > +// >=20 > +#define R_PCIE_EX_LCTL3_OFFSET 0x04 ///< Link Control= 3 > Register >=20 > +#define B_PCIE_EX_LCTL3_PE BIT0 ///< Perform Equa= lization >=20 > + >=20 > +// >=20 > +// L1 Sub-States Extended Capability Register (CAPID:001Eh) >=20 > +// >=20 > +#define V_PCIE_EX_L1S_CID 0x001E ///< Capability = ID >=20 > +#define R_PCIE_EX_L1SCAP_OFFSET 0x04 ///< L1 Sub-States > Capabilities >=20 > +#define B_PCIE_EX_L1SCAP_PTV 0x00F80000 //< Port Tpo= wer_on > value >=20 > +#define N_PCIE_EX_L1SCAP_PTV 19 >=20 > +#define B_PCIE_EX_L1SCAP_PTPOS 0x00030000 //< Port > Tpower_on scale >=20 > +#define N_PCIE_EX_L1SCAP_PTPOS 16 >=20 > +#define B_PCIE_EX_L1SCAP_CMRT 0x0000FF00 //< Common > Mode Restore time >=20 > +#define N_PCIE_EX_L1SCAP_CMRT 8 >=20 > +#define B_PCIE_EX_L1SCAP_L1PSS BIT4 ///< L1 PM substat= es > supported >=20 > +#define B_PCIE_EX_L1SCAP_AL1SS BIT3 ///< ASPM L1.1 sup= ported >=20 > +#define B_PCIE_EX_L1SCAP_AL12S BIT2 ///< ASPM L1.2 sup= ported >=20 > +#define B_PCIE_EX_L1SCAP_PPL11S BIT1 ///< PCI-PM L1.1 > supported >=20 > +#define B_PCIE_EX_L1SCAP_PPL12S BIT0 ///< PCI-PM L1.2 > supported >=20 > +#define R_PCIE_EX_L1SCTL1_OFFSET 0x08 ///< L1 Sub-States > Control 1 >=20 > +#define B_PCIE_EX_L1SCTL1_L1SSEIE BIT4 >=20 > +#define N_PCIE_EX_L1SCTL1_L12LTRTLSV 29 >=20 > +#define N_PCIE_EX_L1SCTL1_L12LTRTLV 16 >=20 > +#define R_PCIE_EX_L1SCTL2_OFFSET 0x0C ///< L1 Sub-States > Control 2 >=20 > +#define N_PCIE_EX_L1SCTL2_POWT 3 >=20 > + >=20 > +// >=20 > +// PTM Extended Capability Register (CAPID:001Fh) >=20 > +// >=20 > +#define V_PCIE_EX_PTM_CID 0x001F ///< Capability= ID >=20 > +#define R_PCIE_EX_PTMCAP_OFFSET 0x04 ///< PTM Capabili= ties >=20 > +#define R_PCIE_EX_PTMCTL_OFFSET 0x08 ///< PTM Control > Register >=20 > + >=20 > +// >=20 > +// Base Address Offset >=20 > +// >=20 > +#define B_PCI_BAR_MEMORY_TYPE_MASK (BIT1 | BIT2) >=20 > +#define B_PCI_BAR_MEMORY_TYPE_64 BIT2 >=20 > + >=20 > +// >=20 > +// PCI Express Extended Capability Header >=20 > +// >=20 > +#define R_PCIE_CFG_EXCAP_OFFSET 0x100 >=20 > + >=20 > +#endif >=20 > diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Pins/GpioPinsVer2L= p.h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/Pins/GpioPinsVer2Lp.h > new file mode 100644 > index 0000000000..ef94790985 > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Pins/GpioPinsVer2Lp.h > @@ -0,0 +1,110 @@ > +/** @file >=20 > + GPIO pins for TGL-PCH-LP, >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _GPIO_PINS_VER2_LP_H_ >=20 > +#define _GPIO_PINS_VER2_LP_H_ >=20 > +/// >=20 > +/// This header file should be used together with >=20 > +/// PCH GPIO lib in C and ASL. All defines used >=20 > +/// must match both ASL/C syntax >=20 > +/// >=20 > + >=20 > +/// >=20 > +/// Unique ID used in GpioPad defines >=20 > +/// >=20 > +#define GPIO_VER2_LP_CHIPSET_ID 0x9 >=20 > + >=20 > +/// >=20 > +/// TGL LP GPIO Groups >=20 > +/// Use below for functions from PCH GPIO Lib which >=20 > +/// require GpioGroup as argument >=20 > +/// >=20 > +#define GPIO_VER2_LP_GROUP_GPP_B 0x0900 >=20 > +#define GPIO_VER2_LP_GROUP_GPP_A 0x0902 >=20 > +#define GPIO_VER2_LP_GROUP_GPP_R 0x0903 >=20 > +#define GPIO_VER2_LP_GROUP_GPD 0x0905 >=20 > +#define GPIO_VER2_LP_GROUP_GPP_S 0x0906 >=20 > +#define GPIO_VER2_LP_GROUP_GPP_H 0x0907 >=20 > +#define GPIO_VER2_LP_GROUP_GPP_D 0x0908 >=20 > +#define GPIO_VER2_LP_GROUP_GPP_C 0x090B >=20 > +#define GPIO_VER2_LP_GROUP_GPP_F 0x090C >=20 > +#define GPIO_VER2_LP_GROUP_GPP_E 0x090E >=20 > + >=20 > + >=20 > +/// >=20 > +/// TGL LP GPIO pins >=20 > +/// Use below for functions from PCH GPIO Lib which >=20 > +/// require GpioPad as argument. Encoding used here >=20 > +/// has all information required by library functions >=20 > +/// >=20 > +#define GPIO_VER2_LP_GPP_B2 0x09000002 >=20 > +#define GPIO_VER2_LP_GPP_B4 0x09000004 >=20 > +#define GPIO_VER2_LP_GPP_B14 0x0900000E >=20 > +#define GPIO_VER2_LP_GPP_B15 0x0900000F >=20 > +#define GPIO_VER2_LP_GPP_B16 0x09000010 >=20 > +#define GPIO_VER2_LP_GPP_B18 0x09000012 >=20 > +#define GPIO_VER2_LP_GPP_B23 0x09000017 >=20 > +#define GPIO_VER2_LP_GSPI0_CLK_LOOPBK 0x09000018 >=20 > + >=20 > +#define GPIO_VER2_LP_GPP_A10 0x0902000A >=20 > +#define GPIO_VER2_LP_GPP_A11 0x0902000B >=20 > +#define GPIO_VER2_LP_GPP_A13 0x0902000D >=20 > +#define GPIO_VER2_LP_GPP_A14 0x0902000E >=20 > +#define GPIO_VER2_LP_GPP_A23 0x09020017 >=20 > +#define GPIO_VER2_LP_ESPI_CLK_LOOPBK 0x09020018 >=20 > + >=20 > +#define GPIO_VER2_LP_GPP_R5 0x09030005 >=20 > +#define GPIO_VER2_LP_GPP_R6 0x09030006 >=20 > + >=20 > +#define GPIO_VER2_LP_GPD7 0x09050007 >=20 > + >=20 > +#define GPIO_VER2_LP_INPUT3VSEL 0x0905000C >=20 > + >=20 > +#define GPIO_VER2_LP_GPP_H0 0x09070000 >=20 > +#define GPIO_VER2_LP_GPP_H1 0x09070001 >=20 > +#define GPIO_VER2_LP_GPP_H12 0x0907000C >=20 > +#define GPIO_VER2_LP_GPP_H13 0x0907000D >=20 > +#define GPIO_VER2_LP_GPP_H15 0x0907000F >=20 > +#define GPIO_VER2_LP_GPP_H19 0x09070013 >=20 > + >=20 > +#define GPIO_VER2_LP_GPP_D16 0x09080010 >=20 > +#define GPIO_VER2_LP_GSPI2_CLK_LOOPBK 0x09080014 >=20 > + >=20 > +#define GPIO_VER2_LP_GPP_C2 0x090B0002 >=20 > +#define GPIO_VER2_LP_GPP_C5 0x090B0005 >=20 > +#define GPIO_VER2_LP_GPP_C8 0x090B0008 >=20 > +#define GPIO_VER2_LP_GPP_C12 0x090B000C >=20 > +#define GPIO_VER2_LP_GPP_C13 0x090B000D >=20 > +#define GPIO_VER2_LP_GPP_C14 0x090B000E >=20 > +#define GPIO_VER2_LP_GPP_C15 0x090B000F >=20 > +#define GPIO_VER2_LP_GPP_C22 0x090B0016 >=20 > +#define GPIO_VER2_LP_GPP_C23 0x090B0017 >=20 > + >=20 > +#define GPIO_VER2_LP_GPP_F4 0x090C0004 >=20 > +#define GPIO_VER2_LP_GPP_F5 0x090C0005 >=20 > +#define GPIO_VER2_LP_GPP_F9 0x090C0009 >=20 > +#define GPIO_VER2_LP_GPP_F10 0x090C000A >=20 > +#define GPIO_VER2_LP_GPP_F20 0x090C0014 >=20 > +#define GPIO_VER2_LP_GPP_F21 0x090C0015 >=20 > +#define GPIO_VER2_LP_GPPF_CLK_LOOPBK 0x090C0018 >=20 > + >=20 > +#define GPIO_VER2_LP_GPP_E3 0x090E0003 >=20 > +#define GPIO_VER2_LP_GPP_E7 0x090E0007 >=20 > +#define GPIO_VER2_LP_GPP_E8 0x090E0008 >=20 > +#define GPIO_VER2_LP_GPP_E22 0x090E0016 >=20 > +#define GPIO_VER2_LP_GPP_E23 0x090E0017 >=20 > +#define GPIO_VER2_LP_GPPE_CLK_LOOPBK 0x090E0018 >=20 > + >=20 > +// >=20 > +// GPIO Pin Muxing >=20 > +// Determines a selection of physical pad for a given signal. >=20 > +// Please refer to GPIO_NATIVE_PAD type. >=20 > +// If certain signal is not listed below it means that it can be enabled >=20 > +// only on a single pad and muxing setting is not needed. >=20 > +// >=20 > +#define GPIO_VER2_LP_MUXING_SERIALIO_I2C4_SDA_GPP_H8 > 0x1947CC08 >=20 > +#define GPIO_VER2_LP_MUXING_SERIALIO_I2C4_SCL_GPP_H9 > 0x1947AC09 >=20 > +#endif // _GPIO_PINS_VER2_LP_H_ >=20 > diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/FlashRegs= .h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/FlashRegs.h > new file mode 100644 > index 0000000000..215fd0407e > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/FlashRegs.h > @@ -0,0 +1,72 @@ > +/** @file >=20 > + Register names for Flash registers >=20 > + >=20 > + Conventions: >=20 > + >=20 > + - Register definition format: >=20 > + > Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterS > pace_RegisterName >=20 > + - Prefix: >=20 > + Definitions beginning with "R_" are registers >=20 > + Definitions beginning with "B_" are bits within registers >=20 > + Definitions beginning with "V_" are meaningful values within the bit= s >=20 > + Definitions beginning with "S_" are register size >=20 > + Definitions beginning with "N_" are the bit position >=20 > + - [GenerationName]: >=20 > + Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc= .). >=20 > + Register name without GenerationName applies to all generations. >=20 > + - [ComponentName]: >=20 > + This field indicates the component name that the register belongs to= (e.g. > PCH, SA etc.) >=20 > + Register name without ComponentName applies to all components. >=20 > + Register that is specific to -LP denoted by "_PCH_LP_" in component > name. >=20 > + - SubsystemName: >=20 > + This field indicates the subsystem name of the component that the > register belongs to >=20 > + (e.g. PCIE, USB, SATA, GPIO, PMC etc.). >=20 > + - RegisterSpace: >=20 > + MEM - MMIO space register of subsystem. >=20 > + IO - IO space register of subsystem. >=20 > + PCR - Private configuration register of subsystem. >=20 > + CFG - PCI configuration space register of subsystem. >=20 > + - RegisterName: >=20 > + Full register name. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _FLASH_REGS_H_ >=20 > +#define _FLASH_REGS_H_ >=20 > + >=20 > +// >=20 > +// Flash Descriptor Base Address Region (FDBAR) from Flash Region 0 >=20 > +// >=20 > +#define R_FLASH_FDBAR_FLASH_MAP0 0x04 >=20 > +#define B_FLASH_FDBAR_NC 0x00000300 = ///< Number Of > Components >=20 > +#define N_FLASH_FDBAR_NC 8 = ///< Number Of > Components >=20 > +#define R_FLASH_FDBAR_FLASH_MAP1 0x08 >=20 > +#define B_FLASH_FDBAR_FPSBA 0x00FF0000 = ///< PCH > Strap Base Address, [23:16] represents [11:4] >=20 > +#define N_FLASH_FDBAR_FPSBA 16 = ///< PCH Strap > base Address bit position >=20 > +#define N_FLASH_FDBAR_FPSBA_REPR 4 = ///< PCH Strap > base Address bit represents position >=20 > +#define B_FLASH_FDBAR_PCHSL 0xFF000000 = ///< PCH > Strap Length, [31:24] represents number of Dwords >=20 > +#define N_FLASH_FDBAR_PCHSL 24 = ///< PCH Strap > Length bit position >=20 > +#define R_FLASH_FDBAR_FLASH_MAP2 0x0C >=20 > +#define B_FLASH_FDBAR_FCPUSBA 0x00000FFC = ///< CPU > Strap Base Address [11:2] >=20 > +#define N_FLASH_FDBAR_FCPUSBA 2 = ///< CPU Strap > Base Address bit position >=20 > +#define B_FLASH_FDBAR_CPUSL 0x00FF0000 = ///< CPU > Strap Length, [23:16] represents number of Dwords >=20 > +#define N_FLASH_FDBAR_CPUSL 16 = ///< CPU Strap > Length bit position >=20 > + >=20 > +// >=20 > +// Flash Component Base Address (FCBA) from Flash Region 0 >=20 > +// >=20 > +#define R_FLASH_FCBA_FLCOMP 0x00 = ///< Flash > Components Register >=20 > +#define B_FLASH_FLCOMP_COMP1_MASK 0xF0 = ///< Flash > Component 1 Size MASK >=20 > +#define N_FLASH_FLCOMP_COMP1 4 = ///< Flash > Component 1 Size bit position >=20 > +#define B_FLASH_FLCOMP_COMP0_MASK 0x0F = ///< Flash > Component 0 Size MASK >=20 > +#define V_FLASH_FLCOMP_COMP_512KB 0x80000 >=20 > +// >=20 > +// Descriptor Upper Map Section from Flash Region 0 >=20 > +// >=20 > +#define R_FLASH_UMAP1 0xEFC = ///< Flash Upper > Map 1 >=20 > +#define B_FLASH_UMAP1_MDTBA 0xFF000000 = ///< MIP > Descriptor Table Base Address >=20 > +#define N_FLASH_UMAP1_MDTBA 24 = ///< MDTBA bits > position >=20 > +#define N_FLASH_UMAP1_MDTBA_REPR 4 = ///< MDTBA > address representation position >=20 > + >=20 > +#endif >=20 > diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/GpioRegs.= h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/GpioRegs.h > new file mode 100644 > index 0000000000..e4bf2018b7 > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/GpioRegs.h > @@ -0,0 +1,121 @@ > +/** @file >=20 > + Register names for PCH GPIO >=20 > + >=20 > +Conventions: >=20 > + >=20 > + - Register definition format: >=20 > + > Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterS > pace_RegisterName >=20 > + - Prefix: >=20 > + Definitions beginning with "R_" are registers >=20 > + Definitions beginning with "B_" are bits within registers >=20 > + Definitions beginning with "V_" are meaningful values within the bit= s >=20 > + Definitions beginning with "S_" are register size >=20 > + Definitions beginning with "N_" are the bit position >=20 > + - [GenerationName]: >=20 > + Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc= .). >=20 > + Register name without GenerationName applies to all generations. >=20 > + - [ComponentName]: >=20 > + This field indicates the component name that the register belongs to= (e.g. > PCH, SA etc.) >=20 > + Register name without ComponentName applies to all components. >=20 > + Register that is specific to -LP denoted by "_PCH_LP_" in component > name. >=20 > + - SubsystemName: >=20 > + This field indicates the subsystem name of the component that the > register belongs to >=20 > + (e.g. PCIE, USB, SATA, GPIO, PMC etc.). >=20 > + - RegisterSpace: >=20 > + MEM - MMIO space register of subsystem. >=20 > + IO - IO space register of subsystem. >=20 > + PCR - Private configuration register of subsystem. >=20 > + CFG - PCI configuration space register of subsystem. >=20 > + - RegisterName: >=20 > + Full register name. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _GPIO_REGS_H_ >=20 > +#define _GPIO_REGS_H_ >=20 > + >=20 > +// >=20 > +// PADCFG register is split into multiple DW registers >=20 > +// S_GPIO_PCR_PADCFG refers to number of bytes used by all those > registers for one pad >=20 > +// >=20 > +#define S_GPIO_PCR_PADCFG 0x10 >=20 > + >=20 > +// >=20 > +// Pad Configuration Register DW0 >=20 > +// >=20 > + >=20 > +//Pad Reset Config >=20 > +#define B_GPIO_PCR_RST_CONF (BIT31 | BIT30) >=20 > +#define N_GPIO_PCR_RST_CONF 30 >=20 > +#define V_GPIO_PCR_RST_CONF_POW_GOOD 0x00 >=20 > +#define V_GPIO_PCR_RST_CONF_DEEP_RST 0x01 >=20 > +#define V_GPIO_PCR_RST_CONF_GPIO_RST 0x02 >=20 > +#define V_GPIO_PCR_RST_CONF_RESUME_RST 0x03 // Only for GPD > Group >=20 > + >=20 > +//RX Raw Override to 1 >=20 > +#define B_GPIO_PCR_RX_RAW1 BIT28 >=20 > +#define N_GPIO_PCR_RX_RAW1 28 >=20 > + >=20 > +//RX Level/Edge Configuration >=20 > +#define B_GPIO_PCR_RX_LVL_EDG (BIT26 | BIT25) >=20 > +#define N_GPIO_PCR_RX_LVL_EDG 25 >=20 > + >=20 > +//RX Invert >=20 > +#define B_GPIO_PCR_RXINV BIT23 >=20 > +#define N_GPIO_PCR_RXINV 23 >=20 > + >=20 > +//GPIO Input Route IOxAPIC >=20 > +#define B_GPIO_PCR_RX_APIC_ROUTE BIT20 >=20 > + >=20 > +//GPIO Input Route SCI >=20 > +#define B_GPIO_PCR_RX_SCI_ROUTE BIT19 >=20 > + >=20 > +//GPIO Input Route SMI >=20 > +#define B_GPIO_PCR_RX_SMI_ROUTE BIT18 >=20 > + >=20 > +//GPIO Input Route NMI >=20 > +#define B_GPIO_PCR_RX_NMI_ROUTE BIT17 >=20 > +#define N_GPIO_PCR_RX_NMI_ROUTE 17 >=20 > + >=20 > +//GPIO Pad Mode >=20 > +#define B_GPIO_PCR_PAD_MODE (BIT12 | BIT11 | BIT10) >=20 > +#define N_GPIO_PCR_PAD_MODE 10 >=20 > + >=20 > +//GPIO RX Disable >=20 > +#define B_GPIO_PCR_RXDIS BIT9 >=20 > + >=20 > +//GPIO TX Disable >=20 > +#define B_GPIO_PCR_TXDIS BIT8 >=20 > +#define N_GPIO_PCR_TXDIS 8 >=20 > + >=20 > +//GPIO RX State >=20 > +#define B_GPIO_PCR_RX_STATE BIT1 >=20 > +#define N_GPIO_PCR_RX_STATE 1 >=20 > + >=20 > +//GPIO TX State >=20 > +#define B_GPIO_PCR_TX_STATE BIT0 >=20 > +#define N_GPIO_PCR_TX_STATE 0 >=20 > + >=20 > +//Termination >=20 > +#define B_GPIO_PCR_TERM (BIT13 | BIT12 | BIT11 | BIT10) >=20 > +#define N_GPIO_PCR_TERM 10 >=20 > + >=20 > +//Interrupt number >=20 > +#define B_GPIO_PCR_INTSEL 0x7F >=20 > +#define N_GPIO_PCR_INTSEL 0 >=20 > + >=20 > +/// >=20 > +/// GPIO SMI data used for EFI_SMM_GPI_DISPATCH2_PROTOCOL >=20 > +/// Below defines are to be used internally by PCH SMI dispatcher only >=20 > +/// >=20 > +#define PCH_GPIO_NUM_SUPPORTED_GPIS 512 >=20 > +#define S_GPIO_PCR_GP_SMI_STS 4 >=20 > + >=20 > +/// >=20 > +/// Groups mapped to 2-tier General Purpose Event will all be under >=20 > +/// one master GPE_111 (0x6F) >=20 > +/// >=20 > +#define PCH_GPIO_2_TIER_MASTER_GPE_NUMBER 0x6F >=20 > + >=20 > +#endif // _GPIO_REGS_H_ >=20 > diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/GpioRegsV= er2.h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/GpioRegsVer2.h > new file mode 100644 > index 0000000000..1dc05869dd > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/GpioRegsVer2.h > @@ -0,0 +1,226 @@ > +/** @file >=20 > + Register names for VER2 GPIO >=20 > + >=20 > +Conventions: >=20 > + >=20 > + - Register definition format: >=20 > + > Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterS > pace_RegisterName >=20 > + - Prefix: >=20 > + Definitions beginning with "R_" are registers >=20 > + Definitions beginning with "B_" are bits within registers >=20 > + Definitions beginning with "V_" are meaningful values within the bit= s >=20 > + Definitions beginning with "S_" are register size >=20 > + Definitions beginning with "N_" are the bit position >=20 > + - [GenerationName]: >=20 > + Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc= .). >=20 > + Register name without GenerationName applies to all generations. >=20 > + - [ComponentName]: >=20 > + This field indicates the component name that the register belongs to= (e.g. > PCH, SA etc.) >=20 > + Register name without ComponentName applies to all components. >=20 > + Register that is specific to -LP denoted by "_PCH_LP_" in component > name. >=20 > + - SubsystemName: >=20 > + This field indicates the subsystem name of the component that the > register belongs to >=20 > + (e.g. PCIE, USB, SATA, GPIO, PMC etc.). >=20 > + - RegisterSpace: >=20 > + MEM - MMIO space register of subsystem. >=20 > + IO - IO space register of subsystem. >=20 > + PCR - Private configuration register of subsystem. >=20 > + CFG - PCI configuration space register of subsystem. >=20 > + - RegisterName: >=20 > + Full register name. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _GPIO_REGS_VER2_H_ >=20 > +#define _GPIO_REGS_VER2_H_ >=20 > + >=20 > +// >=20 > +// PCH-LP GPIO >=20 > +// >=20 > +#define GPIO_VER2_PCH_LP_GPIO_GPP_B_PAD_MAX 26 >=20 > +#define GPIO_VER2_PCH_LP_GPIO_GPP_A_PAD_MAX 25 >=20 > +#define GPIO_VER2_PCH_LP_GPIO_GPP_R_PAD_MAX 8 >=20 > +#define GPIO_VER2_PCH_LP_GPIO_GPD_PAD_MAX 17 >=20 > +#define GPIO_VER2_PCH_LP_GPIO_GPP_S_PAD_MAX 8 >=20 > +#define GPIO_VER2_PCH_LP_GPIO_GPP_H_PAD_MAX 24 >=20 > +#define GPIO_VER2_PCH_LP_GPIO_GPP_D_PAD_MAX 21 >=20 > +#define GPIO_VER2_PCH_LP_GPIO_GPP_F_PAD_MAX 25 >=20 > +#define GPIO_VER2_PCH_LP_GPIO_GPP_C_PAD_MAX 24 >=20 > +#define GPIO_VER2_PCH_LP_GPIO_GPP_E_PAD_MAX 25 >=20 > +#define GPIO_VER2_PCH_LP_GPIO_CPU_PAD_MAX 15 >=20 > + >=20 > +// >=20 > +// PCH-LP GPIO registers >=20 > +// >=20 > + >=20 > +// >=20 > +// GPIO Community 0 Private Configuration Registers >=20 > +// >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_PAD_OWN 0x20 >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_PAD_OWN 0x38 >=20 > + >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_PADCFGLOCK 0x80 >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_PADCFGLOCKTX 0x84 >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_PADCFGLOCK 0x90 >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_PADCFGLOCKTX 0x94 >=20 > + >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_HOSTSW_OWN 0xB0 >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_HOSTSW_OWN 0xB8 >=20 > + >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_GPI_IS 0x0100 >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_GPI_IS 0x0108 >=20 > + >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_GPI_IE 0x0120 >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_GPI_IE 0x0128 >=20 > + >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_GPI_GPE_STS 0x0140 >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_GPI_GPE_STS 0x0148 >=20 > + >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_GPI_GPE_EN 0x0160 >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_GPI_GPE_EN 0x0168 >=20 > + >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_SMI_STS 0x0180 >=20 > + >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_SMI_EN 0x01A0 >=20 > + >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_NMI_STS 0x01C0 >=20 > + >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_NMI_EN 0x01E0 >=20 > + >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_PADCFG_OFFSET > 0x700 >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_PADCFG_OFFSET > 0x9A0 >=20 > + >=20 > +// >=20 > +// GPIO Community 1 Private Configuration Registers >=20 > +// >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_PAD_OWN 0x20 >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_PAD_OWN 0x24 >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_PAD_OWN 0x30 >=20 > + >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_PADCFGLOCK 0x80 >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_PADCFGLOCKTX 0x84 >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_PADCFGLOCK 0x88 >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_PADCFGLOCKTX 0x8C >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_PADCFGLOCK 0x90 >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_PADCFGLOCKTX 0x94 >=20 > + >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_HOSTSW_OWN 0xB0 >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_HOSTSW_OWN 0xB4 >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_HOSTSW_OWN 0xB8 >=20 > + >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_GPI_IS 0x0100 >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_GPI_IS 0x0104 >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_GPI_IS 0x0108 >=20 > + >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_GPI_IE 0x0120 >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_GPI_IE 0x0124 >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_GPI_IE 0x0128 >=20 > + >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_GPI_GPE_STS 0x0140 >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_GPI_GPE_STS 0x0144 >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_GPI_GPE_STS 0x0148 >=20 > + >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_GPI_GPE_EN 0x0160 >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_GPI_GPE_EN 0x0164 >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_GPI_GPE_EN 0x0168 >=20 > + >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_SMI_STS 0x0188 >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_SMI_EN 0x01A8 >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_NMI_STS 0x01C8 >=20 > + >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_NMI_EN 0x01E8 >=20 > + >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_PADCFG_OFFSET > 0x700 >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_PADCFG_OFFSET > 0x780 >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_PADCFG_OFFSET > 0x900 >=20 > + >=20 > +// >=20 > +// GPIO Community 2 Private Configuration Registers >=20 > +// >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_PAD_OWN 0x20 >=20 > + >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_PADCFGLOCK 0x80 >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_PADCFGLOCKTX 0x84 >=20 > + >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_HOSTSW_OWN 0xB0 >=20 > + >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_GPI_IS 0x0100 >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_GPI_IE 0x0120 >=20 > + >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_GPI_GPE_STS 0x0140 >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_GPI_GPE_EN 0x0160 >=20 > + >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_PADCFG_OFFSET 0x700 >=20 > + >=20 > +// >=20 > +// GPIO Community 4 Private Configuration Registers >=20 > +// >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_PAD_OWN 0x20 >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_PAD_OWN 0x2C >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_PAD_OWN 0x40 >=20 > + >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_PADCFGLOCK 0x80 >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_PADCFGLOCKTX 0x84 >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_PADCFGLOCK 0x88 >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_PADCFGLOCKTX 0x8C >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_PADCFGLOCK 0x98 >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_PADCFGLOCKTX 0x9C >=20 > + >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_HOSTSW_OWN 0xB0 >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_HOSTSW_OWN 0xB4 >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_HOSTSW_OWN 0xBC >=20 > + >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_GPI_IS 0x0100 >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_GPI_IS 0x0104 >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_GPI_IS 0x010C >=20 > + >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_GPI_IE 0x0120 >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_GPI_IE 0x0124 >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_GPI_IE 0x012C >=20 > + >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_GPI_GPE_STS 0x0140 >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_GPI_GPE_STS 0x0144 >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_GPI_GPE_STS 0x014C >=20 > + >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_GPI_GPE_EN 0x0160 >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_GPI_GPE_EN 0x0164 >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_GPI_GPE_EN 0x016C >=20 > + >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_SMI_STS 0x0180 >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_SMI_STS 0x018C >=20 > + >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_SMI_EN 0x01A0 >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_SMI_EN 0x01AC >=20 > + >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_NMI_STS 0x01C0 >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_NMI_STS 0x01CC >=20 > + >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_NMI_EN 0x01E0 >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_NMI_EN 0x01EC >=20 > + >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_PADCFG_OFFSET > 0x700 >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_PADCFG_OFFSET > 0x880 >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_PADCFG_OFFSET > 0xA70 >=20 > + >=20 > +// >=20 > +// GPIO Community 5 Private Configuration Registers >=20 > +// >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_PAD_OWN 0x20 >=20 > + >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_PADCFGLOCK 0x80 >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_PADCFGLOCKTX 0x84 >=20 > + >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_HOSTSW_OWN 0xB0 >=20 > + >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_GPI_IS 0x0100 >=20 > + >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_GPI_IE 0x0120 >=20 > + >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_GPI_GPE_STS 0x0140 >=20 > + >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_GPI_GPE_EN 0x0160 >=20 > + >=20 > +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_PADCFG_OFFSET > 0x700 >=20 > + >=20 > +#endif // _GPIO_REGS_VER2_H_ >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/PchDmi14Regs.h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/PchDmi14Regs.h > new file mode 100644 > index 0000000000..5447fabccf > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/PchDmi14Regs.h > @@ -0,0 +1,16 @@ > +/** @file >=20 > + Register names for PCH DMI SIP14 >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _PCH_DMI14_REGS_H_ >=20 > +#define _PCH_DMI14_REGS_H_ >=20 > + >=20 > +// >=20 > +// DMI Control >=20 > +// >=20 > +#define R_PCH_DMI14_PCR_DMIC 0x2234 = ///< > DMI Control >=20 > +#define B_PCH_DMI14_PCR_DMIC_SRL BIT31 = ///< > Secured register lock >=20 > + >=20 > +#endif >=20 > diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/PchDmiReg= s.h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/PchDmiRegs.h > new file mode 100644 > index 0000000000..e9e6f80327 > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/PchDmiRegs.h > @@ -0,0 +1,36 @@ > +/** @file >=20 > + Register names for PCH DMI and OP-DMI >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _PCH_DMI_REGS_H_ >=20 > +#define _PCH_DMI_REGS_H_ >=20 > + >=20 > +// >=20 > +// PCH DMI Chipset Configuration Registers (PID:DMI) >=20 > +// >=20 > + >=20 > +// >=20 > +// PCH DMI Source Decode PCRs (Common) >=20 > +// >=20 > +#define R_PCH_DMI_PCR_LPCLGIR1 0x2730 = ///< LPC > Generic I/O Range 1 >=20 > +#define R_PCH_DMI_PCR_LPCGMR 0x2740 = ///< LPC > Generic Memory Range >=20 > +#define R_PCH_DMI_PCR_SEGIR 0x27BC = ///< Second > ESPI Generic I/O Range >=20 > +#define R_PCH_DMI_PCR_SEGMR 0x27C0 = ///< > Second ESPI Generic Memory Range >=20 > +#define R_PCH_DMI_PCR_LPCBDE 0x2744 = ///< LPC > BIOS Decode Enable >=20 > +#define R_PCH_DMI_PCR_UCPR 0x2748 = ///< uCode > Patch Region >=20 > +#define B_PCH_DMI_PCR_UCPR_UPRE BIT0 = ///< > uCode Patch Region Enable >=20 > +#define R_PCH_DMI_PCR_GCS 0x274C = ///< Generic > Control and Status >=20 > +#define B_PCH_DMI_PCR_BBS BIT10 = ///< Boot BIOS > Strap >=20 > +#define B_PCH_DMI_PCR_RPR BIT11 = ///< Reserved > Page Route >=20 > +#define B_PCH_DMI_PCR_BILD BIT0 = ///< BIOS > Interface Lock-Down >=20 > +#define R_PCH_DMI_PCR_IOT1 0x2750 = ///< I/O Trap > Register 1 >=20 > +#define R_PCH_DMI_PCR_LPCIOD 0x2770 = ///< LPC I/O > Decode Ranges >=20 > +#define R_PCH_DMI_PCR_LPCIOE 0x2774 = ///< LPC I/O > Enables >=20 > +#define R_PCH_DMI_PCR_TCOBASE 0x2778 = ///< TCO > Base Address >=20 > +#define B_PCH_DMI_PCR_TCOBASE_TCOBA 0xFFE0 = ///< > TCO Base Address Mask >=20 > +#define R_PCH_DMI_PCR_GPMR1 0x277C = ///< > General Purpose Memory Range 1 >=20 > +#define R_PCH_DMI_PCR_GPMR1DID 0x2780 = ///< > General Purpose Memory Range 1 Destination ID >=20 > + >=20 > +#endif >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/PchPcieRpRegs.h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/PchPcieRpRegs.h > new file mode 100644 > index 0000000000..c3497b1013 > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/PchPcieRpRegs.h > @@ -0,0 +1,93 @@ > +/** @file >=20 > + Register names for PCH PCI-E root port devices >=20 > + >=20 > + Conventions: >=20 > + >=20 > + - Register definition format: >=20 > + > Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterS > pace_RegisterName >=20 > + - Prefix: >=20 > + Definitions beginning with "R_" are registers >=20 > + Definitions beginning with "B_" are bits within registers >=20 > + Definitions beginning with "V_" are meaningful values within the bit= s >=20 > + Definitions beginning with "S_" are register size >=20 > + Definitions beginning with "N_" are the bit position >=20 > + - [GenerationName]: >=20 > + Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc= .). >=20 > + Register name without GenerationName applies to all generations. >=20 > + - [ComponentName]: >=20 > + This field indicates the component name that the register belongs to= (e.g. > PCH, SA etc.) >=20 > + Register name without ComponentName applies to all components. >=20 > + Register that is specific to -LP denoted by "_PCH_LP_" in component > name. >=20 > + - SubsystemName: >=20 > + This field indicates the subsystem name of the component that the > register belongs to >=20 > + (e.g. PCIE, USB, SATA, GPIO, PMC etc.). >=20 > + - RegisterSpace: >=20 > + MEM - MMIO space register of subsystem. >=20 > + IO - IO space register of subsystem. >=20 > + PCR - Private configuration register of subsystem. >=20 > + CFG - PCI configuration space register of subsystem. >=20 > + - RegisterName: >=20 > + Full register name. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _PCH_REGS_PCIE_H_ >=20 > +#define _PCH_REGS_PCIE_H_ >=20 > + >=20 > +#define R_PCH_PCIE_CFG_CLIST 0x40 >=20 > +#define R_PCH_PCIE_CFG_LCAP (R_PCH_PCIE_CFG_CL= IST + > R_PCIE_LCAP_OFFSET) >=20 > +#define N_PCH_PCIE_CFG_LCAP_PN 24 >=20 > +#define R_PCH_PCIE_CFG_LCTL (R_PCH_PCIE_CFG_CL= IST + > R_PCIE_LCTL_OFFSET) >=20 > +#define R_PCH_PCIE_CFG_LSTS (R_PCH_PCIE_CFG_CL= IST + > R_PCIE_LSTS_OFFSET) >=20 > +#define R_PCH_PCIE_CFG_SLCAP (R_PCH_PCIE_CFG_CL= IST + > R_PCIE_SLCAP_OFFSET) >=20 > +#define R_PCH_PCIE_CFG_SLSTS (R_PCH_PCIE_CFG_CL= IST + > R_PCIE_SLSTS_OFFSET) >=20 > + >=20 > +#define R_PCH_PCIE_CFG_MPC2 0xD4 >=20 > +#define B_PCH_PCIE_CFG_MPC2_EOIFD BIT1 >=20 > + >=20 > +#define R_PCH_PCIE_CFG_MPC 0xD8 >=20 > +#define S_PCH_PCIE_CFG_MPC 4 >=20 > +#define B_PCH_PCIE_CFG_MPC_PMCE BIT31 >=20 > +#define B_PCH_PCIE_CFG_MPC_HPME BIT1 >=20 > +#define N_PCH_PCIE_CFG_MPC_HPME 1 >=20 > + >=20 > +#define R_PCH_PCIE_CFG_SMSCS 0xDC >=20 > +#define S_PCH_PCIE_CFG_SMSCS 4 >=20 > +#define B_PCH_PCIE_CFG_SMSCS_PMCS BIT31 >=20 > +#define N_PCH_PCIE_CFG_SMSCS_LERSMIS 5 >=20 > +#define N_PCH_PCIE_CFG_SMSCS_HPLAS 4 >=20 > +#define N_PCH_PCIE_CFG_SMSCS_HPPDM 1 >=20 > + >=20 > +//CES.RE, CES.BT, CES.BD >=20 > + >=20 > +#define R_PCH_PCIE_CFG_EX_SPEECH 0xA30 ///< Seconda= ry PCI > Express Extended Capability Header >=20 > +#define R_PCH_PCIE_CFG_EX_LCTL3 > (R_PCH_PCIE_CFG_EX_SPEECH + R_PCIE_EX_LCTL3_OFFSET) >=20 > + >=20 > +#define R_PCH_PCIE_CFG_LTROVR 0x400 >=20 > +#define B_PCH_PCIE_CFG_LTROVR_LTRNSROVR BIT31 ///< LTR Non= - > Snoop Requirement Bit Override >=20 > +#define B_PCH_PCIE_CFG_LTROVR_LTRSROVR BIT15 ///< LTR > Snoop Requirement Bit Override >=20 > + >=20 > +#define R_PCH_PCIE_CFG_LTROVR2 0x404 >=20 > +#define B_PCH_PCIE_CFG_LTROVR2_FORCE_OVERRIDE BIT3 ///< LTR > Force Override Enable >=20 > +#define B_PCH_PCIE_CFG_LTROVR2_LOCK BIT2 ///< LTR Over= ride > Lock >=20 > +#define B_PCH_PCIE_CFG_LTROVR2_LTRNSOVREN BIT1 ///< LTR > Non-Snoop Override Enable >=20 > +#define B_PCH_PCIE_CFG_LTROVR2_LTRSOVREN BIT0 ///< LTR > Snoop Override Enable >=20 > + >=20 > +#define R_PCH_PCIE_CFG_PCIEPMECTL 0x420 >=20 > +#define B_PCH_PCIE_CFG_PCIEPMECTL_DLSULPPGE BIT30 >=20 > +#define B_PCH_PCIE_CFG_PCIEPMECTL_L1LE BIT17 >=20 > +#define B_PCH_PCIE_CFG_PCIEPMECTL_L1FSOE BIT0 >=20 > + >=20 > +#define R_PCH_PCIE_CFG_EQCFG1 0x450 >=20 > +#define S_PCH_PCIE_CFG_EQCFG1 4 >=20 > +#define N_PCH_PCIE_CFG_EQCFG1_LERSMIE 21 >=20 > + >=20 > +// >=20 > +// PCIE PCRs (PID:SPA SPB SPC SPD SPE SPF) >=20 > +// >=20 > +#define R_SPX_PCR_PCD 0 //= /< Port configuration > and disable >=20 > +#define B_SPX_PCR_PCD_RP1FN (BIT2 | BIT1 | BIT0) //= /< Port 1 > Function Number >=20 > +#define S_SPX_PCR_PCD_RP_FIELD 4 //= /< 4 bits for each > RP FN >=20 > + >=20 > +#endif >=20 > diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/PmcRegs.h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/PmcRegs.h > new file mode 100644 > index 0000000000..fac1497773 > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/PmcRegs.h > @@ -0,0 +1,258 @@ > +/** @file >=20 > + Register names for PCH PMC device >=20 > + >=20 > + Conventions: >=20 > + >=20 > + - Register definition format: >=20 > + > Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterS > pace_RegisterName >=20 > + - Prefix: >=20 > + Definitions beginning with "R_" are registers >=20 > + Definitions beginning with "B_" are bits within registers >=20 > + Definitions beginning with "V_" are meaningful values within the bit= s >=20 > + Definitions beginning with "S_" are register size >=20 > + Definitions beginning with "N_" are the bit position >=20 > + - [GenerationName]: >=20 > + Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc= .). >=20 > + Register name without GenerationName applies to all generations. >=20 > + - [ComponentName]: >=20 > + This field indicates the component name that the register belongs to= (e.g. > PCH, SA etc.) >=20 > + Register name without ComponentName applies to all components. >=20 > + Register that is specific to -LP denoted by "_PCH_LP_" in component > name. >=20 > + - SubsystemName: >=20 > + This field indicates the subsystem name of the component that the > register belongs to >=20 > + (e.g. PCIE, USB, SATA, GPIO, PMC etc.). >=20 > + - RegisterSpace: >=20 > + MEM - MMIO space register of subsystem. >=20 > + IO - IO space register of subsystem. >=20 > + PCR - Private configuration register of subsystem. >=20 > + CFG - PCI configuration space register of subsystem. >=20 > + - RegisterName: >=20 > + Full register name. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _PCH_REGS_PMC_H_ >=20 > +#define _PCH_REGS_PMC_H_ >=20 > + >=20 > +// >=20 > +// ACPI and legacy I/O register offsets from ACPIBASE >=20 > +// >=20 > +#define R_ACPI_IO_PM1_STS 0x00 >=20 > +#define S_ACPI_IO_PM1_STS 2 >=20 > +#define B_ACPI_IO_PM1_STS_WAK BIT15 >=20 > +#define B_ACPI_IO_PM1_STS_PCIEXP_WAKE_STS BIT14 >=20 > +#define B_ACPI_IO_PM1_STS_PRBTNOR BIT11 >=20 > +#define B_ACPI_IO_PM1_STS_RTC BIT10 >=20 > +#define B_ACPI_IO_PM1_STS_PWRBTN BIT8 >=20 > +#define B_ACPI_IO_PM1_STS_GBL BIT5 >=20 > +#define B_ACPI_IO_PM1_STS_TMROF BIT0 >=20 > +#define N_ACPI_IO_PM1_STS_RTC 10 >=20 > +#define N_ACPI_IO_PM1_STS_PWRBTN 8 >=20 > +#define N_ACPI_IO_PM1_STS_TMROF 0 >=20 > + >=20 > +#define R_ACPI_IO_PM1_EN 0x02 >=20 > +#define S_ACPI_IO_PM1_EN 2 >=20 > +#define B_ACPI_IO_PM1_EN_PWRBTN BIT8 >=20 > +#define N_ACPI_IO_PM1_EN_RTC 10 >=20 > +#define N_ACPI_IO_PM1_EN_PWRBTN 8 >=20 > +#define N_ACPI_IO_PM1_EN_TMROF 0 >=20 > + >=20 > +#define R_ACPI_IO_PM1_CNT 0x04 >=20 > +#define B_ACPI_IO_PM1_CNT_SLP_EN BIT13 >=20 > +#define B_ACPI_IO_PM1_CNT_SLP_TYP (BIT12 | BIT11 | BIT10) >=20 > +#define V_ACPI_IO_PM1_CNT_S0 0 >=20 > +#define V_ACPI_IO_PM1_CNT_S1 BIT10 >=20 > +#define V_ACPI_IO_PM1_CNT_S3 (BIT12 | BIT10) >=20 > +#define V_ACPI_IO_PM1_CNT_S4 (BIT12 | BIT11) >=20 > +#define V_ACPI_IO_PM1_CNT_S5 (BIT12 | BIT11 | BIT10) >=20 > +#define B_ACPI_IO_PM1_CNT_SCI_EN BIT0 >=20 > + >=20 > +#define R_ACPI_IO_PM1_TMR 0x08 >=20 > +#define B_ACPI_IO_PM1_TMR_VAL 0xFFFFFF >=20 > +#define V_ACPI_IO_PM1_TMR_MAX_VAL 0x1000000 ///< Th= e > timer is 24 bit overflow >=20 > + >=20 > +#define R_ACPI_IO_SMI_EN 0x30 >=20 > +#define S_ACPI_IO_SMI_EN 4 >=20 > +#define B_ACPI_IO_SMI_EN_LEGACY_USB2 BIT17 >=20 > +#define B_ACPI_IO_SMI_EN_TCO BIT13 >=20 > +#define B_ACPI_IO_SMI_EN_BIOS_RLS BIT7 >=20 > +#define B_ACPI_IO_SMI_EN_SWSMI_TMR BIT6 >=20 > +#define B_ACPI_IO_SMI_EN_APMC BIT5 >=20 > +#define B_ACPI_IO_SMI_EN_LEGACY_USB BIT3 >=20 > +#define B_ACPI_IO_SMI_EN_BIOS BIT2 >=20 > +#define B_ACPI_IO_SMI_EN_EOS BIT1 >=20 > +#define B_ACPI_IO_SMI_EN_GBL_SMI BIT0 >=20 > +#define N_ACPI_IO_SMI_EN_LEGACY_USB3 31 >=20 > +#define N_ACPI_IO_SMI_EN_ESPI 28 >=20 > +#define N_ACPI_IO_SMI_EN_PERIODIC 14 >=20 > +#define N_ACPI_IO_SMI_EN_TCO 13 >=20 > +#define N_ACPI_IO_SMI_EN_MCSMI 11 >=20 > +#define N_ACPI_IO_SMI_EN_SWSMI_TMR 6 >=20 > +#define N_ACPI_IO_SMI_EN_APMC 5 >=20 > +#define N_ACPI_IO_SMI_EN_ON_SLP_EN 4 >=20 > +#define N_ACPI_IO_SMI_EN_LEGACY_USB 3 >=20 > + >=20 > +#define R_ACPI_IO_SMI_STS 0x34 >=20 > +#define S_ACPI_IO_SMI_STS 4 >=20 > +#define B_ACPI_IO_SMI_STS_GPIO_UNLOCK BIT27 >=20 > +#define B_ACPI_IO_SMI_STS_SMBUS BIT16 >=20 > +#define B_ACPI_IO_SMI_STS_PERIODIC BIT14 >=20 > +#define B_ACPI_IO_SMI_STS_TCO BIT13 >=20 > +#define B_ACPI_IO_SMI_STS_MCSMI BIT11 >=20 > +#define B_ACPI_IO_SMI_STS_SWSMI_TMR BIT6 >=20 > +#define B_ACPI_IO_SMI_STS_APM BIT5 >=20 > +#define B_ACPI_IO_SMI_STS_ON_SLP_EN BIT4 >=20 > +#define B_ACPI_IO_SMI_STS_BIOS BIT2 >=20 > +#define N_ACPI_IO_SMI_STS_LEGACY_USB3 31 >=20 > +#define N_ACPI_IO_SMI_STS_ESPI 28 >=20 > +#define N_ACPI_IO_SMI_STS_SPI 26 >=20 > +#define N_ACPI_IO_SMI_STS_MONITOR 21 >=20 > +#define N_ACPI_IO_SMI_STS_PCI_EXP 20 >=20 > +#define N_ACPI_IO_SMI_STS_SMBUS 16 >=20 > +#define N_ACPI_IO_SMI_STS_SERIRQ 15 >=20 > +#define N_ACPI_IO_SMI_STS_PERIODIC 14 >=20 > +#define N_ACPI_IO_SMI_STS_TCO 13 >=20 > +#define N_ACPI_IO_SMI_STS_MCSMI 11 >=20 > +#define N_ACPI_IO_SMI_STS_GPIO_SMI 10 >=20 > +#define N_ACPI_IO_SMI_STS_GPE0 9 >=20 > +#define N_ACPI_IO_SMI_STS_PM1_STS_REG 8 >=20 > +#define N_ACPI_IO_SMI_STS_SWSMI_TMR 6 >=20 > +#define N_ACPI_IO_SMI_STS_APM 5 >=20 > +#define N_ACPI_IO_SMI_STS_ON_SLP_EN 4 >=20 > +#define N_ACPI_IO_SMI_STS_LEGACY_USB 3 >=20 > + >=20 > +#define R_ACPI_IO_DEVACT_STS 0x44 >=20 > +#define B_ACPI_IO_DEVACT_STS_KBC BIT12 >=20 > +#define B_ACPI_IO_DEVACT_STS_PIRQDH BIT9 >=20 > +#define B_ACPI_IO_DEVACT_STS_PIRQCG BIT8 >=20 > +#define B_ACPI_IO_DEVACT_STS_PIRQBF BIT7 >=20 > +#define B_ACPI_IO_DEVACT_STS_PIRQAE BIT6 >=20 > + >=20 > +#define R_ACPI_IO_GPE0_STS_127_96 0x6C >=20 > +#define S_ACPI_IO_GPE0_STS_127_96 4 >=20 > +#define B_ACPI_IO_GPE0_STS_127_96_WADT BIT18 >=20 > +#define B_ACPI_IO_GPE0_STS_127_96_USB_CON_DSX_STS BIT17 >=20 > +#define B_ACPI_IO_GPE0_STS_127_96_LAN_WAKE BIT16 >=20 > +#define B_ACPI_IO_GPE0_STS_127_96_PME_B0 BIT13 >=20 > +#define B_ACPI_IO_GPE0_STS_127_96_PME BIT11 >=20 > +#define B_ACPI_IO_GPE0_STS_127_96_BATLOW BIT10 >=20 > +#define B_ACPI_IO_GPE0_STS_127_96_RI BIT8 >=20 > +#define B_ACPI_IO_GPE0_STS_127_96_SMB_WAK BIT7 >=20 > +#define B_ACPI_IO_GPE0_STS_127_96_SWGPE BIT2 >=20 > +#define N_ACPI_IO_GPE0_STS_127_96_PME_B0 13 >=20 > +#define N_ACPI_IO_GPE0_STS_127_96_PME 11 >=20 > + >=20 > +#define R_ACPI_IO_GPE0_EN_127_96 0x7C >=20 > +#define S_ACPI_IO_GPE0_EN_127_96 4 >=20 > +#define B_ACPI_IO_GPE0_EN_127_96_WADT BIT18 >=20 > +#define B_ACPI_IO_GPE0_EN_127_96_LAN_WAKE BIT16 >=20 > +#define B_ACPI_IO_GPE0_EN_127_96_PME_B0 BIT13 >=20 > +#define B_ACPI_IO_GPE0_EN_127_96_ME_SCI BIT12 >=20 > +#define B_ACPI_IO_GPE0_EN_127_96_PME BIT11 >=20 > +#define B_ACPI_IO_GPE0_EN_127_96_BATLOW BIT10 >=20 > +#define B_ACPI_IO_GPE0_EN_127_96_RI BIT8 >=20 > +#define B_ACPI_IO_GPE0_EN_127_96_SWGPE BIT2 >=20 > +#define N_ACPI_IO_GPE0_EN_127_96_PME_B0 13 >=20 > +#define N_ACPI_IO_GPE0_EN_127_96_PME 11 >=20 > + >=20 > +// >=20 > +// TCO register I/O map >=20 > +// >=20 > +#define R_TCO_IO_TCO1_STS 0x04 >=20 > +#define S_TCO_IO_TCO1_STS 2 >=20 > +#define B_TCO_IO_TCO1_STS_DMISERR BIT12 >=20 > +#define B_TCO_IO_TCO1_STS_DMISMI BIT10 >=20 > +#define B_TCO_IO_TCO1_STS_DMISCI BIT9 >=20 > +#define B_TCO_IO_TCO1_STS_BIOSWR BIT8 >=20 > +#define B_TCO_IO_TCO1_STS_NEWCENTURY BIT7 >=20 > +#define B_TCO_IO_TCO1_STS_TIMEOUT BIT3 >=20 > +#define B_TCO_IO_TCO1_STS_TCO_INT BIT2 >=20 > +#define B_TCO_IO_TCO1_STS_SW_TCO_SMI BIT1 >=20 > +#define N_TCO_IO_TCO1_STS_DMISMI 10 >=20 > +#define N_TCO_IO_TCO1_STS_BIOSWR 8 >=20 > +#define N_TCO_IO_TCO1_STS_NEWCENTURY 7 >=20 > +#define N_TCO_IO_TCO1_STS_TIMEOUT 3 >=20 > +#define N_TCO_IO_TCO1_STS_SW_TCO_SMI 1 >=20 > +#define N_TCO_IO_TCO1_STS_NMI2SMI 0 >=20 > + >=20 > +#define R_TCO_IO_TCO2_STS 0x06 >=20 > +#define S_TCO_IO_TCO2_STS 2 >=20 > +#define B_TCO_IO_TCO2_STS_SECOND_TO BIT1 >=20 > +#define B_TCO_IO_TCO2_STS_INTRD_DET BIT0 >=20 > +#define N_TCO_IO_TCO2_STS_INTRD_DET 0 >=20 > + >=20 > +#define R_TCO_IO_TCO1_CNT 0x08 >=20 > +#define S_TCO_IO_TCO1_CNT 2 >=20 > +#define B_TCO_IO_TCO1_CNT_LOCK BIT12 >=20 > +#define N_TCO_IO_TCO1_CNT_NMI2SMI_EN 9 >=20 > + >=20 > +#define R_TCO_IO_TCO2_CNT 0x0A >=20 > +#define S_TCO_IO_TCO2_CNT 2 >=20 > +#define N_TCO_IO_TCO2_CNT_INTRD_SEL 2 >=20 > + >=20 > +// >=20 > +// PWRM Registers >=20 > +// >=20 > +#define R_PMC_PWRM_GEN_PMCON_A 0x1020 > ///< in CNL located in PWRM >=20 > +#define B_PMC_PWRM_GEN_PMCON_A_GBL_RST_STS BIT24 >=20 > +#define B_PMC_PWRM_GEN_PMCON_A_DISB BIT23 >=20 > +#define B_PMC_PWRM_GEN_PMCON_A_ALLOW_L1LOW_C0 BIT19 >=20 > +#define B_PMC_PWRM_GEN_PMCON_A_MS4V BIT18 >=20 > +#define B_PMC_PWRM_GEN_PMCON_A_SUS_PWR_FLR BIT16 >=20 > +#define B_PMC_PWRM_GEN_PMCON_A_PWR_FLR BIT14 >=20 > +#define B_PMC_PWRM_GEN_PMCON_A_HOST_RST_STS BIT9 >=20 > +#define B_PMC_PWRM_GEN_PMCON_A_ESPI_SMI_LOCK BIT8 >=20 > +#define B_PMC_PWRM_GEN_PMCON_A_AFTERG3_EN BIT0 >=20 > +#define B_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL 0xC0 >=20 > +#define V_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL_64MS 0xC0 >=20 > +#define V_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL_32MS 0x80 >=20 > +#define V_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL_16MS 0x40 >=20 > +#define V_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL_1_5MS 0x00 >=20 > +#define B_PMC_PWRM_GEN_PMCON_A_PER_SMI_SEL 0x6 >=20 > +#define V_PMC_PWRM_GEN_PMCON_A_PER_SMI_64S 0x0000 >=20 > +#define V_PMC_PWRM_GEN_PMCON_A_PER_SMI_32S 0x0002 >=20 > +#define V_PMC_PWRM_GEN_PMCON_A_PER_SMI_16S 0x0004 >=20 > +#define V_PMC_PWRM_GEN_PMCON_A_PER_SMI_8S 0x0006 >=20 > + >=20 > +#define R_PMC_PWRM_GEN_PMCON_B 0x1024 >=20 > +#define B_PMC_PWRM_GEN_PMCON_B_SLPSX_STR_POL_LOCK > BIT18 ///< Lock down SLP_S3/SLP_S4 Minimum Assertion width >=20 > +#define B_PMC_PWRM_GEN_PMCON_B_PWRBTN_LVL BIT9 >=20 > +#define B_PMC_PWRM_GEN_PMCON_B_SMI_LOCK BIT4 >=20 > +#define B_PMC_PWRM_GEN_PMCON_B_RTC_PWR_STS BIT2 >=20 > + >=20 > +#define R_PMC_PWRM_CRID 0x1030 = ///< > Configured Revision ID >=20 > +#define V_PMC_PWRM_CRID_RID_SEL_CRID0 1 >=20 > +#define B_PMC_PWRM_CRID_CRID_LK BIT31 = ///< CRID > Lock >=20 > + >=20 > +#define R_PMC_PWRM_ETR3 0x1048 = ///< in CNL this > is PWRM register >=20 > +#define B_PMC_PWRM_ETR3_CF9LOCK BIT31 = ///< CF9h > Lockdown >=20 > +#define B_PMC_PWRM_ETR3_CF9GR BIT20 = ///< CF9h > Global Reset >=20 > +#define B_PMC_PWRM_ETR3_CWORWRE BIT18 >=20 > + >=20 > +#define R_PMC_PWRM_CFG 0x1818 = ///< > Power Management Configuration >=20 > +#define B_PMC_PWRM_CFG_DBG_MODE_LOCK BIT27 > ///< Debug Mode Lock >=20 > +#define B_PMC_PWRM_CFG_PMCREAD_DISABLE BIT22 > ///< Disable Reads to PMC >=20 > +#define B_PMC_PWRM_CFG_TIMING_TPCH25 (BIT1 | BIT0= ) > ///< tPCH25 timing >=20 > + >=20 > +#define R_PMC_PWRM_DSX_CFG 0x1834 = ///< > Deep SX Configuration >=20 > +#define B_PMC_PWRM_DSX_CFG_LAN_WAKE_EN BIT0 > ///< LAN_WAKE Pin DeepSx Enable >=20 > + >=20 > +#define R_PMC_PWRM_GPIO_CFG 0x1920 >=20 > +#define B_PMC_PWRM_GPIO_CFG_GPE0_DW2 (BIT11 | BIT= 10 | > BIT9 | BIT8) >=20 > +#define N_PMC_PWRM_GPIO_CFG_GPE0_DW2 8 >=20 > +#define B_PMC_PWRM_GPIO_CFG_GPE0_DW1 (BIT7 | BIT6= | > BIT5 | BIT4) >=20 > +#define N_PMC_PWRM_GPIO_CFG_GPE0_DW1 4 >=20 > +#define B_PMC_PWRM_GPIO_CFG_GPE0_DW0 (BIT3 | BIT2= | > BIT1 | BIT0) >=20 > +#define N_PMC_PWRM_GPIO_CFG_GPE0_DW0 0 >=20 > + >=20 > +#define R_PMC_PWRM_HPR_CAUSE0 0x192C ///= < Host > partition reset causes >=20 > +#define B_PMC_PWRM_HPR_CAUSE0_GBL_TO_HOST BIT15 ///= < > Global reset converted to Host reset >=20 > + >=20 > +#define R_PMC_PWRM_ST_PG_FDIS_PMC_1 0x1E20 ///< > Static PG Related Function Disable Register 1 >=20 > +#define B_PMC_PWRM_ST_PG_FDIS_PMC_1_ST_FDIS_LK BIT31 > ///< Static Function Disable Lock (ST_FDIS_LK) >=20 > + >=20 > +#define R_PMC_PWRM_FUSE_DIS_RD_2 0x1E44 ///< = Fuse > Disable Read 2 Register >=20 > +#define B_PMC_PWRM_FUSE_DIS_RD_2_GBE_FUSE_SS_DIS BIT0 > ///< GBE Fuse or Soft Strap Disable >=20 > + >=20 > +#endif >=20 > diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/RtcRegs.h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/RtcRegs.h > new file mode 100644 > index 0000000000..5824663d22 > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/RtcRegs.h > @@ -0,0 +1,45 @@ > +/** @file >=20 > + Register names for RTC device >=20 > + >=20 > +Conventions: >=20 > + >=20 > + - Register definition format: >=20 > + > Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterS > pace_RegisterName >=20 > + - Prefix: >=20 > + Definitions beginning with "R_" are registers >=20 > + Definitions beginning with "B_" are bits within registers >=20 > + Definitions beginning with "V_" are meaningful values within the bit= s >=20 > + Definitions beginning with "S_" are register size >=20 > + Definitions beginning with "N_" are the bit position >=20 > + - [GenerationName]: >=20 > + Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc= .). >=20 > + Register name without GenerationName applies to all generations. >=20 > + - [ComponentName]: >=20 > + This field indicates the component name that the register belongs to= (e.g. > PCH, SA etc.) >=20 > + Register name without ComponentName applies to all components. >=20 > + Register that is specific to -LP denoted by "_PCH_LP_" in component > name. >=20 > + - SubsystemName: >=20 > + This field indicates the subsystem name of the component that the > register belongs to >=20 > + (e.g. PCIE, USB, SATA, GPIO, PMC etc.). >=20 > + - RegisterSpace: >=20 > + MEM - MMIO space register of subsystem. >=20 > + IO - IO space register of subsystem. >=20 > + PCR - Private configuration register of subsystem. >=20 > + CFG - PCI configuration space register of subsystem. >=20 > + - RegisterName: >=20 > + Full register name. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _REGS_RTC_H_ >=20 > +#define _REGS_RTC_H_ >=20 > + >=20 > +#define R_RTC_IO_INDEX 0x70 >=20 > +#define R_RTC_IO_TARGET 0x71 >=20 > +#define R_RTC_IO_INDEX_ALT 0x74 >=20 > +#define R_RTC_IO_TARGET_ALT 0x75 >=20 > +#define R_RTC_IO_EXT_INDEX_ALT 0x76 >=20 > +#define R_RTC_IO_REGD 0x0D >=20 > + >=20 > +#endif >=20 > diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/SataRegs.= h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/SataRegs.h > new file mode 100644 > index 0000000000..2037bb003d > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/SataRegs.h > @@ -0,0 +1,56 @@ > +/** @file >=20 > + Register names for SATA controllers >=20 > + >=20 > + Conventions: >=20 > + >=20 > + - Register definition format: >=20 > + > Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterS > pace_RegisterName >=20 > + - Prefix: >=20 > + Definitions beginning with "R_" are registers >=20 > + Definitions beginning with "B_" are bits within registers >=20 > + Definitions beginning with "V_" are meaningful values within the bit= s >=20 > + Definitions beginning with "S_" are register size >=20 > + Definitions beginning with "N_" are the bit position >=20 > + - [GenerationName]: >=20 > + Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc= .). >=20 > + Register name without GenerationName applies to all generations. >=20 > + - [ComponentName]: >=20 > + This field indicates the component name that the register belongs to= (e.g. > PCH, SA etc.) >=20 > + Register name without ComponentName applies to all components. >=20 > + Register that is specific to -LP denoted by "_PCH_LP_" in component > name. >=20 > + - SubsystemName: >=20 > + This field indicates the subsystem name of the component that the > register belongs to >=20 > + (e.g. PCIE, USB, SATA, GPIO, PMC etc.). >=20 > + - RegisterSpace: >=20 > + MEM - MMIO space register of subsystem. >=20 > + IO - IO space register of subsystem. >=20 > + PCR - Private configuration register of subsystem. >=20 > + CFG - PCI configuration space register of subsystem. >=20 > + - RegisterName: >=20 > + Full register name. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _SATA_REGS_H_ >=20 > +#define _SATA_REGS_H_ >=20 > + >=20 > +// >=20 > +// SATA Controller Common Registers >=20 > +// >=20 > +#define R_SATA_CFG_AHCI_BAR 0x24 >=20 > +#define R_SATA_CFG_MAP 0x90 >=20 > +#define N_SATA_CFG_MAP_SPD 16 >=20 > +#define R_SATA_CFG_PCS 0x94 >=20 > +#define B_SATA_CFG_PCS_P0P BIT16 >=20 > +#define R_SATA_CFG_SATAGC 0x9C >=20 > +#define B_SATA_CFG_SATAGC_ASSEL (BIT2 | BIT1 | BIT0) >=20 > +#define V_SATA_CFG_SATAGC_ASSEL_2K 0x0 >=20 > +#define V_SATA_CFG_SATAGC_ASSEL_16K 0x1 >=20 > +#define V_SATA_CFG_SATAGC_ASSEL_32K 0x2 >=20 > +#define V_SATA_CFG_SATAGC_ASSEL_64K 0x3 >=20 > +#define V_SATA_CFG_SATAGC_ASSEL_128K 0x4 >=20 > +#define V_SATA_CFG_SATAGC_ASSEL_256K 0x5 >=20 > +#define V_SATA_CFG_SATAGC_ASSEL_512K 0x6 >=20 > + >=20 > +#endif >=20 > diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/SerialIoR= egs.h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/SerialIoRegs.h > new file mode 100644 > index 0000000000..9864dd872d > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/SerialIoRegs.h > @@ -0,0 +1,47 @@ > +/** @file >=20 > + Register names for Serial IO Controllers >=20 > + >=20 > + Conventions: >=20 > + >=20 > + - Register definition format: >=20 > + > Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterS > pace_RegisterName >=20 > + - Prefix: >=20 > + Definitions beginning with "R_" are registers >=20 > + Definitions beginning with "B_" are bits within registers >=20 > + Definitions beginning with "V_" are meaningful values within the bit= s >=20 > + Definitions beginning with "S_" are register size >=20 > + Definitions beginning with "N_" are the bit position >=20 > + - [GenerationName]: >=20 > + Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc= .). >=20 > + Register name without GenerationName applies to all generations. >=20 > + - [ComponentName]: >=20 > + This field indicates the component name that the register belongs to= (e.g. > PCH, SA etc.) >=20 > + Register name without ComponentName applies to all components. >=20 > + Register that is specific to -LP denoted by "_PCH_LP_" in component > name. >=20 > + - SubsystemName: >=20 > + This field indicates the subsystem name of the component that the > register belongs to >=20 > + (e.g. PCIE, USB, SATA, GPIO, PMC etc.). >=20 > + - RegisterSpace: >=20 > + MEM - MMIO space register of subsystem. >=20 > + IO - IO space register of subsystem. >=20 > + PCR - Private configuration register of subsystem. >=20 > + CFG - PCI configuration space register of subsystem. >=20 > + - RegisterName: >=20 > + Full register name. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _SERIAL_IO_REGS_H_ >=20 > +#define _SERIAL_IO_REGS_H_ >=20 > + >=20 > +// >=20 > +// Serial IO Controllers PCI Configuration Registers >=20 > +// registers accessed using PciD21FxRegBase + offset >=20 > +// >=20 > +#define R_SERIAL_IO_CFG_BAR0_LOW 0x10 >=20 > +#define R_SERIAL_IO_CFG_BAR0_HIGH 0x14 >=20 > + >=20 > +#define R_SERIAL_IO_CFG_PME_CTRL_STS 0x84 >=20 > + >=20 > +#endif //_SERIAL_IO_REGS_H_ >=20 > diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/UsbRegs.h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/UsbRegs.h > new file mode 100644 > index 0000000000..ea832873bf > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/UsbRegs.h > @@ -0,0 +1,51 @@ > +/** @file >=20 > + Register names for USB Host and device controller >=20 > + >=20 > + Conventions: >=20 > + >=20 > + - Register definition format: >=20 > + > Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterS > pace_RegisterName >=20 > + - Prefix: >=20 > + Definitions beginning with "R_" are registers >=20 > + Definitions beginning with "B_" are bits within registers >=20 > + Definitions beginning with "V_" are meaningful values within the bit= s >=20 > + Definitions beginning with "S_" are register size >=20 > + Definitions beginning with "N_" are the bit position >=20 > + - [GenerationName]: >=20 > + Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc= .). >=20 > + Register name without GenerationName applies to all generations. >=20 > + - [ComponentName]: >=20 > + This field indicates the component name that the register belongs to= (e.g. > PCH, SA etc.) >=20 > + Register name without ComponentName applies to all components. >=20 > + Register that is specific to -LP denoted by "_PCH_LP_" in component > name. >=20 > + - SubsystemName: >=20 > + This field indicates the subsystem name of the component that the > register belongs to >=20 > + (e.g. PCIE, USB, SATA, GPIO, PMC etc.). >=20 > + - RegisterSpace: >=20 > + MEM - MMIO space register of subsystem. >=20 > + IO - IO space register of subsystem. >=20 > + PCR - Private configuration register of subsystem. >=20 > + CFG - PCI configuration space register of subsystem. >=20 > + - RegisterName: >=20 > + Full register name. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _USB_REGS_H_ >=20 > +#define _USB_REGS_H_ >=20 > + >=20 > +// >=20 > +// XHCI PCI Config Space registers >=20 > +// >=20 > +#define R_XHCI_CFG_PWR_CNTL_STS 0x74 >=20 > +#define B_XHCI_CFG_PWR_CNTL_STS_PWR_STS (BIT1 | BIT0) >=20 > +#define V_XHCI_CFG_PWR_CNTL_STS_PWR_STS_D3 (BIT1 | BIT0) >=20 > + >=20 > +// >=20 > +// xDCI (OTG) MMIO registers >=20 > +// >=20 > +#define R_XDCI_MEM_GCTL 0xC110 ///< Xdci Global C= trl >=20 > + >=20 > +#endif // _USB_REGS_H_ >=20 > + >=20 > diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/SerialIoDevices.h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/SerialIoDevices.h > new file mode 100644 > index 0000000000..e2e1cf2ad2 > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/SerialIoDevices.h > @@ -0,0 +1,213 @@ > +/** @file >=20 > + Serial IO policy >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _SERIAL_IO_DEVICES_H_ >=20 > +#define _SERIAL_IO_DEVICES_H_ >=20 > + >=20 > +#include >=20 > +#include >=20 > + >=20 > +#pragma pack (push,1) >=20 > + >=20 > +/** >=20 > + Available working modes for SerialIo SPI Host Controller >=20 > + >=20 > + 0: SerialIoSpiDisabled; >=20 > + - Device is placed in D3 >=20 > + - Gpio configuration is skipped >=20 > + - PSF: >=20 > + !important! If given device is Function 0 and other higher fun= ctions on > given device >=20 > + are enabled, PSF disabling is skipped. PSF default= will remain and > device PCI CFG Space will still be visible. >=20 > + This is needed to allow PCI enumerator access func= tions above 0 > in a multifunction device. >=20 > + 1: SerialIoSpiPci; >=20 > + - Gpio pin configuration in native mode for each assigned pin >=20 > + - Device will be enabled in PSF >=20 > + - Only BAR0 will be enabled >=20 > + 2: SerialIoSpiHidden; >=20 > + - Gpio pin configuration in native mode for each assigned pin >=20 > + - Device disabled in the PSF >=20 > + - Both BARs are enabled, BAR1 becomes devices Pci Config Space >=20 > + - BAR0 assigned from the global PCH reserved memory range, > reported as motherboard resource by SIRC >=20 > + @note >=20 > + If this controller is located at function 0 and it's mode is = set to hidden it > will not be visible in the PCI space. >=20 > +**/ >=20 > +typedef enum { >=20 > + SerialIoSpiDisabled, >=20 > + SerialIoSpiPci, >=20 > + SerialIoSpiHidden >=20 > +} SERIAL_IO_SPI_MODE; >=20 > + >=20 > +/** >=20 > + Used to set Inactive/Idle polarity of Spi Chip Select >=20 > +**/ >=20 > +typedef enum { >=20 > + SerialIoSpiCsActiveLow =3D 0, >=20 > + SerialIoSpiCsActiveHigh =3D 1 >=20 > +} SERIAL_IO_CS_POLARITY; >=20 > + >=20 > +/** >=20 > + The SERIAL_IO_SPI_CONFIG provides the configurations to set the Serial > IO SPI controller >=20 > +**/ >=20 > +typedef struct { >=20 > + UINT8 Mode; ///< SerialIoS= piPci see > SERIAL_IO_SPI_MODE >=20 > + UINT8 DefaultCsOutput; ///< 0 =3D CS0= CS1, CS2, CS3. > Default CS used by the SPI HC >=20 > + UINT8 CsPolarity[PCH_MAX_SERIALIO_SPI_CHIP_SELECTS]; ///< Selects > SPI ChipSelect signal polarity, 0 =3D low 1 =3D High >=20 > + UINT8 CsEnable[PCH_MAX_SERIALIO_SPI_CHIP_SELECTS]; ///< 0 =3D > Enable 1 =3D Disable. Based on this setting GPIO for given SPIx CSx w= ill be > configured in Native mode >=20 > + UINT8 CsMode; ///< 0 =3D HW = Control 1 =3D SW > Control. Sets Chip Select Control mode Hardware or Software. >=20 > + UINT8 CsState; ///< 0 =3D CS = is set to low 1 =3D CS is > set to high >=20 > +} SERIAL_IO_SPI_CONFIG; >=20 > + >=20 > +/** >=20 > + Available working modes for SerialIo UART Host Controller >=20 > + >=20 > + 0: SerialIoUartDisabled; >=20 > + - Device is placed in D3 >=20 > + - Gpio configuration is skipped >=20 > + - PSF: >=20 > + !important! If given device is Function 0 and other higher fun= ctions on > given device >=20 > + are enabled, PSF disabling is skipped. PSF default= will remain and > device PCI CFG Space will still be visible. >=20 > + This is needed to allow PCI enumerator access func= tions above 0 > in a multifunction device. >=20 > + 1: SerialIoUartPci; >=20 > + - Designated for Serial IO UART OS driver usage >=20 > + - Gpio pin configuration in native mode for each assigned pin >=20 > + - Device will be enabled in PSF >=20 > + - Only BAR0 will be enabled >=20 > + 2: SerialIoUartHidden; >=20 > + - Designated for BIOS and/or DBG2 OS kernel debug >=20 > + - Gpio pin configuration in native mode for each assigned pin >=20 > + - Device disabled in the PSF >=20 > + - Both BARs are enabled, BAR1 becomes devices Pci Config Space >=20 > + - BAR0 assigned from the global PCH reserved memory range, > reported as motherboard resource by SIRC >=20 > + @note >=20 > + If this controller is located at function 0 and it's mode is = set to hidden it > will not be visible in the PCI space. >=20 > + 3: SerialIoUartCom; >=20 > + - Designated for 16550/PNP0501 compatible COM device >=20 > + - Gpio pin configuration in native mode for each assigned pin >=20 > + - Device disabled in the PSF >=20 > + - Both BARs are enabled, BAR1 becomes devices Pci Config Space >=20 > + - BAR0 assigned from the global PCH reserved memory range, > reported as motherboard resource by SIRC >=20 > + 4: SerialIoUartSkipInit; >=20 > + - Gpio configuration is skipped >=20 > + - PSF configuration is skipped >=20 > + - BAR assignemnt is skipped >=20 > + - D-satate setting is skipped >=20 > + >=20 > +**/ >=20 > +typedef enum { >=20 > + SerialIoUartDisabled, >=20 > + SerialIoUartPci, >=20 > + SerialIoUartHidden, >=20 > + SerialIoUartCom, >=20 > + SerialIoUartSkipInit >=20 > +} SERIAL_IO_UART_MODE; >=20 > + >=20 > +/** >=20 > + UART Settings >=20 > +**/ >=20 > +typedef struct { >=20 > + UINT32 BaudRate; ///< 115200 Max 6000000 MdePkg.dec > PcdUartDefaultBaudRate >=20 > + UINT8 Parity; ///< 1 - No Parity see EFI_PARITY_TYP= E > MdePkg.dec PcdUartDefaultParity >=20 > + UINT8 DataBits; ///< 8 MdePkg.dec PcdUartDefaultDataBi= ts >=20 > + UINT8 StopBits; ///< 1 - One Stop Bit see > EFI_STOP_BITS_TYPE MdePkg.dec PcdUartDefaultStopBits >=20 > + UINT8 AutoFlow; ///< FALSE IntelFrameworkModulePkg.ds= c > PcdIsaBusSerialUseHalfHandshake >=20 > +} SERIAL_IO_UART_ATTRIBUTES; >=20 > + >=20 > +/** >=20 > + UART signals pin muxing settings. If signal can be enable only on a si= ngle > pin >=20 > + then this parameter is ignored by RC. Refer to > GPIO_*_MUXING_SERIALIO_UARTx_* in GpioPins*.h >=20 > + for supported settings on a given platform >=20 > +**/ >=20 > +typedef struct { >=20 > + UINT32 Rx; ///< RXD Pin mux configuration. Refer to > GPIO_*_MUXING_SERIALIO_UARTx_RXD_* >=20 > + UINT32 Tx; ///< TXD Pin mux configuration. Refer to > GPIO_*_MUXING_SERIALIO_UARTx_TXD_* >=20 > + UINT32 Rts; ///< RTS Pin mux configuration. Refer to > GPIO_*_MUXING_SERIALIO_UARTx_RTS_* >=20 > + UINT32 Cts; ///< CTS Pin mux configuration. Refer to > GPIO_*_MUXING_SERIALIO_UARTx_CTS_* >=20 > +} UART_PIN_MUX; >=20 > + >=20 > +/** >=20 > + Serial IO UART Controller Configuration >=20 > +**/ >=20 > +typedef struct { >=20 > + SERIAL_IO_UART_ATTRIBUTES Attributes; ///< see > SERIAL_IO_UART_ATTRIBUTES >=20 > + UART_PIN_MUX PinMux; ///< UART pin mux configuration >=20 > + UINT8 Mode; ///< SerialIoUartPci s= ee > SERIAL_IO_UART_MODE >=20 > + UINT8 DBG2; ///< FALSE If TRUE add= s UART to > DBG2 table and overrides UartPg to SerialIoUartPgDisabled >=20 > + UINT8 PowerGating; ///< SerialIoUartPgAuto Applies > to Hidden/COM/SkipInit see SERIAL_IO_UART_PG >=20 > + UINT8 DmaEnable; ///< TRUE Applies to > SerialIoUartPci only. Informs OS driver to use DMA, if false it will run = in PIO > mode >=20 > +} SERIAL_IO_UART_CONFIG; >=20 > + >=20 > +typedef enum { >=20 > + SerialIoUartPgDisabled, ///< No _PS0/_PS3 support, device left in D0, > after initialization >=20 > +/** >=20 > + In mode: SerialIoUartCom; >=20 > + _PS0/_PS3 that supports getting device out of reset >=20 > + In mode: SerialIoUartPci >=20 > + Keeps UART in D0 and assigns Fixed MMIO for SEC/PEI usage onl= y >=20 > +**/ >=20 > + SerialIoUartPgEnabled, >=20 > + SerialIoUartPgAuto ///< _PS0 and _PS3, detection through ACPI if > device was initialized prior to first PG. If it was used (DBG2) PG is dis= abled, >=20 > +} SERIAL_IO_UART_PG; >=20 > + >=20 > +/** >=20 > + Available working modes for SerialIo I2C Host Controller >=20 > + >=20 > + 0: SerialIoI2cDisabled; >=20 > + - Device is placed in D3 >=20 > + - Gpio configuration is skipped >=20 > + - PSF: >=20 > + !important! If given device is Function 0 and other higher fun= ctions on > given device >=20 > + are enabled, PSF disabling is skipped. PSF default= will remain and > device PCI CFG Space will still be visible. >=20 > + This is needed to allow PCI enumerator access func= tions above 0 > in a multifunction device. >=20 > + 1: SerialIoI2cPci; >=20 > + - Gpio pin configuration in native mode for each assigned pin >=20 > + - Device will be enabled in PSF >=20 > + - Only BAR0 will be enabled >=20 > + 2: SerialIoI2cHidden; >=20 > + - Gpio pin configuration in native mode for each assigned pin >=20 > + - Device disabled in the PSF >=20 > + - Both BARs are enabled, BAR1 becomes devices Pci Config Space >=20 > + - BAR0 assigned from the global PCH reserved memory range, > reported as motherboard resource by SIRC >=20 > + @note >=20 > + If this controller is located at function 0 and it's mode is = set to hidden it > will not be visible in the PCI space. >=20 > +**/ >=20 > +typedef enum { >=20 > + SerialIoI2cDisabled, >=20 > + SerialIoI2cPci, >=20 > + SerialIoI2cHidden >=20 > +} SERIAL_IO_I2C_MODE; >=20 > + >=20 > +/** >=20 > + I2C signals pin muxing settings. If signal can be enable only on a sin= gle pin >=20 > + then this parameter is ignored by RC. Refer to > GPIO_*_MUXING_SERIALIO_I2Cx_* in GpioPins*.h >=20 > + for supported settings on a given platform >=20 > +**/ >=20 > +typedef struct { >=20 > + UINT32 Sda; ///< SDA Pin mux configuration. Refer to > GPIO_*_MUXING_SERIALIO_I2Cx_SDA_* >=20 > + UINT32 Scl; ///< SCL Pin mux configuration. Refer to > GPIO_*_MUXING_SERIALIO_I2Cx_SCL_* >=20 > +} I2C_PIN_MUX; >=20 > + >=20 > +/** >=20 > + Serial IO I2C Controller Configuration >=20 > +**/ >=20 > +typedef struct { >=20 > + UINT8 Mode; /// SerialIoI2cPci see SERIAL_IO_I2C_= MODE >=20 > + /** >=20 > + I2C Pads Internal Termination. >=20 > + For more information please see Platform Design Guide. >=20 > + Supported values (check GPIO_ELECTRICAL_CONFIG for reference): >=20 > + GpioTermNone: No termination, >=20 > + GpioTermWpu1K: 1kOhm weak pull-up, >=20 > + GpioTermWpu5K: 5kOhm weak pull-up, >=20 > + GpioTermWpu20K: 20kOhm weak pull-up >=20 > + **/ >=20 > + UINT8 PadTermination; >=20 > + UINT8 Reserved[2]; >=20 > + I2C_PIN_MUX PinMux; ///< I2C pin mux configuration >=20 > +} SERIAL_IO_I2C_CONFIG; >=20 > + >=20 > +#pragma pack (pop) >=20 > + >=20 > +#endif // _SERIAL_IO_DEVICES_H_ >=20 > diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/SiConfigHob.h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/SiConfigHob.h > new file mode 100644 > index 0000000000..191bd815a1 > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/SiConfigHob.h > @@ -0,0 +1,17 @@ > +/** @file >=20 > + Silicon Config HOB is used for gathering platform >=20 > + related Intel silicon information and config setting. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _SI_CONFIG_HOB_H_ >=20 > +#define _SI_CONFIG_HOB_H_ >=20 > + >=20 > +#include >=20 > + >=20 > +extern EFI_GUID gSiConfigHobGuid; >=20 > + >=20 > +// Rename SI_CONFIG_HOB into SI_CONFIG_HOB_DATA for it does not > follow HOB structure. >=20 > +typedef CONST SI_CONFIG SI_CONFIG_HOB_DATA; >=20 > +#endif >=20 > diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/SiPolicyStruct.h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/SiPolicyStruct.h > new file mode 100644 > index 0000000000..7b646d8972 > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/SiPolicyStruct.h > @@ -0,0 +1,64 @@ > +/** @file >=20 > + Intel reference code configuration policies. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _SI_POLICY_STRUCT_H_ >=20 > +#define _SI_POLICY_STRUCT_H_ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +/** >=20 > + Silicon Policy revision number >=20 > + Any change to this structure will result in an update in the revision = number >=20 > + >=20 > + This member specifies the revision of the Silicon Policy. This field i= s used to > indicate change >=20 > + to the policy structure. >=20 > + >=20 > + Revision 1: >=20 > + - Initial version. >=20 > +**/ >=20 > +#define SI_POLICY_REVISION 1 >=20 > + >=20 > +/** >=20 > + Silicon pre-memory Policy revision number >=20 > + Any change to this structure will result in an update in the revision = number >=20 > + >=20 > + Revision 1: >=20 > + - Initial version. >=20 > +**/ >=20 > +#define SI_PREMEM_POLICY_REVISION 1 >=20 > + >=20 > + >=20 > +/** >=20 > + SI Policy PPI in Pre-Mem\n >=20 > + All SI config block change history will be listed here\n\n >=20 > + >=20 > + - Revision 1: >=20 > + - Initial version.\n >=20 > +**/ >=20 > +struct _SI_PREMEM_POLICY_STRUCT { >=20 > + CONFIG_BLOCK_TABLE_HEADER TableHeader; ///< Config Block Table > Header >=20 > +/* >=20 > + Individual Config Block Structures are added here in memory as part of > AddConfigBlock() >=20 > +*/ >=20 > +}; >=20 > + >=20 > +/** >=20 > + SI Policy PPI\n >=20 > + All SI config block change history will be listed here\n\n >=20 > + >=20 > + - Revision 1: >=20 > + - Initial version.\n >=20 > +**/ >=20 > +struct _SI_POLICY_STRUCT { >=20 > + CONFIG_BLOCK_TABLE_HEADER TableHeader; ///< Config Block Table > Header >=20 > +/* >=20 > + Individual Config Block Structures are added here in memory as part of > AddConfigBlock() >=20 > +*/ >=20 > +}; >=20 > + >=20 > +#endif >=20 > -- > 2.24.0.windows.2