From: "Nate DeSimone" <nathaniel.l.desimone@intel.com>
To: "Luo, Heng" <heng.luo@intel.com>,
"devel@edk2.groups.io" <devel@edk2.groups.io>
Cc: "Chaganty, Rangasai V" <rangasai.v.chaganty@intel.com>
Subject: Re: [PATCH 01/40] TigerlakeSiliconPkg: Add package and Include/ConfigBlock headers
Date: Thu, 4 Feb 2021 03:51:19 +0000 [thread overview]
Message-ID: <BN6PR1101MB21471BA56D09858C79BE5E78CDB39@BN6PR1101MB2147.namprd11.prod.outlook.com> (raw)
In-Reply-To: <20210201013657.1833-1-heng.luo@intel.com>
Hi Heng,
CpuPcieConfigGen3.h is only used on Rocket Lake boards for backwards socket compatibility with Comet Lake. It is not needed for Tiger Lake. Please remove it. Also, there are some fields missing from CPU_PCIE_CONFIG, please see inline.
Thanks,
Nate
> -----Original Message-----
> From: Luo, Heng <heng.luo@intel.com>
> Sent: Sunday, January 31, 2021 5:36 PM
> To: devel@edk2.groups.io
> Cc: Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Desimone,
> Nathaniel L <nathaniel.l.desimone@intel.com>
> Subject: [PATCH 01/40] TigerlakeSiliconPkg: Add package and
> Include/ConfigBlock headers
>
> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171
>
> Create the TigerlakeSiliconPkg to provide an initial package for
> silicon initialization code for Tiger Lake (TGL) products.
>
> * Major areas of functionality are categorized into CPU, IpBlock, Fru,
> Platform Controller Hub (PCH), and System Agent subdirectories.
> * Common libraries and headers are kept at the root of the package.
>
> Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
> Signed-off-by: Heng Luo <heng.luo@intel.com>
> ---
> Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Cnvi/CnviConfig.h
> | 67 ++++++++++++++++++++++++++++++++++++++++++++++++++
>
> Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/CpuDmi/CpuDmiPreM
> emConfig.h | 86
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++
>
> Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/CpuPcieRp/Gen3/CpuP
> cieConfigGen3.h | 347
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++
>
> Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/CpuPcieRp/Gen4/CpuP
> cieConfig.h | 490
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++
> Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Dci/DciConfig.h
> | 72 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
> Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Espi/EspiConfig.h
> | 61 ++++++++++++++++++++++++++++++++++++++++++++++
> Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Fivr/FivrConfig.h
> | 170
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> +++++++++++
> Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Gbe/GbeConfig.h
> | 33 +++++++++++++++++++++++++
> Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Gna/GnaConfig.h
> | 31 +++++++++++++++++++++++
> Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Gpio/GpioDevConfig.h
> | 37 ++++++++++++++++++++++++++++
>
> Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Graphics/Gen12/Graph
> icsConfig.h | 211
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> +++++++++++++++++++++++++++++++++++++++++
> Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Hda/HdAudioConfig.h
> | 227
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> +++++++++++++++++++++++++++++++++++++++++++++++++++++
>
> Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/HostBridge/HostBridge
> Config.h | 62
> ++++++++++++++++++++++++++++++++++++++++++++++
>
> Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/HybridGraphics/Hybrid
> GraphicsConfig.h | 66
> +++++++++++++++++++++++++++++++++++++++++++++++++
>
> Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/HybridStorage/HybridS
> torageConfig.h | 36 +++++++++++++++++++++++++++
> Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Ieh/IehConfig.h
> | 34 ++++++++++++++++++++++++++
> Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Ish/IshConfig.h
> | 134
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++
> Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Itss/InterruptConfig.h
> | 58 ++++++++++++++++++++++++++++++++++++++++++++
> Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Itss/IoApicConfig.h
> | 60 +++++++++++++++++++++++++++++++++++++++++++++
> Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Me/MePeiConfig.h
> | 117
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> +++++++++++++++++++++++++++++
>
> Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Memory/Ver2/Memor
> yConfig.h | 478
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> +++++++
>
> Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Overclocking/Overcloc
> kingConfig.h | 236
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++
> Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/P2sb/P2sbConfig.h
> | 34 ++++++++++++++++++++++++++
>
> Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/PchDmi/PchDmiConfig.
> h | 44 +++++++++++++++++++++++++++++++++
>
> Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/PcieRp/PchPcieRp/Pch
> PcieRpConfig.h | 368
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> +++++++++++++++++++++++++++++++++++++++++
> Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/PcieRp/PcieConfig.h
> | 213
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++
> Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Pmc/AdrConfig.h
> | 86
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++
> Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Pmc/PmConfig.h
> | 391
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> +
> Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Psf/PsfConfig.h
> | 32 ++++++++++++++++++++++++
> Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Rst/RstConfig.h
> | 82
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> +++
> Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Rtc/RtcConfig.h
> | 38 +++++++++++++++++++++++++++++
> Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Sata/SataConfig.h
> | 168
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> +++++++++
> Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Scs/ScsConfig.h
> | 139
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++
>
> Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/SerialIo/SerialIoConfig.
> h | 32 ++++++++++++++++++++++++
> Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/SiConfig.h
> | 152
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> +++++++++++++++++++++++++++++++++++++++++++++++++++++++
> Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/SiPreMemConfig.h
> | 67 ++++++++++++++++++++++++++++++++++++++++++++++++++
> Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Smbus/SmbusConfig.h
> | 50 ++++++++++++++++++++++++++++++++++++++
> Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Spi/SpiConfig.h
> | 43 ++++++++++++++++++++++++++++++++
> Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Tcss/TcssPeiConfig.h
> | 145
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++
> Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Thc/ThcConfig.h
> | 73
> +++++++++++++++++++++++++++++++++++++++++++++++++++++++
>
> Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Thermal/ThermalConfi
> g.h | 153
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++
>
> Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/TraceHub/TraceHubCo
> nfig.h | 101
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> +++++++++++++++++
> Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Usb/Usb2PhyConfig.h
> | 81
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> +++
> Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Usb/Usb3HsioConfig.h
> | 138
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> +++++++++++++++++++++++++++++++++++++++++++++
> Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Usb/UsbConfig.h
> | 149
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> +++++++++++++++++++++++++++++++++++++++++++++++++++++
>
> Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/VoltageRegulator/Cpu
> PowerMgmtVrConfig.h | 114
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> +++++++++++++++++++++++++++
> Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Vtd/VtdConfig.h
> | 64 ++++++++++++++++++++++++++++++++++++++++++++++++
>
> Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Wdt/WatchDogConfig.
> h | 31 +++++++++++++++++++++++
> Silicon/Intel/TigerlakeSiliconPkg/SiPkg.dec | 1208
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> +++++++++++++++++++++++++++
> 49 files changed, 7309 insertions(+)
>
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Cnvi/CnviConfig.h
> b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Cnvi/CnviConfig.h
> new file mode 100644
> index 0000000000..de1f4159f0
> --- /dev/null
> +++
> b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Cnvi/CnviConfig.h
> @@ -0,0 +1,67 @@
> +/** @file
>
> + CNVi policy
>
> +
>
> + Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +**/
>
> +#ifndef _CNVI_CONFIG_H_
>
> +#define _CNVI_CONFIG_H_
>
> +
>
> +#define CNVI_CONFIG_REVISION 1
>
> +extern EFI_GUID gCnviConfigGuid;
>
> +
>
> +#pragma pack (push,1)
>
> +
>
> +/**
>
> + CNVi Mode options
>
> +**/
>
> +typedef enum {
>
> + CnviModeDisabled = 0,
>
> + CnviModeAuto
>
> +} CNVI_MODE;
>
> +
>
> +
>
> +/**
>
> + CNVi signals pin muxing settings. If signal can be enable only on a single pin
>
> + then this parameter is ignored by RC. Refer to GPIO_*_MUXING_CNVI_*
> in GpioPins*.h
>
> + for supported settings on a given platform
>
> +**/
>
> +typedef struct {
>
> + UINT32 RfReset; ///< RF_RESET# Pin mux configuration. Refer to
> GPIO_*_MUXING_CNVI_RF_RESET_*
>
> + UINT32 Clkreq; ///< CLKREQ Pin mux configuration. Refer to
> GPIO_*_MUXING_CNVI_*_CLKREQ_*
>
> +} CNVI_PIN_MUX;
>
> +
>
> +/**
>
> + The CNVI_CONFIG block describes the expected configuration of the CNVi
> IP.
>
> +
>
> + <b>Revision 1</b>:
>
> + - Initial version.
>
> +**/
>
> +typedef struct {
>
> + CONFIG_BLOCK_HEADER Header; ///< Config Block Header
>
> + /**
>
> + This option allows for automatic detection of Connectivity Solution.
>
> + Auto Detection assumes that CNVi will be enabled when available;
>
> + Disable allows for disabling CNVi.
>
> + CnviModeDisabled = Disabled,
>
> + <b>CnviModeAuto = Auto Detection</b>
>
> + **/
>
> + UINT32 Mode : 1;
>
> + UINT32 BtCore : 1; ///< The option to turn ON or OFF the BT Core.
> 0: Disabled, <b>1: Enabled</b>
>
> + /**
>
> + The option to enable or disable BT Audio Offload.
>
> + <b>0: Disabled</b>, 1: Enabled
>
> + @note This feature only support with Intel(R) Wireless-AX 22560
>
> + **/
>
> + UINT32 BtAudioOffload : 1;
>
> + UINT32 RsvdBits : 29;
>
> + /**
>
> + CNVi PinMux Configuration
>
> + RESET#/CLKREQ to CRF, can have two alternative mappings, depending on
> board routing requirements.
>
> + **/
>
> + CNVI_PIN_MUX PinMux;
>
> +} CNVI_CONFIG;
>
> +
>
> +#pragma pack (pop)
>
> +
>
> +#endif // _CNVI_CONFIG_H_
>
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/CpuDmi/CpuDmiPre
> MemConfig.h
> b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/CpuDmi/CpuDmiPre
> MemConfig.h
> new file mode 100644
> index 0000000000..527febb0a4
> --- /dev/null
> +++
> b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/CpuDmi/CpuDmiPre
> MemConfig.h
> @@ -0,0 +1,86 @@
> +/** @file
>
> + DMI policy
>
> +
>
> + Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +**/
>
> +#ifndef _CPU_DMI_PREMEM_CONFIG_H_
>
> +#define _CPU_DMI_PREMEM_CONFIG_H_
>
> +
>
> +#include <ConfigBlock.h>
>
> +#include <Register/SaRegsHostBridge.h>
>
> +
>
> +#define DMI_CONFIG_REVISION 1
>
> +
>
> +#define CPU_DMI_HWEQ_COEFFS_MAX 8
>
> +
>
> +#pragma pack (push,1)
>
> +///
>
> +/// The values before AutoConfig match the setting of PCI Express Base
> Specification 1.1, please be careful for adding new feature
>
> +///
>
> +typedef enum {
>
> + DmiAspmDisabled,
>
> + DmiAspmL0s,
>
> + DmiAspmL1,
>
> + DmiAspmL0sL1,
>
> + DmiAspmAutoConfig,
>
> + DmiAspmMax
>
> +} DMI_ASPM;
>
> +
>
> +
>
> +/**
>
> + The CPU_DMI_CONFIG block describes the expected configuration of the
> CPU for DMI.
>
> + <b>Revision 1</b>:
>
> + - Initial version.
>
> +**/
>
> +typedef struct {
>
> + CONFIG_BLOCK_HEADER Header; ///< Config Block Header
>
> +
>
> +/**
>
> + - <b>Auto</b> (0x0) : Maximum possible link speed (Default)
>
> + - Gen1 (0x1) : Limit Link to Gen1 Speed
>
> + - Gen2 (0x2) : Limit Link to Gen2 Speed CpuDmiPreMemConfig
>
> + - Gen3 (0x3) : Limit Link to Gen3 Speed
>
> + **/
>
> + UINT8 DmiMaxLinkSpeed;
>
> + /**
>
> + <b>(Test)</b> DMI Equalization Phase 2 Enable Control
>
> + - Disabled (0x0) : Disable phase 2
>
> + - Enabled (0x1) : Enable phase 2
>
> + - <b>Auto</b> (0x2) : Use the current default method (Default)
>
> + **/
>
> + UINT8 DmiGen3EqPh2Enable;
>
> + /**
>
> + <b>(Test)</b> Selects the method for performing Phase3 of Gen3
> Equalization on DMI
>
> + - <b>Auto</b> (0x0) : Use the current default method (Default)
>
> + - HwEq (0x1) : Use Adaptive Hardware Equalization
>
> + - SwEq (0x2) : Use Adaptive Software Equalization (Implemented in
> BIOS Reference Code)
>
> + - Static (0x3) : Use the Static EQs provided in DmiGen3EndPointPreset
> array for Phase1 AND Phase3 (Instead of just Phase1)
>
> + - Disabled (0x4) : Bypass Equalization Phase 3
>
> + **/
>
> + UINT8 DmiGen3EqPh3Method;
>
> + /**
>
> + <b>(Test)</b> Program DMI Gen3 EQ Phase1 Static Presets
>
> + - Disabled (0x0) : Disable EQ Phase1 Static Presets Programming
>
> + - <b>Enabled</b> (0x1) : Enable EQ Phase1 Static Presets Programming
> (Default)
>
> + **/
>
> + UINT8 DmiGen3ProgramStaticEq;
>
> + UINT8 DmiDeEmphasis; ///< DeEmphasis control
> for DMI (-6 dB and -3.5 dB are the options)
>
> + UINT8 DmiAspm;
>
> + UINT8 DmiAspmCtrl; ///< ASPM configuration on
> the CPU side of the DMI/OPI Link. Default is <b>DmiAspmAutoConfig</b>
>
> + UINT8 DmiAspmL1ExitLatency; ///< ASPM
> configuration on the CPU side of the DMI/OPI Link. Default is
> <b>DmiAspmAutoConfig</b>
>
> + UINT8 DmiGen3RootPortPreset[SA_DMI_MAX_LANE]; ///<
> Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is
> default for each lane
>
> + UINT8 DmiGen3EndPointPreset[SA_DMI_MAX_LANE]; ///<
> Used for programming DMI Gen3 preset values per lane. Range: 0-9, 7 is
> default for each lane
>
> + UINT8 DmiGen3EndPointHint[SA_DMI_MAX_LANE]; ///< Hint
> value per lane for the DMI Gen3 End Point. Range: 0-6, 2 is default for each
> lane
>
> +
>
> + /**
>
> + DMI Gen3 RxCTLEp per-Bundle control. The range of the setting is (0-15).
> This setting
>
> + has to be specified based upon platform design and must follow the
> guideline. Default is 12.
>
> + **/
>
> +
>
> + UINT8 DmiGen3RxCtlePeaking[SA_DMI_MAX_BUNDLE];
>
> +} CPU_DMI_PREMEM_CONFIG;
>
> +
>
> +#pragma pack (pop)
>
> +
>
> +#endif // _CPU_DMI_CONFIG_H_
>
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/CpuPcieRp/Gen3/Cp
> uPcieConfigGen3.h
> b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/CpuPcieRp/Gen3/Cp
> uPcieConfigGen3.h
> new file mode 100644
> index 0000000000..593e63b4f1
> --- /dev/null
> +++
> b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/CpuPcieRp/Gen3/Cp
> uPcieConfigGen3.h
> @@ -0,0 +1,347 @@
> +/** @file
>
> +Pcie root port policy
>
> +
>
> + Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +**/
>
> +
>
> +#ifndef _CPU_PCIE_CONFIG_GEN3_H_
>
> +#define _CPU_PCIE_CONFIG_GEN3_H_
>
> +
>
> +#include <Library/GpioLib.h>
>
> +#include <Library/CpuPcieInfoFruLib.h>
>
> +#include <PcieConfig.h>
>
> +#include <ConfigBlock.h>
>
> +#include <Register/SaRegsHostBridge.h>
>
> +
>
> +#pragma pack(push, 1)
>
> +
>
> +#define CPU_PCIE_PEI_PREMEM_CONFIG_GEN3_REVISION 1
>
> +
>
> +#define L0_SET BIT0
>
> +#define L1_SET BIT1
>
> +
>
> +
>
> +///
>
> +/// SA GPIO Data Structure
>
> +///
>
> +typedef struct {
>
> + GPIO_PAD GpioPad; ///< Offset 0: GPIO Pad
>
> + UINT8 Value; ///< Offset 4: GPIO Value
>
> + UINT8 Rsvd0[3]; ///< Offset 5: Reserved for 4 bytes alignment
>
> + UINT32 Active : 1; ///< Offset 8: 0=Active Low; 1=Active High
>
> + UINT32 RsvdBits0 : 31;
>
> +} SA_GPIO_INFO_PCIE;
>
> +
>
> +///
>
> +/// SA Board PEG GPIO Info
>
> +///
>
> +typedef struct {
>
> + SA_GPIO_INFO_PCIE SaPeg0ResetGpio; ///< Offset 0: PEG0 PERST#
> GPIO assigned, must be a PCH GPIO pin
>
> + SA_GPIO_INFO_PCIE SaPeg3ResetGpio; ///< Offset 12: PEG3 PERST#
> GPIO assigned, must be a PCH GPIO pin
>
> + BOOLEAN GpioSupport; ///< Offset 24: 1=Supported; 0=Not
> Supported
>
> + UINT8 Rsvd0[3]; ///< Offset 25: Reserved for 4 bytes alignment
>
> +} PEG_GPIO_DATA;
>
> +
>
> +/**
>
> +PCI Express and DMI controller configuration\n
>
> +@note <b>Optional.</b> These policies will be ignored if there is no PEG
> port present on board.
>
> +<b>Revision 1</b>:
>
> +- Initial version.
>
> +**/
>
> +typedef struct {
>
> + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27
> Config Block Header
>
> + /**
>
> + Offset 28:0 :
>
> + <b>(Test)</b> DMI Link Speed Control
>
> + - <b>Auto</b> (0x0) : Maximum possible link speed (Default)
>
> + - Gen1 (0x1) : Limit Link to Gen1 Speed
>
> + - Gen2 (0x2) : Limit Link to Gen2 Speed
>
> + - Gen3 (0x3) : Limit Link to Gen3 Speed
>
> + **/
>
> + UINT8 DmiMaxLinkSpeed;
>
> + /**
>
> + Offset 28:2 :
>
> + <b>(Test)</b> DMI Equalization Phase 2 Enable Control
>
> + - Disabled (0x0) : Disable phase 2
>
> + - Enabled (0x1) : Enable phase 2
>
> + - <b>Auto</b> (0x2) : Use the current default method (Default)
>
> + **/
>
> + UINT8 DmiGen3EqPh2Enable;
>
> + /**
>
> + Offset 28:4 :
>
> + <b>(Test)</b> Selects the method for performing Phase3 of Gen3
> Equalization on DMI
>
> + - <b>Auto</b> (0x0) : Use the current default method (Default)
>
> + - HwEq (0x1) : Use Adaptive Hardware Equalization
>
> + - SwEq (0x2) : Use Adaptive Software Equalization (Implemented in
> BIOS Reference Code)
>
> + - Static (0x3) : Use the Static EQs provided in DmiGen3EndPointPreset
> array for Phase1 AND Phase3 (Instead of just Phase1)
>
> + - Disabled (0x4) : Bypass Equalization Phase 3
>
> + **/
>
> + UINT8 DmiGen3EqPh3Method;
>
> + /**
>
> + Offset 28:7 :
>
> + <b>(Test)</b> Program DMI Gen3 EQ Phase1 Static Presets
>
> + - Disabled (0x0) : Disable EQ Phase1 Static Presets Programming
>
> + - <b>Enabled</b> (0x1) : Enable EQ Phase1 Static Presets Programming
> (Default)
>
> + **/
>
> + UINT8 DmiGen3ProgramStaticEq;
>
> +
>
> + /**
>
> + Offset 28:8 to 28:15 :
>
> + <b>(Test)</b> PEG Enable Control
>
> + - Disabled (0x0) : Disable PEG Port
>
> + - Enabled (0x1) : Enable PEG Port (If Silicon SKU permits it)
>
> + - <b>Auto</b> (0x2) : If an endpoint is present, enable the PEG Port,
> Disable otherwise (Default)
>
> + **/
>
> + UINT8 Peg0Enable; ///< Enable/Disable PEG 0:1:0 Root Port
>
> + UINT8 Peg1Enable; ///< <b>(Test)</b> Enable/Disable PEG
> 0:1:1 Root Port
>
> + UINT8 Peg2Enable; ///< <b>(Test)</b> Enable/Disable PEG
> 0:1:2 Root Port
>
> + UINT8 Peg3Enable; ///< <b>(Test)</b> Enable/Disable PEG
> 0:6:0 Root Port. Applicable on certain CNL- SKUs and newer silicon.
>
> +
>
> + /**
>
> + Offset 28:16 :
>
> + <b>(Test)</b> PCIe Link Speed Control
>
> + - <b>Auto</b> (0x0) : Maximum possible Link speed (Default)
>
> + - Gen1 (0x1) : Limit Link to Gen1 Speed
>
> + - Gen2 (0x2) : Limit Link to Gen2 Speed
>
> + - Gen3 (0x3) : Limit Link to Gen3 Speed
>
> + **/
>
> + UINT8 Peg0MaxLinkSpeed; ///< PCIe Link Speed Control for
> PEG 0:1:0 Root Port.
>
> + UINT8 Peg1MaxLinkSpeed; ///< <b>(Test)</b> PCIe Link
> Speed Control for PEG 0:1:1 Root Port.
>
> + UINT8 Peg2MaxLinkSpeed; ///< <b>(Test)</b> PCIe Link
> Speed Control for PEG 0:1:2 Root Port.
>
> + UINT8 Peg3MaxLinkSpeed; ///< <b>(Test)</b> PCIe Link
> Speed Control for PEG 0:6:0 Root Port. Applicable on certain CNL- SKUs and
> newer silicon.
>
> +
>
> + /**
>
> + Offset 32:0 :
>
> + <b>(Test)</b> PCIe Link Width Control
>
> + - <b>Auto</b> (0x0) : Maximum possible Link width (Default)
>
> + - X1 (0x1) : Limit Link to X1 Width
>
> + - X2 (0x2) : Limit Link to X2 Width
>
> + - X4 (0x3) : Limit Link to X4 Width
>
> + - X8 (0x4) : Limit Link to X8 Width
>
> + **/
>
> + UINT8 Peg0MaxLinkWidth; ///< PCIe Link Width Control for
> PEG 0:1:0 Root Port.
>
> + UINT8 Peg1MaxLinkWidth; ///< <b>(Test)</b> PCIe Link Width
> Control for PEG 0:1:1 Root Port.
>
> + UINT8 Peg2MaxLinkWidth; ///< <b>(Test)</b> PCIe Link Width
> Control for PEG 0:1:2 Root Port.
>
> + UINT8 Peg3MaxLinkWidth; ///< <b>(Test)</b> PCIe Link Width
> Control for PEG 0:6:0 Root Port. Applicable on certain CNL- SKUs and newer
> silicon.
>
> + /**
>
> + Offset 32:12 to 32:15 :
>
> + Power down unused lanes on the PEG Root Port.
>
> + - Disabled (0x0) : No power saving.
>
> + - <b>Auto</b> (0x1) : Bios will power down unused lanes based on the
> max possible link width
>
> + **/
>
> + UINT8 Peg0PowerDownUnusedLanes; ///< Power down
> unused lanes on the PEG 0:1:0 Root Port.
>
> + UINT8 Peg1PowerDownUnusedLanes; ///< Power down
> unused lanes on the PEG 0:1:1 Root Port.
>
> + UINT8 Peg2PowerDownUnusedLanes; ///< Power down
> unused lanes on the PEG 0:1:2 Root Port.
>
> + UINT8 Peg3PowerDownUnusedLanes; ///< Power down
> unused lanes on the PEG 0:6:0 Root Port. Applicable on certain CNL- SKUs
> and newer silicon.
>
> +
>
> + /**
>
> + Offset 32:16 to 32:23 :
>
> + <b>(Test)</b> PCIe Equalization Phase 2 Enable Control
>
> + - Disabled (0x0) : Disable phase 2
>
> + - Enabled (0x1) : Enable phase 2
>
> + - <b>Auto</b> (0x2) : Use the current default method (Default)
>
> + **/
>
> + UINT8 Peg0Gen3EqPh2Enable; ///< Phase2 EQ enable on the
> PEG 0:1:0 Root Port.
>
> + UINT8 Peg1Gen3EqPh2Enable; ///< <b>(Test)</b> Phase2 EQ
> enable on the PEG 0:1:1 Root Port.
>
> + UINT8 Peg2Gen3EqPh2Enable; ///< <b>(Test)</b> Phase2 EQ
> enable on the PEG 0:1:2 Root Port.
>
> + UINT8 Peg3Gen3EqPh2Enable; ///< <b>(Test)</b> Phase2 EQ
> enable on the PEG 0:6:0 Root Port. Applicable on certain CNL- SKUs and
> newer silicon.
>
> +
>
> + /**
>
> + Offset 36:0 to 36:11 :
>
> + <b>(Test)</b> Select the method for performing Phase3 of Gen3
> Equalization.
>
> + - <b>Auto</b> (0x0) : Use the current default method (Default)
>
> + - HwEq (0x1) : Use Adaptive Hardware Equalization
>
> + - SwEq (0x2) : Use Adaptive Software Equalization (Implemented in
> BIOS Reference Code)
>
> + - Static (0x3) : Use the Static EQs provided in PegGen3EndPointPreset
> array for Phase1 AND Phase3 (Instead of just Phase1)
>
> + - Disabled (0x4) : Bypass Equalization Phase 3
>
> + **/
>
> + UINT8 Peg0Gen3EqPh3Method; ///< Phase3 EQ method on
> the PEG 0:1:0 Root Port.
>
> + UINT8 Peg1Gen3EqPh3Method; ///< <b>(Test)</b> Phase3
> EQ method on the PEG 0:1:1 Root Port.
>
> + UINT8 Peg2Gen3EqPh3Method; ///< <b>(Test)</b> Phase3
> EQ method on the PEG 0:1:2 Root Port.
>
> + UINT8 Peg3Gen3EqPh3Method; ///< <b>(Test)</b> Phase3
> EQ method on the PEG 0:6:0 Root Port. Applicable on certain CNL- SKUs and
> newer silicon.
>
> + /**
>
> + Offset 36:12 :
>
> + <b>(Test)</b> Program PEG Gen3 EQ Phase1 Static Presets
>
> + - Disabled (0x0) : Disable EQ Phase1 Static Presets Programming
>
> + - <b>Enabled</b> (0x1) : Enable EQ Phase1 Static Presets Programming
> (Default)
>
> + **/
>
> + UINT8 PegGen3ProgramStaticEq;
>
> + /**
>
> + Offset 36:13 :
>
> + <b>(Test)</b> Always Attempt Gen3 Software Equalization
>
> +
>
> + When enabled, Gen3 Software Equalization will be executed every boot.
> When disabled, it will be only executed if the CPU
>
> + or EP is changed, otherwise it is skipped and the previous EQ value will be
> re-used.
>
> +
>
> + This setting will only have an effect if Software Equalization is enabled and
> OEM Platform Code implements
>
> + save/restore of the PegDataPtr data (see below). If PegDataPtr is not
> saved/restored RC forces this to be enabled.
>
> +
>
> + - <b>Disabled</b> (0x0) : Reuse EQ settings saved/restored from NVRAM
> whenever possible (Default)
>
> + - Enabled (0x1) : Re-test and generate new EQ values every boot, not
> recommended
>
> + **/
>
> + UINT8 Gen3SwEqAlwaysAttempt;
>
> + /**
>
> + Offset 36:14 to 36:16 :
>
> + <b>(Test)</b> Select number of TxEq presets to test in the PCIe/DMI
> Software Equalization Algorithm
>
> + - P7,P3,P5,P8 (0x0) : Test Presets 7, 3, 5, and 8
>
> + - P0-P9 (0x1) : Test Presets 0-9
>
> + - <b>Auto</b> (0x2) : Use the current default method (Default)
>
> + Auto will test Presets 7, 3, 5, and 8. It is possible for this default to change
> over time;
>
> + using "Auto" will ensure Reference Code always uses the latest default
> settings.
>
> + @warning Do not change from the default. Hard to detect issues are likely.
>
> + **/
>
> + UINT8 Gen3SwEqNumberOfPresets;
>
> + /**
>
> + Offset 36:17 to 36:18:
>
> + <b>(Test)</b> Offset 36 Enable use of the Voltage Offset and Centering
> Test in the PCIe Software Equalization Algorithm
>
> + - Disabled (0x0) : Disable VOC Test
>
> + - Enabled (0x1) : Enable VOC Test
>
> + - <b>Auto</b> (0x2) : Use the current default (Default)
>
> + **/
>
> + UINT8 Gen3SwEqEnableVocTest;
>
> + /**
>
> + Offset 36:19 :
>
> + Select when PCIe ASPM programming will happen in relation to the Oprom
>
> + - <b>Before</b> (0x0) : Do PCIe ASPM programming before Oprom.
> (Default)
>
> + - After (0x1) : Do PCIe ASPM programming after Oprom. This will
> require an SMI handler to save/restore ASPM settings.
>
> + **/
>
> + UINT8 InitPcieAspmAfterOprom;
>
> + /**
>
> + Offset 36:20 :
>
> + <b>(Test)</b> PCIe Rx Compliance Testing Mode
>
> + - <b>Disabled</b> (0x0) : Normal Operation - Disable PCIe Rx
> Compliance testing (Default)
>
> + - Enabled (0x1) : PCIe Rx Compliance Test Mode - PEG controller is in Rx
> Compliance Testing Mode; it should only be set when doing PCIe compliance
> testing
>
> + **/
>
> + UINT8 PegRxCemTestingMode;
>
> +
>
> + /**
>
> + Offset 36:21 to 36:24 :
>
> + <b>(Test)</b> PCIe Rx Compliance Loopback Lane
>
> +
>
> + When PegRxCemTestingMode is Enabled, the specificied Lane (0 - 15) will
> be
>
> + used for RxCEMLoopback.
>
> +
>
> + Default is Lane 0.
>
> + **/
>
> + UINT8 PegRxCemLoopbackLane;
>
> + /**
>
> + Offset 36:25 to 36:28 :
>
> + <b>(Test)</b> Generate PCIe BDAT Margin Table. Set this policy to enable
> the generation and addition of PCIe margin data to the BDAT table.
>
> + - <b>Disabled</b> (0x0) : Normal Operation - Disable PCIe BDAT
> margin data generation (Default)
>
> + - PortData (0x1) : Port Data - Generate PCIe BDAT margin data
>
> + **/
>
> + UINT8 PegGenerateBdatMarginTable;
>
> + /**
>
> + Offset 36:29 :
>
> + <b>(Test)</b> PCIe Non-Protocol Awareness for Rx Compliance Testing
>
> + - <b>Disabled</b> (0x0) : Normal Operation - Disable non-protocol
> awareness (Default)
>
> + - Enabled (0x1) : Non-Protocol Awareness Enabled - Enable non-
> protocol awareness for compliance testing
>
> + **/
>
> + UINT8 PegRxCemNonProtocolAwareness;
>
> + /**
>
> + Offset 36:30 :
>
> + <b>(Test)</b> PCIe Disable Spread Spectrum Clocking. This feature should
> be TRUE only for compliance testing
>
> + - <b>False</b> (0x0) : Normal Operation - SSC enabled
> (Default)
>
> + - True (0x1) : Disable SSC - Disable SSC for compliance
> testing
>
> + **/
>
> + UINT8 PegDisableSpreadSpectrumClocking;
>
> +
>
> + UINT8 DmiGen3RootPortPreset[SA_DMI_MAX_LANE_VER1];
> ///< Offset 40 Used for programming DMI Gen3 preset values per lane.
> Range: 0-9, 8 is default for each lane
>
> + UINT8 DmiGen3EndPointPreset[SA_DMI_MAX_LANE_VER1];
> ///< Offset 44 Used for programming DMI Gen3 preset values per lane.
> Range: 0-9, 7 is default for each lane
>
> + UINT8 DmiGen3EndPointHint[SA_DMI_MAX_LANE_VER1];
> ///< Offset 48 Hint value per lane for the DMI Gen3 End Point. Range: 0-6, 2 is
> default for each lane
>
> + /**
>
> + Offset 48/60 :
>
> + DMI Gen3 RxCTLEp per-Bundle control. The range of the setting is (0-15).
> This setting
>
> + has to be specified based upon platform design and must follow the
> guideline. Default is 12.
>
> + **/
>
> +
>
> + UINT8 DmiGen3RxCtlePeaking[SA_DMI_MAX_BUNDLE_VER1];
>
> +
>
> + UINT8 PegGen3RootPortPreset[SA_PEG_MAX_LANE_GEN3];
> ///< Offset 54 <b>(Test)</b> Used for programming PEG Gen3 preset values
> per lane. Range: 0-9, 8 is default for each lane
>
> + UINT8 PegGen3EndPointPreset[SA_PEG_MAX_LANE_GEN3];
> ///< Offset 70 <b>(Test)</b> Used for programming PEG Gen3 preset values
> per lane. Range: 0-9, 7 is default for each lane
>
> + UINT8 PegGen3EndPointHint[SA_PEG_MAX_LANE_GEN3];
> ///< Offset 86 <b>(Test)</b> Hint value per lane for the PEG Gen3 End Point.
> Range: 0-6, 2 is default for each lane
>
> + /**
>
> + Offset 102:
>
> + PCIe Gen3 RxCTLEp per-Bundle control. The range of the setting is (0-15).
> This setting
>
> + has to be specified based upon platform design and must follow the
> guideline. Default is 12.
>
> + **/
>
> + UINT8 PegGen3RxCtlePeaking[SA_PEG_MAX_BUNDLE_GEN3];
>
> + /**
>
> + Offset 110:
>
> + <b>(Test)</b>Used for PCIe Gen3 Software Equalization. Range: 0-65535,
> default is 1000.
>
> + @warning Do not change from the default. Hard to detect issues are likely.
>
> + @note An attack on this policy could result in an apparent hang,
>
> + but the system will eventually boot. This variable should be protected.
>
> + **/
>
> + UINT16 Gen3SwEqJitterDwellTime;
>
> + /**
>
> + Offset 112:
>
> + This is a memory data pointer for saved preset search results. The
> reference code will store
>
> + the Gen3 Preset Search results in the SaPegHob. In order to skip the Gen3
>
> + preset search on boots where the PEG card configuration has not changed
> since the previous boot,
>
> + platform code can save the contents of the SaPegHob in DXE (When it
> present and for size reported by Header.HobLength)
>
> + and provide a pointer to a restored copy of that data. Default value is
> NULL, which results in a full
>
> + preset search every boot.
>
> +
>
> + @note An attack on this policy could prevent the PCIe display from
> working until a boot when
>
> + PegDataPtr is NULL or Gen3SwEqAlwaysAttempt is enabled. The variable
> used to save the
>
> + preset search results should be protected in a way that it can only be
> modified by the
>
> + platform manufacturer.
>
> + **/
>
> + VOID *PegDataPtr;
>
> + /**
>
> + Offset 116:
>
> + <b>(Test)</b>Used for PCIe Gen3 Software Equalization. Range: 0-65535,
> default is 1.
>
> + @warning Do not change from the default. Hard to detect issues are likely.
>
> + **/
>
> + UINT16 Gen3SwEqJitterErrorTarget;
>
> +
>
> + /**
>
> + Offset 118:
>
> + <b>(Test)</b>Used for PCIe Gen3 Software Equalization. Range: 0-65535,
> default is 10000.
>
> + @warning Do not change from the default. Hard to detect issues are likely.
>
> + @note An attack on this policy could result in an apparent hang,
>
> + but the system will eventually boot. This variable should be protected.
>
> + **/
>
> + UINT16 Gen3SwEqVocDwellTime;
>
> +
>
> + /**
>
> + Offset 120:
>
> + <b>(Test)</b>Used for PCIe Gen3 Software Equalization. Range: 0-65535,
> default is 2.
>
> + @warning Do not change from the default. Hard to detect issues are likely.
>
> + **/
>
> + UINT16 Gen3SwEqVocErrorTarget;
>
> + /**
>
> + Offset 122:
>
> + PCIe Hot Plug Enable/Disable. It has 2 policies.
>
> + - Disabled (0x0) : No hotplug.
>
> + - Enabled (0x1) : Bios assist hotplug.
>
> + **/
>
> + UINT8 PegRootPortHPE[SA_PEG_MAX_FUN_GEN3];
>
> + UINT8 DmiDeEmphasis; ///< Offset 125 This field is
> used to describe the DeEmphasis control for DMI (-6 dB and -3.5 dB are the
> options)
>
> + UINT8 Rsvd0[3]; ///< Offset 126
>
> + /**
>
> + Offset 128:
>
> + This contains the PCIe PERST# GPIO information. This structure is required
>
> + for PCIe Gen3 operation. The reference code will use the information in
> this structure in
>
> + order to reset PCIe Gen3 devices during equalization, if necessary. Refer
> to the Platform
>
> + Developer's Guide (PDG) for additional details.
>
> + **/
>
> + PEG_GPIO_DATA PegGpioData;
>
> +
>
> + /**
>
> + Offset 156
>
> + <b>(Test)</b> PCIe Override RxCTLE. This feature should only be true to
> disable RxCTLE adaptive behavior for compliance testing
>
> + - <b>False</b> (0x0) : Normal Operation - RxCTLE adaptive
> behavior enabled (Default)
>
> + - True (0x1) : Override RxCTLE - Disable RxCTLE adaptive
> behavior to keep the configured RxCTLE peak values unmodified
>
> + From CFL onwards, modularity is introduced to this setup option so that
> the RxCTLE adaptive behavior could be controlled at the controller level.
>
> + Making this variable a UINT8 to accomodate the values of all controllers as
> bit definition
>
> + **/
>
> + UINT8 PegGen3RxCtleOverride;
>
> +
>
> +} PCIE_PEI_PREMEM_CONFIG_GEN3;
>
> +
>
> +#pragma pack (pop)
>
> +
>
> +#endif // _CPU_PCIE_CONFIG_GEN3_H_
>
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/CpuPcieRp/Gen4/Cp
> uPcieConfig.h
> b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/CpuPcieRp/Gen4/Cp
> uPcieConfig.h
> new file mode 100644
> index 0000000000..5941b6ad4a
> --- /dev/null
> +++
> b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/CpuPcieRp/Gen4/Cp
> uPcieConfig.h
> @@ -0,0 +1,490 @@
> +/** @file
>
> + Pcie root port policy
>
> +
>
> + Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +**/
>
> +
>
> +#ifndef _CPU_PCIE_CONFIG_H_
>
> +#define _CPU_PCIE_CONFIG_H_
>
> +
>
> +#include <Library/GpioLib.h>
>
> +#include <Library/CpuPcieInfoFruLib.h>
>
> +#include <PcieConfig.h>
>
> +#include <ConfigBlock.h>
>
> +#include <Register/SaRegsHostBridge.h>
>
> +
>
> +#pragma pack(push, 1)
>
> +
>
> +#define CPU_PCIE_PEI_PREMEM_CONFIG_REVISION 1
>
> +#define CPU_PCIE_RP_PREMEM_CONFIG_REVISION 4
>
> +
>
> +/**
>
> + Making any setup structure change after code frozen
>
> + will need to maintain backward compatibility, bump up
>
> + structure revision and update below history table\n
>
> + <b>Revision 1</b>: - Initial version.
>
> + <b>Revision 2</b>: - Add Gen3TxOverride and Gen4TxOverride
>
> + <b>Revision 3</b>: - Deprecate Dekel Suqelch Workaround Setup
> Variable
>
> + <b>Revision 4</b>: - Add FOMS Control Policy Setup Variable
>
> + <b>Revision 5</b>: - Add Gen3HwEqOverride and Gen4HwEqOverride
>
> + <b>Revision 6</b>: - Align revision with CPU_PCIE_RP_CONFIG_REVISION
> value
>
> +**/
>
> +
>
> +#define CPU_PCIE_RP_CONFIG_REVISION 6
>
> +
>
> +#define L0_SET BIT0
>
> +#define L1_SET BIT1
>
> +
>
> +
>
> +
>
> +
>
> +/**
>
> + PCI Express and DMI controller configuration\n
>
> + @note <b>Optional.</b> These policies will be ignored if there is no PEG
> port present on board.
>
> + <b>Revision 1</b>:
>
> + - Initial version.
>
> +**/
>
> +typedef struct {
>
> + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27
> Config Block Header
>
> + /**
>
> + Offset 28:0 :
>
> + <b>(Test)</b> DMI Link Speed Control
>
> + - <b>Auto</b> (0x0) : Maximum possible link speed (Default)
>
> + - Gen1 (0x1) : Limit Link to Gen1 Speed
>
> + - Gen2 (0x2) : Limit Link to Gen2 Speed
>
> + - Gen3 (0x3) : Limit Link to Gen3 Speed
>
> + **/
>
> + UINT32 DmiMaxLinkSpeed : 2;
>
> + /**
>
> + Offset 28:2 :
>
> + <b>(Test)</b> DMI Equalization Phase 2 Enable Control
>
> + - Disabled (0x0) : Disable phase 2
>
> + - Enabled (0x1) : Enable phase 2
>
> + - <b>Auto</b> (0x2) : Use the current default method (Default)
>
> + **/
>
> + UINT32 DmiGen3EqPh2Enable : 2;
>
> + /**
>
> + Offset 28:4 :
>
> + <b>(Test)</b> Selects the method for performing Phase3 of Gen3
> Equalization on DMI
>
> + - <b>Auto</b> (0x0) : Use the current default method (Default)
>
> + - HwEq (0x1) : Use Adaptive Hardware Equalization
>
> + - SwEq (0x2) : Use Adaptive Software Equalization (Implemented in
> BIOS Reference Code)
>
> + - Static (0x3) : Use the Static EQs provided in DmiGen3EndPointPreset
> array for Phase1 AND Phase3 (Instead of just Phase1)
>
> + - Disabled (0x4) : Bypass Equalization Phase 3
>
> + **/
>
> + UINT32 DmiGen3EqPh3Method : 3;
>
> + /**
>
> + Offset 28:7 :
>
> + <b>(Test)</b> Program DMI Gen3 EQ Phase1 Static Presets
>
> + - Disabled (0x0) : Disable EQ Phase1 Static Presets Programming
>
> + - <b>Enabled</b> (0x1) : Enable EQ Phase1 Static Presets Programming
> (Default)
>
> + **/
>
> + UINT32 DmiGen3ProgramStaticEq : 1;
>
> + UINT32 RsvdBits0 : 24; ///< Offset 28:8 :Reserved
> for future use
>
> +
>
> + /**
>
> + Offset 32:0 :
>
> + Select when PCIe ASPM programming will happen in relation to the Oprom
>
> + - <b>Before</b> (0x0) : Do PCIe ASPM programming before Oprom.
> (Default)
>
> + - After (0x1) : Do PCIe ASPM programming after Oprom. This will
> require an SMI handler to save/restore ASPM settings.
>
> + **/
>
> + UINT32 InitPcieAspmAfterOprom : 1;
>
> + UINT32 RsvdBits1 : 31; ///< Offset 32:1 :Reserved for future use
>
> +
>
> + UINT8 DmiGen3RootPortPreset[SA_DMI_MAX_LANE]; ///<
> Offset 36 Used for programming DMI Gen3 preset values per lane. Range: 0-
> 9, 8 is default for each lane
>
> + UINT8 DmiGen3EndPointPreset[SA_DMI_MAX_LANE]; ///<
> Offset 40/44 Used for programming DMI Gen3 preset values per lane. Range:
> 0-9, 7 is default for each lane
>
> + UINT8 DmiGen3EndPointHint[SA_DMI_MAX_LANE]; ///<
> Offset 44/52 Hint value per lane for the DMI Gen3 End Point. Range: 0-6, 2 is
> default for each lane
>
> + /**
>
> + Offset 48/60 :
>
> + DMI Gen3 RxCTLEp per-Bundle control. The range of the setting is (0-15).
> This setting
>
> + has to be specified based upon platform design and must follow the
> guideline. Default is 12.
>
> + **/
>
> +
>
> + UINT8 DmiGen3RxCtlePeaking[SA_DMI_MAX_BUNDLE];
>
> +
>
> + UINT8 DmiDeEmphasis; ///< Offset 64 This field is
> used to describe the DeEmphasis control for DMI (-6 dB and -3.5 dB are the
> options)
>
> + UINT8 Rsvd0[3]; ///< Offset 65
>
> +} PCIE_PEI_PREMEM_CONFIG;
>
> +
>
> +
>
> +/**
>
> + CPU PCIe Root Port Pre-Memory Configuration
>
> + Contains Root Port settings and capabilities
>
> + <b>Revision 1</b>: - Initial version.
>
> + <b>Revision 2</b>: - Adding Dekel Suqelch Workaround Setup Variable
>
> + <b>Revision 3</b>: - Deprecate Dekel Suqelch Workaround Setup
> Variable
>
> + <b>Revision 4</b>: - Adding CDR Relock Setup Variable
>
> +**/
>
> +typedef struct {
>
> + CONFIG_BLOCK_HEADER Header; ///< Config Block
> Header
>
> + /**
>
> + Root Port enabling mask.
>
> + Bit0 presents RP1, Bit1 presents RP2, and so on.
>
> + 0: Disable; <b>1: Enable</b>.
>
> + **/
>
> + UINT32 RpEnabledMask;
>
> + /**
>
> + Assertion on Link Down GPIOs
>
> + - <b>Disabled</b> (0x0) : Disable assertion on Link Down GPIOs(Default)
>
> + - Enabled (0x1) : Enable assertion on Link Down GPIOs
>
> + **/
>
> + UINT8 LinkDownGpios;
>
> + /**
>
> + Enable ClockReq Messaging
>
> + - <b>Disabled</> (0x0) : Disable ClockReq Messaging(Default)
>
> + - Enabled (0x1) : Enable ClockReq Messaging
>
> + **/
>
> + UINT8 ClkReqMsgEnable;
>
> + /**
>
> + Dekel Recipe Workaround
>
> + <b>2</b>
>
> + 1=Minimal, 9=Maximum,
>
> + **/
>
> + UINT8 DekelSquelchWa; // Deprecated variable
>
> + UINT8 Rsvd0[1];
>
> + /**
>
> + Determines each PCIE Port speed capability.
>
> + <b>0: Auto</b>; 1: Gen1; 2: Gen2; 3: Gen3; 4: Gen4 (see:
> CPU_PCIE_SPEED)
>
> + **/
>
> + UINT8 PcieSpeed[CPU_PCIE_MAX_ROOT_PORTS];
>
> + /**
>
> + To Enable/Disable CDR Relock
>
> + <b>0: Disable</b>; 1: Enable
>
> + **/
>
> + UINT8 CdrRelock[CPU_PCIE_MAX_ROOT_PORTS];
>
> + /**
>
> + This policy is used while programming DEKEL Recipe
>
> + <b>0: Disable</b>; 1: Enable
>
> + **/
>
> + UINT8 Xl1el[CPU_PCIE_MAX_ROOT_PORTS];
>
> +
>
> +} CPU_PCIE_RP_PREMEM_CONFIG;
>
> +
>
> +typedef enum {
>
> + CpuPcieOverrideDisabled = 0,
>
> + CpuPcieL1L2Override = 0x01,
>
> + CpuPcieL1SubstatesOverride = 0x02,
>
> + CpuPcieL1L2AndL1SubstatesOverride = 0x03,
>
> + CpuPcieLtrOverride = 0x04
>
> +} CPU_PCIE_OVERRIDE_CONFIG;
>
> +
>
> +/**
>
> + PCIe device table entry entry
>
> +
>
> + The PCIe device table is being used to override PCIe device ASPM settings.
>
> + To take effect table consisting of such entries must be instelled as PPI
>
> + on gPchPcieDeviceTablePpiGuid.
>
> + Last entry VendorId must be 0.
>
> +**/
>
> +typedef struct {
>
> + UINT16 VendorId; ///< The vendor Id of Pci Express card ASPM
> setting override, 0xFFFF means any Vendor ID
>
> + UINT16 DeviceId; ///< The Device Id of Pci Express card ASPM
> setting override, 0xFFFF means any Device ID
>
> + UINT8 RevId; ///< The Rev Id of Pci Express card ASPM setting
> override, 0xFF means all steppings
>
> + UINT8 BaseClassCode; ///< The Base Class Code of Pci Express card
> ASPM setting override, 0xFF means all base class
>
> + UINT8 SubClassCode; ///< The Sub Class Code of Pci Express card
> ASPM setting override, 0xFF means all sub class
>
> + UINT8 EndPointAspm; ///< Override device ASPM (see:
> CPU_PCIE_ASPM_CONTROL)
>
> + ///< Bit 1 must be set in OverrideConfig for this field to
> take effect
>
> + UINT16 OverrideConfig; ///< The override config bitmap (see:
> CPU_PCIE_OVERRIDE_CONFIG).
>
> + /**
>
> + The L1Substates Capability Offset Override. (applicable if bit 2 is set in
> OverrideConfig)
>
> + This field can be zero if only the L1 Substate value is going to be override.
>
> + **/
>
> + UINT16 L1SubstatesCapOffset;
>
> + /**
>
> + L1 Substate Capability Mask. (applicable if bit 2 is set in OverrideConfig)
>
> + Set to zero then the L1 Substate Capability [3:0] is ignored, and only L1s
> values are override.
>
> + Only bit [3:0] are applicable. Other bits are ignored.
>
> + **/
>
> + UINT8 L1SubstatesCapMask;
>
> + /**
>
> + L1 Substate Port Common Mode Restore Time Override. (applicable if bit
> 2 is set in OverrideConfig)
>
> + L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid
> value of 0, but not the L1sTpowerOnValue.
>
> + If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime,
> L1sTpowerOnScale, and L1sTpowerOnValue are ignored,
>
> + and only L1SubstatesCapOffset is override.
>
> + **/
>
> + UINT8 L1sCommonModeRestoreTime;
>
> + /**
>
> + L1 Substate Port Tpower_on Scale Override. (applicable if bit 2 is set in
> OverrideConfig)
>
> + L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid
> value of 0, but not the L1sTpowerOnValue.
>
> + If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime,
> L1sTpowerOnScale, and L1sTpowerOnValue are ignored,
>
> + and only L1SubstatesCapOffset is override.
>
> + **/
>
> + UINT8 L1sTpowerOnScale;
>
> + /**
>
> + L1 Substate Port Tpower_on Value Override. (applicable if bit 2 is set in
> OverrideConfig)
>
> + L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid
> value of 0, but not the L1sTpowerOnValue.
>
> + If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime,
> L1sTpowerOnScale, and L1sTpowerOnValue are ignored,
>
> + and only L1SubstatesCapOffset is override.
>
> + **/
>
> + UINT8 L1sTpowerOnValue;
>
> +
>
> + /**
>
> + SnoopLatency bit definition
>
> + Note: All Reserved bits must be set to 0
>
> +
>
> + BIT[15] - When set to 1b, indicates that the values in bits 9:0 are valid
>
> + When clear values in bits 9:0 will be ignored
>
> + BITS[14:13] - Reserved
>
> + BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in these bits
>
> + 000b - 1 ns
>
> + 001b - 32 ns
>
> + 010b - 1024 ns
>
> + 011b - 32,768 ns
>
> + 100b - 1,048,576 ns
>
> + 101b - 33,554,432 ns
>
> + 110b - Reserved
>
> + 111b - Reserved
>
> + BITS[9:0] - Snoop Latency Value. The value in these bits will be multiplied
> with
>
> + the scale in bits 12:10
>
> +
>
> + This field takes effect only if bit 3 is set in OverrideConfig.
>
> + **/
>
> + UINT16 SnoopLatency;
>
> + /**
>
> + NonSnoopLatency bit definition
>
> + Note: All Reserved bits must be set to 0
>
> +
>
> + BIT[15] - When set to 1b, indicates that the values in bits 9:0 are valid
>
> + When clear values in bits 9:0 will be ignored
>
> + BITS[14:13] - Reserved
>
> + BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in these bits
>
> + 000b - 1 ns
>
> + 001b - 32 ns
>
> + 010b - 1024 ns
>
> + 011b - 32,768 ns
>
> + 100b - 1,048,576 ns
>
> + 101b - 33,554,432 ns
>
> + 110b - Reserved
>
> + 111b - Reserved
>
> + BITS[9:0] - Non Snoop Latency Value. The value in these bits will be
> multiplied with
>
> + the scale in bits 12:10
>
> +
>
> + This field takes effect only if bit 3 is set in OverrideConfig.
>
> + **/
>
> + UINT16 NonSnoopLatency;
>
> +
>
> + /**
>
> + Forces LTR override to be permanent
>
> + The default way LTR override works is:
>
> + rootport uses LTR override values provided by BIOS until connected
> device sends an LTR message, then it will use values from the message
>
> + This settings allows force override of LTR mechanism. If it's enabled, then:
>
> + rootport will use LTR override values provided by BIOS forever; LTR
> messages sent from connected device will be ignored
>
> + **/
>
> + UINT8 ForceLtrOverride;
>
> + UINT8 Reserved[3];
>
> +} CPU_PCIE_DEVICE_OVERRIDE;
>
> +
>
> +enum CPU_PCIE_SPEED {
>
> + CpuPcieAuto,
>
> + CpuPcieGen1,
>
> + CpuPcieGen2,
>
> + CpuPcieGen3,
>
> + CpuPcieGen4,
>
> + CpuPcieGen5
>
> +};
>
> +
>
> +///
>
> +/// The values before AutoConfig match the setting of PCI Express Base
> Specification 1.1, please be careful for adding new feature
>
> +///
>
> +typedef enum {
>
> + CpuPcieAspmDisabled,
>
> + CpuPcieAspmL0s,
>
> + CpuPcieAspmL1,
>
> + CpuPcieAspmL0sL1,
>
> + CpuPcieAspmAutoConfig,
>
> + CpuPcieAspmMax
>
> +} CPU_PCIE_ASPM_CONTROL;
>
> +
>
> +/**
>
> + Refer to SA EDS for the SA implementation values corresponding
>
> + to below PCI-E spec defined ranges
>
> +**/
>
> +typedef enum {
>
> + CpuPcieL1SubstatesDisabled,
>
> + CpuPcieL1SubstatesL1_1,
>
> + CpuPcieL1SubstatesL1_1_2,
>
> + CpuPcieL1SubstatesMax
>
> +} CPU_PCIE_L1SUBSTATES_CONTROL;
>
> +
>
> +enum CPU_PCIE_MAX_PAYLOAD {
>
> + CpuPcieMaxPayload128 = 0,
>
> + CpuPcieMaxPayload256,
>
> + CpuPcieMaxPayload512,
>
> + CpuPcieMaxPayloadMax
>
> +};
>
> +
>
> +enum CPU_PCIE_COMPLETION_TIMEOUT {
>
> + CpuPcieCompletionTO_Default,
>
> + CpuPcieCompletionTO_50_100us,
>
> + CpuPcieCompletionTO_1_10ms,
>
> + CpuPcieCompletionTO_16_55ms,
>
> + CpuPcieCompletionTO_65_210ms,
>
> + CpuPcieCompletionTO_260_900ms,
>
> + CpuPcieCompletionTO_1_3P5s,
>
> + CpuPcieCompletionTO_4_13s,
>
> + CpuPcieCompletionTO_17_64s,
>
> + CpuPcieCompletionTO_Disabled
>
> +};
>
> +
>
> +
>
> +enum CPU_PCIE_GEN3_PRESET_COEFF_SELECTION {
>
> + CpuPcieGen3PresetSelection,
>
> + CpuPcieGen3CoefficientSelection
>
> +};
>
> +
>
> +enum CPU_PCIE_GEN4_PRESET_COEFF_SELECTION {
>
> + CpuPcieGen4PresetSelection,
>
> + CpuPcieGen4CoefficientSelection
>
> +};
>
> +
>
> +typedef enum {
>
> + CpuPcieEqDefault = 0, ///< @deprecated since revision 3. Behaves as
> PchPcieEqHardware.
>
> + CpuPcieEqHardware = 1, ///< Hardware equalization
>
> + CpuPcieEqStaticCoeff = 4 ///< Fixed equalization (requires Coefficient
> settings per lane)
>
> +} CPU_PCIE_EQ_METHOD;
>
> +
>
> +
>
> +/**
>
> + Represent lane specific PCIe Gen3 equalization parameters.
>
> +**/
>
> +typedef struct {
>
> + UINT8 Cm; ///< Coefficient C-1
>
> + UINT8 Cp; ///< Coefficient C+1
>
> + UINT8 PegGen3RootPortPreset; ///< <b>(Test)</b> Used for
> programming PEG Gen3 preset values per lane. Range: 0-9, 8 is default for
> each lane
>
> + UINT8 PegGen3EndPointPreset; ///< <b>(Test)</b> Used for
> programming PEG Gen3 preset values per lane. Range: 0-9, 7 is default for
> each lane
>
> + UINT8 PegGen3EndPointHint; ///< <b>(Test)</b> Hint value
> per lane for the PEG Gen3 End Point. Range: 0-6, 2 is default for each lane
>
> + UINT8 PegGen4RootPortPreset; ///< <b>(Test)</b> Used for
> programming PEG Gen4 preset values per lane. Range: 0-9, 8 is default for
> each lane
>
> + UINT8 PegGen4EndPointPreset; ///< <b>(Test)</b> Used for
> programming PEG Gen4 preset values per lane. Range: 0-9, 7 is default for
> each lane
>
> + UINT8 PegGen4EndPointHint; ///< <b>(Test)</b> Hint value
> per lane for the PEG Gen4 End Point. Range: 0-6, 2 is default for each lane
>
> +} CPU_PCIE_EQ_LANE_PARAM;
>
> +
>
> +/**
>
> + The CPU_PCI_ROOT_PORT_CONFIG describe the feature and capability of
> each CPU PCIe root port.
>
> +**/
>
> +typedef struct {
>
> +
>
> + UINT32 ExtSync : 1; ///< Indicate whether the extended
> synch is enabled. <b>0: Disable</b>; 1: Enable.
>
> + UINT32 VcEnabled : 1; ///< Virtual Channel. 0: Disable; <b>1:
> Enable</b>
>
> + UINT32 MultiVcEnabled : 1; ///< Multiple Virtual Channel. 0:
> Disable; <b>1: Enable</b>
>
> + UINT32 PeerToPeer : 1; ///< Peer to Peer Mode. <b>0:
> Disable</b>; 1: Enable.
>
> + UINT32 RsvdBits0 : 28; ///< Reserved bits
>
> + /**
>
> + PCIe Gen4 Equalization Method
>
> + - HwEq (0x1) : Hardware Equalization (Default)
>
> + - StaticEq (0x2) : Static Equalization
>
> + **/
>
> + UINT8 Gen4EqPh3Method;
>
> + UINT8 FomsCp; ///< FOM Score Board Control Policy
>
> + UINT8 RsvdBytes0[2]; ///< Reserved bytes
>
> +
>
> + //
>
> + // Gen3 Equalization settings
>
> + //
>
> + UINT32 Gen3Uptp : 4; ///< <b>(Test)</b> Upstream Port
> Transmitter Preset used during Gen3 Link Equalization. Used for all lanes.
> Default is <b>7</b>.
>
> + UINT32 Gen3Dptp : 4; ///< <b>(Test)</b> Downstream Port
> Transmiter Preset used during Gen3 Link Equalization. Used for all lanes.
> Default is <b>7</b>.
>
> + //
>
> + // Gen4 Equalization settings
>
> + //
>
> + UINT32 Gen4Uptp : 4; ///< <b>(Test)</b> Upstream Port
> Transmitter Preset used during Gen4 Link Equalization. Used for all lanes.
> Default is <b>7</b>.
>
> + UINT32 Gen4Dptp : 4; ///< <b>(Test)</b> Downstream Port
> Transmiter Preset used during Gen4 Link Equalization. Used for all lanes.
> Default is <b>7</b>.
>
> + //
>
> + // Gen5 Equalization settings
>
> + //
>
> + UINT32 Gen5Uptp : 4; ///< <b>(Test)</b> Upstream Port
> Transmitter Preset used during Gen5 Link Equalization. Used for all lanes.
> Default is <b>7</b>.
>
> + UINT32 Gen5Dptp : 4; ///< <b>(Test)</b> Downstream Port
> Transmiter Preset used during Gen5 Link Equalization. Used for all lanes.
> Default is <b>7</b>.
>
> + UINT32 RsvdBits1 : 8; ///< Reserved Bits
>
> +
>
> + PCIE_ROOT_PORT_COMMON_CONFIG PcieRpCommonConfig;
> ///< <b>(Test)</b> Includes policies which are common to both SA and PCH
> RootPort
>
> +
>
> +} CPU_PCIE_ROOT_PORT_CONFIG;
>
> +
>
> +/**
>
> + The CPU_PCIE_CONFIG block describes the expected configuration of the
> CPU PCI Express controllers
>
> + <b>Revision 1< / b>:
>
> + -Initial version.
>
> + <b>Revision 2</b>:
>
> + - SlotSelection policy added
>
> + <b>Revision 3</b>
>
> + - Deprecate PegGen3ProgramStaticEq and PegGen4ProgramStaticEq
>
> + <b>Revision 4</b>:
>
> + - Deprecating SetSecuredRegisterLock
>
> + <b>Revision 5</b>:
>
> + - Adding Serl
>
> +**/
>
> +typedef struct {
>
> + CONFIG_BLOCK_HEADER Header; ///< Config Block Header
>
> + ///
>
> + /// These members describe the configuration of each SA PCIe root port.
>
> + ///
>
> + CPU_PCIE_ROOT_PORT_CONFIG
> RootPort[CPU_PCIE_MAX_ROOT_PORTS];
>
> + ///
>
> + /// Gen3 Equalization settings for physical PCIe lane, index 0 represents
> PCIe lane 1, etc.
>
> + /// Corresponding entries are used when root port EqPh3Method is
> PchPcieEqStaticCoeff (default).
>
> + ///
>
> + CPU_PCIE_EQ_LANE_PARAM
> EqPh3LaneParam[SA_PEG_MAX_LANE];
>
> + ///
>
> + /// List of coefficients used during equalization (applicable to both
> software and hardware EQ)
>
> + ///
>
> + PCIE_EQ_PARAM
> HwEqGen4CoeffList[PCIE_HWEQ_COEFFS_MAX]; // Deprecated Policy
>
> +
>
> + PCIE_COMMON_CONFIG PcieCommonConfig; /// <
> <b>(Test)</b> Includes policies which are common to both SA and PCH PCIe
>
> +
>
> + UINT32 FiaProgramming : 1; /// < Skip Fia Configuration and
> lock if enable
>
> + ///
>
> + /// This member describes whether the PCI Express Clock Gating for each
> root port
>
> + /// is enabled by platform modules. <b>0: Disable</b>; 1: Enable.
>
> + ///
>
> + UINT32 ClockGating : 1;
>
> + ///
>
> + /// This member describes whether the PCI Express Power Gating for each
> root port
>
> + /// is enabled by platform modules. <b>0: Disable</b>; 1: Enable.
>
> + ///
>
> + UINT32 PowerGating : 1;
>
> + // Deprecated Policy
>
> + /**
>
> + <b>(Test)</b> Program PEG Gen3 EQ Phase1 Static Presets
>
> + - Disabled (0x0) : Disable EQ Phase1 Static Presets Programming
>
> + - <b>Enabled</b> (0x1) : Enable EQ Phase1 Static Presets Programming
> (Default)
>
> + **/
>
> + UINT32 PegGen3ProgramStaticEq : 1;
>
> +
>
> + // Deprecated Policy
>
> + /**
>
> + <b>(Test)</b> Program PEG Gen4 EQ Phase1 Static Presets
>
> + - Disabled (0x0) : Disable EQ Phase1 Static Presets Programming
>
> + - <b>Enabled</b> (0x1) : Enable EQ Phase1 Static Presets Programming
> (Default)
>
> + **/
>
> + UINT32 PegGen4ProgramStaticEq : 1;
>
> + /**
>
> + <b>(Test)</b> Cpu Pcie Secure Register Lock
>
> + - Disabled (0x0)
>
> + - <b>Enabled</b> (0x1)
>
> + **/
>
> + UINT32 SetSecuredRegisterLock : 1; // Deprecated Policy
>
> + ///
>
> + /// This member allows to select between the PCI Express M2 or CEMx4
> slot <b>1: PCIe M2</b>; 0: CEMx4 slot.
>
> + ///
>
> + UINT32 SlotSelection : 1;
>
> + ///
>
> + /// Set/Clear Serl(Secure Equalization Register Lock)
>
> + ///
>
> + UINT32 Serl : 1;
>
> +
>
> + UINT32 RsvdBits0 : 24;
>
> +
>
> + /**
>
> + PCIe device override table
>
> + The PCIe device table is being used to override PCIe device ASPM
> settings.
>
> + This is a pointer points to a 32bit address. And it's only used in PostMem
> phase.
>
> + Please refer to PCH_PCIE_DEVICE_OVERRIDE structure for the table.
>
> + Last entry VendorId must be 0.
>
> + The prototype of this policy is:
>
> + CPU_PCIE_DEVICE_OVERRIDE *PcieDeviceOverrideTablePtr;
>
> + **/
>
> + UINT32 PcieDeviceOverrideTablePtr;
>
> + } CPU_PCIE_CONFIG;
There are two fields missing from this definition:
CPU_PCIE_ROOT_PORT_CONFIG2 RootPort2[CPU_PCIE_MAX_ROOT_PORTS];
PCIE_COMMON_CONFIG2 PcieCommonConfig2;
>
> +
>
> +#pragma pack (pop)
>
> +
>
> +#endif // _CPU_PCIE_CONFIG_H_
>
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Dci/DciConfig.h
> b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Dci/DciConfig.h
> new file mode 100644
> index 0000000000..445642da1f
> --- /dev/null
> +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Dci/DciConfig.h
> @@ -0,0 +1,72 @@
> +/** @file
>
> + Dci policy
>
> +
>
> + Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +**/
>
> +#ifndef _DCI_CONFIG_H_
>
> +#define _DCI_CONFIG_H_
>
> +
>
> +#define DCI_PREMEM_CONFIG_REVISION 2
>
> +extern EFI_GUID gDciPreMemConfigGuid;
>
> +
>
> +#pragma pack (push,1)
>
> +
>
> +typedef enum {
>
> + DciDbcDisabled = 0x0,
>
> + DciDbcUsb2 = 0x1,
>
> + DciDbcUsb3 = 0x2,
>
> + DciDbcBoth = 0x3,
>
> + DciDbcNoChange = 0x4,
>
> + DciDbcMax
>
> +} DCI_DBC_MODE;
>
> +
>
> +typedef enum {
>
> + Usb3TcDbgDisabled = 0x0,
>
> + Usb3TcDbgEnabled = 0x1,
>
> + Usb3TcDbgNoChange = 0x2,
>
> + Usb3TcDbgMax
>
> +} DCI_USB3_TYPE_C_DEBUG_MODE;
>
> +
>
> +/**
>
> + The PCH_DCI_PREMEM_CONFIG block describes policies related to Direct
> Connection Interface (DCI)
>
> +
>
> + <b>Revision 1</b>:
>
> + - Initial version.
>
> + <b>Revision 2</b>:
>
> + - Added DciModphyPg
>
> + - change to use data in byte unit rather than bit-field
>
> +**/
>
> +typedef struct {
>
> + CONFIG_BLOCK_HEADER Header; ///< Config Block Header
>
> + /**
>
> + DCI enable.
>
> + Determine if to enable DCI debug from host.
>
> + <b>0:Disabled</b>; 1:Enabled
>
> + **/
>
> + UINT8 DciEn;
>
> + /**
>
> + USB DbC enable mode.
>
> + Disabled: Clear both USB2/3DBCEN; USB2: Set USB2DBCEN; USB3: Set
> USB3DBCEN; Both: Set both USB2/3DBCEN; No Change: Comply with HW
> value
>
> + Refer to definition of DCI_USB_DBC_MODE for supported settings.
>
> + 0:Disabled; 1:USB2; 2:USB3; 3:Both; <b>4:No Change</b>
>
> + **/
>
> + UINT8 DciDbcMode;
>
> + /**
>
> + Enable Modphy power gate when DCI is enable. It must be disabled for 4-
> wire DCI OOB. Set default to HW default : Disabled
>
> + <b>0:Disabled</b>; 1:Enabled
>
> + **/
>
> + UINT8 DciModphyPg;
>
> + /**
>
> + USB3 Type-C UFP2DFP kenel / platform debug support. No change will do
> nothing to UFP2DFP configuration.
>
> + When enabled, USB3 Type C UFP (upstream-facing port) may switch to
> DFP (downstream-facing port) for first connection.
>
> + It must be enabled for USB3 kernel(kernel mode debug) and platform
> debug(DFx, DMA, Trace) over UFP Type-C receptacle.
>
> + Refer to definition of DCI_USB_TYPE_C_DEBUG_MODE for supported
> settings.
>
> + 0:Disabled; 1:Enabled; <b>2:No Change</b>
>
> + **/
>
> + UINT8 DciUsb3TypecUfpDbg;
>
> +} PCH_DCI_PREMEM_CONFIG;
>
> +
>
> +#pragma pack (pop)
>
> +
>
> +#endif // _DCI_CONFIG_H_
>
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Espi/EspiConfig.h
> b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Espi/EspiConfig.h
> new file mode 100644
> index 0000000000..260b582702
> --- /dev/null
> +++
> b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Espi/EspiConfig.h
> @@ -0,0 +1,61 @@
> +/** @file
>
> + Espi policy
>
> +
>
> + Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +**/
>
> +#ifndef _ESPI_CONFIG_H_
>
> +#define _ESPI_CONFIG_H_
>
> +
>
> +#define ESPI_CONFIG_REVISION 2
>
> +extern EFI_GUID gEspiConfigGuid;
>
> +
>
> +#pragma pack (push,1)
>
> +
>
> +/**
>
> + This structure contains the policies which are related to ESPI.
>
> +
>
> + <b>Revision 1</b>:
>
> + - Initial revision
>
> + <b>Revision 2</b>:
>
> + - Added LockLinkConfiguration field to config block
>
> +**/
>
> +typedef struct {
>
> + CONFIG_BLOCK_HEADER Header; ///< Config Block Header
>
> + /**
>
> + LPC (eSPI) Memory Range Decode Enable. When TRUE, then the range
>
> + specified in PCLGMR[31:16] is enabled for decoding to LPC (eSPI).
>
> + <b>0: FALSE</b>, 1: TRUE
>
> + **/
>
> + UINT32 LgmrEnable : 1;
>
> + /**
>
> + eSPI Master and Slave BME settings.
>
> + When TRUE, then the BME bit enabled in eSPI Master and Slave.
>
> + 0: FALSE, <b>1: TRUE </b>
>
> + **/
>
> + UINT32 BmeMasterSlaveEnabled : 1;
>
> + /**
>
> + Master HOST_C10 (Virtual Wire) to Slave Enable (VWHC10OE)
>
> + <b>0b: Disable HOST_C10 reporting (HOST_C10 indication from PMC is
> ignored)</b>
>
> + 1b: Enable HOST_C10 reporting to Slave via eSPI Virtual Wire (upon
> receiving a HOST_C10 indication from PMC)
>
> + **/
>
> + UINT32 HostC10ReportEnable : 1;
>
> + /**
>
> + eSPI Link Configuration Lock (SBLCL)
>
> + If set to TRUE then communication through SET_CONFIG/GET_CONFIG
>
> + to eSPI slaves addresses from range 0x0 - 0x7FF
>
> + <b>1: TRUE</b>, 0: FALSE
>
> + **/
>
> + UINT32 LockLinkConfiguration : 1;
>
> + /**
>
> + Hardware Autonomous Enable (HAE)
>
> + If set to TRUE, then the IP may request a PG whenever it is idle
>
> + **/
>
> + UINT32 EspiPmHAE : 1;
>
> + UINT32 RsvdBits : 27; ///< Reserved bits
>
> +} PCH_ESPI_CONFIG;
>
> +
>
> +#pragma pack (pop)
>
> +
>
> +#endif // _ESPI_CONFIG_H_
>
> +
>
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Fivr/FivrConfig.h
> b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Fivr/FivrConfig.h
> new file mode 100644
> index 0000000000..0df2755280
> --- /dev/null
> +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Fivr/FivrConfig.h
> @@ -0,0 +1,170 @@
> +/** @file
>
> + PCH FIVR policy
>
> +
>
> + Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +**/
>
> +#ifndef _FIVR_CONFIG_H_
>
> +#define _FIVR_CONFIG_H_
>
> +
>
> +#define FIVR_CONFIG_REVISION 1
>
> +extern EFI_GUID gFivrConfigGuid;
>
> +
>
> +#pragma pack (push,1)
>
> +
>
> +/**
>
> + Rail support in S0ix and Sx
>
> + Settings other than FivrRailDisabled can be OR'ed
>
> +**/
>
> +typedef enum {
>
> + FivrRailDisabled = 0,
>
> + FivrRailInS0i1S0i2 = BIT0,
>
> + FivrRailInS0i3 = BIT1,
>
> + FivrRailInS3 = BIT2,
>
> + FivrRailInS4 = BIT3,
>
> + FivrRailInS5 = BIT4,
>
> + FivrRailInS0ix = FivrRailInS0i1S0i2 | FivrRailInS0i3,
>
> + FivrRailInSx = FivrRailInS3 | FivrRailInS4 | FivrRailInS5,
>
> + FivrRailAlwaysOn = FivrRailInS0ix | FivrRailInSx
>
> +} FIVR_RAIL_SX_STATE;
>
> +
>
> +typedef enum {
>
> + FivrRetentionActive = BIT0,
>
> + FivrNormActive = BIT1,
>
> + FivrMinActive = BIT2,
>
> + FivrMinRetention = BIT3
>
> +} FIVR_RAIL_SUPPORTED_VOLTAGE;
>
> +
>
> +/**
>
> + Structure for V1p05/Vnn VR rail configuration
>
> +**/
>
> +typedef struct {
>
> + /**
>
> + Mask to enable the usage of external VR rail in specific S0ix or Sx states
>
> + Use values from FIVR_RAIL_SX_STATE
>
> + The default is <b>FivrRailDisabled</b>.
>
> + **/
>
> + UINT32 EnabledStates : 5;
>
> +
>
> + /**
>
> + VR rail voltage value that will be used in S0i2/S0i3 states.
>
> + This value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...)
>
> + The default for Vnn is set to <b>420 - 1050 mV</b>.
>
> + **/
>
> + UINT32 Voltage : 11;
>
> + /**
>
> + @deprecated
>
> + THIS POLICY IS DEPRECATED, PLEASE USE IccMaximum INSTEAD
>
> + VR rail Icc Max Value
>
> + Granularity of this setting is 1mA and maximal possible value is 500mA
>
> + The default is <b> 0mA </b>.
>
> + **/
>
> + UINT32 IccMax : 8;
>
> +
>
> + /**
>
> + This register holds the control hold off values to be used when
>
> + changing the rail control for external bypass value in us
>
> + **/
>
> + UINT32 CtrlRampTmr : 8;
>
> +
>
> + /**
>
> + Mask to set the supported configuration in VR rail.
>
> + Use values from FIVR_RAIL_SUPPORTED_VOLTAGE
>
> + **/
>
> + UINT32 SupportedVoltageStates : 4;
>
> +
>
> + /**
>
> + VR rail Icc Maximum Value
>
> + Granularity of this setting is 1mA and maximal possible value is 500mA
>
> + The default is <b> 0mA </b>.
>
> + **/
>
> + UINT32 IccMaximum : 16;
>
> +
>
> + UINT32 RsvdBits1 : 12;
>
> +
>
> +} FIVR_EXT_RAIL_CONFIG;
>
> +
>
> +
>
> +/**
>
> + Structure for VCCIN_AUX voltage rail configuration
>
> +**/
>
> +typedef struct {
>
> + /**
>
> + Transition time in microseconds from Low Current Mode Voltage to High
> Current Mode Voltage.
>
> + Voltage transition time required by motherboard voltage regulator when
> PCH changes
>
> + the VCCIN_AUX regulator set point from the low current mode voltage
> and high current mode voltage.
>
> + This field has 1us resolution.
>
> + When value is 0 PCH will not transition VCCIN_AUX to low current mode
> voltage.
>
> + The default is <b> 0xC </b>.
>
> + **/
>
> + UINT8 LowToHighCurModeVolTranTime;
>
> +
>
> + /**
>
> + Transition time in microseconds from Retention Mode Voltage to High
> Current Mode Voltage.
>
> + Voltage transition time required by motherboard voltage regulator when
> PCH changes
>
> + the VCCIN_AUX regulator set point from the retention mode voltage to
> high current mode voltage.
>
> + This field has 1us resolution.
>
> + When value is 0 PCH will not transition VCCIN_AUX to retention voltage.
>
> + The default is <b> 0x36 </b>.
>
> + **/
>
> + UINT8 RetToHighCurModeVolTranTime;
>
> +
>
> + /**
>
> + Transition time in microseconds from Retention Mode Voltage to Low
> Current Mode Voltage.
>
> + Voltage transition time required by motherboard voltage regulator when
> PCH changes
>
> + the VCCIN_AUX regulator set point from the retention mode voltage to
> low current mode voltage.
>
> + This field has 1us resolution.
>
> + When value is 0 PCH will not transition VCCIN_AUX to retention voltage.
>
> + The default is <b> 0x2B </b>.
>
> + **/
>
> + UINT8 RetToLowCurModeVolTranTime;
>
> + UINT8 RsvdByte1;
>
> + /**
>
> + Transition time in microseconds from Off (0V) to High Current Mode
> Voltage.
>
> + Voltage transition time required by motherboard voltage regulator when
> PCH changes
>
> + the VCCIN_AUX regulator set point from 0V to the high current mode
> voltage.
>
> + This field has 1us resolution.
>
> + 0 = Transition to 0V is disabled
>
> + Setting this field to 0 sets VCCIN_AUX as a fixed rail that stays on
>
> + in all S0 & Sx power states after initial start up on G3 exit
>
> + The default is <b> 0x96 </b>.
>
> + **/
>
> + UINT32 OffToHighCurModeVolTranTime : 11;
>
> + UINT32 RsvdBits1 : 21;
>
> +} FIVR_VCCIN_AUX_CONFIG;
>
> +
>
> +/**
>
> + The PCH_FIVR_CONFIG block describes FIVR settings.
>
> +**/
>
> +typedef struct {
>
> + CONFIG_BLOCK_HEADER Header; ///< Config Block Header
>
> + /**
>
> + External V1P05 VR rail configuration.
>
> + **/
>
> + FIVR_EXT_RAIL_CONFIG ExtV1p05Rail;
>
> + /**
>
> + External Vnn VR rail configuration.
>
> + **/
>
> + FIVR_EXT_RAIL_CONFIG ExtVnnRail;
>
> + /**
>
> + Additional External Vnn VR rail configuration that will get applied
>
> + in Sx entry SMI callback. Required only if External Vnn VR
>
> + needs different settings for Sx than those specified in ExtVnnRail.
>
> + **/
>
> + FIVR_EXT_RAIL_CONFIG ExtVnnRailSx;
>
> + /**
>
> + VCCIN_AUX voltage rail configuration.
>
> + **/
>
> + FIVR_VCCIN_AUX_CONFIG VccinAux;
>
> +
>
> + /**
>
> + Enable/Disable FIVR Dynamic Power Management
>
> + Default is <b> 1 </b>.
>
> + **/
>
> + UINT32 FivrDynPm : 1;
>
> + UINT32 RsvdBits2 : 31;
>
> +} PCH_FIVR_CONFIG;
>
> +
>
> +#pragma pack (pop)
>
> +
>
> +#endif // _FIVR_CONFIG_H_
>
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Gbe/GbeConfig.h
> b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Gbe/GbeConfig.h
> new file mode 100644
> index 0000000000..cb9411f9e8
> --- /dev/null
> +++
> b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Gbe/GbeConfig.h
> @@ -0,0 +1,33 @@
> +/** @file
>
> + Gigabit Ethernet policy
>
> +
>
> + Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +**/
>
> +#ifndef _GBE_CONFIG_H_
>
> +#define _GBE_CONFIG_H_
>
> +
>
> +#define GBE_CONFIG_REVISION 1
>
> +extern EFI_GUID gGbeConfigGuid;
>
> +
>
> +#pragma pack (push,1)
>
> +
>
> +/**
>
> + PCH intergrated GBE controller configuration settings.
>
> +**/
>
> +typedef struct {
>
> + CONFIG_BLOCK_HEADER Header; ///< Config Block Header
>
> + /**
>
> + Determines if enable PCH internal GBE, 0: Disable; <b>1: Enable</b>.
>
> + When Enable is changed (from disabled to enabled or from enabled to
> disabled),
>
> + it needs to set LAN Disable regsiter, which might be locked by FDSWL
> register.
>
> + So it's recommendated to issue a global reset when changing the status
> for PCH Internal LAN.
>
> + **/
>
> + UINT32 Enable : 1;
>
> + UINT32 LtrEnable : 1; ///< <b>0: Disable</b>; 1: Enable LTR capabilty of
> PCH internal LAN.
>
> + UINT32 RsvdBits0 : 30; ///< Reserved bits
>
> +} GBE_CONFIG;
>
> +
>
> +#pragma pack (pop)
>
> +
>
> +#endif // _GBE_CONFIG_H_
>
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Gna/GnaConfig.h
> b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Gna/GnaConfig.h
> new file mode 100644
> index 0000000000..87649253c6
> --- /dev/null
> +++
> b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Gna/GnaConfig.h
> @@ -0,0 +1,31 @@
> +/** @file
>
> + Policy definition for GNA Config Block
>
> +
>
> + Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +**/
>
> +#ifndef _GNA_CONFIG_H_
>
> +#define _GNA_CONFIG_H_
>
> +#pragma pack(push, 1)
>
> +
>
> +#define GNA_CONFIG_REVISION 1
>
> +/**
>
> + GNA config block for configuring GNA.\n
>
> + <b>Revision 1</b>:
>
> + - Initial version.
>
> +**/
>
> +typedef struct {
>
> + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config
> Block Header
>
> + /**
>
> + Offset 28:0
>
> + This policy enables the GNA Device (SA Device 8) if supported.
>
> + If FALSE, all other policies in this config block will be ignored.
>
> + <b>1=TRUE</b>;
>
> + 0=FALSE.
>
> + **/
>
> + UINT32 GnaEnable : 1;
>
> + UINT32 RsvdBits0 : 31; ///< Offset 28:1 :Reserved for future use
>
> +} GNA_CONFIG;
>
> +#pragma pack(pop)
>
> +
>
> +#endif // _GNA_CONFIG_H_
>
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Gpio/GpioDevConfig
> .h
> b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Gpio/GpioDevConfig
> .h
> new file mode 100644
> index 0000000000..1a724f14da
> --- /dev/null
> +++
> b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Gpio/GpioDevConfig
> .h
> @@ -0,0 +1,37 @@
> +/** @file
>
> + GPIO device policy
>
> +
>
> + Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +**/
>
> +#ifndef _GPIO_DEV_CONFIG_H_
>
> +#define _GPIO_DEV_CONFIG_H_
>
> +
>
> +extern EFI_GUID gGpioDxeConfigGuid;
>
> +
>
> +#define GPIO_DXE_CONFIG_REVISION 1
>
> +
>
> +#pragma pack (push,1)
>
> +
>
> +/**
>
> + This structure contains the DXE policies which are related to GPIO device.
>
> +
>
> + <b>Revision 1:</b>
>
> + - Inital version.
>
> +**/
>
> +typedef struct {
>
> + CONFIG_BLOCK_HEADER Header; ///< Config Block Header
>
> + /**
>
> + If GPIO ACPI device is not used by OS it can be hidden. In such case
>
> + no other device exposed to the system can reference GPIO device in one
>
> + of its resources through GpioIo(..) or GpioInt(..) ACPI descriptors.
>
> + <b>0: Disable</b>; 1: Enable
>
> + **/
>
> + UINT32 HideGpioAcpiDevice : 1;
>
> + UINT32 RsvdBits : 31; ///< Reserved bits
>
> +
>
> +} GPIO_DXE_CONFIG;
>
> +
>
> +#pragma pack (pop)
>
> +
>
> +#endif // _GPIO_DEV_CONFIG_H_
>
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Graphics/Gen12/Gra
> phicsConfig.h
> b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Graphics/Gen12/Gra
> phicsConfig.h
> new file mode 100644
> index 0000000000..c3b134b830
> --- /dev/null
> +++
> b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Graphics/Gen12/Gra
> phicsConfig.h
> @@ -0,0 +1,211 @@
> +/** @file
>
> + Policy definition for Internal Graphics Config Block.
>
> +
>
> + Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +**/
>
> +#ifndef _GRAPHICS_CONFIG_H_
>
> +#define _GRAPHICS_CONFIG_H_
>
> +#pragma pack(push, 1)
>
> +
>
> +#define GRAPHICS_PEI_PREMEM_CONFIG_REVISION 3
>
> +#define GRAPHICS_PEI_CONFIG_REVISION 7
>
> +#define GRAPHICS_DXE_CONFIG_REVISION 1
>
> +
>
> +#define DDI_DEVICE_NUMBER 4
>
> +#define MAX_BCLM_ENTRIES 20
>
> +
>
> +
>
> +//
>
> +// DDI defines
>
> +//
>
> +typedef enum {
>
> + DdiDisable = 0x00,
>
> + DdiDdcEnable = 0x01,
>
> +} DDI_DDC_TBT_VAL;
>
> +
>
> +typedef enum {
>
> + DdiHpdDisable = 0x00,
>
> + DdiHpdEnable = 0x01,
>
> +} DDI_HPD_VAL;
>
> +
>
> +typedef enum {
>
> + DdiPortDisabled = 0x00,
>
> + DdiPortEdp = 0x01,
>
> + DdiPortMipiDsi = 0x02,
>
> +} DDI_PORT_SETTINGS;
>
> +
>
> +/**
>
> + This structure configures the Native GPIOs for DDI port per VBT settings.
>
> +**/
>
> +typedef struct {
>
> + UINT8 DdiPortAConfig; /// The Configuration of DDI port A, this settings
> must match VBT's settings. DdiPortDisabled - No LFP is connected on
> DdiPortA, <b>DdiPortEdp - Set DdiPortA to eDP</b>, DdiPortMipiDsi - Set
> DdiPortA to MIPI DSI
>
> + UINT8 DdiPortBConfig; /// The Configuration of DDI port B, this settings
> must match VBT's settings. DdiPortDisabled - No LFP is connected on
> DdiPortB, <b>DdiPortEdp - Set DdiPortB to eDP</b>, DdiPortMipiDsi - Set
> DdiPortB to MIPI DSI
>
> + UINT8 DdiPortAHpd; /// The HPD setting of DDI Port A, this settings must
> match VBT's settings. <b>DdiHpdDisable - Disable HPD</b>, DdiHpdEnable -
> Enable HPD
>
> + UINT8 DdiPortBHpd; /// The HPD setting of DDI Port B, this settings must
> match VBT's settings. DdiHpdDisable - Disable HPD, <b>DdiHpdEnable -
> Enable HPD</b>
>
> + UINT8 DdiPortCHpd; /// The HPD setting of DDI Port C, this settings must
> match VBT's settings. <b>DdiHpdDisable - Disable HPD</b>, DdiHpdEnable -
> Enable HPD
>
> + UINT8 DdiPort1Hpd; /// The HPD setting of DDI Port 1, this settings must
> match VBT's settings. <b>DdiHpdDisable - Disable HPD</b>, DdiHpdEnable -
> Enable HPD
>
> + UINT8 DdiPort2Hpd; /// The HPD setting of DDI Port 2, this settings must
> match VBT's settings. <b>DdiHpdDisable - Disable HPD</b>, DdiHpdEnable -
> Enable HPD
>
> + UINT8 DdiPort3Hpd; /// The HPD setting of DDI Port 3, this settings must
> match VBT's settings. <b>DdiHpdDisable - Disable HPD</b>, DdiHpdEnable -
> Enable HPD
>
> + UINT8 DdiPort4Hpd; /// The HPD setting of DDI Port 4, this settings must
> match VBT's settings. <b>DdiHpdDisable - Disable HPD</b>, DdiHpdEnable -
> Enable HPD
>
> + UINT8 DdiPortADdc; /// The DDC setting of DDI Port A, this settings must
> match VBT's settings. <b>DdiDisable - Disable DDC</b>, DdiDdcEnable -
> Enable DDC
>
> + UINT8 DdiPortBDdc; /// The DDC setting of DDI Port B, this settings must
> match VBT's settings. DdiDisable - Disable DDC, <b>DdiDdcEnable - Enable
> DDC </b>
>
> + UINT8 DdiPortCDdc; /// The DDC setting of DDI Port C, this settings must
> match VBT's settings. <b>DdiDisable - Disable DDC</b>, DdiDdcEnable -
> Enable DDC
>
> + UINT8 DdiPort1Ddc; /// The DDC setting of DDI Port 1, this settings must
> match VBT's settings. <b>DdiDisable - Disable DDC</b>, DdiDdcEnable -
> Enable DDC
>
> + UINT8 DdiPort2Ddc; /// The DDC setting of DDI Port 2, this settings must
> match VBT's settings. <b>DdiDisable - Disable DDC</b>, DdiDdcEnable -
> Enable DDC
>
> + UINT8 DdiPort3Ddc; /// The DDC setting of DDI Port 3, this settings must
> match VBT's settings. <b>DdiDisable - Disable DDC</b>, DdiDdcEnable -
> Enable DDC
>
> + UINT8 DdiPort4Ddc; /// The DDC setting of DDI Port 4, this settings must
> match VBT's settings. <b>DdiDisable - Disable DDC</b>, DdiDdcEnable -
> Enable DDC
>
> +} DDI_CONFIGURATION;
>
> +
>
> +/**
>
> + This Configuration block is to configure GT related PreMem
> data/variables.\n
>
> + <b>Revision 1</b>:
>
> + - Initial version.
>
> + <b>Revision 2</b>:
>
> + - Added DfdRestoreEnable.
>
> + <b>Revision 3</b>:
>
> + - Added DdiConfiguration.
>
> + <b>Revision 4</b>:
>
> + - Added GmAdr64 and made GmAdr obselete
>
> +**/
>
> +typedef struct {
>
> + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block
> Header
>
> + /**
>
> + Offset 28
>
> + Selection of the primary display device: 0=iGFX, 1=PEG, 2=PCIe Graphics
> on PCH, <b>3=AUTO</b>, 4=Switchable Graphics\n
>
> + When AUTO mode selected, the priority of display devices is: PCIe
> Graphics on PCH > PEG > iGFX
>
> + **/
>
> + UINT8 PrimaryDisplay;
>
> + /**
>
> + Offset 29
>
> + Intel Gfx Support. It controls enabling/disabling iGfx device.
>
> + When AUTO mode selected, iGFX will be turned off when external
> graphics detected.
>
> + If FALSE, all other polices can be ignored.
>
> + <b>2 = AUTO</b>;
>
> + 0 = FALSE;
>
> + 1 = TRUE.
>
> + **/
>
> + UINT8 InternalGraphics;
>
> + /**
>
> + Offset 30
>
> + Pre-allocated memory for iGFX\n
>
> + 0 = 0MB,1 or 247 = 32MB,\n
>
> + 2 = 64MB,\n
>
> + 240 = 4MB, 241 = 8MB,\n
>
> + 242 = 12MB, 243 = 16MB,\n
>
> + 244 = 20MB, 245 = 24MB,\n
>
> + 246 = 28MB, 248 = 36MB,\n
>
> + 249 = 40MB, 250 = 44MB,\n
>
> + 251 = 48MB, 252 = 52MB,\n
>
> + 253 = 56MB,<b> 254 = 60MB</b>,\n
>
> + <b>Note: enlarging pre-allocated memory for iGFX may need to reduce
> MmioSize because of 4GB boundary limitation</b>
>
> + **/
>
> + UINT16 IgdDvmt50PreAlloc;
>
> + UINT8 PanelPowerEnable; ///< Offset 32 :<b>(Test)</b> Control
> for enabling/disabling VDD force bit (Required only for early enabling of eDP
> panel): 0=FALSE, <b>1=TRUE</b>
>
> + UINT8 ApertureSize; ///< Offset 33 :Graphics aperture size
> (256MB is the recommended size as per BWG) : 0=128MB,
> <b>1=256MB</b>, 3=512MB, 7=1024MB, 15=2048MB.
>
> + UINT8 GtPsmiSupport; ///< Offset 34 :PSMI support On/Off:
> <b>0=FALSE</b>, 1=TRUE
>
> + UINT8 PsmiRegionSize; ///< Offset 35 :Psmi region size:
> <b>0=32MB</b>, 1=288MB, 2=544MB, 3=800MB, 4=1056MB
>
> + UINT8 DismSize; ///< Offset 36 :DiSM Size for 2LM Sku:
> <b>0=0GB</b>, 1=1GB, 2=2GB, 3=3GB, 4=4GB, 5=5GB, 6=6GB, 7=7GB
>
> + UINT8 DfdRestoreEnable; ///< Offset 37 :Display memory map
> programming for DFD Restore <b>0- Disable</b>, 1- Enable
>
> + UINT16 GttSize; ///< Offset 38 :Selection of iGFX GTT Memory
> size: 1=2MB, 2=4MB, <b>3=8MB</b>
>
> + /**
>
> + Offset 40
>
> + Temp Address of System Agent GTTMMADR: Default is
> <b>0xAF000000</b>
>
> + **/
>
> + UINT32 GttMmAdr;
>
> + UINT32 GmAdr; ///< Offset 44 Obsolete not to be used, use
> GmAdr64
>
> + DDI_CONFIGURATION DdiConfiguration; ///< Offset 48 DDI
> configuration, need to match with VBT settings.
>
> +
>
> + UINT8 GtClosEnable; ///< Offset 50 Gt ClOS
>
> + UINT8 Rsvd0[7]; ///< Offset 51 Reserved for 4 bytes of
> alignment
>
> + /**
>
> + Offset 58
>
> + Temp Address of System Agent GMADR: Default is <b>0xB0000000</b>
>
> + **/
>
> + UINT64 GmAdr64;
>
> +} GRAPHICS_PEI_PREMEM_CONFIG;
>
> +
>
> +/**
>
> + This configuration block is to configure IGD related variables used in
> PostMem PEI.
>
> + If Intel Gfx Device is not supported, all policies can be ignored.
>
> + <b>Revision 1</b>:
>
> + - Initial version.
>
> + <b>Revision 2</b>:
>
> + - Removed DfdRestoreEnable.
>
> + <b>Revision 3</b>:
>
> + - Removed DdiConfiguration.
>
> + <b>Revision 4</b>:
>
> + - Added new CdClock frequency
>
> + <b>Revision 5</b>:
>
> + - Added GT Chicket bits
>
> + <b>Revision 6</b>:
>
> + - Added LogoPixelHeight and LogoPixelWidth
>
> + <b>Revision 7</b>:
>
> + - Added SkipFspGop
>
> +
>
> +**/
>
> +typedef struct {
>
> + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block
> Header
>
> + UINT8 RenderStandby; ///< Offset 28 :<b>(Test)</b> This field
> is used to enable or disable RC6 (Render Standby): 0=FALSE, <b>1=TRUE</b>
>
> + UINT8 PmSupport; ///< Offset 29 :<b>(Test)</b> IGD PM
> Support TRUE/FALSE: 0=FALSE, <b>1=TRUE</b>
>
> + /**
>
> + Offset 30
>
> + CdClock Frequency select\n
>
> + <b>0xFF = Auto. Max CdClock freq based on Reference Clk</b> \n
>
> + 0: 192 Mhz, 1: 307.2 Mhz, 2: 312 Mhz, 3: 324 Mhz, 4: 326.4 Mhz, 5: 552
> Mhz, 6: 556.8 Mhz, 7: 648 Mhz, 8: 652.8 Mhz
>
> +
>
> + **/
>
> + UINT16 CdClock;
>
> + UINT8 PeiGraphicsPeimInit; ///< Offset 32 : This policy is used to
> enable/disable Intel Gfx PEIM.<b>0- Disable</b>, 1- Enable
>
> + UINT8 CdynmaxClampEnable; ///< Offset 33 : This policy is used to
> enable/disable CDynmax Clamping Feature (CCF) <b>1- Enable</b>, 0-
> Disable
>
> + UINT16 GtFreqMax; ///< Offset 34 : <b>(Test)</b> Max GT
> frequency limited by user in multiples of 50MHz: Default value which
> indicates normal frequency is <b>0xFF</b>
>
> + UINT8 DisableTurboGt; ///< Offset 36 : This policy is used to
> enable/disable DisableTurboGt <b>0- Disable</b>, 1- Enable
>
> + UINT8 SkipCdClockInit; ///< Offset 37 : SKip full CD clock
> initialization. <b>0- Disable</b>, 1- Enable
>
> + UINT8 RC1pFreqEnable; ///< Offset 38 : This policy is used to
> enable/disable RC1p Frequency. <b>0- Disable</b>, 1- Enable
>
> + UINT8 PavpEnable; ///< Offset 39 :IGD PAVP TRUE/FALSE:
> 0=FALSE, <b>1=TRUE</b>
>
> + VOID* LogoPtr; ///< Offset 40 Address of Intel Gfx PEIM
> Logo to be displayed
>
> + UINT32 LogoSize; ///< Offset 44 Intel Gfx PEIM Logo Size
>
> + VOID* GraphicsConfigPtr; ///< Offset 48 Address of the Graphics
> Configuration Table
>
> + VOID* BltBufferAddress; ///< Offset 52 Address of Blt buffer for
> PEIM Logo use
>
> + UINT32 BltBufferSize; ///< Offset 56 The size for Blt Buffer,
> calculating by PixelWidth * PixelHeight * 4 bytes (the size of
> EFI_GRAPHICS_OUTPUT_BLT_PIXEL)
>
> + UINT8 ProgramGtChickenBits; ///< Offset 60 Program GT Chicket
> bits in GTTMMADR + 0xD00 BITS [3:1].
>
> + UINT8 SkipFspGop; ///< Offset 61 This policy is used to skip
> PEIM GOP in FSP.<b>0- Use FSP provided GOP driver</b>, 1- Skip FSP
> provided GOP driver
>
> + UINT8 Rsvd1[2]; ///< Offset 62 Reserved for 4 bytes
> alignment
>
> + UINT32 LogoPixelHeight; ///< Offset 64 Address of
> LogoPixelHeight for PEIM Logo use
>
> + UINT32 LogoPixelWidth; ///< Offset 68 Address of
> LogoPixelWidth for PEIM Logo use
>
> +} GRAPHICS_PEI_CONFIG;
>
> +
>
> +/**
>
> + This configuration block is to configure IGD related variables used in DXE.
>
> + If Intel Gfx Device is not supported or disabled, all policies will be ignored.
>
> + The data elements should be initialized by a Platform Module.\n
>
> + <b>Revision 1</b>:
>
> + - Initial version.
>
> +**/
>
> +typedef struct {
>
> + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27: Config Block
> Header
>
> + UINT32 Size; ///< Offset 28 - 31: This field gives the size of
> the GOP VBT Data buffer
>
> + EFI_PHYSICAL_ADDRESS VbtAddress; ///< Offset 32 - 39: This field
> points to the GOP VBT data buffer
>
> + UINT8 PlatformConfig; ///< Offset 40: This field gives the
> Platform Configuration Information (0=Platform is S0ix Capable for ULT SKUs
> only, <b>1=Platform is not S0ix Capable</b>, 2=Force Platform is S0ix
> Capable for All SKUs)
>
> + UINT8 AlsEnable; ///< Offset 41: Ambient Light Sensor
> Enable: <b>0=Disable</b>, 2=Enable
>
> + UINT8 BacklightControlSupport; ///< Offset 42: Backlight Control
> Support: 0=PWM Inverted, <b>2=PWM Normal</b>
>
> + UINT8 IgdBootType; ///< Offset 43: IGD Boot Type CMOS
> option: <b>0=Default</b>, 0x01=CRT, 0x04=EFP, 0x08=LFP, 0x20=EFP3,
> 0x40=EFP2, 0x80=LFP2
>
> + UINT32 IuerStatusVal; ///< Offset 44 - 47: Offset 16 This field
> holds the current status of all the supported Ultrabook events (Intel(R)
> Ultrabook Event Status bits)
>
> + CHAR16 GopVersion[0x10]; ///< Offset 48 - 79:This field holds
> the GOP Driver Version. It is an Output Protocol and updated by the Silicon
> code
>
> + /**
>
> + Offset 80: IGD Panel Type CMOS option\n
>
> + <b>0=Default</b>, 1=640X480LVDS, 2=800X600LVDS, 3=1024X768LVDS,
> 4=1280X1024LVDS, 5=1400X1050LVDS1\n
>
> + 6=1400X1050LVDS2, 7=1600X1200LVDS, 8=1280X768LVDS,
> 9=1680X1050LVDS, 10=1920X1200LVDS, 13=1600X900LVDS\n
>
> + 14=1280X800LVDS, 15=1280X600LVDS, 16=2048X1536LVDS,
> 17=1366X768LVDS
>
> + **/
>
> + UINT8 IgdPanelType;
>
> + UINT8 IgdPanelScaling; ///< Offset 81: IGD Panel Scaling:
> <b>0=AUTO</b>, 1=OFF, 6=Force scaling
>
> + UINT8 IgdBlcConfig; ///< Offset 82: Backlight Control
> Support: 0=PWM Inverted, <b>2=PWM Normal</b>
>
> + UINT8 IgdDvmtMemSize; ///< Offset 83: IGD DVMT Memory
> Size: 1=128MB, <b>2=256MB</b>, 3=MAX
>
> + UINT8 GfxTurboIMON; ///< Offset 84: IMON Current Value:
> 14=Minimal, <b>31=Maximum</b>
>
> + UINT8 Reserved[3]; ///< Offset 85: Reserved for DWORD
> alignment.
>
> + UINT16 BCLM[MAX_BCLM_ENTRIES]; ///< Offset 88: IGD Backlight
> Brightness Level Duty cycle Mapping Table.
>
> +} GRAPHICS_DXE_CONFIG;
>
> +#pragma pack(pop)
>
> +
>
> +#endif // _GRAPHICS_CONFIG_H_
>
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Hda/HdAudioConfig.
> h
> b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Hda/HdAudioConfig.
> h
> new file mode 100644
> index 0000000000..a2e0a65e45
> --- /dev/null
> +++
> b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Hda/HdAudioConfig.
> h
> @@ -0,0 +1,227 @@
> +/** @file
>
> + HDAUDIO policy
>
> +
>
> + Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +**/
>
> +#ifndef _HDAUDIO_CONFIG_H_
>
> +#define _HDAUDIO_CONFIG_H_
>
> +
>
> +#include <ConfigBlock.h>
>
> +#include <PchLimits.h>
>
> +
>
> +#define HDAUDIO_PREMEM_CONFIG_REVISION 2
>
> +#define HDAUDIO_CONFIG_REVISION 1
>
> +#define HDAUDIO_DXE_CONFIG_REVISION 1
>
> +
>
> +extern EFI_GUID gHdAudioPreMemConfigGuid;
>
> +extern EFI_GUID gHdAudioConfigGuid;
>
> +extern EFI_GUID gHdAudioDxeConfigGuid;
>
> +
>
> +#pragma pack (push,1)
>
> +
>
> +///
>
> +/// The PCH_HDAUDIO_CONFIG block describes the expected configuration
> of the Intel HD Audio feature.
>
> +///
>
> +
>
> +#define HDAUDIO_VERB_TABLE_VIDDID(Vid,Did)
> (UINT32)((UINT16)Vid | ((UINT16)Did << 16))
>
> +#define HDAUDIO_VERB_TABLE_RID_SDI_SIZE(Rid,Sdi,VerbTableSize)
> (UINT32)((UINT8)Rid | ((UINT8)Sdi << 8) | ((UINT16)VerbTableSize << 16))
>
> +#define HDAUDIO_VERB_TABLE_CMD_SIZE(VerbTable) ((sizeof
> (VerbTable) - sizeof (HDA_VERB_TABLE_HEADER)) / (sizeof (UINT32)))
>
> +
>
> +///
>
> +/// Use this macro to create HDAUDIO_VERB_TABLE and populate size
> automatically
>
> +///
>
> +#define HDAUDIO_VERB_TABLE_INIT(Vid,Did,Rid,Sdi,...) \
>
> +{ \
>
> + { Vid, Did, Rid, Sdi, (sizeof((UINT32[]){__VA_ARGS__})/sizeof(UINT32)) }, \
>
> + { __VA_ARGS__ } \
>
> +}
>
> +
>
> +
>
> +/**
>
> + Azalia verb table header
>
> + Every verb table should contain this defined header and followed by azalia
> verb commands.
>
> +**/
>
> +typedef struct {
>
> + UINT16 VendorId; ///< Codec Vendor ID
>
> + UINT16 DeviceId; ///< Codec Device ID
>
> + UINT8 RevisionId; ///< Revision ID of the codec. 0xFF matches any
> revision.
>
> + UINT8 SdiNum; ///< SDI number, 0xFF matches any SDI.
>
> + UINT16 DataDwords; ///< Number of data DWORDs following the
> header.
>
> +} HDA_VERB_TABLE_HEADER;
>
> +
>
> +#ifdef _MSC_VER
>
> +//
>
> +// Disable "zero-sized array in struct/union" extension warning.
>
> +// Used for neater verb table definitions.
>
> +//
>
> +#pragma warning (push)
>
> +#pragma warning (disable: 4200)
>
> +#endif
>
> +typedef struct {
>
> + HDA_VERB_TABLE_HEADER Header;
>
> + UINT32 Data[];
>
> +} HDAUDIO_VERB_TABLE;
>
> +#ifdef _MSC_VER
>
> +#pragma warning (pop)
>
> +#endif
>
> +
>
> +typedef struct {
>
> + UINT32 ClkA; ///< Pin mux configuration. Refer to
> GPIO_*_MUXING_DMIC*_CLKA_*
>
> + UINT32 ClkB; ///< Pin mux configuration. Refer to
> GPIO_*_MUXING_DMIC*_CLKB_*
>
> + UINT32 Data; ///< Pin mux configuration. Refer to
> GPIO_*_MUXING_DMIC*_DATA_*
>
> +} HDA_DMIC_PIN_MUX;
>
> +
>
> +/**
>
> + HD Audio Link Policies
>
> +**/
>
> +typedef struct {
>
> + UINT32 Enable : 1; ///< HDA interface enable. When enabled related
> pins will be switched to native mode: <b>0: Disable</b>; 1: Enable.
>
> + UINT32 RsvdBits0 : 31;
>
> + UINT8 SdiEnable[PCH_MAX_HDA_SDI]; ///< HDA SDI signal enable.
> When enabled related SDI pins will be switched to appropriate native mode:
> <b>0: Disable</b>; 1: Enable
>
> + UINT8 Reserved[(4 - (PCH_MAX_HDA_SDI % 4)) % 4]; ///< Padding for
> SDI enable table.
>
> +} HDA_LINK_HDA;
>
> +
>
> +/**
>
> + HD Audio DMIC Interface Policies
>
> +**/
>
> +typedef struct {
>
> + UINT32 Enable : 1; ///< HDA DMIC interface enable. When
> enabled related pins will be switched to native mode: <b>0: Disable</b>; 1:
> Enable.
>
> + UINT32 DmicClockSelect : 2; ///< DMIC link clock select: <b>0:
> Both</b>, 1: ClkA, 2: ClkB; default is "Both"
>
> + UINT32 RsvdBits0 : 29;
>
> + HDA_DMIC_PIN_MUX PinMux; ///< Pin mux configuration.
>
> +} HDA_LINK_DMIC;
>
> +
>
> +/**
>
> + HD Audio SSP Interface Policies
>
> +**/
>
> +typedef struct {
>
> + UINT32 Enable : 1; ///< HDA SSP interface enable. When enabled
> related pins will be switched to native mode: <b>0: Disable</b>; 1: Enable.
>
> + UINT32 RsvdBits0 : 31;
>
> +} HDA_LINK_SSP;
>
> +
>
> +/**
>
> + HD Audio SNDW Interface Policies
>
> +**/
>
> +typedef struct {
>
> + UINT32 Enable : 1; ///< HDA SNDW interface enable. When
> enabled related pins will be switched to native mode: <b>0: Disable</b>; 1:
> Enable.
>
> + UINT32 RsvdBits0 : 31;
>
> +} HDA_LINK_SNDW;
>
> +
>
> +
>
> +/**
>
> + This structure contains the policies which are related to HD Audio device
> (cAVS).
>
> +
>
> + <b>Revision 1:</b>
>
> + - Inital version.
>
> +
>
> +**/
>
> +typedef struct {
>
> + CONFIG_BLOCK_HEADER Header; ///< Config Block Header
>
> + UINT32 Pme : 1; ///< Azalia wake-on-ring, <b>0: Disable</b>; 1:
> Enable
>
> + UINT32 CodecSxWakeCapability : 1; ///< Capability to detect wake
> initiated by a codec in Sx (eg by modem codec), <b>0: Disable</b>; 1: Enable
>
> + UINT32 HdAudioLinkFrequency : 4; ///< HDA-Link frequency
> (PCH_HDAUDIO_LINK_FREQUENCY enum): <b>2: 24MHz</b>, 1: 12MHz, 0:
> 6MHz
>
> + UINT32 RsvdBits0 : 26; ///< Reserved bits 0
>
> + /**
>
> + Number of the verb table entry defined in VerbTablePtr.
>
> + Each entry points to a verb table which contains HDAUDIO_VERB_TABLE
> structure and verb command blocks.
>
> + **/
>
> + UINT8 VerbTableEntryNum;
>
> + UINT8 Rsvd0[3]; ///< Reserved bytes, align to multiple 4
>
> + /**
>
> + Pointer to a verb table array.
>
> + This pointer points to 32bits address, and is only eligible and consumed in
> post mem phase.
>
> + Each entry points to a verb table which contains HDAUDIO_VERB_TABLE
> structure and verb command blocks.
>
> + The prototype of this is:
>
> + HDAUDIO_VERB_TABLE **VerbTablePtr;
>
> + **/
>
> + UINT32 VerbTablePtr;
>
> +} HDAUDIO_CONFIG;
>
> +
>
> +/**
>
> + This structure contains the premem policies which are related to HD Audio
> device (cAVS).
>
> +
>
> + <b>Revision 1:</b>
>
> + - Inital version.
>
> + <b>Revision 2:</b>
>
> + - Add DmicClockSelect
>
> +**/
>
> +typedef struct {
>
> + CONFIG_BLOCK_HEADER Header; ///< Config Block Header
>
> + UINT32 Enable : 1; ///< Intel HD Audio (Azalia) enablement: 0:
> Disable, <b>1: Enable</b>
>
> + UINT32 DspEnable : 1; ///< DSP enablement: 0: Disable; <b>1:
> Enable</b>
>
> + UINT32 VcType : 1; ///< Virtual Channel Type Select: <b>0:
> VC0</b>, 1: VC1
>
> + /**
>
> + Universal Audio Architecture compliance for DSP enabled system:
>
> + <b>0: Not-UAA Compliant (Intel SST driver supported only)</b>,
>
> + 1: UAA Compliant (HDA Inbox driver or SST driver supported)
>
> + **/
>
> + UINT32 DspUaaCompliance : 1;
>
> + UINT32 IDispLinkFrequency : 4; ///< iDisp-Link frequency
> (PCH_HDAUDIO_LINK_FREQUENCY enum): <b>4: 96MHz</b>, 3: 48MHz
>
> + UINT32 IDispLinkTmode : 3; ///< iDisp-Link T-Mode
> (PCH_HDAUDIO_IDISP_TMODE enum): <b>0: 2T</b>, 1: 1T, 2: 4T, 3: 8T, 4:
> 16T
>
> + UINT32 IDispCodecDisconnect : 1; ///< iDisplay Audio Codec
> disconnection, <b>0: Not disconnected, enumerable</b>; 1: Disconnected
> SDI, not enumerable
>
> + UINT32 PowerGatingSupported : 1; ///< Power Gating supported: <b>0:
> Not supported</b>, 1: Supported
>
> + UINT32 RsvdBits : 19; ///< Reserved bits 0
>
> +
>
> + /**
>
> + Audio Link Mode configuration bitmask.
>
> + Allows to configure enablement of the following interfaces: HDA-Link,
> DMIC, SSP, SoundWire.
>
> + **/
>
> +
>
> + HDA_LINK_HDA AudioLinkHda; ///< HDA-Link enablement: 0:
> Disable; <b>1: Enable</b>.
>
> + /**
>
> + DMIC link enablement: 0: Disable; <b>1: Enable</b>.
>
> + DMIC0 LKF: Muxed with SNDW2/SNDW4.
>
> + **/
>
> + HDA_LINK_DMIC AudioLinkDmic [2];
>
> + /**
>
> + I2S/SSP link enablement: <b>0: Disable</b>; 1: Enable.
>
> + SSP0/1 LKF: Muxed with HDA.
>
> + @note Since the I2S/SSP2 pin set contains pads which are also used for
> CNVi purpose, enabling AudioLinkSsp2
>
> + is exclusive with CNVi is present.
>
> + **/
>
> + HDA_LINK_SSP AudioLinkSsp [PCH_MAX_HDA_SSP_LINK_NUM];
>
> + /**
>
> + SoundWire link enablement: <b>0: Disable</b>; 1: Enable.
>
> + SNDW2 LKF: Muxed with DMIC0/DMIC1.
>
> + SNDW3 LKF: Muxed with DMIC1.
>
> + SNDW4 LKF: Muxed with DMIC0.
>
> + **/
>
> + HDA_LINK_SNDW AudioLinkSndw
> [PCH_MAX_HDA_SNDW_LINK_NUM];
>
> +
>
> +
>
> + UINT16 ResetWaitTimer; ///< <b>(Test)</b> The delay timer
> after Azalia reset, the value is number of microseconds. Default is
> <b>600</b>.
>
> + UINT8 Rsvd0[2]; ///< Reserved bytes, align to multiple 4
>
> +
>
> +} HDAUDIO_PREMEM_CONFIG;
>
> +
>
> +typedef struct {
>
> + UINT32 AutonomousClockStop : 1; ///< SoundWire1 link
> autonomous clock stop capability: <b>0: Disable</b>; 1: Enable
>
> + UINT32 DataOnActiveIntervalSelect : 2; ///< SoundWire1 link data on
> active interval select 0: 3 clock periods; <b>1: 4 clock periods</b>; 2: 5 clock
> periods; 3: 6 clock periods
>
> + UINT32 DataOnDelaySelect : 1; ///< SoundWire1 link data on delay
> select 0: 2 clock periods; <b>1: 3 clock periods</b>
>
> + UINT32 RsvdBits1 : 28; ///< Reserved bits 1
>
> +} HDAUDIO_SNDW_CONFIG;
>
> +
>
> +/**
>
> + This structure contains the DXE policies which are related to HD Audio
> device (cAVS).
>
> + <b>Revision 1:</b>
>
> + - Inital version.
>
> +**/
>
> +typedef struct {
>
> + CONFIG_BLOCK_HEADER Header; ///< Config Block Header
>
> + /**
>
> + SNDW configuration for exposed via SNDW ACPI tables:
>
> + **/
>
> + HDAUDIO_SNDW_CONFIG
> SndwConfig[PCH_MAX_HDA_SNDW_LINK_NUM];
>
> + /**
>
> + Bitmask of supported DSP features:
>
> + [BIT0] - WoV; [BIT1] - BT Sideband; [BIT2] - Codec VAD; [BIT5] - BT Intel
> HFP; [BIT6] - BT Intel A2DP
>
> + [BIT7] - DSP based speech pre-processing disabled; [BIT8] - 0: Intel WoV,
> 1: Windows Voice Activation
>
> + Default is <b>zero</b>.
>
> + **/
>
> + UINT32 DspFeatureMask;
>
> +} HDAUDIO_DXE_CONFIG;
>
> +
>
> +#pragma pack (pop)
>
> +
>
> +#endif // _HDAUDIO_CONFIG_H_
>
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/HostBridge/HostBrid
> geConfig.h
> b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/HostBridge/HostBrid
> geConfig.h
> new file mode 100644
> index 0000000000..67335be92e
> --- /dev/null
> +++
> b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/HostBridge/HostBrid
> geConfig.h
> @@ -0,0 +1,62 @@
> +/** @file
>
> + Configurations for HostBridge
>
> +
>
> + Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +**/
>
> +#ifndef _HOST_BRIDGE_CONFIG_H_
>
> +#define _HOST_BRIDGE_CONFIG_H_
>
> +
>
> +#include <ConfigBlock.h>
>
> +
>
> +#define HOST_BRIDGE_PREMEM_CONFIG_REVISION 1
>
> +#define HOST_BRIDGE_PEI_CONFIG_REVISION 1
>
> +
>
> +extern EFI_GUID gHostBridgePeiPreMemConfigGuid;
>
> +extern EFI_GUID gHostBridgePeiConfigGuid;
>
> +
>
> +#pragma pack (push,1)
>
> +
>
> +/**
>
> + This configuration block describes HostBridge settings in PreMem.\n
>
> + <b>Revision 1</b>:
>
> + - Initial version.
>
> +**/
>
> +typedef struct {
>
> + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block
> Header
>
> + UINT32 MchBar; ///< Offset 28 Address of System Agent
> MCHBAR: <b>0xFEDC0000(TGL)/0xFED10000(RKL)/0xFEA80000(JSL)<b>
>
> + UINT32 DmiBar; ///< Offset 32 Address of System Agent
> DMIBAR: <b>0xFEDA0000</b>
>
> + UINT32 EpBar; ///< Offset 36 Address of System Agent
> EPBAR: <b>0xFEDA1000</b>
>
> + UINT32 GdxcBar; ///< Offset 40 Address of System Agent
> GDXCBAR: <b>0xFED84000</b>
>
> + UINT32 RegBar; ///< Offset 44 Address of System Agent
> REGBAR: <b>0xFB000000</b>
>
> + UINT32 EdramBar; ///< Offset 48 Address of System Agent
> EDRAMBAR: <b>0xFED80000</b>
>
> + /**
>
> + Offset 52 :
>
> + Size of reserved MMIO space for PCI devices\n
>
> + <b>0=AUTO</b>, 512=512MB, 768=768MB, 1024=1024MB, 1280=1280MB,
> 1536=1536MB, 1792=1792MB,
>
> + 2048=2048MB, 2304=2304MB, 2560=2560MB, 2816=2816MB,
> 3072=3072MB\n
>
> + When AUTO mode selected, the MMIO size will be calculated by required
> MMIO size from PCIe devices detected.
>
> + **/
>
> + UINT32 MmioSize;
>
> + UINT32 MmioSizeAdjustment; ///< Offset 56 Increase (given
> positive value) or Decrease (given negative value) the Reserved MMIO size
> when Dynamic Tolud/AUTO mode enabled (in MBs): <b>0=no
> adjustment</b>
>
> + UINT8 EnableAbove4GBMmio; ///< Offset 60 Enable/disable
> above 4GB MMIO resource support: 0=Disable, <b>1=Enable</b>
>
> + UINT8 Reserved[3]; ///< Offset 61 Reserved for future use.
>
> +} HOST_BRIDGE_PREMEM_CONFIG;
>
> +
>
> +
>
> +/**
>
> + This configuration block describes HostBridge settings in Post-Mem.\n
>
> + <b>Revision 1</b>:
>
> + - Initial version.
>
> +**/
>
> +typedef struct {
>
> + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block
> Header
>
> + UINT8 Device4Enable; ///< Offser 28 :This policy is used to
> control enable or disable System Agent Thermal device (0,4,0).
> <b>0=FALSE</b>, 1=TRUE.
>
> + UINT8 ChapDeviceEnable; ///< Offset 29 :<b>(Test)</b>This
> policy is used to control enable or disable System Agent Chap device (0,7,0).
> <b>0=FALSE</b>, 1=TRUE.
>
> + UINT8 SkipPamLock; ///< Offset 30 :To skip PAM register
> locking. @note It is still recommended to set PCI Config space B0: D0: F0:
> Offset 80h[0]=1 in platform code even Silicon code skipped this.\n <b>0=All
> PAM registers will be locked in Silicon code</b>, 1=Skip lock PAM registers in
> Silicon code.
>
> + UINT8 EdramTestMode; ///< Offset 28 :EDRAM Test Mode. For
> EDRAM stepping - 0- EDRAM SW Disable, 1- EDRAM SW Enable, <b> 2-
> EDRAM HW Mode</b>
>
> +} HOST_BRIDGE_PEI_CONFIG;
>
> +
>
> +#pragma pack (pop)
>
> +
>
> +#endif
>
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/HybridGraphics/Hybr
> idGraphicsConfig.h
> b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/HybridGraphics/Hybr
> idGraphicsConfig.h
> new file mode 100644
> index 0000000000..3f420aed48
> --- /dev/null
> +++
> b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/HybridGraphics/Hybr
> idGraphicsConfig.h
> @@ -0,0 +1,66 @@
> +/** @file
>
> + Hybrid Graphics policy definitions
>
> +
>
> + Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +**/
>
> +#ifndef _HYBRID_GRAPHICS_CONFIG_H_
>
> +#define _HYBRID_GRAPHICS_CONFIG_H_
>
> +
>
> +#define HYBRID_GRAPHICS_CONFIG_REVISION 2
>
> +
>
> +#pragma pack(push, 1)
>
> +///
>
> +/// GPIO Support
>
> +///
>
> +typedef enum {
>
> + NotSupported = 0,
>
> + PchGpio,
>
> + I2CGpio,
>
> +} GPIO_SUPPORT;
>
> +
>
> +///
>
> +/// CPU PCIe GPIO Data Structure
>
> +///
>
> +typedef struct {
>
> + UINT8 ExpanderNo; ///< Offset 0 Expander No For I2C based GPIO
>
> + BOOLEAN Active; ///< Offset 1 0=Active Low; 1=Active High
>
> + UINT8 Rsvd0[2]; ///< Offset 2 Reserved
>
> + UINT32 GpioNo; ///< Offset 4 GPIO pad
>
> +} CPU_PCIE_GPIO_INFO;
>
> +
>
> +/**
>
> + CPU PCIE RTD3 GPIO Data Structure
>
> +**/
>
> +typedef struct {
>
> + CPU_PCIE_GPIO_INFO HoldRst; ///< Offset 0 This field contain PCIe HLD
> RESET GPIO value and level information
>
> + CPU_PCIE_GPIO_INFO PwrEnable; ///< Offset 8 This field contain PCIe
> PWR Enable GPIO value and level information
>
> + UINT32 WakeGpioNo; ///< Offset 16 This field contain PCIe RTD3
> Device Wake GPIO Number
>
> + UINT8 GpioSupport; ///< Offset 20 Depends on board design the
> GPIO configuration may be different: <b>0=Not Supported</b>, 1=PCH
> Based, 2=I2C based
>
> + UINT8 Rsvd0[3]; ///< Offset 21
>
> +} CPU_PCIE_RTD3_GPIO;
>
> +
>
> +/**
>
> + This Configuration block configures CPU PCI Express 0/1/2 RTD3 GPIOs &
> Root Port.
>
> + Hybrid Gfx uses the same GPIOs & Root port as PCI Express 0/1/2 RTD3.
>
> + <b>Revision 1</b>:
>
> + - Initial version.
>
> + <b>Revision 2</b>:
>
> + - Add HgSlot Policy: PEG or PCH Slot Slection for Hybrid Graphics
>
> +**/
>
> +typedef struct {
>
> + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block
> Header
>
> + CPU_PCIE_RTD3_GPIO CpuPcie0Rtd3Gpio; ///< Offset 28 RTD3 GPIOs
> used for PCIe
>
> + UINT8 RootPortIndex; ///< Offset 52 Root Port Index number
> used for HG
>
> + UINT8 HgMode; ///< Offset 53 HgMode:
> <b>0=Disabled</b>, 1=HG Muxed, 2=HG Muxless, 3=PEG
>
> + UINT16 HgSubSystemId; ///< Offset 54 Hybrid Graphics
> Subsystem ID: <b>2212</b>
>
> + UINT16 HgDelayAfterPwrEn; ///< Offset 56 Dgpu Delay after
> Power enable using Setup option: 0=Minimal, 1000=Maximum, <b>300=300
> microseconds</b>
>
> + UINT16 HgDelayAfterHoldReset; ///< Offset 58 Dgpu Delay after
> Hold Reset using Setup option: 0=Minimal, 1000=Maximum, <b>100=100
> microseconds</b>
>
> + CPU_PCIE_RTD3_GPIO CpuPcie1Rtd3Gpio; ///< Offset 60 RTD3 GPIOs
> used for PCIe
>
> + CPU_PCIE_RTD3_GPIO CpuPcie2Rtd3Gpio; ///< Offset 84 RTD3 GPIOs
> used for PCIe
>
> + CPU_PCIE_RTD3_GPIO CpuPcie3Rtd3Gpio; ///< Offset 108 RTD3 GPIOs
> used for PCIe
>
> + UINT8 HgSlot; ///< Offset 132 Slot selection between PEG
> and PCH
>
> + UINT8 Rsvd0[3]; ///< Offset 133 Reserved Bytes
>
> +} HYBRID_GRAPHICS_CONFIG;
>
> +#pragma pack(pop)
>
> +#endif // _HYBRID_GRAPHICS_CONFIG_H_
>
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/HybridStorage/Hybri
> dStorageConfig.h
> b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/HybridStorage/Hybri
> dStorageConfig.h
> new file mode 100644
> index 0000000000..705fe43751
> --- /dev/null
> +++
> b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/HybridStorage/Hybri
> dStorageConfig.h
> @@ -0,0 +1,36 @@
> +/** @file
>
> + Hybrid Storage policy
>
> +
>
> + Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +**/
>
> +#ifndef _HYBRID_STORAGE_CONFIG_H_
>
> +#define _HYBRID_STORAGE_CONFIG_H_
>
> +
>
> +#include <ConfigBlock.h>
>
> +
>
> +#define HYBRID_STORAGE_CONFIG_REVISION 1
>
> +
>
> +extern EFI_GUID gHybridStorageConfigGuid;
>
> +
>
> +#pragma pack (push,1)
>
> +
>
> +/**
>
> + The HYBRID_STORAGE_CONFIG block describes the expected
> configuration for Hybrid Storage device
>
> +
>
> + <b>Revision 1</b>:
>
> + - Init version
>
> +**/
>
> +typedef struct {
>
> + CONFIG_BLOCK_HEADER Header; ///< Config Block Header
>
> + /**
>
> + Hybrid Storage Mode
>
> + <b>0: Disable</b>, 1: Enable Dynamic Configuration
>
> + **/
>
> + UINT8 HybridStorageMode;
>
> + UINT8 RsvdBytes[3];
>
> +} HYBRID_STORAGE_CONFIG;
>
> +
>
> +#pragma pack (pop)
>
> +
>
> +#endif // _HYBRID_STORAGE_CONFIG_H_
>
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Ieh/IehConfig.h
> b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Ieh/IehConfig.h
> new file mode 100644
> index 0000000000..a9275152f5
> --- /dev/null
> +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Ieh/IehConfig.h
> @@ -0,0 +1,34 @@
> +/** @file
>
> + Integrated Error Handler policy.
>
> +
>
> + Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +**/
>
> +
>
> +#ifndef _IEH_CONFIG_H_
>
> +#define _IEH_CONFIG_H_
>
> +
>
> +#define IEH_MODE_BYPASS 0
>
> +#define IEH_MODE_ENABLE 1
>
> +
>
> +#define IEH_CONFIG_REVISION 1
>
> +extern EFI_GUID gIehConfigGuid;
>
> +
>
> +#pragma pack (push,1)
>
> +
>
> +/**
>
> + The IEH_CONFIG block describes the expected configuration of the PCH
>
> + Integrated Error Handler.
>
> +**/
>
> +typedef struct {
>
> + CONFIG_BLOCK_HEADER Header; ///< Config Block Header
>
> + /**
>
> + IEH mode <b>0: Bypass Mode</b>; 1: Enable
>
> + **/
>
> + UINT32 Mode : 1;
>
> + UINT32 RsvdBits0 : 31; ///< Reserved bits
>
> +} IEH_CONFIG;
>
> +
>
> +#pragma pack (pop)
>
> +
>
> +#endif // _IEH_CONFIG_H_
>
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Ish/IshConfig.h
> b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Ish/IshConfig.h
> new file mode 100644
> index 0000000000..75a11e3052
> --- /dev/null
> +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Ish/IshConfig.h
> @@ -0,0 +1,134 @@
> +/** @file
>
> + ISH policy
>
> +
>
> + Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +**/
>
> +#ifndef _ISH_CONFIG_H_
>
> +#define _ISH_CONFIG_H_
>
> +
>
> +#define ISH_PREMEM_CONFIG_REVISION 1
>
> +#define ISH_CONFIG_REVISION 1
>
> +extern EFI_GUID gIshPreMemConfigGuid;
>
> +extern EFI_GUID gIshConfigGuid;
>
> +
>
> +#pragma pack (push,1)
>
> +
>
> +/**
>
> + ISH GPIO settings
>
> +**/
>
> +typedef struct {
>
> + /**
>
> + GPIO signals pin muxing settings. If signal can be enable only on a single
> pin
>
> + then this parameter should be set to 0. Refer to
> GPIO_*_MUXING_ISH_*x_* in GpioPins*.h
>
> + for supported settings on a given platform
>
> + **/
>
> + UINT32 PinMux; ///< GPIO Pin mux configuration. Refer to
> GPIO_*_MUXING_ISH_*x_MOSI_*
>
> + /**
>
> + GPIO Pads Internal Termination.
>
> + For more information please see Platform Design Guide.
>
> + Check GPIO_ELECTRICAL_CONFIG for reference
>
> + **/
>
> + UINT32 PadTermination;
>
> +} ISH_GPIO_CONFIG;
>
> +
>
> +/**
>
> + SPI signals settings.
>
> +**/
>
> +typedef struct {
>
> + ISH_GPIO_CONFIG Mosi; ///< MOSI Pin configuration.
>
> + ISH_GPIO_CONFIG Miso; ///< MISO Pin configuration.
>
> + ISH_GPIO_CONFIG Clk; ///< CLK Pin configuration.
>
> + ISH_GPIO_CONFIG Cs[PCH_MAX_ISH_SPI_CS_PINS]; ///< CS Pin
> configuration.
>
> +} ISH_SPI_PIN_CONFIG;
>
> +
>
> +
>
> +/**
>
> + UART signals settings.
>
> +**/
>
> +typedef struct {
>
> + ISH_GPIO_CONFIG Rx; ///< RXD Pin configuration.
>
> + ISH_GPIO_CONFIG Tx; ///< TXD Pin configuration.
>
> + ISH_GPIO_CONFIG Rts; ///< RTS Pin configuration.
>
> + ISH_GPIO_CONFIG Cts; ///< CTS Pin configuration.
>
> +} ISH_UART_PIN_CONFIG;
>
> +
>
> +
>
> +/**
>
> + I2C signals settings.
>
> +**/
>
> +typedef struct {
>
> + ISH_GPIO_CONFIG Sda; ///< SDA Pin configuration.
>
> + ISH_GPIO_CONFIG Scl; ///< SCL Pin configuration.
>
> +} ISH_I2C_PIN_CONFIG;
>
> +
>
> +
>
> +/**
>
> + Struct contains GPIO pins assigned and signal settings of SPI
>
> +**/
>
> +typedef struct {
>
> + UINT8 Enable; ///< ISH SPI GPIO pins assigned: <b>0:
> False</b> 1: True
>
> + UINT8 CsEnable[PCH_MAX_ISH_SPI_CS_PINS]; ///< ISH SPI CS pins
> assigned: <b>0: False</b> 1: True
>
> + UINT16 RsvdField0; ///< Reserved field
>
> + ISH_SPI_PIN_CONFIG PinConfig;
>
> +} ISH_SPI;
>
> +
>
> +
>
> +/**
>
> + Struct contains GPIO pins assigned and signal settings of UART
>
> +**/
>
> +typedef struct {
>
> + UINT32 Enable : 1; ///< ISH UART GPIO pins assigned: <b>0:
> False</b> 1: True
>
> + UINT32 RsvdBits0 : 31; ///< Reserved Bits
>
> + ISH_UART_PIN_CONFIG PinConfig;
>
> +} ISH_UART;
>
> +
>
> +/**
>
> + Struct contains GPIO pins assigned and signal settings of I2C
>
> +**/
>
> +typedef struct {
>
> + UINT32 Enable : 1; ///< ISH I2C GPIO pins assigned: <b>0:
> False</b> 1: True
>
> + UINT32 RsvdBits0 : 31; ///< Reserved Bits
>
> + ISH_I2C_PIN_CONFIG PinConfig;
>
> +} ISH_I2C;
>
> +
>
> +/**
>
> + Struct contains GPIO pins assigned and signal settings of GP
>
> +**/
>
> +typedef struct {
>
> + UINT32 Enable : 1; ///< ISH GP GPIO pins assigned: <b>0:
> False</b> 1: True
>
> + UINT32 RsvdBits0 : 31; ///< Reserved Bits
>
> + ISH_GPIO_CONFIG PinConfig;
>
> +} ISH_GP;
>
> +
>
> +///
>
> +/// The ISH_CONFIG block describes Integrated Sensor Hub device.
>
> +///
>
> +typedef struct {
>
> + CONFIG_BLOCK_HEADER Header; ///< Config Block Header
>
> + ISH_SPI Spi[PCH_MAX_ISH_SPI_CONTROLLERS];
>
> + ISH_UART Uart[PCH_MAX_ISH_UART_CONTROLLERS];
>
> + ISH_I2C I2c[PCH_MAX_ISH_I2C_CONTROLLERS];
>
> + ISH_GP Gp[PCH_MAX_ISH_GP_PINS];
>
> +
>
> + UINT32 PdtUnlock : 1; ///< ISH PDT Unlock Msg: <b>0:
> False</b> 1: True
>
> + UINT32 RsvdBits0 : 31; ///< Reserved Bits
>
> +
>
> +} ISH_CONFIG;
>
> +
>
> +///
>
> +/// Premem Policy for Integrated Sensor Hub device.
>
> +///
>
> +typedef struct {
>
> + CONFIG_BLOCK_HEADER Header; ///< Config Block Header
>
> + /**
>
> + ISH Controler 0: Disable; <b>1: Enable</b>.
>
> + For Desktop sku, the ISH POR should be disabled. <b> 0:Disable </b>.
>
> + **/
>
> + UINT32 Enable : 1;
>
> + UINT32 RsvdBits0 : 31; ///< Reserved Bits
>
> +} ISH_PREMEM_CONFIG;
>
> +
>
> +#pragma pack (pop)
>
> +
>
> +#endif // _ISH_CONFIG_H_
>
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Itss/InterruptConfig.
> h
> b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Itss/InterruptConfig.
> h
> new file mode 100644
> index 0000000000..7f6fa8675b
> --- /dev/null
> +++
> b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Itss/InterruptConfig.
> h
> @@ -0,0 +1,58 @@
> +/** @file
>
> + Interrupt policy
>
> +
>
> + Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +**/
>
> +#ifndef _INTERRUPT_CONFIG_H_
>
> +#define _INTERRUPT_CONFIG_H_
>
> +
>
> +#define INTERRUPT_CONFIG_REVISION 1
>
> +extern EFI_GUID gInterruptConfigGuid;
>
> +
>
> +#pragma pack (push,1)
>
> +
>
> +//
>
> +// --------------------- Interrupts Config ------------------------------
>
> +//
>
> +typedef enum {
>
> + PchNoInt, ///< No Interrupt Pin
>
> + PchIntA,
>
> + PchIntB,
>
> + PchIntC,
>
> + PchIntD
>
> +} PCH_INT_PIN;
>
> +
>
> +///
>
> +/// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin,
> IRQ and interrupt mode for PCH device.
>
> +///
>
> +typedef struct {
>
> + UINT8 Device; ///< Device number
>
> + UINT8 Function; ///< Device function
>
> + UINT8 IntX; ///< Interrupt pin: INTA-INTD (see PCH_INT_PIN)
>
> + UINT8 Irq; ///< IRQ to be set for device.
>
> +} PCH_DEVICE_INTERRUPT_CONFIG;
>
> +
>
> +#define PCH_MAX_DEVICE_INTERRUPT_CONFIG 128 ///< Number of all
> PCH devices
>
> +#define PCH_MAX_PXRC_CONFIG 8 ///< Number of PXRC
> registers in ITSS
>
> +#define PCH_MAX_ITSS_IPC_REGS 4 ///< Number of IPC registers
> in ITSS
>
> +#define PCH_MAX_ITSS_IRQ_NUM 120 ///< Maximum number of
> IRQs
>
> +
>
> +
>
> +///
>
> +/// The PCH_INTERRUPT_CONFIG block describes interrupt settings for
> PCH.
>
> +///
>
> +typedef struct {
>
> + CONFIG_BLOCK_HEADER Header; ///< Config
> Block Header
>
> + UINT8 NumOfDevIntConfig; ///< Number of
> entries in DevIntConfig table
>
> + UINT8 Rsvd0[3]; ///< Reserved bytes, align
> to multiple 4.
>
> + PCH_DEVICE_INTERRUPT_CONFIG
> DevIntConfig[PCH_MAX_DEVICE_INTERRUPT_CONFIG]; ///< Array which
> stores PCH devices interrupts settings
>
> + UINT8 GpioIrqRoute; ///< Interrupt routing
> for GPIO. Default is <b>14</b>.
>
> + UINT8 SciIrqSelect; ///< Interrupt select for
> SCI. Default is <b>9</b>.
>
> + UINT8 TcoIrqSelect; ///< Interrupt select for
> TCO. Default is <b>9</b>.
>
> + UINT8 TcoIrqEnable; ///< Enable IRQ
> generation for TCO. <b>0: Disable</b>; 1: Enable.
>
> +} PCH_INTERRUPT_CONFIG;
>
> +
>
> +#pragma pack (pop)
>
> +
>
> +#endif // _INTERRUPT_CONFIG_H_
>
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Itss/IoApicConfig.h
> b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Itss/IoApicConfig.h
> new file mode 100644
> index 0000000000..726a27f7a1
> --- /dev/null
> +++
> b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Itss/IoApicConfig.h
> @@ -0,0 +1,60 @@
> +/** @file
>
> + IoApic policy
>
> +
>
> + Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +**/
>
> +#ifndef _IOAPIC_CONFIG_H_
>
> +#define _IOAPIC_CONFIG_H_
>
> +
>
> +#define IOAPIC_CONFIG_REVISION 1
>
> +extern EFI_GUID gIoApicConfigGuid;
>
> +
>
> +#pragma pack (push,1)
>
> +
>
> +/**
>
> + The PCH_IOAPIC_CONFIG block describes the expected configuration of
> the PCH
>
> + IO APIC, it's optional and PCH code would ignore it if the BdfValid bit is
>
> + not TRUE. Bus:device:function fields will be programmed to the register
>
> + P2SB IBDF(P2SB PCI offset R6Ch-6Dh), it's using for the following purpose:
>
> + As the Requester ID when initiating Interrupt Messages to the processor.
>
> + As the Completer ID when responding to the reads targeting the IOxAPI's
>
> + Memory-Mapped I/O registers.
>
> + This field defaults to Bus 0: Device 31: Function 0 after reset. BIOS can
>
> + program this field to provide a unique Bus:Device:Function number for the
>
> + internal IOxAPIC.
>
> + The address resource range of IOAPIC must be reserved in E820 and ACPI
> as
>
> + system resource.
>
> +**/
>
> +typedef struct {
>
> + CONFIG_BLOCK_HEADER Header; ///< Config Block Header
>
> + UINT32 IoApicEntry24_119 : 1; ///< 0: Disable; <b>1: Enable</b>
> IOAPIC Entry 24-119
>
> + /**
>
> + Enable 8254 Static Clock Gating during early POST time. 0: Disable, <b>1:
> Enable</b>
>
> + Setting 8254CGE is required to support SLP_S0.
>
> + Enable this if 8254 timer is not used.
>
> + However, set 8254CGE=1 in POST time might fail to boot legacy OS using
> 8254 timer.
>
> + Make sure it is disabled to support legacy OS using 8254 timer.
>
> + @note:
>
> + For some OS environment that it needs to set 8254CGE in late state it
> should
>
> + set this policy to FALSE and use ItssSet8254ClockGateState (TRUE) in
> SMM later.
>
> + This is also required during S3 resume.
>
> + To avoid SMI requirement in S3 reusme path, it can enable the
> Enable8254ClockGatingOnS3
>
> + and RC will do 8254 CGE programming in PEI during S3 resume with
> BOOT_SAI.
>
> + **/
>
> + UINT32 Enable8254ClockGating : 1;
>
> + /**
>
> + Enable 8254 Static Clock Gating on S3 resume path. 0: Disable, <b>1:
> Enable</b>
>
> + This is only applicable when Enable8254ClockGating is disabled.
>
> + If Enable8254ClockGating is enabled, RC will do the 8254 CGE
> programming on
>
> + S3 resume path as well.
>
> + **/
>
> + UINT32 Enable8254ClockGatingOnS3 : 1;
>
> + UINT32 RsvdBits1 : 29; ///< Reserved bits
>
> + UINT8 IoApicId; ///< This member determines IOAPIC ID.
> Default is <b>0x02</b>.
>
> + UINT8 Rsvd0[3]; ///< Reserved bytes
>
> +} PCH_IOAPIC_CONFIG;
>
> +
>
> +#pragma pack (pop)
>
> +
>
> +#endif // _IOAPIC_CONFIG_H_
>
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Me/MePeiConfig.h
> b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Me/MePeiConfig.h
> new file mode 100644
> index 0000000000..82786501f0
> --- /dev/null
> +++
> b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Me/MePeiConfig.h
> @@ -0,0 +1,117 @@
> +/** @file
>
> + ME config block for PEI phase
>
> +
>
> + Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +**/
>
> +#ifndef _ME_PEI_CONFIG_H_
>
> +#define _ME_PEI_CONFIG_H_
>
> +
>
> +#define ME_PEI_PREMEM_CONFIG_REVISION 2
>
> +extern EFI_GUID gMePeiPreMemConfigGuid;
>
> +
>
> +#ifndef PLATFORM_POR
>
> +#define PLATFORM_POR 0
>
> +#endif
>
> +#ifndef FORCE_ENABLE
>
> +#define FORCE_ENABLE 1
>
> +#endif
>
> +#ifndef FORCE_DISABLE
>
> +#define FORCE_DISABLE 2
>
> +#endif
>
> +
>
> +#pragma pack (push,1)
>
> +
>
> +/**
>
> + ME Pei Pre-Memory Configuration Structure.
>
> +
>
> + <b>Revision 1:</b>
>
> + - Initial version.
>
> + <b>Revision 2:</b>
>
> + - Add SkipCpuReplacementCheck Option.
>
> + <b>Revision 3:</b>
>
> + - Deprecate SendDidMsg.
>
> +**/
>
> +typedef struct {
>
> + CONFIG_BLOCK_HEADER Header; ///< Config Block Header
>
> + UINT32 HeciTimeouts : 1; ///< 0: Disable; <b>1: Enable</b> -
> HECI Send/Receive Timeouts.
>
> + /**
>
> + <b>(Test)</b>
>
> + <b>0: Disabled</b>
>
> + 1: ME DID init stat 0 - Success
>
> + 2: ME DID init stat 1 - No Memory in Channels
>
> + 3: ME DID init stat 2 - Memory Init Error
>
> + **/
>
> + UINT32 DidInitStat : 2;
>
> + /**
>
> + <b>(Test)</b>
>
> + <b>0: Set to 0 to enable polling for CPU replacement</b>
>
> + 1: Set to 1 will disable polling for CPU replacement
>
> + **/
>
> + UINT32 DisableCpuReplacedPolling : 1;
>
> + UINT32 SendDidMsg : 1; ///< <b>(Deprecated)</b> 0: Disable;
> <b>1: Enable</b> - Enable/Disable to send DID message.
>
> + /**
>
> + <b>(Test)</b>
>
> + <b>0: ME BIOS will check each messages before sending</b>
>
> + 1: ME BIOS always sends messages without checking
>
> + **/
>
> + UINT32 DisableMessageCheck : 1;
>
> + /**
>
> + <b>(Test)</b>
>
> + The SkipMbpHob policy determines whether ME BIOS Payload data will
> be requested during boot
>
> + in a MBP message. If set to 1, BIOS will send the MBP message with
> SkipMbp flag
>
> + set causing CSME to respond with MKHI header only and no MBP data
>
> + <b>0: ME BIOS will keep MBP and create HOB for MBP data</b>
>
> + 1: ME BIOS will skip MBP data
>
> + **/
>
> + UINT32 SkipMbpHob : 1;
>
> + UINT32 HeciCommunication2 : 1; ///< <b>(Test)</b> <b>0:
> Disable</b>; 1: Enable - Enable/Disable HECI2.
>
> + UINT32 KtDeviceEnable : 1; ///< <b>(Test)</b> 0: Disable; <b>1:
> Enable</b> - Enable/Disable Kt Device.
>
> + UINT32 SkipCpuReplacementCheck : 1; ///< <b>(Test)</b> <b>0:
> Disable</b>; 1: Enable - Enable/Disable to skip CPU replacement check.
>
> + UINT32 RsvdBits : 22; ///< Reserved for future use & Config
> block alignment
>
> + UINT32 Heci1BarAddress; ///< HECI1 BAR address.
>
> + UINT32 Heci2BarAddress; ///< HECI2 BAR address.
>
> + UINT32 Heci3BarAddress; ///< HECI3 BAR address.
>
> +} ME_PEI_PREMEM_CONFIG;
>
> +#pragma pack (pop)
>
> +
>
> +
>
> +#define ME_PEI_CONFIG_REVISION 3
>
> +extern EFI_GUID gMePeiConfigGuid;
>
> +
>
> +#pragma pack (push,1)
>
> +
>
> +/**
>
> + ME Pei Post-Memory Configuration Structure.
>
> +
>
> + <b>Revision 1:</b>
>
> + - Initial version.
>
> + <b>Revision 2</b>:
>
> + - Deprecated Heci3Enabled.
>
> + <b>Revision 3</b>
>
> + - Added EnforceEDebugMode.
>
> +**/
>
> +
>
> +typedef struct {
>
> + CONFIG_BLOCK_HEADER Header; ///< Config Block Header
>
> +
>
> + UINT32 EndOfPostMessage : 2; ///< 0: Disabled; 1: Send in PEI;
> <b>2: Send in DXE</b> - Send EOP at specific phase.
>
> + UINT32 Heci3Enabled : 1; ///< @deprecated
>
> + UINT32 DisableD0I3SettingForHeci : 1; ///< <b>(Test)</b> <b>0:
> Disable</b>; 1: Enable - Enable/Disable D0i3 for HECI.
>
> + /**
>
> + Enable/Disable Me Unconfig On Rtc Clear. If enabled, BIOS will send
> MeUnconfigOnRtcClearDisable Msg with parameter 0.
>
> + It will cause ME to unconfig if RTC is cleared.
>
> + - 0: Disable
>
> + - <b>1: Enable</b>
>
> + - 2: Cmos is clear, status unkonwn
>
> + - 3: Reserved
>
> + **/
>
> + UINT32 MeUnconfigOnRtcClear : 2;
>
> + UINT32 MctpBroadcastCycle : 1; ///< <b>(Test)</b> <b>0:
> Disable</b>; 1: Enable - Program registers for MCTP Cycle.
>
> + UINT32 EnforceEDebugMode : 1; ///< <b>0: Disable</b>; 1:
> Enable - Enforces ME to enter Enhanced Debug Mode
>
> + UINT32 RsvdBits : 24; ///< Reserved for future use & Config
> block alignment
>
> +} ME_PEI_CONFIG;
>
> +
>
> +#pragma pack (pop)
>
> +
>
> +#endif // _ME_PEI_CONFIG_H_
>
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Memory/Ver2/Mem
> oryConfig.h
> b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Memory/Ver2/Mem
> oryConfig.h
> new file mode 100644
> index 0000000000..17c0a10eee
> --- /dev/null
> +++
> b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Memory/Ver2/Mem
> oryConfig.h
> @@ -0,0 +1,478 @@
> +/** @file
>
> + Policy definition of Memory Config Block
>
> +
>
> + Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +**/
>
> +#ifndef _MEMORY_CONFIG_H_
>
> +#define _MEMORY_CONFIG_H_
>
> +
>
> +
>
> +#pragma pack(push, 1)
>
> +
>
> +// MEMORY_CONFIG_REVISION 3 adds DDR5 PDA Enumeration training
> within MEMORY_CONFIGURATION
>
> +// MEMORY_CONFIG_REVISION 4 adds LPDDR4 Command Mirroring within
> MEMORY_CONFIGURATION
>
> +// MEMORY_CONFIG_REVISION 5 adds CpuBclkSpread option within
> MEMORY_CONFIGURATION
>
> +// MEMORY_CONFIG_REVISION 6 adds McParity option within
> MEMORY_CONFIGURATION
>
> +// MEMORY_CONFIG_REVISION 7 adds VddqVoltageOverride option within
> MEMORY_CONFIGURATION
>
> +// MEMORY_CONFIG_REVISION 8 adds ExtendedBankHashing option
> within MEMORY_CONFIGURATION
>
> +// MEMORY_CONFIG_REVISION 9 adds IbeccErrorInj option within
> MEMORY_CONFIGURATION
>
> +#define MEMORY_CONFIG_REVISION 9
>
> +///
>
> +/// MEMORY_CONFIG interface definitions
>
> +///
>
> +#define MRC_MAX_RCOMP_TARGETS 5
>
> +///
>
> +/// Memory SubSystem Definitions
>
> +///
>
> +#define MEM_CFG_MAX_CONTROLLERS 2
>
> +#define MEM_CFG_MAX_CHANNELS 4
>
> +#define MEM_CFG_MAX_CHANNEL_SHARE_REGS 2
>
> +#define MEM_CFG_MAX_DIMMS 2
>
> +#define MEM_CFG_MAX_RANKS_PER_DIMM 2
>
> +#define MEM_CFG_NUM_BYTES_MAPPED 2
>
> +#define MEM_CFG_MAX_SPD_SIZE 1024
>
> +#define MEM_CFG_MAX_SOCKETS
> (MEM_CFG_MAX_CONTROLLERS * MEM_CFG_MAX_CHANNELS *
> MEM_CFG_MAX_DIMMS)
>
> +#define MEM_CFG_MAX_ROWS
> (MEM_CFG_MAX_RANKS_PER_DIMM * MEM_CFG_MAX_SOCKETS)
>
> +#ifndef MEM_MAX_SAGV_POINTS
>
> +#define MEM_MAX_SAGV_POINTS 4
>
> +#endif
>
> +#define MEM_MAX_IBECC_REGIONS 8
>
> +///
>
> +/// SMRAM Memory Range
>
> +///
>
> +#define PEI_MR_SMRAM_ABSEG_MASK 0x01
>
> +#define PEI_MR_SMRAM_HSEG_MASK 0x02
>
> +
>
> +///
>
> +/// SA SPD profile selections.
>
> +///
>
> +typedef enum {
>
> + Default, ///< 0, Default SPD
>
> + UserDefined, ///< 1, User Defined profile
>
> + XMPProfile1, ///< 2, XMP Profile 1
>
> + XMPProfile2, ///< 3, XMP Profile 2
>
> + XMPProfileMax = 0xFF ///< Ensures SA_SPD is UINT8
>
> +} SA_SPD;
>
> +
>
> +///
>
> +/// Define the boot modes used by the SPD read function.
>
> +///
>
> +typedef enum {
>
> + SpdCold, ///< Cold boot
>
> + SpdWarm, ///< Warm boot
>
> + SpdS3, ///< S3 resume
>
> + SpdFast, ///< Fast boot
>
> + SpdBootModeMax ///< Delimiter
>
> +} SPD_BOOT_MODE;
>
> +
>
> +/**
>
> + SPD Data Buffer
>
> +**/
>
> +typedef struct {
>
> + UINT8
> SpdData[MEM_CFG_MAX_CONTROLLERS][MEM_CFG_MAX_CHANNELS][M
> EM_CFG_MAX_DIMMS][MEM_CFG_MAX_SPD_SIZE]; ///< SpdData
>
> +//Next Field Offset 2048
>
> +} SPD_DATA_BUFFER;
>
> +
>
> +/**
>
> + DqDqs Mapping
>
> +**/
>
> +typedef struct {
>
> + UINT8
> DqsMapCpu2Dram[MEM_CFG_MAX_CONTROLLERS][MEM_CFG_MAX_CHA
> NNELS][MEM_CFG_NUM_BYTES_MAPPED]; ///< DqsMapCpu2Dram
>
> + UINT8
> DqMapCpu2Dram[MEM_CFG_MAX_CONTROLLERS][MEM_CFG_MAX_CHA
> NNELS][MEM_CFG_NUM_BYTES_MAPPED][8]; ///< DqMapCpu2Dram
>
> +//Next Field Offset 16
>
> +} SA_MEMORY_DQDQS_MAPPING;
>
> +
>
> +/**
>
> + Rcomp Policies
>
> +**/
>
> +typedef struct {
>
> + UINT16 RcompResistor; ///< Offset 0: Reference RCOMP
> resistors on motherboard ~ 100 ohms
>
> + UINT16 RcompTarget[MRC_MAX_RCOMP_TARGETS]; ///< Offset 1:
> RCOMP target values for DqOdt, DqDrv, CmdDrv, CtlDrv, ClkDrv
>
> +//Next Field Offset 16
>
> +} SA_MEMORY_RCOMP;
>
> +
>
> +/**
>
> + SPD Offset Table
>
> +**/
>
> +typedef struct {
>
> + UINT16 Start; ///< Offset 0
>
> + UINT16 End; ///< Offset 2
>
> + UINT8 BootMode; ///< Offset 4
>
> + UINT8 Reserved3[3]; ///< Offset 5 Reserved for future use
>
> +} SPD_OFFSET_TABLE;
>
> +
>
> +///
>
> +/// SA memory address decode.
>
> +///
>
> +typedef struct
>
> +{
>
> + UINT8 Controller; ///< Offset 0 Zero based Controller number
>
> + UINT8 Channel; ///< Offset 1 Zero based Channel number
>
> + UINT8 Dimm; ///< Offset 2 Zero based DIMM number
>
> + UINT8 Rank; ///< Offset 3 Zero based Rank number
>
> + UINT8 BankGroup; ///< Offset 4 Zero based Bank Group number
>
> + UINT8 Bank; ///< Offset 5 Zero based Bank number
>
> + UINT16 Cas; ///< Offset 6 Zero based CAS number
>
> + UINT32 Ras; ///< Offset 8 Zero based RAS number
>
> +} SA_ADDRESS_DECODE;
>
> +
>
> +typedef UINT8 (EFIAPI * SA_IO_READ_8) (UINTN IoAddress);
> ///< CPU I/O port 8-bit read.
>
> +typedef UINT16 (EFIAPI * SA_IO_READ_16) (UINTN IoAddress);
> ///< CPU I/O port 16-bit read.
>
> +typedef UINT32 (EFIAPI * SA_IO_READ_32) (UINTN IoAddress);
> ///< CPU I/O port 32-bit read.
>
> +typedef UINT8 (EFIAPI * SA_IO_WRITE_8) (UINTN IoAddress,
> UINT8 Value);
> ///< CPU I/O port 8-bit write.
>
> +typedef UINT16 (EFIAPI * SA_IO_WRITE_16) (UINTN IoAddress,
> UINT16 Value);
> ///< CPU I/O port 16-bit write.
>
> +typedef UINT32 (EFIAPI * SA_IO_WRITE_32) (UINTN IoAddress,
> UINT32 Value);
> ///< CPU I/O port 32-bit write.
>
> +typedef UINT8 (EFIAPI * SA_MMIO_READ_8) (UINTN Address);
> ///< Memory Mapped I/O port 8-bit read.
>
> +typedef UINT16 (EFIAPI * SA_MMIO_READ_16) (UINTN Address);
> ///< Memory Mapped I/O port 16-bit read.
>
> +typedef UINT32 (EFIAPI * SA_MMIO_READ_32) (UINTN Address);
> ///< Memory Mapped I/O port 32-bit read.
>
> +typedef UINT64 (EFIAPI * SA_MMIO_READ_64) (UINTN Address);
> ///< Memory Mapped I/O port 64-bit read.
>
> +typedef UINT8 (EFIAPI * SA_MMIO_WRITE_8) (UINTN Address,
> UINT8 Value);
> ///< Memory Mapped I/O port 8-bit write.
>
> +typedef UINT16 (EFIAPI * SA_MMIO_WRITE_16) (UINTN Address,
> UINT16 Value);
> ///< Memory Mapped I/O port 16-bit write.
>
> +typedef UINT32 (EFIAPI * SA_MMIO_WRITE_32) (UINTN Address,
> UINT32 Value);
> ///< Memory Mapped I/O port 32-bit write.
>
> +typedef UINT64 (EFIAPI * SA_MMIO_WRITE_64) (UINTN Address,
> UINT64 Value);
> ///< Memory Mapped I/O port 64-bit write.
>
> +typedef UINT8 (EFIAPI * SA_SMBUS_READ_8) (UINTN Address,
> RETURN_STATUS *Status);
> ///< Smbus 8-bit read.
>
> +typedef UINT16 (EFIAPI * SA_SMBUS_READ_16) (UINTN Address,
> RETURN_STATUS *Status);
> ///< Smbus 16-bit read.
>
> +typedef UINT8 (EFIAPI * SA_SMBUS_WRITE_8) (UINTN Address,
> UINT8 Value, RETURN_STATUS *Status);
> ///< Smbus 8-bit write.
>
> +typedef UINT16 (EFIAPI * SA_SMBUS_WRITE_16) (UINTN Address,
> UINT16 Value, RETURN_STATUS *Status);
> ///< Smbus 16-bit write.
>
> +typedef UINT32 (EFIAPI * SA_GET_PCI_DEVICE_ADDRESS) (UINT8 Bus,
> UINT8 Device, UINT8 Function, UINT8 Offset);
> ///< Get PCI device address.
>
> +typedef UINT32 (EFIAPI * SA_GET_PCIE_DEVICE_ADDRESS) (UINT8 Bus,
> UINT8 Device, UINT8 Function, UINT8 Offset);
> ///< Get PCI express device address.
>
> +typedef VOID (EFIAPI * SA_GET_RTC_TIME) (UINT8 *Second,
> UINT8 *Minute, UINT8 *Hour, UINT8 *Day, UINT8 *Month, UINT16 *Year);
> ///< Get the current time value.
>
> +typedef UINT64 (EFIAPI * SA_GET_CPU_TIME) (VOID);
> ///< The current CPU time in milliseconds.
>
> +typedef VOID * (EFIAPI * SA_MEMORY_COPY) (VOID *Destination,
> CONST VOID *Source, UINTN NumBytes);
> ///< Perform byte copy operation.
>
> +typedef VOID * (EFIAPI * SA_MEMORY_SET_BYTE) (VOID *Buffer,
> UINTN NumBytes, UINT8 Value);
> ///< Perform byte initialization operation.
>
> +typedef VOID * (EFIAPI * SA_MEMORY_SET_WORD) (VOID *Buffer,
> UINTN NumWords, UINT16 Value);
> ///< Perform word initialization operation.
>
> +typedef VOID * (EFIAPI * SA_MEMORY_SET_DWORD) (VOID *Buffer,
> UINTN NumDwords, UINT32 Value);
> ///< Perform dword initialization operation.
>
> +typedef UINT64 (EFIAPI * SA_LEFT_SHIFT_64) (UINT64 Data, UINTN
> NumBits);
> ///< Left shift the 64-bit data value by specified number of bits.
>
> +typedef UINT64 (EFIAPI * SA_RIGHT_SHIFT_64) (UINT64 Data, UINTN
> NumBits);
> ///< Right shift the 64-bit data value by specified number of bits.
>
> +typedef UINT64 (EFIAPI * SA_MULT_U64_U32) (UINT64
> Multiplicand, UINT32 Multiplier);
> ///< Multiply a 64-bit data value by a 32-bit data value.
>
> +typedef UINT64 (EFIAPI * SA_DIV_U64_U64) (UINT64 Dividend,
> UINT64 Divisor, UINT64 *Remainder);
> ///< Divide a 64-bit data value by a 64-bit data value.
>
> +typedef BOOLEAN (EFIAPI * SA_GET_SPD_DATA)
> (SPD_BOOT_MODE BootMode, UINT8 SpdAddress, UINT8 *Buffer, UINT8
> *Ddr3Table, UINT32 Ddr3TableSize, UINT8 *Ddr4Table, UINT32
> Ddr4TableSize, UINT8 *LpddrTable, UINT32 LpddrTableSize); ///< Read
> the SPD data over the SMBus, at the given SmBus SPD address and copy the
> data to the data structure.
>
> +typedef UINT8 (EFIAPI * SA_GET_MC_ADDRESS_DECODE) (UINT64
> Address, SA_ADDRESS_DECODE *DramAddress);
>
> +typedef UINT8 (EFIAPI * SA_GET_MC_ADDRESS_ENCODE)
> (SA_ADDRESS_DECODE *DramAddress, UINT64 Address);
>
> +typedef BOOLEAN (EFIAPI * SA_GET_RANDOM_NUMBER) (UINT32
> *Rand);
> ///< Get the next random 32-bit number.
>
> +typedef EFI_STATUS (EFIAPI * SA_CPU_MAILBOX_READ) (UINT32 Type,
> UINT32 Command, UINT32 *Value, UINT32 *Status);
> ///< Perform a CPU mailbox read.
>
> +typedef EFI_STATUS (EFIAPI * SA_CPU_MAILBOX_WRITE) (UINT32 Type,
> UINT32 Command, UINT32 Value, UINT32 *Status);
> ///< Perform a CPU mailbox write.
>
> +typedef UINT32 (EFIAPI * SA_GET_MEMORY_VDD) (VOID
> *GlobalData, UINT32 DefaultVdd);
> ///< Get the current memory voltage (VDD).
>
> +typedef UINT32 (EFIAPI * SA_SET_MEMORY_VDD) (VOID
> *GlobalData, UINT32 DefaultVdd, UINT32 Value);
> ///< Set the memory voltage (VDD) to the given value.
>
> +typedef UINT32 (EFIAPI * SA_CHECKPOINT) (VOID *GlobalData,
> UINT32 CheckPoint, VOID *Scratch);
> ///< Check point that is called at various points in the MRC.
>
> +typedef VOID (EFIAPI * SA_DEBUG_HOOK) (VOID *GlobalData,
> UINT16 DisplayDebugNumber);
> ///< Typically used to display to the I/O port 80h.
>
> +typedef UINT8 (EFIAPI * SA_CHANNEL_EXIST) (VOID *Outputs,
> UINT8 Channel);
> ///< Returns whether Channel is or is not present.
>
> +typedef INT32 (EFIAPI * SA_PRINTF) (VOID *Debug, UINT32
> Level, char *Format, ...);
> ///< Print to output stream/device.
>
> +typedef VOID (EFIAPI * SA_DEBUG_PRINT) (VOID *String);
> ///< Output a string to the debug stream/device.
>
> +typedef UINT32 (EFIAPI * SA_CHANGE_MARGIN) (VOID
> *GlobalData, UINT8 Param, INT32 Value0, INT32 Value1, UINT8 EnMultiCast,
> UINT8 Channel, UINT8 RankIn, UINT8 Byte, UINT8 BitIn, UINT8
> UpdateMrcData, UINT8 SkipWait, UINT32 RegFileParam); ///< Change the
> margin.
>
> +typedef UINT8 (EFIAPI * SA_SIGN_EXTEND) (UINT8 Value, UINT8
> OldMsb, UINT8 NewMsb);
> ///< Sign extends OldMSB to NewMSB Bits (Eg: Bit 6 to Bit 7).
>
> +typedef VOID (EFIAPI * SA_SHIFT_PI_COMMAND_TRAIN) (VOID
> *GlobalData, UINT8 Channel, UINT8 Iteration, UINT8 RankMask, UINT8
> GroupMask, INT32 NewValue, UINT8 UpdateHost);
> ///< Move CMD/CTL/CLK/CKE PIs during training.
>
> +typedef VOID (EFIAPI * SA_UPDATE_VREF) (VOID *GlobalData,
> UINT8 Channel, UINT8 RankMask, UINT16 DeviceMask, UINT8 VrefType,
> INT32 Offset, BOOLEAN UpdateMrcData, BOOLEAN PDAmode, BOOLEAN
> SkipWait); ///< Update the Vref value and wait until it is
> stable.
>
> +typedef UINT8 (EFIAPI * SA_GET_RTC_CMOS) (UINT8 Location);
> ///< Get the current value of the specified RTC CMOS location.
>
> +typedef UINT64 (EFIAPI * SA_MSR_READ_64) (UINT32 Location);
> ///< Get the current value of the specified MSR location.
>
> +typedef UINT64 (EFIAPI * SA_MSR_WRITE_64) (UINT32 Location,
> UINT64 Data);
> ///< Set the current value of the specified MSR location.
>
> +typedef VOID (EFIAPI * SA_MRC_RETURN_FROM_SMC) (VOID
> *GlobalData, UINT32 MrcStatus);
> ///< Hook function after returning from MrcStartMemoryConfiguration()
>
> +typedef VOID (EFIAPI * SA_MRC_DRAM_RESET) (UINT32
> PciEBaseAddress, UINT32 ResetValue);
> ///< Assert or deassert DRAM_RESET# pin; this is used in JEDEC Reset.
>
> +typedef VOID (EFIAPI * SA_DELAY_NS) (VOID *GlobalData,
> UINT32 DelayNs);
> ///< Delay (stall) for the given amount of nanoseconds.
>
> +typedef VOID (EFIAPI * SA_SET_LOCK_PRMRR) (UINT64
> PrmrrBaseAddress, UINT32 PrmrrSize);
>
> +
>
> +
>
> +///
>
> +/// Function calls into the SA.
>
> +///
>
> +typedef struct {
>
> + SA_IO_READ_8 IoRead8; ///< Offset 0: - CPU I/O port 8-bit
> read.
>
> + SA_IO_READ_16 IoRead16; ///< Offset 4: - CPU I/O port 16-
> bit read.
>
> + SA_IO_READ_32 IoRead32; ///< Offset 8: - CPU I/O port 32-
> bit read.
>
> + SA_IO_WRITE_8 IoWrite8; ///< Offset 12: - CPU I/O port 8-bit
> write.
>
> + SA_IO_WRITE_16 IoWrite16; ///< Offset 16: - CPU I/O port 16-
> bit write.
>
> + SA_IO_WRITE_32 IoWrite32; ///< Offset 20: - CPU I/O port 32-
> bit write.
>
> + SA_MMIO_READ_8 MmioRead8; ///< Offset 24: - Memory
> Mapped I/O port 8-bit read.
>
> + SA_MMIO_READ_16 MmioRead16; ///< Offset 28: - Memory
> Mapped I/O port 16-bit read.
>
> + SA_MMIO_READ_32 MmioRead32; ///< Offset 32: - Memory
> Mapped I/O port 32-bit read.
>
> + SA_MMIO_READ_64 MmioRead64; ///< Offset 36: - Memory
> Mapped I/O port 64-bit read.
>
> + SA_MMIO_WRITE_8 MmioWrite8; ///< Offset 40: - Memory
> Mapped I/O port 8-bit write.
>
> + SA_MMIO_WRITE_16 MmioWrite16; ///< Offset 44: - Memory
> Mapped I/O port 16-bit write.
>
> + SA_MMIO_WRITE_32 MmioWrite32; ///< Offset 48: - Memory
> Mapped I/O port 32-bit write.
>
> + SA_MMIO_WRITE_64 MmioWrite64; ///< Offset 52: - Memory
> Mapped I/O port 64-bit write.
>
> + SA_SMBUS_READ_8 SmbusRead8; ///< Offset 56: - Smbus 8-bit
> read.
>
> + SA_SMBUS_READ_16 SmbusRead16; ///< Offset 60: - Smbus 16-
> bit read.
>
> + SA_SMBUS_WRITE_8 SmbusWrite8; ///< Offset 64: - Smbus 8-
> bit write.
>
> + SA_SMBUS_WRITE_16 SmbusWrite16; ///< Offset 68: - Smbus
> 16-bit write.
>
> + SA_GET_PCI_DEVICE_ADDRESS GetPciDeviceAddress; ///< Offset 72: -
> Get PCI device address.
>
> + SA_GET_PCIE_DEVICE_ADDRESS GetPcieDeviceAddress; ///< Offset 76: -
> Get PCI express device address.
>
> + SA_GET_RTC_TIME GetRtcTime; ///< Offset 80: - Get the
> current time value.
>
> + SA_GET_CPU_TIME GetCpuTime; ///< Offset 84: - The current
> CPU time in milliseconds.
>
> + SA_MEMORY_COPY CopyMem; ///< Offset 88: - Perform
> byte copy operation.
>
> + SA_MEMORY_SET_BYTE SetMem; ///< Offset 92: - Perform
> byte initialization operation.
>
> + SA_MEMORY_SET_WORD SetMemWord; ///< Offset 96: -
> Perform word initialization operation.
>
> + SA_MEMORY_SET_DWORD SetMemDword; ///< Offset 100: -
> Perform dword initialization operation.
>
> + SA_LEFT_SHIFT_64 LeftShift64; ///< Offset 104: - Left shift the
> 64-bit data value by specified number of bits.
>
> + SA_RIGHT_SHIFT_64 RightShift64; ///< Offset 108: - Right shift the
> 64-bit data value by specified number of bits.
>
> + SA_MULT_U64_U32 MultU64x32; ///< Offset 112: - Multiply a
> 64-bit data value by a 32-bit data value.
>
> + SA_DIV_U64_U64 DivU64x64; ///< Offset 116: - Divide a 64-bit
> data value by a 64-bit data value.
>
> + SA_GET_SPD_DATA GetSpdData; ///< Offset 120: - Read the
> SPD data over the SMBus, at the given SmBus SPD address and copy the data
> to the data structure.
>
> + SA_GET_RANDOM_NUMBER GetRandomNumber; ///< Offset 124: -
> Get the next random 32-bit number.
>
> + SA_CPU_MAILBOX_READ CpuMailboxRead; ///< Offset 128: -
> Perform a CPU mailbox read.
>
> + SA_CPU_MAILBOX_WRITE CpuMailboxWrite; ///< Offset 132: -
> Perform a CPU mailbox write.
>
> + SA_GET_MEMORY_VDD GetMemoryVdd; ///< Offset 136: - Get
> the current memory voltage (VDD).
>
> + SA_SET_MEMORY_VDD SetMemoryVdd; ///< Offset 140: - Set
> the memory voltage (VDD) to the given value.
>
> + SA_CHECKPOINT CheckPoint; ///< Offset 144: - Check point
> that is called at various points in the MRC.
>
> + SA_DEBUG_HOOK DebugHook; ///< Offset 148: - Typically
> used to display to the I/O port 80h.
>
> + SA_DEBUG_PRINT DebugPrint; ///< Offset 152: - Output a
> string to the debug stream/device.
>
> + SA_GET_RTC_CMOS GetRtcCmos; ///< Offset 156: - Get the
> current value of the specified RTC CMOS location.
>
> + SA_MSR_READ_64 ReadMsr64; ///< Offset 160: - Get the
> current value of the specified MSR location.
>
> + SA_MSR_WRITE_64 WriteMsr64; ///< Offset 164 - Set the
> current value of the specified MSR location.
>
> + SA_MRC_RETURN_FROM_SMC MrcReturnFromSmc; ///< Offset 168 -
> Hook function after returning from MrcStartMemoryConfiguration()
>
> + SA_MRC_DRAM_RESET MrcDramReset; ///< Offset 172 - Assert
> or deassert DRAM_RESET# pin; this is used in JEDEC Reset.
>
> + SA_DELAY_NS MrcDelayNs; ///< Offset 176 - Delay (stall) for
> the given amount of nanoseconds.
>
> +} SA_FUNCTION_CALLS;
>
> +
>
> +///
>
> +/// Function calls into the MRC.
>
> +///
>
> +typedef struct {
>
> + SA_CHANNEL_EXIST MrcChannelExist; ///< Offset 0: - Returns
> whether Channel is or is not present.
>
> + SA_PRINTF MrcPrintf; ///< Offset 4: - Print to output
> stream/device.
>
> + SA_CHANGE_MARGIN MrcChangeMargin; ///< Offset 8: - Change
> the margin.
>
> + SA_SIGN_EXTEND MrcSignExtend; ///< Offset 12: - Sign extends
> OldMSB to NewMSB Bits (Eg: Bit 6 to Bit 7).
>
> + SA_SHIFT_PI_COMMAND_TRAIN ShiftPiCommandTrain; ///< Offset 16: -
> Move CMD/CTL/CLK/CKE PIs during training.
>
> + SA_UPDATE_VREF MrcUpdateVref; ///< Offset 20: - Update the
> Vref value and wait until it is stable.
>
> +} SA_MEMORY_FUNCTIONS;
>
> +
>
> +/**
>
> + Memory Configuration
>
> + The contents of this structure are CRC'd by the MRC for option change
> detection.
>
> + This structure is copied en mass to the MrcInput structure. If you add fields
> here, you must update the MrcInput structure.
>
> + <b>Revision 1</b>: - Initial version.
>
> + <b>Revision 2</b>: - Adding ChHashOverride option.
>
> + <b>Revision 3</b>: - Adding PDA enumeration option.
>
> + <b>Revision 4</b>: - Adding LPDDR4 Command Mirroring.
>
> + <b>Revision 5</b>: - Adding CpuBclkSpread option.
>
> + <b>Revision 6</b>: - Adding McParity option.
>
> + <b>Revision 7</b>: - Adding VddqVoltageOverride option.
>
> + <b>Revision 8</b>: - Adding ExtendedBankHashing option.
>
> + <b>Revision 9</b>: - Adding IbeccErrorInj option
>
> + **/
>
> +typedef struct {
>
> + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
>
> + UINT16 Size; ///< Offset 28 The size of this structure, in bytes.
> Must be the first entry in this structure.
>
> + UINT8 HobBufferSize; ///< Offset 30 Size of HOB buffer for MRC
>
> +
>
> + UINT8 SpdProfileSelected; ///< Offset 31 SPD XMP profile selection - for
> XMP supported DIMM: <b>0=Default DIMM profile</b>, 1=Customized
> profile, 2=XMP profile 1, 3=XMP profile 2.
>
> +
>
> + // The following parameters are used only when SpdProfileSelected is
> UserDefined (CUSTOM PROFILE)
>
> + UINT16 tCL; ///< Offset 32 User defined Memory Timing tCL
> value, valid when SpdProfileSelected is CUSTOM_PROFILE:
> <b>0=AUTO</b>, 31=Maximum.
>
> + UINT16 tRCDtRP; ///< Offset 34 User defined Memory Timing tRCD
> value (same as tRP), valid when SpdProfileSelected is CUSTOM_PROFILE:
> <b>0=AUTO</b>, 63=Maximum
>
> + UINT16 tRAS; ///< Offset 36 User defined Memory Timing tRAS
> value, valid when SpdProfileSelected is CUSTOM_PROFILE:
> <b>0=AUTO</b>, 64=Maximum.
>
> + UINT16 tWR; ///< Offset 38 User defined Memory Timing tWR
> value, valid when SpdProfileSelected is CUSTOM_PROFILE:
> <b>0=AUTO</b>, legal values: 5, 6, 7, 8, 10, 12, 14, 16, 18, 20, 24.
>
> + UINT16 tRFC; ///< Offset 40 User defined Memory Timing tRFC
> value, valid when SpdProfileSelected is CUSTOM_PROFILE:
> <b>0=AUTO</b>, 1023=Maximum.
>
> + UINT16 tRRD; ///< Offset 42 User defined Memory Timing tRRD
> value, valid when SpdProfileSelected is CUSTOM_PROFILE:
> <b>0=AUTO</b>, 15=Maximum.
>
> + UINT16 tWTR; ///< Offset 44 User defined Memory Timing tWTR
> value, valid when SpdProfileSelected is CUSTOM_PROFILE:
> <b>0=AUTO</b>, 28=Maximum.
>
> + UINT16 tRTP; ///< Offset 46 User defined Memory Timing tRTP
> value, valid when SpdProfileSelected is CUSTOM_PROFILE:
> <b>0=AUTO</b>, 15=Maximum. DDR4 legal values: 5, 6, 7, 8, 9, 10, 12
>
> + UINT16 tFAW; ///< Offset 48 User defined Memory Timing tFAW
> value, valid when SpdProfileSelected is CUSTOM_PROFILE:
> <b>0=AUTO</b>, 63=Maximum.
>
> + UINT16 tCWL; ///< Offset 50 User defined Memory Timing tCWL
> value, valid when SpdProfileSelected is CUSTOM_PROFILE:
> <b>0=AUTO</b>, 20=Maximum.
>
> + UINT16 tREFI; ///< Offset 52 User defined Memory Timing tREFI
> value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>,
> 65535=Maximum.
>
> + UINT16 PciIndex; ///< Offset 54 Pci index register address:
> <b>0xCF8=Default</b>
>
> + UINT16 PciData; ///< Offset 56 Pci data register address:
> <b>0xCFC=Default</b>
>
> + UINT16 VddVoltage; ///< Offset 58 DRAM voltage (Vdd) in millivolts:
> <b>0=Platform Default (no override)</b>, 1200=1.2V, 1350=1.35V etc.
>
> + UINT16 Idd3n; ///< Offset 60 EPG Active standby current (Idd3N)
> in milliamps from DIMM datasheet.
>
> + UINT16 Idd3p; ///< Offset 62 EPG Active power-down current
> (Idd3P) in milliamps from DIMM datasheet.
>
> +
>
> + UINT32 EccSupport:1; ///< Offset 64 Bit 0 - DIMM Ecc Support
> option - for Desktop only: 0=Disable, <b>1=Enable</b>
>
> + UINT32 MrcSafeConfig:1; ///< Bit 1 - MRC Safe Mode:
> <b>0=Disable</b>, 1=Enable
>
> + UINT32 RemapEnable:1; ///< Bit 2 - This option is used to
> control whether to enable/disable memory remap above 4GB: 0=Disable,
> <b>1=Enable</b>.
>
> + UINT32 ScramblerSupport:1; ///< Bit 3 - Memory scrambler
> support: 0=Disable, <b>1=Enable</b>
>
> + UINT32 Vc1ReadMeter:1; ///< Bit 4 - VC1 Read Metering
> Enable: 0=Disable, <b>1=Enable</b>
>
> + UINT32 ForceSingleSubchannel:1; ///< Bit 5 - TRUE means use
> SubChannel0 only (for LPDDR4): <b>0=Disable</b>, 1=Enable
>
> + UINT32 SimicsFlag:1; ///< Bit 6 - Option to Enable SIMICS:
> 0=Disable, <b>1=Enable</b>
>
> + UINT32 Ddr4DdpSharedClock:1; ///< Bit 7 - Select if CLK0 is shared
> between Rank0 and Rank1 in DDR4 DDP package. <b>0=Not shared</b>,
> 1=Shared
>
> + UINT32 SharedZqPin:1; ///< Bit 8 - Select if the ZQ resistor is
> shared between Ranks in DDR4/LPDDR4 DRAM Packages <b>0=Not
> Shared</b>, 1=Shared
>
> + UINT32 LpDqsOscEn:1; ///< Bit 9 - LPDDR Write DQ/DQS
> Retraining: 0=Disable, <b>1=Enable</b>
>
> + UINT32 RmtPerTask:1; ///< Bit 10 - Rank Margin Tool Per Task.
> <b>0 = Disabled</b>, 1 = Enabled
>
> + UINT32 TrainTrace:1; ///< Bit 11 - Trained state tracing debug.
> <b>0 = Disabled</b>, 1 = Enabled
>
> + UINT32 SafeMode:1; ///< Bit 12 - Define if safe mode is
> enabled for MC/IO
>
> + UINT32 MsHashEnable:1; ///< Bit 13 - Controller Hash Enable:
> 0=Disable, <b>1=Enable</b>
>
> + UINT32 DisPgCloseIdleTimeout:1; ///< Bit 14 - Disable Page Close
> Idle Timeout: 0=Enable, <b>1=Disable</b>
>
> + UINT32 Ibecc:1; ///< Bit 15 - Inband ECC - for LPDDR4,
> LPDDR5 and DDR4 only: <b>0=Disable</b>, 1=Enable
>
> + UINT32 IbeccParity:1; ///< Bit 16 - Inband ECC Parity Control -
> for LPDDR4, LPDDR5 and DDR4 only: <b>0=Disable</b>, 1=Enable
>
> + UINT32 IbeccOperationMode:2; ///< Bits 17:18 - Inband ECC
> Operation Mode: 0=Functional Mode protects requests based on the
> address range, <b>1=Makes all requests non protected and ignore range
> checks</b>, 2=Makes all requests protected and ignore range checks
>
> + UINT32 ChHashOverride:1; ///< Bit 19 - Select if Channel Hash
> setting values will be taken from input parameters or automatically taken
> from POR values depending on DRAM type detected.
>
> + UINT32 McParity:1; ///< Bit 20 - MC Parity Control - Enable
> Parity for CMI/MC: <b>0=Disable</b>, 1=Enable
>
> + UINT32 IbeccErrorInj:1; ///< Bit 21 - In-Band ECC Error Injection:
> 1=Enable, <b>0=Disable</b>
>
> + UINT32 RsvdO64B22t31:10; ///< Bits 22:31 reserved
>
> + /**
>
> + Disables a DIMM slot in the channel even if a DIMM is present\n
>
> + Array index represents the channel number (0 = channel 0, 1 = channel
> 1)\n
>
> + <b>0x0 = DIMM 0 and DIMM 1 enabled</b>\n
>
> + 0x1 = DIMM 0 disabled, DIMM 1 enabled\n
>
> + 0x2 = DIMM 0 enabled, DIMM 1 disabled\n
>
> + 0x3 = DIMM 0 and DIMM 1 disabled (will disable the whole channel)\n
>
> + **/
>
> + UINT8
> DisableDimmChannel[MEM_CFG_MAX_CONTROLLERS][MEM_CFG_MAX_C
> HANNELS]; ///< Offset 68-75
>
> + UINT8 Ratio; ///< Offset 76 DDR Frequency ratio, to multiply by
> 133 or 100 MHz depending on RefClk. <b>0 = Auto</b>
>
> + UINT8 ProbelessTrace; ///< Offset 77 Probeless Trace:
> <b>0=Disabled</b>, <b>1=Enabled</b>
>
> + /**
>
> + - Channel Hash Enable.\n
>
> + NOTE: BIT7 will interleave the channels at a 2 cache-line granularity, BIT8
> at 4 and BIT9 at 8\n
>
> + 0=BIT6, <B>1=BIT7</B>, 2=BIT8, 3=BIT9
>
> + **/
>
> + UINT8 ChHashInterleaveBit; ///< Offset 78 Option to select interleave
> Address bit. Valid values are 0 - 3 for BITS 6 - 9 (Valid values for BDW are 0-7
> for BITS 6 - 13)
>
> + UINT8 SmramMask; ///< Offset 79 Reserved memory ranges for
> SMRAM
>
> + UINT32 BClkFrequency; ///< Offset 80 Base reference clock value, in
> Hertz: <b>100000000 = 100Hz</b>, 125000000=125Hz, 167000000=167Hz,
> 250000000=250Hz
>
> +
>
> + /// Training Algorithms 1 Offset 84
>
> + UINT32 ECT:1; ///< Bit 0 - Enable/Disable Early Command Training.
> Note it is not recommended to change this setting from the default value:
> <b>0=Disable</b>, 1=Enable.
>
> + UINT32 SOT:1; ///< Bit 1 - Enable/Disable Sense Amp Offset
> Training. Note it is not recommended to change this setting from the default
> value: 0=Disable, <b>1=Enable</b>.
>
> + UINT32 ERDMPRTC2D:1; ///< Bit 2 - Enable/Disable Early ReadMPR
> Timing Centering 2D. Note it is not recommended to change this setting from
> the default value: 0=Disable, <b>1=Enable</b>.
>
> + UINT32 RDMPRT:1; ///< Bit 3 - Enable/Disable Read MPR Training.
> Note it is not recommended to change this setting from the default value:
> 0=Disable, <b>1=Enable</b>.
>
> + UINT32 RCVET:1; ///< Bit 4 - Enable/Disable Receive Enable
> Training. Note it is not recommended to change this setting from the default
> value: 0=Disable, <b>1=Enable</b>.
>
> + UINT32 JWRL:1; ///< Bit 5 - Enable/Disable JEDEC Write Leveling
> Training. Note it is not recommended to change this setting from the default
> value: 0=Disable, <b>1=Enable</b>.
>
> + UINT32 EWRTC2D:1; ///< Bit 6 - Enable/Disable Early Write Time
> Centering 2D Training. Note it is not recommended to change this setting
> from the default value: 0=Disable, <b>1=Enable</b>.
>
> + UINT32 ERDTC2D:1; ///< Bit 7 - Enable/Disable Early Read Time
> Centering 2D Training. Note it is not recommended to change this setting
> from the default value: 0=Disable, <b>1=Enable</b>.
>
> + UINT32 WRTC1D:1; ///< Bit 8 - Enable/Disable 1D Write Timing
> Centering Training. Note it is not recommended to change this setting from
> the default value: 0=Disable, <b>1=Enable</b>.
>
> + UINT32 WRVC1D:1; ///< Bit 9 - Enable/Disable 1D Write Voltage
> Centering Training. Note it is not recommended to change this setting from
> the default value: 0=Disable, <b>1=Enable</b>.
>
> + UINT32 RDTC1D:1; ///< Bit 10 - Enable/Disable 1D Read Timing
> Centering Training. Note it is not recommended to change this setting from
> the default value: 0=Disable, <b>1=Enable</b>.
>
> + UINT32 DIMMODTT:1; ///< Bit 11 - Enable/Disable DIMM ODT
> Training. Note it is not recommended to change this setting from the default
> value: <b>0=Disable</b>, 1=Enable.
>
> + UINT32 DIMMRONT:1; ///< Bit 12 - Enable/Disable DIMM RON
> training. Note it is not recommended to change this setting from the default
> value: 0=Disable, <b>1=Enable</b>.
>
> + UINT32 WRDSEQT:1; ///< Bit 13 - Enable/Disable Write Drive
> Strength / Equalization Training 2D. Note it is not recommended to change
> this setting from the default value: <b>0=Disable</b>, 1=Enable.
>
> + UINT32 WRSRT:1; ///< Bit 14 - Enable/Disable Write Slew Rate
> traning. Note it is not recommended to change this setting from the default
> value: 0=Disable, <b>1=Enable.</b>
>
> + UINT32 RDODTT:1; ///< Bit 15 - Enable/Disable Read ODT Training.
> Note it is not recommended to change this setting from the default value:
> <b>0=Disable</b>, 1=Enable.
>
> + UINT32 RDEQT:1; ///< Bit 16 - Enable/Disable Read Equalization
> Training. Note it is not recommended to change this setting from the default
> value: <b>0=Disable</b>, 1=Enable.
>
> + UINT32 RDAPT:1; ///< Bit 17 - Enable/Disable Read Amplifier Power
> Training. Note it is not recommended to change this setting from the default
> value: <b>0=Disable</b>, 1=Enable.
>
> + UINT32 WRTC2D:1; ///< Bit 18 - Enable/Disable 2D Write Timing
> Centering Training. Note it is not recommended to change this setting from
> the default value: 0=Disable, <b>1=Enable</b>.
>
> + UINT32 RDTC2D:1; ///< Bit 19 - Enable/Disable 2D Read Timing
> Centering Training. Note it is not recommended to change this setting from
> the default value: 0=Disable, <b>1=Enable</b>.
>
> + UINT32 WRVC2D:1; ///< Bit 20 - Enable/Disable 2D Write Voltage
> Centering Training. Note it is not recommended to change this setting from
> the default value: 0=Disable, <b>1=Enable</b>.
>
> + UINT32 RDVC2D:1; ///< Bit 21 - Enable/Disable 2D Read Voltage
> Centering Training. Note it is not recommended to change this setting from
> the default value: 0=Disable, <b>1=Enable</b>.
>
> + UINT32 CMDVC:1; ///< Bit 22 - Enable/Disable Command Vref
> Centering Training. Note it is not recommended to change this setting from
> the default value 0=Disable, <b>1=Enable</b>.
>
> + UINT32 LCT:1; ///< Bit 23 - Enable/Disable Late Command Training.
> Note it is not recommended to change this setting from the default value:
> 0=Disable, <b>1=Enable</b>.
>
> + UINT32 RTL:1; ///< Bit 24 - Enable/Disable Round Trip Latency
> function. Note it is not recommended to change this setting from the default
> value: 0=Disable, <b>1=Enable</b>.
>
> + UINT32 TAT:1; ///< Bit 25 - Enable/Disable Turn Around Time
> function. Note it is not recommended to change this setting from the default
> value: <b>0=Disable</b>, 1=Enable.
>
> + UINT32 RMT:1; ///< Bit 26 - Enable/Disable Rank Margin Tool
> function: <b>0=Disable</b>, 1=Enable.
>
> + UINT32 MEMTST:1; ///< Bit 27 - Enable/Disable Memory Test
> function: <b>0=Disable</b>, 1=Enable.
>
> + UINT32 ALIASCHK:1; ///< Bit 28 - Enable/Disable DIMM SPD Alias
> Check: 0=Disable, <b>1=Enable</b>
>
> + UINT32 RCVENC1D:1; ///< Bit 29 - Enable/Disable Receive Enable
> Centering Training (LPDDR Only). Note it is not recommended to change this
> setting from the default value: <b>0=Disable</b>, 1=Enable
>
> + UINT32 RMC:1; ///< Bit 30 - Enable/Disable Retrain Margin Check.
> Note it is not recommended to change this setting from the default value:
> <b>0=Disable</b>, 1=Enable
>
> + UINT32 WRDSUDT:1; ///< Bit 31 - Enable/Disable Write Drive
> Strength Up/Dn independently. Note it is not recommended to change this
> setting from the default value: <b>0=Disable</b>, 1=Enable
>
> + /// Training Algorithms 2 Offset 88
>
> + UINT32 DCC : 1; ///< Bit 0 - Enable/Disable Duty Cycle Correction:
> 0=Disable, 1=Enable.
>
> + UINT32 RDVC1D : 1; ///< Bit 1 - Enable/Disable Read Voltage
> Centering 1D: 0=Disable, 1=Enable.
>
> + UINT32 TXTCO : 1; ///< Bit 2 - Enable/Disable Write TCO Comp
> Training: 0=Disable, 1=Enable.
>
> + UINT32 CLKTCO : 1; ///< Bit 3 - Enable/Disable Clock TCO Comp
> Training: 0=Disable, 1=Enable.
>
> + UINT32 CMDSR : 1; ///< Bit 4 - Enable/Disable CMD Slew Rate
> Training: 0=Disable, 1=Enable.
>
> + UINT32 CMDDSEQ : 1; ///< Bit 5 - Enable/Disable CMD Drive Strength
> and Tx Equalization: 0=Disable, 1=Enable.
>
> + UINT32 DIMMODTCA : 1; ///< Bit 6 - Enable/Disable Dimm ODT CA
> Training: 0=Disable, 1=Enable.
>
> + UINT32 TXTCODQS : 1; ///< Bit 7 - Enable/Disable Write TCO Dqs
> Training: 0=Disable, 1=Enable.
>
> + UINT32 CMDDRUD : 1; ///< Bit 8 - Enable/Disable CMD/CTL Drive
> Strength Up/Dn 2D: 0=Disable, 1=Enable.
>
> + UINT32 VCCDLLBP : 1; ///< Bit 9 - Enable/Disable VccDLL bypass to
> VccIOG training: 0=Disable, 1=Enable.
>
> + UINT32 PVTTDNLP : 1; ///< Bit 10 - Enable/Disable PanicVttDnLp
> Training: 0=Disable, 1=Enable.
>
> + UINT32 RDVREFDC : 1; ///< Bit 11 - Enable/Disable Read Vref Decap
> Training: 0=Disable, 1=Enable.
>
> + UINT32 VDDQT : 1; ///< Bit 12 - Enable/Disable Vddq Training:
> 0=Disable, 1=Enable.
>
> + UINT32 RMTBIT : 1; ///< Bit 13 - Enable/Disable Rank Margin Tool Per
> Bit: 0=Disable, 1=Enable.
>
> + UINT32 PDA : 1; ///< BIT 14 - Enable/Disable PDA Enumeration
> Training. Note it is not recommended to change this setting from the default
> value: 0=Disable, <b>1=Enable</b>.
>
> + UINT32 WRITE0 : 1; ///< BIT 15 - Write0 feature enablement
>
> + UINT32 ReservedBits2 :16; ///< Bits 16:31 - Reserved
>
> +
>
> + UINT32 MrcTimeMeasure:1; ///< Offset 92 Bit 0 - Enables serial debug
> level to display the MRC execution times only: <b>0=Disable</b>, 1=Enable
>
> + UINT32 MrcFastBoot:1; ///< Bit 1 - Enables the MRC fast boot
> path for faster cold boot execution: 0=Disable, <b>1=Enable</b>
>
> + UINT32 DqPinsInterleaved:1; ///< Bit 2 - Interleaving mode of
> DQ/DQS pins which depends on board routing: <b>0=Disable</b>, 1=Enable
>
> + UINT32 RankInterleave:1; ///< Bit 3 - Rank Interleave Mode:
> 0=Disable, <b>1=Enable</b>
>
> + UINT32 EnhancedInterleave:1; ///< Bit 4 - Enhanced Interleave
> Mode: 0=Disable, <b>1=Enable</b>
>
> + UINT32 WeaklockEn:1; ///< Bit 5 - Weak Lock Enable:
> 0=Disable, <b>1=Enable</b>
>
> + UINT32 ChHashEnable:1; ///< Bit 6 - Channel Hash Enable:
> 0=Disable, <b>1=Enable</b>
>
> + UINT32 EnablePwrDn:1; ///< Bit 7 - Enable Power Down control
> for DDR: 0=PCODE control, <b>1=BIOS control</b>
>
> + UINT32 EnablePwrDnLpddr:1; ///< Bit 8 - Enable Power Down for
> LPDDR: 0=PCODE control, <b>1=BIOS control</b>
>
> + UINT32 SrefCfgEna:1; ///< Bit 9 - Enable Self Refresh:
> 0=Disable, <b>1=Enable</b>
>
> + UINT32 ThrtCkeMinDefeatLpddr:1; ///< Bit 10 - Throttler CKE min
> defeature for LPDDR: 0=Disable, <b>1=Enable</b>
>
> + UINT32 ThrtCkeMinDefeat:1; ///< Bit 11 - Throttler CKE min
> defeature: <b>0=Disable</b>, 1=Enable
>
> + UINT32 AutoSelfRefreshSupport:1; ///< Bit 12 - FALSE = No auto self
> refresh support, <b>TRUE = auto self refresh support</b>
>
> + UINT32 ExtTemperatureSupport:1; ///< Bit 13 - FALSE = No extended
> temperature support, <b>TRUE = extended temperature support</b>
>
> + UINT32 MobilePlatform:1; ///< Bit 14 - Memory controller device
> id indicates: <b>TRUE if mobile</b>, FALSE if not. Note: This will be auto-
> detected and updated.
>
> + UINT32 Force1Dpc:1; ///< Bit 15 - TRUE means force one DIMM
> per channel, <b>FALSE means no limit</b>
>
> + UINT32 ForceSingleRank:1; ///< Bit 16 - TRUE means use Rank0
> only (in each DIMM): <b>0=Disable</b>, 1=Enable
>
> + UINT32 VttTermination:1; ///< Bit 17 - Vtt Termination for Data
> ODT: <b>0=Disable</b>, 1=Enable
>
> + UINT32 VttCompForVsshi:1; ///< Bit 18 - Enable/Disable Vtt
> Comparator For Vsshi: <b>0=Disable</b>, 1=Enable
>
> + UINT32 ExitOnFailure:1; ///< Bit 19 - MRC option for exit on
> failure or continue on failure: 0=Disable, <b>1=Enable</b>
>
> + UINT32 NewFeatureEnable1:1; ///< Bit 20 - Generic enable knob
> for new feature set 1 <b>0: Disable </b>; 1: Enable
>
> + UINT32 NewFeatureEnable2:1; ///< Bit 21 - Generic enable knob
> for new feature set 2 <b>0: Disable </b>; 1: Enable
>
> + UINT32 RhPrevention:1; ///< Bit 22 - RH Prevention
> Enable/Disable: 0=Disable, <b>1=Enable</b>
>
> + UINT32 RhSolution:1; ///< Bit 23 - Type of solution to be used
> for RHP - 0/1 = HardwareRhp/Refresh2x
>
> + UINT32 RefreshPanicWm:4; ///< Bit 24-27 - Refresh Panic
> Watermark, Range 1-8, default 8.
>
> + UINT32 RefreshHpWm:4; ///< Bit 28-31 - Refresh High Profile
> Watermark, Range 1-7, default 7.
>
> + UINT32 VddSettleWaitTime; ///< Offset 96 Amount of time in
> microseconds to wait for Vdd to settle on top of 200us required by JEDEC
> spec: <b>Default=0</b>
>
> + UINT16 SrefCfgIdleTmr; ///< Offset 100 Self Refresh idle timer:
> <b>512=Minimal</b>, 65535=Maximum
>
> + UINT16 ChHashMask; ///< Offset 102 Channel Hash Mask:
> 0x0001=BIT6 set(Minimal), 0x3FFF=BIT[19:6] set(Maximum), <b>0x30CE=
> BIT[19:18, 13:12 ,9:7] set</b>
>
> + UINT16 DdrFreqLimit; ///< Offset 104 Memory Frequency setting:
> 3=1067, 5=1333, 7=1600, 9=1867, 11=2133, 13=2400, <b>15=2667</b>
>
> + UINT8 MaxRttWr; ///< Offset 106 Maximum DIMM RTT_WR to use
> in power training: <b>0=ODT Off</b>, 1 = 120 ohms
>
> + UINT8 ThrtCkeMinTmr; ///< Offset 107 Throttler CKE min timer:
> 0=Minimal, 0xFF=Maximum, <b>0x00=Default</b>
>
> + UINT8 ThrtCkeMinTmrLpddr; ///< Offset 108 Throttler CKE min timer for
> LPDDR: 0=Minimal, 0xFF=Maximum, <b>0x00=Default</b>
>
> + BOOLEAN PerBankRefresh; ///< Offset 109 Enables and Disables the
> per bank refresh. This only impacts memory technologies that support PBR:
> LPDDR3, LPDDR4. FALSE=Disabled, <b>TRUE=Enabled</b>
>
> + UINT8 SaGv; ///< Offset 110 SA GV: <b>0=Disabled</b>,
> 1=Point1, 2=Point2, 3=Point3, 4=Point4, 5=Enabled
>
> + UINT8 NModeSupport; ///< Offset 111 Memory N Mode Support -
> Enable user to select Auto, 1N or 2N: <b>0=AUTO</b>, 1=1N, 2=2N.
>
> + UINT8 RefClk; ///< Offset 112 Selects the DDR base reference
> clock. 0x01 = 100MHz, <b>0x00 = 133MHz</b>
>
> + UINT8 EnCmdRate; ///< Offset 113 CMD Rate Enable: 0=Disable,
> 5=2 CMDs, <b>7=3 CMDs</b>, 9=4 CMDs, 11=5 CMDs, 13=6 CMDs, 15=7
> CMDs
>
> + UINT8 Refresh2X; ///< Offset 114 Refresh 2x: <b>0=Disable</b>,
> 1=Enable for WARM or HOT, 2=Enable for HOT only
>
> + UINT8 EpgEnable; ///< Offset 115 Enable Energy Performance Gain.
>
> + UINT8 UserThresholdEnable; ///< Offset 116 Flag to manually select the
> DIMM CLTM Thermal Threshold, 0=Disable, 1=Enable, <b>0=Default</b>
>
> + UINT8 UserBudgetEnable; ///< Offset 117 Flag to manually select the
> Budget Registers for CLTM Memory Dimms , 0=Disable, 1=Enable,
> <b>0=Default</b>
>
> + UINT8 RetrainOnFastFail; ///< Offset 118 Restart MRC in Cold mode if
> SW MemTest fails during Fast flow. 0 = Disabled, <b>1 = Enabled</b>
>
> + UINT8 PowerDownMode; ///< Offset 119 CKE Power Down Mode:
> <b>0xFF=AUTO</b>, 0=No Power Down, 1= APD mode, 6=PPD-DLL Off
> mode
>
> + UINT8 PwdwnIdleCounter; ///< Offset 120 CKE Power Down Mode
> Idle Counter: 0=Minimal, 255=Maximum, <b>0x80=0x80 DCLK</b>
>
> + UINT8 CmdRanksTerminated; ///< Offset 121 LPDDR: Bitmask of ranks
> that have CA bus terminated. <b>0x01=Default, Rank0 is terminating and
> Rank1 is non-terminating</b>
>
> + UINT16 MsHashMask; ///< Offset 122 Controller Hash Mask:
> 0x0001=BIT6 set(Minimal), 0x3FFF=BIT[19:6] set(Maximum), <b>0x30CE=
> BIT[19:18, 13:12 ,9:7] set</b>
>
> + UINT32 Lp5CccConfig; ///< Offset 124 BitMask where bits [3:0] are
> controller 0 Channel [3:0] and [7:4] are Controller 1 Channel [3:0]. 0 selects
> Ascending mapping and 1 selects Descending mapping.
>
> + UINT8 RMTLoopCount; ///< Offset 128 Indicates the Loop Count to
> be used for Rank Margin Tool Testing: 1=Minimal, 32=Maximum, 0=AUTO,
> <b>0=Default</b>
>
> + UINT8 MsHashInterleaveBit; ///< Offset 129 Option to select interleave
> Address bit. Valid values are 0 - 3 for BITS 6 - 9
>
> + UINT8 GearRatio; ///< Offset 130 This input control's the current
> gear expressed as an integer when SAGV is disabled: <b>0=Default</b>, 1, 2.
>
> + UINT8 Ddr4OneDpc; ///< Offset 131 DDR4 1DPC performance
> feature: 0 - Disabled; 1 - Enabled on DIMM0 only, 2 - Enabled on DIMM1 only;
> 3 - Enabled on both DIMMs. (bit [0] - DIMM0, bit [1] - DIMM1)
>
> + UINT32 BclkRfiFreq[MEM_MAX_SAGV_POINTS]; ///< Offset 132 Bclk RFI
> Frequency for each SAGV point in Hz units. 98000000Hz = 98MHz <b>0 - No
> RFI Tuning</b>. Range is 98Mhz-100Mhz.
>
> + UINT16 SaGvFreq[MEM_MAX_SAGV_POINTS]; ///< Offset 148
> Frequency per SAGV point. 0 is Auto, otherwise holds the frequency value
> expressed as an integer: <b>0=Default</b>, 1067, 1333, 1600, 1800, 1867,
> etc.
>
> + /**
>
> + Offset 156 Gear ratio per SAGV point. 0 is Auto, otherwise holds the Gear
> ratio expressed as an integer: <b>0=Default</b>, 1, 2.
>
> + Only valid combinations of Gear Ratio per point is:
>
> + | point | set1 | set2 | set3
>
> + | 0 | 1 | 2 | 2
>
> + | 1 | 1 | 2 | 2
>
> + | 2 | 1 | 2 | 2
>
> + | 3 | 1 | 2 | 1
>
> + **/
>
> + UINT8 SaGvGear[MEM_MAX_SAGV_POINTS]; ///< Offset 156
>
> + UINT8 IbeccProtectedRegionEnable[MEM_MAX_IBECC_REGIONS]; ///<
> Offset 160 Enable use of address range for ECC Protection:
> <b>0=Default</b>, 1
>
> + UINT16 IbeccProtectedRegionBase[MEM_MAX_IBECC_REGIONS]; ///<
> Offset 168 Base address for address range of ECC Protection:
> <b>0=Default</b>, 1
>
> + UINT16 IbeccProtectedRegionMask[MEM_MAX_IBECC_REGIONS]; ///<
> Offset 184 Mask address for address range of ECC Protection:
> <b>0=Default</b>, 1
>
> + UINT32 CmdMirror; ///< Offset 200 BitMask where bits [3:0] are
> controller 0 Channel [3:0] and [7:4] are Controller 1 Channel [3:0]. 0 = No
> Command Mirror and 1 = Command Mirror.
>
> + UINT8 CpuBclkSpread; ///< Offset 204 CPU BCLK Spread Specturm: 0
> = Disabled; <b>1 = Enabled</b>
>
> + UINT8 ExtendedBankHashing; ///< Offset 205 Enable EBH Extended
> Bank Hashing: 0=Disabled; <b>1 = Enabled</b>.
>
> + UINT16 VddqVoltageOverride; ///< Offset 206 VccddqVoltage override
> in # of 1mV
>
> + UINT8 MarginLimitCheck; ///< Offset 208 Margin limit
> check enable: <b>0=Disable</b>, 1=L1 only, 2=L2 only, 3=Both L1 and L2
>
> + UINT8 RsvdO209; ///< Offset 209
>
> + UINT16 MarginLimitL2; ///< Offset 210 Margin limit
> check L2 threshold: <b>100=Default</b>
>
> +} MEMORY_CONFIGURATION;
>
> +
>
> +/// Memory Configuration
>
> +/// The contents of this structure are not CRC'd by the MRC for option
> change detection.
>
> +/// <b>Revision 1</b>: - Initial version.
>
> +/// <b>Revision 2</b>: - Added MemTestOnWarmBoot
>
> +typedef struct {
>
> + CONFIG_BLOCK_HEADER Header; ///< Offset 0-23 Config Block
> Header
>
> + SA_FUNCTION_CALLS SaCall; ///< Offset 24 Function calls into
> the SA.
>
> + SA_MEMORY_FUNCTIONS MrcCall; ///< Offset 204 Function calls
> into the MRC.
>
> + SPD_DATA_BUFFER *SpdData; ///< Offset 240 Memory SPD
> data, will be used by the MRC when SPD SmBus address is zero.
>
> + UINT32 Reserved0;
>
> + SA_MEMORY_DQDQS_MAPPING *DqDqsMap; ///< Offset 244
> LPDDR DQ bit and DQS byte swizzling between CPU and DRAM.
>
> + SA_MEMORY_RCOMP *RcompData; ///< Offset 248 DDR RCOMP
> resistors and target values.
>
> + UINT64 PlatformMemorySize; ///< Offset 252 The minimum
> platform memory size required to pass control into DXE
>
> + UINT32 CleanMemory:1; ///< Offset 256 Ask MRC to clear
> memory content: <b>FALSE=Do not Clear Memory</b>; TRUE=Clear
> Memory
>
> + UINT32 ReservedBits5:31;
>
> + /**
>
> + Sets the serial debug message level\n
>
> + 0x00 = Disabled\n
>
> + 0x01 = Errors only\n
>
> + 0x02 = Errors and Warnings\n
>
> + <b>0x03 = Errors, Warnings, and Info</b>\n
>
> + 0x04 = Errors, Warnings, Info, and Events\n
>
> + 0x05 = Displays Memory Init Execution Time Summary only\n
>
> + **/
>
> + UINT8 SerialDebugLevel; ///< Offset 260
>
> + UINT8 MemTestOnWarmBoot; ///< Offset 261 Run Base
> Memory Test On WarmBoot: 0=Disabled, <b>1=Enabled</b>
>
> + UINT8 Reserved11[2]; ///< Offset 262 - 263 Reserved
>
> +} MEMORY_CONFIG_NO_CRC;
>
> +#pragma pack(pop)
>
> +
>
> +#endif // _MEMORY_CONFIG_H_
>
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Overclocking/Overcl
> ockingConfig.h
> b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Overclocking/Overcl
> ockingConfig.h
> new file mode 100644
> index 0000000000..462c02cef1
> --- /dev/null
> +++
> b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Overclocking/Overcl
> ockingConfig.h
> @@ -0,0 +1,236 @@
> +/** @file
>
> + Overclocking Config Block.
>
> +
>
> + Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +**/
>
> +#ifndef _OVERCLOCKING_PREMEM_CONFIG_H_
>
> +#define _OVERCLOCKING_PREMEM_CONFIG_H_
>
> +
>
> +#define OVERCLOCKING_CONFIG_REVISION 9
>
> +
>
> +extern EFI_GUID gOverclockingPreMemConfigGuid;
>
> +
>
> +#pragma pack (push,1)
>
> +
>
> +//
>
> +// Max number of VF point offset
>
> +//
>
> +#ifndef CPU_OC_MAX_VF_POINTS
>
> +#define CPU_OC_MAX_VF_POINTS 0xF
>
> +#endif
>
> +
>
> +#ifndef CPU_OC_MAX_CORES
>
> +#define CPU_OC_MAX_CORES 8
>
> +#endif
>
> +/**
>
> + Overclocking Configuration Structure.
>
> +
>
> + <b>Revision 1</b>:
>
> + - Initial version.
>
> + <b>Revision 2</b>
>
> + - Add PerCoreHtDisable
>
> + <b>Revision 3</b>
>
> + - Add Avx2VoltageScaleFactor and Avx512VoltageScaleFactor
>
> + <b>Revision 4</b>
>
> + - Add CoreVfPointOffsetMode & CoreVfPointOffset & CoreVfPointRatio &
> CoreVfPointCount
>
> + <b>Revision 5</b>
>
> + - Change OcLock default to 'Enabled'
>
> + <b>Revision 6</b>:
>
> + - Add DisableCoreMask.
>
> + <b>Revision 7</b>
>
> + Add UnlimitedIccMax
>
> + <b>Revision 8</b>
>
> + - Add PerCoreRatioOverride and PerCoreRatio for Per Core PState
> overclocking.
>
> + <b>Revision 9</b>
>
> + - Add VccInVoltageOverride.
>
> +**/
>
> +typedef struct {
>
> + CONFIG_BLOCK_HEADER Header; ///< Config Block Header
>
> + /**
>
> + Overclocking support. This controls whether OC mailbox transactions are
> sent.
>
> + If disabled, all policies in this config block besides OcSupport and OcLock
> will be ignored.
>
> + <b>0: Disable</b>;
>
> + 1: Enable.
>
> + @note If PcdOverclockEnable is disabled, this should also be disabled.
>
> + **/
>
> + UINT32 OcSupport : 1;
>
> + UINT32 OcLock : 1; ///< If enabled, sets OC lock bit in MSR
> 0x194[20], locking the OC mailbox and other OC configuration settings.; 0:
> Disable; <b>1: Enable (Lock)</b>.
>
> + /**
>
> + Core voltage mode, specifies which voltage mode the processor will be
> operating.
>
> + <b>0: Adaptive Mode</b> allows the processor to interpolate a voltage
> curve when beyond fused P0 range;
>
> + 1: Override, sets one voltage for for the entire frequency range, Pn-P0.
>
> + **/
>
> + UINT32 CoreVoltageMode : 1;
>
> + UINT32 CorePllVoltageOffset : 6; ///< Core PLL voltage offset.
> <b>0: No offset</b>. Range 0-63 in 17.5mv units.
>
> + UINT32 Avx2RatioOffset : 5; ///< AVX2 Ratio Offset. <b>0: No
> offset</b>. Range is 0-31. Used to lower the AVX ratio to maximize possible
> ratio for SSE workload.
>
> + UINT32 Avx3RatioOffset : 5; ///< AVX3 Ratio Offset. <b>0: No
> offset</b>. Range is 0-31. Used to lower the AVX3 ratio to maximize possible
> ratio for SSE workload.
>
> + UINT32 BclkAdaptiveVoltage : 1; ///< Bclk Adaptive Voltage
> enable/disable. <b>0: Disabled</b>, 1: Enabled. When enabled, the CPU V/F
> curves are aware of BCLK frequency when calculated.
>
> + /**
>
> + Ring Downbin enable/disable.
>
> + When enabled, the CPU will force the ring ratio to be lower than the core
> ratio.
>
> + Disabling will allow the ring and core ratios to run at the same frequency.
>
> + Uses OC Mailbox command 0x19.
>
> + 0: Disables Ring Downbin feature. <b>1: Enables Ring downbin
> feature.</b>
>
> + **/
>
> + UINT32 RingDownBin : 1;
>
> + /**
>
> + Ring voltage mode, specifies which voltage mode the processor will be
> operating.
>
> + <b>0: Adaptive Mode</b> allows the processor to interpolate a voltage
> curve when beyond fused P0 range;
>
> + 1: Override, sets one voltage for for the entire frequency range, Pn-P0.
>
> + **/
>
> + UINT32 RingVoltageMode : 1;
>
> + UINT32 GtVoltageMode : 1; ///< Specifies whether GT voltage is
> operating in Adaptive or Override mode: <b>0=Adaptive</b>, 1=Override
>
> + UINT32 RealtimeMemoryTiming : 1; ///< Enable/Disable the message
> sent to the CPU to allow realtime memory timing changes after MRC_DONE.
> <b>0=Disable</b>, 1=Enable
>
> + UINT32 FivrFaults : 1; ///< Fivr Faults. Enable or Disable FIVR Faults.
> 0: Disabled, <b>1: Enabled.</b>
>
> + UINT32 FivrEfficiency : 1; ///< Fivr Efficiency Management. 0:
> Disabled, <b>1: Enabled.</b>
>
> + /**
>
> + Selects Core Voltage & Frequency Point Offset between Legacy and
> Selection modes.
>
> + Need Reset System after enabling OverClocking Feature to Initialize the
> default value.
>
> + <b>0: In Legacy Mode, setting a global offset for the entire VF curve.</b>
>
> + 1: In Selection modes, setting a selected VF point.
>
> + **/
>
> + UINT32 CoreVfPointOffsetMode : 1;
>
> + UINT32 UnlimitedIccMax : 1; ///< Support Unlimited ICCMAX more
> than maximum value 255.75A. <b>0: Disabled</b>, 1: Enabled.
>
> + UINT32 PerCoreRatioOverride : 1; ///< Enable or disable Per Core
> PState OC supported by writing OCMB 0x1D to program new favored core
> ratio to each Core. <b>0: Disable</b>, 1: enable
>
> + UINT32 DynamicMemoryChange : 1; ///< Dynamic Memory Timings
> Changes; <b>0: Disabled</b>; 1: Enabled.
>
> + UINT32 RsvdBits : 2; ///< Reserved for future use
>
> +
>
> + /**
>
> + Maximum core turbo ratio override allows to increase CPU core frequency
> beyond the fused max turbo ratio limit (P0).
>
> + <b>0. no override/HW defaults.</b>. Range 0-85.
>
> + **/
>
> + UINT8 CoreMaxOcRatio;
>
> + UINT8 GtMaxOcRatio; ///< Maximum GT turbo ratio override:
> 0=Minimal, 60=Maximum, <b>0=AUTO</b>
>
> + /**
>
> + Maximum ring ratio override allows to increase CPU ring frequency beyond
> the fused max ring ratio limit.
>
> + <b>0. no override/HW defaults.</b>. Range 0-85.
>
> + **/
>
> + UINT8 RingMaxOcRatio;
>
> + UINT8 RsvdByte1;
>
> + /**
>
> + The core voltage override which is applied to the entire range of cpu core
> frequencies.
>
> + Used when CoreVoltageMode = Override.
>
> + <b>0. no override</b>. Range 0-2000 mV.
>
> + **/
>
> + UINT16 CoreVoltageOverride;
>
> + /**
>
> + Adaptive Turbo voltage target used to define the interpolation voltage
> point when the cpu is operating in turbo mode range.
>
> + Used when CoreVoltageMode = Adaptive.
>
> + <b>0. no override</b>. Range 0-2000mV.
>
> + **/
>
> + UINT16 CoreVoltageAdaptive;
>
> + /**
>
> + The core voltage offset applied on top of all other voltage modes. This
> offset is applied over the entire frequency range.
>
> + This is a 2's complement number in mV units. <b>Default: 0</b> Range: -
> 1000 to 1000.
>
> + **/
>
> + INT16 CoreVoltageOffset;
>
> + /**
>
> + The ring voltage override which is applied to the entire range of cpu ring
> frequencies.
>
> + Used when RingVoltageMode = Override.
>
> + <b>0. no override</b>. Range 0-2000 mV.
>
> + **/
>
> + UINT16 RingVoltageOverride;
>
> + /**
>
> + Adaptive Turbo voltage target used to define the interpolation voltage
> point when the ring is operating in turbo mode range.
>
> + Used when RingVoltageMode = Adaptive.
>
> + <b>0. no override</b>. Range 0-2000mV.
>
> + **/
>
> + UINT16 RingVoltageAdaptive;
>
> + /**
>
> + The ring voltage offset applied on top of all other voltage modes. This
> offset is applied over the entire frequency range.
>
> + This is a 2's complement number in mV units. <b>Default: 0</b> Range: -
> 1000 to 1000.
>
> + **/
>
> + INT16 RingVoltageOffset;
>
> +
>
> + INT16 GtVoltageOffset; ///< The voltage offset applied to GT
> slice. Valid range from -1000mv to 1000mv: <b>0=Minimal</b>,
> 1000=Maximum
>
> + UINT16 GtVoltageOverride; ///< The GT voltage override which
> is applied to the entire range of GT frequencies <b>0=Default</b>
>
> + UINT16 GtExtraTurboVoltage; ///< The adaptive voltage applied
> during turbo frequencies. Valid range from 0 to 2000mV: <b>0=Minimal</b>,
> 2000=Maximum
>
> + INT16 SaVoltageOffset; ///< The voltage offset applied to the
> SA. Valid range from -1000mv to 1000mv: <b>0=Default</b>
>
> + UINT32 GtPllVoltageOffset : 6; ///< GT PLL voltage offset. <b>0:
> No offset</b>. Range 0-63 in 17.5mv units.
>
> + UINT32 RingPllVoltageOffset : 6; ///< Ring PLL voltage offset. <b>0:
> No offset</b>. Range 0-63 in 17.5mv units.
>
> + UINT32 SaPllVoltageOffset : 6; ///< System Agent PLL voltage
> offset. <b>0: No offset</b>. Range 0-63 in 17.5mv units.
>
> + UINT32 McPllVoltageOffset : 6; ///< Memory Controller PLL
> voltage offset. <b>0: No offset</b>. Range 0-63 in 17.5mv units.
>
> + UINT32 RsvdBits1 : 8;
>
> + /**
>
> + TjMax Offset. Specified value here is clipped by pCode (125 - TjMax Offset)
> to support TjMax in the range of 62 to 115 deg Celsius.
>
> + <b> Default: 0 Hardware Defaults </b> Range 10 to 63. 0 = No offset /
> Keep HW default.
>
> + **/
>
> + UINT8 TjMaxOffset;
>
> + UINT8 RsvdByte2[3]; //< Reserved for dword alignment
>
> + /**
>
> + This service controls Core frequency reduction caused by high package
> temperatures for processors that
>
> + implement the Intel Thermal Velocity Boost (TVB) feature. It is required to
> be disabled for supporting
>
> + overclocking at frequencies higher than the default max turbo frequency.
>
> + <b>0: Disables TVB ratio clipping. </b>1: Enables TVB ratio clipping.
>
> + **/
>
> + UINT32 TvbRatioClipping : 1;
>
> + /**
>
> + This service controls thermal based voltage optimizations for processors
> that implement the Intel
>
> + Thermal Velocity Boost (TVB) feature.
>
> + 0: Disables TVB voltage optimization. <b>1: Enables TVB voltage
> optimization.</b>
>
> + **/
>
> + UINT32 TvbVoltageOptimization : 1;
>
> + UINT32 RsvdBits2 : 30;
>
> + /**
>
> + Defines the per-core HT disable mask where: 1 - Disable selected logical
> core HT, 0 - is ignored.
>
> + Input is in HEX and each bit maps to a logical core. Ex. A value of '1F' would
> disable HT for cores 4,3,2,1 and 0.
>
> + <b>Default is 0</b>, all cores have HT enabled. Range is 0 - 0x1FF. You can
> only disable up to MAX_CORE_COUNT - 1.
>
> + **/
>
> + UINT16 PerCoreHtDisable;
>
> + /**
>
> + Avx2 Voltage Guardband Scale Factor
>
> + This controls the AVX2 Voltage Guardband Scale factor applied to AVX2
> workloads.
>
> + Valid range is 0-200 in 1/100 units, where a value of 125 would apply a 1.25
> scale factor.
>
> + A value of 0 means no scale factor applied (no change to voltage on AVX
> commands)
>
> + A value of 100 applies the default voltage guardband values (1.0 factor).
>
> + A value > 100 will increase the voltage guardband on AVX2 workloads.
>
> + A value < 100 will decrease the voltage guardband on AVX2 workloads.
>
> +
>
> + <b>0. No scale factor applied</b>
>
> + **/
>
> + UINT8 Avx2VoltageScaleFactor;
>
> + /**
>
> + Avx512 Voltage Guardband Scale Factor
>
> + This controls the AVX512 Voltage Guardband Scale factor applied to
> AVX512 workloads.
>
> + Valid range is 0-200 in 1/100 units, where a value of 125 would apply a 1.25
> scale factor.
>
> + A value of 0 means no scale factor applied (no change to voltage on AVX
> commands)
>
> + A value of 100 applies the default voltage guardband values (1.0 factor).
>
> + A value > 100 will increase the voltage guardband on AVX512 workloads.
>
> + A value < 100 will decrease the voltage guardband on AVX512 workloads.
>
> +
>
> + <b>0. No scale factor applied</b>
>
> + **/
>
> + UINT8 Avx512VoltageScaleFactor;
>
> + /**
>
> + Array used to specifies the Core Voltage Offset applied to the each
> selected VF Point.
>
> + This voltage is specified in millivolts.
>
> + **/
>
> + INT16 CoreVfPointOffset[CPU_OC_MAX_VF_POINTS];
>
> + UINT8 RsvdByte3[2]; ///< Just to keep native alignment.
>
> + /**
>
> + Array for the each selected VF Point to display the Core Ration.
>
> + **/
>
> + UINT8 CoreVfPointRatio[CPU_OC_MAX_VF_POINTS];
>
> + /**
>
> + Number of supported Core Voltage & Frequency Point.
>
> + **/
>
> + UINT8 CoreVfPointCount;
>
> + /**
>
> + Core mask is a bitwise indication of which core should be disabled. Bit 0 -
> core 0, bit 7 - core 7.
>
> + **/
>
> + UINT32 DisableCoreMask;
>
> + UINT8 PerCoreRatio[CPU_OC_MAX_CORES];
>
> + /**
>
> + The VcccIn voltage override.
>
> + This will override VccIn output voltage level to the voltage value specified.
>
> + The voltage level is fixed and will not change except on PKG C-states or
> resets.
>
> +
>
> + <b>0. no override</b>. Range 0-3000 mV.
>
> + **/
>
> + UINT32 VccInVoltageOverride;
>
> +} OVERCLOCKING_PREMEM_CONFIG;
>
> +
>
> +#pragma pack (pop)
>
> +
>
> +#endif // _CPU_OVERCLOCKING_CONFIG_H_
>
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/P2sb/P2sbConfig.h
> b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/P2sb/P2sbConfig.h
> new file mode 100644
> index 0000000000..69271205b1
> --- /dev/null
> +++
> b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/P2sb/P2sbConfig.h
> @@ -0,0 +1,34 @@
> +/** @file
>
> + P2sb policy
>
> +
>
> + Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +**/
>
> +#ifndef _P2SB_CONFIG_H_
>
> +#define _P2SB_CONFIG_H_
>
> +
>
> +#define P2SB_CONFIG_REVISION 1
>
> +extern EFI_GUID gP2sbConfigGuid;
>
> +
>
> +#pragma pack (push,1)
>
> +
>
> +/**
>
> + This structure contains the policies which are related to P2SB device.
>
> +**/
>
> +typedef struct {
>
> + CONFIG_BLOCK_HEADER Header; ///< Config Block Header
>
> + /**
>
> + <b>(Test)</b>
>
> + The sideband MMIO register access to specific ports will be locked
>
> + before 3rd party code execution. Currently it disables PSFx access.
>
> + This policy unlocks the sideband MMIO space for those IPs.
>
> + <b>0: Lock sideband access </b>; 1: Unlock sideband access.
>
> + NOTE: Do not set this policy "SbAccessUnlock" unless its necessary.
>
> + **/
>
> + UINT32 SbAccessUnlock : 1;
>
> + UINT32 Rsvdbits : 31; ///< Reserved bits
>
> +} PCH_P2SB_CONFIG;
>
> +
>
> +#pragma pack (pop)
>
> +
>
> +#endif // _P2SB_CONFIG_H_
>
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/PchDmi/PchDmiConfi
> g.h
> b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/PchDmi/PchDmiConf
> ig.h
> new file mode 100644
> index 0000000000..b73108bcfd
> --- /dev/null
> +++
> b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/PchDmi/PchDmiConf
> ig.h
> @@ -0,0 +1,44 @@
> +/** @file
>
> + DMI policy
>
> +
>
> + Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +**/
>
> +#ifndef _PCH_DMI_CONFIG_H_
>
> +#define _PCH_DMI_CONFIG_H_
>
> +
>
> +#define PCH_DMI_CONFIG_REVISION 2
>
> +extern EFI_GUID gPchDmiConfigGuid;
>
> +
>
> +
>
> +#pragma pack (push,1)
>
> +
>
> +
>
> +/**
>
> + The PCH_DMI_CONFIG block describes the expected configuration of the
> PCH for DMI.
>
> + <b>Revision 1</b>: - Initial version.
>
> + <b>Revision 2</b>: - Add OpioRecenter
>
> +**/
>
> +typedef struct {
>
> + CONFIG_BLOCK_HEADER Header; ///< Config Block Header
>
> +
>
> + UINT32 PwrOptEnable : 1; ///< <b>0: Disable</b>; 1: Enable DMI
> Power Optimizer on PCH side.
>
> + UINT32 DmiAspmCtrl : 8; ///< ASPM configuration on the PCH side
> of the DMI/OPI Link. Default is <b>PchPcieAspmAutoConfig</b>
>
> + UINT32 CwbEnable : 1; ///< 0: Disable; <b>1: Enable</b> Central
> Write Buffer feature configurable and enabled by default
>
> + UINT32 L1RpCtl : 1; ///< 0: Disable; <b>1: Enable</b> Allow DMI
> enter L1 when all root ports are in L1, L0s or link down. Disabled by default.
>
> + /**
>
> + When set to TRUE turns on:
>
> + - L1 State Controller Power Gating
>
> + - L1 State PHY Data Lane Power Gating
>
> + - PHY Common Lane Power Gating
>
> + - Hardware Autonomous Enable
>
> + - PMC Request Enable and Sleep Enable
>
> + **/
>
> + UINT32 DmiPowerReduction : 1;
>
> + UINT32 OpioRecenter : 1; ///< 0: Disable; <b>1: Enable</b> Opio
> Recentering Disable for Pcie latency
>
> + UINT32 Rsvdbits : 19; ///< Reserved bits
>
> +} PCH_DMI_CONFIG;
>
> +
>
> +#pragma pack (pop)
>
> +
>
> +#endif // _PCH_DMI_CONFIG_H_
>
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/PcieRp/PchPcieRp/Pc
> hPcieRpConfig.h
> b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/PcieRp/PchPcieRp/P
> chPcieRpConfig.h
> new file mode 100644
> index 0000000000..de086473a9
> --- /dev/null
> +++
> b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/PcieRp/PchPcieRp/P
> chPcieRpConfig.h
> @@ -0,0 +1,368 @@
> +/** @file
>
> + PCH Pcie root port policy
>
> +
>
> + Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +**/
>
> +#ifndef _PCH_PCIERP_CONFIG_H_
>
> +#define _PCH_PCIERP_CONFIG_H_
>
> +
>
> +#include <PchLimits.h>
>
> +#include <PcieConfig.h>
>
> +#include <ConfigBlock.h>
>
> +
>
> +#define PCIE_RP_CONFIG_REVISION 1
>
> +#define PCIE_RP_PREMEM_CONFIG_REVISION 1
>
> +#define PCIE_RP_DXE_CONFIG_REVISION 1
>
> +
>
> +extern EFI_GUID gPchPcieConfigGuid;
>
> +extern EFI_GUID gPcieRpPreMemConfigGuid;
>
> +
>
> +#pragma pack (push,1)
>
> +
>
> +#define PCIE_LINK_EQ_COEFFICIENTS_MAX 10
>
> +#define PCIE_LINK_EQ_PRESETS_MAX 11
>
> +
>
> +typedef enum {
>
> + PchPcieOverrideDisabled = 0,
>
> + PchPcieL1L2Override = 0x01,
>
> + PchPcieL1SubstatesOverride = 0x02,
>
> + PchPcieL1L2AndL1SubstatesOverride = 0x03,
>
> + PchPcieLtrOverride = 0x04
>
> +} PCH_PCIE_OVERRIDE_CONFIG;
>
> +
>
> +/**
>
> + PCIe device table entry entry
>
> +
>
> + The PCIe device table is being used to override PCIe device ASPM settings.
>
> + To take effect table consisting of such entries must be instelled as PPI
>
> + on gPchPcieDeviceTablePpiGuid.
>
> + Last entry VendorId must be 0.
>
> +**/
>
> +typedef struct {
>
> + UINT16 VendorId; ///< The vendor Id of Pci Express card ASPM
> setting override, 0xFFFF means any Vendor ID
>
> + UINT16 DeviceId; ///< The Device Id of Pci Express card ASPM
> setting override, 0xFFFF means any Device ID
>
> + UINT8 RevId; ///< The Rev Id of Pci Express card ASPM setting
> override, 0xFF means all steppings
>
> + UINT8 BaseClassCode; ///< The Base Class Code of Pci Express card
> ASPM setting override, 0xFF means all base class
>
> + UINT8 SubClassCode; ///< The Sub Class Code of Pci Express card
> ASPM setting override, 0xFF means all sub class
>
> + UINT8 EndPointAspm; ///< Override device ASPM (see:
> PCH_PCIE_ASPM_CONTROL)
>
> + ///< Bit 1 must be set in OverrideConfig for this field to
> take effect
>
> + UINT16 OverrideConfig; ///< The override config bitmap (see:
> PCH_PCIE_OVERRIDE_CONFIG).
>
> + /**
>
> + The L1Substates Capability Offset Override. (applicable if bit 2 is set in
> OverrideConfig)
>
> + This field can be zero if only the L1 Substate value is going to be override.
>
> + **/
>
> + UINT16 L1SubstatesCapOffset;
>
> + /**
>
> + L1 Substate Capability Mask. (applicable if bit 2 is set in OverrideConfig)
>
> + Set to zero then the L1 Substate Capability [3:0] is ignored, and only L1s
> values are override.
>
> + Only bit [3:0] are applicable. Other bits are ignored.
>
> + **/
>
> + UINT8 L1SubstatesCapMask;
>
> + /**
>
> + L1 Substate Port Common Mode Restore Time Override. (applicable if bit
> 2 is set in OverrideConfig)
>
> + L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid
> value of 0, but not the L1sTpowerOnValue.
>
> + If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime,
> L1sTpowerOnScale, and L1sTpowerOnValue are ignored,
>
> + and only L1SubstatesCapOffset is override.
>
> + **/
>
> + UINT8 L1sCommonModeRestoreTime;
>
> + /**
>
> + L1 Substate Port Tpower_on Scale Override. (applicable if bit 2 is set in
> OverrideConfig)
>
> + L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid
> value of 0, but not the L1sTpowerOnValue.
>
> + If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime,
> L1sTpowerOnScale, and L1sTpowerOnValue are ignored,
>
> + and only L1SubstatesCapOffset is override.
>
> + **/
>
> + UINT8 L1sTpowerOnScale;
>
> + /**
>
> + L1 Substate Port Tpower_on Value Override. (applicable if bit 2 is set in
> OverrideConfig)
>
> + L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid
> value of 0, but not the L1sTpowerOnValue.
>
> + If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime,
> L1sTpowerOnScale, and L1sTpowerOnValue are ignored,
>
> + and only L1SubstatesCapOffset is override.
>
> + **/
>
> + UINT8 L1sTpowerOnValue;
>
> +
>
> + /**
>
> + SnoopLatency bit definition
>
> + Note: All Reserved bits must be set to 0
>
> +
>
> + BIT[15] - When set to 1b, indicates that the values in bits 9:0 are valid
>
> + When clear values in bits 9:0 will be ignored
>
> + BITS[14:13] - Reserved
>
> + BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in these bits
>
> + 000b - 1 ns
>
> + 001b - 32 ns
>
> + 010b - 1024 ns
>
> + 011b - 32,768 ns
>
> + 100b - 1,048,576 ns
>
> + 101b - 33,554,432 ns
>
> + 110b - Reserved
>
> + 111b - Reserved
>
> + BITS[9:0] - Snoop Latency Value. The value in these bits will be multiplied
> with
>
> + the scale in bits 12:10
>
> +
>
> + This field takes effect only if bit 3 is set in OverrideConfig.
>
> + **/
>
> + UINT16 SnoopLatency;
>
> + /**
>
> + NonSnoopLatency bit definition
>
> + Note: All Reserved bits must be set to 0
>
> +
>
> + BIT[15] - When set to 1b, indicates that the values in bits 9:0 are valid
>
> + When clear values in bits 9:0 will be ignored
>
> + BITS[14:13] - Reserved
>
> + BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in these bits
>
> + 000b - 1 ns
>
> + 001b - 32 ns
>
> + 010b - 1024 ns
>
> + 011b - 32,768 ns
>
> + 100b - 1,048,576 ns
>
> + 101b - 33,554,432 ns
>
> + 110b - Reserved
>
> + 111b - Reserved
>
> + BITS[9:0] - Non Snoop Latency Value. The value in these bits will be
> multiplied with
>
> + the scale in bits 12:10
>
> +
>
> + This field takes effect only if bit 3 is set in OverrideConfig.
>
> + **/
>
> + UINT16 NonSnoopLatency;
>
> +
>
> + /**
>
> + Forces LTR override to be permanent
>
> + The default way LTR override works is:
>
> + rootport uses LTR override values provided by BIOS until connected
> device sends an LTR message, then it will use values from the message
>
> + This settings allows force override of LTR mechanism. If it's enabled, then:
>
> + rootport will use LTR override values provided by BIOS forever; LTR
> messages sent from connected device will be ignored
>
> + **/
>
> + UINT8 ForceLtrOverride;
>
> + UINT8 Reserved[3];
>
> +} PCH_PCIE_DEVICE_OVERRIDE;
>
> +
>
> +///
>
> +/// The values before AutoConfig match the setting of PCI Express Base
> Specification 1.1, please be careful for adding new feature
>
> +///
>
> +typedef enum {
>
> + PchPcieAspmDisabled,
>
> + PchPcieAspmL0s,
>
> + PchPcieAspmL1,
>
> + PchPcieAspmL0sL1,
>
> + PchPcieAspmAutoConfig,
>
> + PchPcieAspmMax
>
> +} PCH_PCIE_ASPM_CONTROL;
>
> +
>
> +/**
>
> + Refer to PCH EDS for the PCH implementation values corresponding
>
> + to below PCI-E spec defined ranges
>
> +**/
>
> +typedef enum {
>
> + PchPcieL1SubstatesDisabled,
>
> + PchPcieL1SubstatesL1_1,
>
> + PchPcieL1SubstatesL1_1_2,
>
> + PchPcieL1SubstatesMax
>
> +} PCH_PCIE_L1SUBSTATES_CONTROL;
>
> +
>
> +enum PCH_PCIE_MAX_PAYLOAD {
>
> + PchPcieMaxPayload128 = 0,
>
> + PchPcieMaxPayload256,
>
> + PchPcieMaxPayloadMax
>
> +};
>
> +
>
> +typedef enum {
>
> + PcieLinkHardwareEq = 0, ///< Hardware is responsible for performing
> coefficient/preset search.
>
> + PcieLinkFixedEq ///< No coefficient/preset search is performed. Fixed
> values are used.
>
> +} PCIE_LINK_EQ_METHOD;
>
> +
>
> +typedef enum {
>
> + PcieLinkEqPresetMode = 0, ///< Use presets during PCIe link equalization
>
> + PcieLinkEqCoefficientMode ///< Use coefficients during PCIe link
> equalization
>
> +} PCIE_LINK_EQ_MODE;
>
> +
>
> +typedef struct {
>
> + UINT32 PreCursor; ///< Pre-cursor coefficient
>
> + UINT32 PostCursor; ///< Post-cursor coefficient
>
> +} PCIE_LINK_EQ_COEFFICIENTS;
>
> +
>
> +/**
>
> + PCIe Link EQ Platform Settings
>
> +**/
>
> +typedef struct {
>
> + UINT8 PcieLinkEqMethod; ///< Tells BIOS which link EQ
> method should be used for this port. Please refer to
> PCIE_LINK_EQ_METHOD for details of supported methods. Default:
> PcieLinkHardwareEq
>
> + UINT8 PcieLinkEqMode; ///< Tells BIOS which mode
> should be used for PCIe link EQ. Please refer to PCIE_LINK_EQ_MODE for
> details of supported modes. Default: depends on SoC
>
> + /**
>
> + Specifies if BIOS should perform local transmitter override during phase 2
> of EQ process.
>
> + If enabled value in Ph2LocalTransmitterOverridePreset must be valid.
>
> + <b>0: Disabled</b>; 1: Enabled
>
> + **/
>
> + UINT8 LocalTransmitterOverrideEnable;
>
> + /**
>
> + Tells BIOS how many presets/coefficients should be used during link EQ.
>
> + Entries in the Ph3CoefficientsList or Ph3PresetList(depending on chosen
> mode) need to be valid up to the number specified in this field.
>
> + **/
>
> + UINT8 Ph3NumberOfPresetsOrCoefficients;
>
> +
>
> + PCIE_LINK_EQ_COEFFICIENTS
> Ph3CoefficientsList[PCIE_LINK_EQ_COEFFICIENTS_MAX]; ///< List of the
> PCIe coefficients to be used during equalization process. Only valid if
> PcieLinkEqMode is PcieLinkEqCoefficientMode
>
> + UINT32 Ph3PresetList[PCIE_LINK_EQ_PRESETS_MAX]; ///<
> List of the PCIe preset values to be used during equalization process. Only
> valid if PcieLinkEqMode is PcieLinkEqPresetMode
>
> + UINT32 Ph1DownstreamPortTransmitterPreset; ///< Specifies
> the value of the downstream port transmitter preset to be used during
> phase 1 of the equalization process. Will be applied to all lanes
>
> + UINT32 Ph1UpstreamPortTransmitterPreset; ///< Specifies the
> value of the upstream port transmitter preset to be used during phase 1 of
> the equalization process. Will be applied to all lanes
>
> + /**
>
> + Specifies the preset that should be used during local transmitter override
> during phase 2 of EQ process.
>
> + Used only if LocalTransmitterOverrideEnable is TRUE. Will be applied to all
> PCIe lanes of the root port.
>
> + Valid up to the PCIE_LINK_EQ_PRESET_MAX value. <b>Default: 0<\b>
>
> + **/
>
> + UINT32 Ph2LocalTransmitterOverridePreset;
>
> +} PCIE_LINK_EQ_PLATFORM_SETTINGS;
>
> +
>
> +#define PCH_PCIE_NO_SUCH_CLOCK 0xFF
>
> +
>
> +typedef enum {
>
> + PchClockUsagePchPcie0 = 0,
>
> + PchClockUsagePchPcie1 = 1,
>
> + PchClockUsagePchPcie2 = 2,
>
> + PchClockUsagePchPcie3 = 3,
>
> + PchClockUsagePchPcie4 = 4,
>
> + PchClockUsagePchPcie5 = 5,
>
> + PchClockUsagePchPcie6 = 6,
>
> + PchClockUsagePchPcie7 = 7,
>
> + PchClockUsagePchPcie8 = 8,
>
> + PchClockUsagePchPcie9 = 9,
>
> + PchClockUsagePchPcie10 = 10,
>
> + PchClockUsagePchPcie11 = 11,
>
> + PchClockUsagePchPcie12 = 12,
>
> + PchClockUsagePchPcie13 = 13,
>
> + PchClockUsagePchPcie14 = 14,
>
> + PchClockUsagePchPcie15 = 15,
>
> + PchClockUsagePchPcie16 = 16,
>
> + PchClockUsagePchPcie17 = 17,
>
> + PchClockUsagePchPcie18 = 18,
>
> + PchClockUsagePchPcie19 = 19,
>
> + PchClockUsagePchPcie20 = 20,
>
> + PchClockUsagePchPcie21 = 21,
>
> + PchClockUsagePchPcie22 = 22,
>
> + PchClockUsagePchPcie23 = 23,
>
> + /**
>
> + Quantity of PCH and CPU PCIe ports, as well as their encoding in this
> enum, may change between
>
> + silicon generations and series. Do not assume that PCH port 0 will be
> always encoded by 0.
>
> + Instead, it is recommended to use (PchClockUsagePchPcie0 +
> PchPortIndex) style to be forward-compatible
>
> + **/
>
> + PchClockUsageCpuPcie0 = 0x40,
>
> + PchClockUsageCpuPcie1 = 0x41,
>
> + PchClockUsageCpuPcie2 = 0x42,
>
> + PchClockUsageCpuPcie3 = 0x43,
>
> +
>
> + PchClockUsageLan = 0x70,
>
> + PchClockUsageUnspecified = 0x80, ///< In use for a purpose not listed
> above
>
> + PchClockUsageNotUsed = 0xFF
>
> +} PCH_PCIE_CLOCK_USAGE;
>
> +
>
> +/**
>
> + PCH_PCIE_CLOCK describes PCIe source clock generated by PCH.
>
> +**/
>
> +typedef struct {
>
> + UINT8 Usage; ///< Purpose of given clock (see
> PCH_PCIE_CLOCK_USAGE). Default: Unused, 0xFF
>
> + UINT8 ClkReq; ///< ClkSrc - ClkReq mapping. Default: 1:1 mapping with
> Clock numbers
>
> + UINT8 RsvdBytes[2]; ///< Reserved byte
>
> +} PCH_PCIE_CLOCK;
>
> +
>
> +/**
>
> + The PCH_PCI_EXPRESS_ROOT_PORT_CONFIG describe the feature and
> capability of each PCH PCIe root port.
>
> +**/
>
> +typedef struct {
>
> + PCIE_ROOT_PORT_COMMON_CONFIG PcieRpCommonConfig; ///an
> instance of Pcie Common Config
>
> + UINT8 ExtSync; ///< Indicate whether the extended synch is
> enabled. <b>0: Disable</b>; 1: Enable.
>
> + //
>
> + // Error handlings
>
> + //
>
> + UINT8 SystemErrorEnable; ///< Indicate whether the System Error is
> enabled. <b>0: Disable</b>; 1: Enable.
>
> + /**
>
> + The Multiple VC (MVC) supports hardware to avoid HoQ block for latency
> sensitive TC.
>
> + Currently it is only applicable to Root Ports with 2pX4 port configuration
> with 2 VCs,or
>
> + DMI port configuration with 3 VCs. For Root Ports 2pX4 configuration, two
> RPs (RP0,
>
> + RP2) shall support two PCIe VCs (VC0 & VC1) and the other RPs (RP1, RP3)
> shall be
>
> + disabled.
>
> + <b>0: Disable</b>; 1: Enable
>
> + **/
>
> + UINT8 MvcEnabled;
>
> + /**
>
> + Virtual Pin Port is industry standard introduced to PCIe Hot Plug support in
> systems
>
> + when GPIO pins expansion is needed. It is server specific feature.
>
> + <b>0x00: Default</b>; 0xFF: Disabled
>
> + **/
>
> + UINT8 VppPort;
>
> + UINT8 VppAddress; ///< PCIe Hot Plug VPP SMBus
> Address. Default is zero.
>
> + UINT8 RsvdBytes0[3]; ///< Reserved bytes
>
> +} PCH_PCIE_ROOT_PORT_CONFIG;
>
> +
>
> +/**
>
> + The PCH_PCIE_CONFIG block describes the expected configuration of the
> PCH PCI Express controllers
>
> + <b>Revision 1</b>:
>
> + - Initial version.
>
> +**/
>
> +typedef struct {
>
> + CONFIG_BLOCK_HEADER Header; ///< Config Block Header
>
> + ///
>
> + /// These members describe the configuration of each PCH PCIe root port.
>
> + ///
>
> + PCIE_COMMON_CONFIG PcieCommonConfig;
>
> + PCH_PCIE_ROOT_PORT_CONFIG
> RootPort[PCH_MAX_PCIE_ROOT_PORTS];
>
> + PCIE_LINK_EQ_PLATFORM_SETTINGS PcieLinkEqPlatformSettings; ///<
> Global PCIe link EQ settings that BIOS will use during PCIe link EQ for every
> port.
>
> + ///
>
> + /// <b>0: Use project default equalization settings</b>; 1: Use
> equalization settings from PcieLinkEqPlatformSettings
>
> + ///
>
> + UINT8 OverrideEqualizationDefaults;
>
> + ///
>
> + /// <b>(Test)</b> This member describes whether PCIE root port Port 8xh
> Decode is enabled. <b>0: Disable</b>; 1: Enable.
>
> + ///
>
> + UINT8 EnablePort8xhDecode;
>
> + ///
>
> + /// <b>(Test)</b> The Index of PCIe Port that is selected for Port8xh
> Decode (0 Based)
>
> + ///
>
> + UINT8 PchPciePort8xhDecodePortIndex;
>
> + UINT8 RsvdBytes0[1];
>
> +} PCH_PCIE_CONFIG;
>
> +
>
> +/**
>
> + The PCH_PCIE_RP_PREMEM_CONFIG block describes early configuration
> of the PCH PCI Express controllers
>
> + <b>Revision 1</b>:
>
> + - Initial version.
>
> +**/
>
> +typedef struct {
>
> + CONFIG_BLOCK_HEADER Header; ///< Config Block
> Header
>
> + /**
>
> + Root Port enabling mask.
>
> + Bit0 presents RP1, Bit1 presents RP2, and so on.
>
> + 0: Disable; <b>1: Enable</b>.
>
> + **/
>
> + UINT32 RpEnabledMask;
>
> + /// Configuration of PCIe source clocks
>
> + ///
>
> + PCH_PCIE_CLOCK PcieClock[PCH_MAX_PCIE_CLOCKS];
>
> +
>
> + /**
>
> + Per Controller Bifurcation Configuration
>
> + <b>0: Disabled</b>; 1: 4x1; 2: 1x2_2x1; 3: 2x2; 4: 1x4; 5: 4x2; 6: 1x4_2x2; 7:
> 2x2_1x4; 8: 2x4; 9: 1x8 (see: PCIE_BIFURCATION_CONFIG)
>
> + **/
>
> + UINT8 Bifurcation[PCH_MAX_PCIE_CONTROLLERS];
>
> + UINT8 Rsvd4[(4 - PCH_MAX_PCIE_CONTROLLERS % 4) % 4];
>
> +} PCH_PCIE_RP_PREMEM_CONFIG;
>
> +
>
> +/**
>
> + The PCIE_RP_DXE_CONFIG block describes the expected configuration of
> the PCH PCI Express controllers in DXE phase
>
> +
>
> + <b>Revision 1</b>:
>
> + - Init version
>
> +**/
>
> +typedef struct {
>
> + CONFIG_BLOCK_HEADER Header; ///< Config Block Header
>
> +
>
> + /**
>
> + PCIe device override table
>
> + The PCIe device table is being used to override PCIe device ASPM
> settings.
>
> + And it's only used in DXE phase.
>
> + Please refer to PCH_PCIE_DEVICE_OVERRIDE structure for the table.
>
> + Last entry VendorId must be 0.
>
> + **/
>
> + PCH_PCIE_DEVICE_OVERRIDE *PcieDeviceOverrideTablePtr;
>
> +} PCIE_RP_DXE_CONFIG;
>
> +
>
> +#pragma pack (pop)
>
> +
>
> +#endif // _PCH_PCIERP_CONFIG_H_
>
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/PcieRp/PcieConfig.h
> b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/PcieRp/PcieConfig.h
> new file mode 100644
> index 0000000000..f5859f50d9
> --- /dev/null
> +++
> b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/PcieRp/PcieConfig.h
> @@ -0,0 +1,213 @@
> +/** @file
>
> + PCIe Config Block
>
> +
>
> + Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +**/
>
> +#ifndef _PCIE_CONFIG_H_
>
> +#define _PCIE_CONFIG_H_
>
> +#include <CpuPcieInfo.h>
>
> +
>
> +#define PCIE_CONFIG_REVISION 3
>
> +/*
>
> +<b>Revision 2< / b>:
>
> +FomsCp - Deprecated
>
> +<b>Revision 3< / b>:
>
> +Added PCIE_EQ_PARAM HwEqGen3CoeffList for all
> CPU_PCIE_MAX_ROOT_PORTS
>
> +Added PCIE_EQ_PARAM HwEqGen4CoeffList for all
> CPU_PCIE_MAX_ROOT_PORTS
>
> +Added PCIE_EQ_PARAM HwEqGen5CoeffList for all
> CPU_PCIE_MAX_ROOT_PORTS
>
> +*/
>
> +
>
> +extern EFI_GUID gPcieConfigGuid;
>
> +
>
> +#pragma pack (push,1)
>
> +
>
> +enum PCIE_COMPLETION_TIMEOUT {
>
> + PcieCompletionTO_Default,
>
> + PcieCompletionTO_50_100us,
>
> + PcieCompletionTO_1_10ms,
>
> + PcieCompletionTO_16_55ms,
>
> + PcieCompletionTO_65_210ms,
>
> + PcieCompletionTO_260_900ms,
>
> + PcieCompletionTO_1_3P5s,
>
> + PcieCompletionTO_4_13s,
>
> + PcieCompletionTO_17_64s,
>
> + PcieCompletionTO_Disabled
>
> +};
>
> +
>
> +enum PCIE_SPEED {
>
> + PcieAuto,
>
> + PcieGen1,
>
> + PcieGen2,
>
> + PcieGen3,
>
> + PcieGen4
>
> +};
>
> +
>
> +/**
>
> + Represent lane specific PCIe Gen3 equalization parameters.
>
> +**/
>
> +typedef struct {
>
> + UINT8 Cm; ///< Coefficient C-1
>
> + UINT8 Cp; ///< Coefficient C+1
>
> + UINT8 Rsvd0[2]; ///< Reserved bytes
>
> +} PCIE_EQ_PARAM;
>
> +
>
> +typedef struct {
>
> + UINT16 LtrMaxSnoopLatency; ///< <b>(Test)</b> Latency
> Tolerance Reporting, Max Snoop Latency.
>
> + UINT16 LtrMaxNoSnoopLatency; ///< <b>(Test)</b> Latency
> Tolerance Reporting, Max Non-Snoop Latency.
>
> + UINT8 SnoopLatencyOverrideMode; ///< <b>(Test)</b> Latency
> Tolerance Reporting, Snoop Latency Override Mode.
>
> + UINT8 SnoopLatencyOverrideMultiplier; ///< <b>(Test)</b> Latency
> Tolerance Reporting, Snoop Latency Override Multiplier.
>
> + UINT16 SnoopLatencyOverrideValue; ///< <b>(Test)</b> Latency
> Tolerance Reporting, Snoop Latency Override Value.
>
> + UINT8 NonSnoopLatencyOverrideMode; ///< <b>(Test)</b>
> Latency Tolerance Reporting, Non-Snoop Latency Override Mode.
>
> + UINT8 NonSnoopLatencyOverrideMultiplier; ///< <b>(Test)</b>
> Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier.
>
> + UINT16 NonSnoopLatencyOverrideValue; ///< <b>(Test)</b>
> Latency Tolerance Reporting, Non-Snoop Latency Override Value.
>
> + UINT8 LtrConfigLock; ///< <b>0: Disable</b>; 1: Enable.
>
> + UINT8 ForceLtrOverride;
>
> + UINT16 RsvdByte1;
>
> +} PCIE_LTR_CONFIG;
>
> +
>
> +
>
> +/**
>
> + Specifies the form factor that the slot
>
> + implements. For custom form factors that
>
> + do not require any special handling please
>
> + set PcieFormFactorOther.
>
> +**/
>
> +typedef enum {
>
> + PcieFormFactorOther = 0,
>
> + PcieFormFactorCem,
>
> + PcieFormFactorMiniPci,
>
> + PcieFormFactorM2,
>
> + PcieFormFactorOcuLink,
>
> + PcieFormFactorExpressModule, // Also known as Server IO module(SIOM)
>
> + PcieFormFactorExpressCard,
>
> + PcieFormFactorU2 // Also known as SF-8639
>
> +} PCIE_FORM_FACTOR;
>
> +
>
> +//Note: This structure will be expanded to hold all common PCIe policies
> between SA and PCH RootPort
>
> +typedef struct {
>
> + UINT32 HotPlug : 1; ///< Indicate whether the root port is hot
> plug available. <b>0: Disable</b>; 1: Enable.
>
> + UINT32 PmSci : 1; ///< Indicate whether the root port
> power manager SCI is enabled. 0: Disable; <b>1: Enable</b>.
>
> + UINT32 TransmitterHalfSwing : 1; ///< Indicate whether the
> Transmitter Half Swing is enabled. <b>0: Disable</b>; 1: Enable.
>
> + UINT32 AcsEnabled : 1; ///< Indicate whether the ACS is
> enabled. 0: Disable; <b>1: Enable</b>.
>
> + //
>
> + // Error handlings
>
> + //
>
> + UINT32 AdvancedErrorReporting : 1; ///< Indicate whether the
> Advanced Error Reporting is enabled. <b>0: Disable</b>; 1: Enable.
>
> + UINT32 UnsupportedRequestReport : 1; ///< Indicate whether the
> Unsupported Request Report is enabled. <b>0: Disable</b>; 1: Enable.
>
> + UINT32 FatalErrorReport : 1; ///< Indicate whether the Fatal Error
> Report is enabled. <b>0: Disable</b>; 1: Enable.
>
> + UINT32 NoFatalErrorReport : 1; ///< Indicate whether the No Fatal
> Error Report is enabled. <b>0: Disable</b>; 1: Enable.
>
> + UINT32 CorrectableErrorReport : 1; ///< Indicate whether the
> Correctable Error Report is enabled. <b>0: Disable</b>; 1: Enable.
>
> + UINT32 SystemErrorOnFatalError : 1; ///< Indicate whether the
> System Error on Fatal Error is enabled. <b>0: Disable</b>; 1: Enable.
>
> + UINT32 SystemErrorOnNonFatalError : 1; ///< Indicate whether the
> System Error on Non Fatal Error is enabled. <b>0: Disable</b>; 1: Enable.
>
> + UINT32 SystemErrorOnCorrectableError : 1; ///< Indicate whether the
> System Error on Correctable Error is enabled. <b>0: Disable</b>; 1: Enable.
>
> + /**
>
> + Max Payload Size supported, Default <b>128B</b>, see enum
> CPU_PCIE_MAX_PAYLOAD
>
> + Changes Max Payload Size Supported field in Device Capabilities of the
> root port.
>
> + **/
>
> + UINT32 MaxPayload : 2;
>
> + UINT32 DpcEnabled : 1; ///< Downstream Port Containment.
> 0: Disable; <b>1: Enable</b>
>
> + UINT32 RpDpcExtensionsEnabled : 1; ///< RP Extensions for
> Downstream Port Containment. 0: Disable; <b>1: Enable</b>
>
> + /**
>
> + Indicates how this root port is connected to endpoint. 0: built-in device;
> <b>1: slot</b>
>
> + Built-in is incompatible with hotplug-capable ports.
>
> + **/
>
> + UINT32 SlotImplemented : 1;
>
> + UINT32 PtmEnabled : 1; ///< Enables PTM capability
>
> + UINT32 SlotPowerLimitScale : 2; ///< <b>(Test)</b> Specifies scale
> used for slot power limit value. Leave as 0 to set to default. Default is
> <b>zero</b>.
>
> + UINT32 SlotPowerLimitValue : 12; //< <b>(Test)</b> Specifies
> upper limit on power supplies by slot. Leave as 0 to set to default. Default is
> <b>zero</b>.
>
> + /**
>
> + Probe CLKREQ# signal before enabling CLKREQ# based power
> management.
>
> + Conforming device shall hold CLKREQ# low until CPM is enabled. This
> feature attempts
>
> + to verify CLKREQ# signal is connected by testing pad state before enabling
> CPM.
>
> + In particular this helps to avoid issues with open-ended PCIe slots.
>
> + This is only applicable to non hot-plug ports.
>
> + <b>0: Disable</b>; 1: Enable.
>
> + **/
>
> + UINT32 ClkReqDetect : 1;
>
> + /**
>
> + Set if the slot supports manually operated retention latch.
>
> + **/
>
> + UINT32 MrlSensorPresent : 1;
>
> + UINT32 RelaxedOrder : 1;
>
> + UINT32 NoSnoop : 1;
>
> + UINT32 RsvdBits0 : 28; ///< Reserved bits.
>
> + /**
>
> + PCIe Gen3 Equalization Phase 3 Method (see CPU_PCIE_EQ_METHOD).
>
> + 0: DEPRECATED, hardware equalization; <b>1: hardware
> equalization</b>; 4: Fixed Coefficients
>
> + **/
>
> + UINT8 Gen3EqPh3Method;
>
> + UINT8 PhysicalSlotNumber; ///< Indicates the slot number for
> the root port. Default is the value as root port index.
>
> + UINT8 CompletionTimeout; ///< The completion timeout
> configuration of the root port (see: CPU_PCIE_COMPLETION_TIMEOUT).
> Default is <b>PchPcieCompletionTO_Default</b>.
>
> + //
>
> + // Power Management
>
> + //
>
> + UINT8 Aspm; ///< The ASPM configuration of the root
> port (see: CPU_PCIE_ASPM_CONTROL). Default is
> <b>PchPcieAspmAutoConfig</b>.
>
> + UINT8 L1Substates; ///< The L1 Substates configuration of
> the root port (see: CPU_PCIE_L1SUBSTATES_CONTROL). Default is
> <b>PchPcieL1SubstatesL1_1_2</b>.
>
> + UINT8 LtrEnable; ///< Latency Tolerance Reporting
> Mechanism. <b>0: Disable</b>; 1: Enable.
>
> + UINT8 EnableCpm; ///< Enables Clock Power Management;
> even if disabled, CLKREQ# signal can still be controlled by L1 PM substates
> mechanism
>
> + UINT8 PcieSpeed; ///< Contains speed of PCIe bus (see:
> PCIE_SPEED)
>
> + /**
>
> + <b>(Test)</b>
>
> + Forces LTR override to be permanent
>
> + The default way LTR override works is:
>
> + rootport uses LTR override values provided by BIOS until connected device
> sends an LTR message, then it will use values from the message
>
> + This settings allows force override of LTR mechanism. If it's enabled, then:
>
> + rootport will use LTR override values provided by BIOS forever; LTR
> messages sent from connected device will be ignored
>
> + **/
>
> + PCIE_LTR_CONFIG PcieRpLtrConfig; ///< <b>(Test)</b>
> Latency Tolerance Reporting Policies including LTR limit and Override
>
> + /**
>
> + The number of milliseconds reference code will wait for link to exit Detect
> state for enabled ports
>
> + before assuming there is no device and potentially disabling the port.
>
> + It's assumed that the link will exit detect state before root port
> initialization (sufficient time
>
> + elapsed since PLTRST de-assertion) therefore default timeout is zero.
> However this might be useful
>
> + if device power-up seqence is controlled by BIOS or a specific device
> requires more time to detect.
>
> + In case of non-common clock enabled the default timout is 15ms.
>
> + <b>Default: 0</b>
>
> + **/
>
> + UINT16 DetectTimeoutMs;
>
> + UINT8 FormFactor; // Please check PCIE_FORM_FACTOR for supported
> values
>
> + UINT8 Reserved;
>
> +} PCIE_ROOT_PORT_COMMON_CONFIG;
>
> +
>
> +/**
>
> + PCIe Common Config
>
> + @note This structure will be expanded to hold all common PCIe policies
> between SA and PCH
>
> +**/
>
> +typedef struct {
>
> + ///
>
> + /// This member describes whether Peer Memory Writes are enabled on
> the platform. <b>0: Disable</b>; 1: Enable.
>
> + ///
>
> + UINT32 EnablePeerMemoryWrite : 1;
>
> + /**
>
> + RpFunctionSwap allows BIOS to use root port function number swapping
> when root port of function 0 is disabled.
>
> + A PCIE device can have higher functions only when Function0 exists. To
> satisfy this requirement,
>
> + BIOS will always enable Function0 of a device that contains more than 0
> enabled root ports.
>
> + - <b>Enabled: One of enabled root ports get assigned to Function0.</b>
>
> + This offers no guarantee that any particular root port will be available at a
> specific DevNr:FuncNr location
>
> + - Disabled: Root port that corresponds to Function0 will be kept visible
> even though it might be not used.
>
> + That way rootport - to - DevNr:FuncNr assignment is constant. This
> option will impact ports 1, 9, 17.
>
> + NOTE: This option will not work if ports 1, 9, 17 are fused or configured
> for RST PCIe storage or disabled through policy
>
> + In other words, it only affects ports that would become hidden
> because they have no device connected.
>
> + NOTE: Disabling function swap may have adverse impact on power
> management. This option should ONLY
>
> + be used when each one of root ports 1, 9, 17:
>
> + - is configured as PCIe and has correctly configured ClkReq signal, or
>
> + - does not own any mPhy lanes (they are configured as SATA or USB)
>
> + **/
>
> + UINT32 RpFunctionSwap : 1;
>
> + /**
>
> + Compliance Test Mode shall be enabled when using Compliance Load
> Board.
>
> + <b>0: Disable</b>, 1: Enable
>
> + **/
>
> + UINT32 ComplianceTestMode : 1;
>
> + UINT32 RsvdBits0 : 29; ///< Reserved bits
>
> + ///
>
> + /// List of coefficients used during equalization (applicable to both
> software and hardware EQ)
>
> + /// Deprecated Policy
>
> + ///
>
> + PCIE_EQ_PARAM
> HwEqGen3CoeffList[PCIE_HWEQ_COEFFS_MAX];
>
> +} PCIE_COMMON_CONFIG;
>
> +
>
> +
>
> +#pragma pack (pop)
>
> +#endif // _PCIE_CONFIG_H_
>
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Pmc/AdrConfig.h
> b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Pmc/AdrConfig.h
> new file mode 100644
> index 0000000000..5c7811823d
> --- /dev/null
> +++
> b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Pmc/AdrConfig.h
> @@ -0,0 +1,86 @@
> +/** @file
>
> + ADR policy
>
> +
>
> + Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +**/
>
> +
>
> +#ifndef _ADR_CONFIG_H_
>
> +#define _ADR_CONFIG_H_
>
> +
>
> +#include <ConfigBlock.h>
>
> +
>
> +#define ADR_CONFIG_REVISION 1
>
> +extern EFI_GUID gAdrConfigGuid;
>
> +
>
> +#pragma pack (push,1)
>
> +
>
> +typedef enum {
>
> + AdrScale1us,
>
> + AdrScale10us,
>
> + AdrScale100us,
>
> + AdrScale1ms,
>
> + AdrScale10ms,
>
> + AdrScale100ms,
>
> + AdrScale1s,
>
> + AdrScale10s
>
> +} ADR_TIMER_SCALE;
>
> +
>
> +/**
>
> + ADR Source Enable
>
> +**/
>
> +typedef union {
>
> + struct {
>
> + UINT32 Reserved1 : 1;
>
> + UINT32 AdrSrcPbo : 1;
>
> + UINT32 AdrSrcPmcUncErr : 1;
>
> + UINT32 AdrSrcPchThrm : 1;
>
> + UINT32 AdrSrcMePbo : 1;
>
> + UINT32 AdrSrcCpuThrm : 1;
>
> + UINT32 AdrSrcMegbl : 1;
>
> + UINT32 AdrSrcLtReset : 1;
>
> + UINT32 AdrSrcPmcWdt : 1;
>
> + UINT32 AdrSrcMeWdt : 1;
>
> + UINT32 AdrSrcPmcFw : 1;
>
> + UINT32 AdrSrcPchpwrFlr : 1;
>
> + UINT32 AdrSrcSyspwrFlr : 1;
>
> + UINT32 Reserved2 : 1;
>
> + UINT32 AdrSrcMiaUxsErr : 1;
>
> + UINT32 AdrSrcMiaUxErr : 1;
>
> + UINT32 AdrSrcCpuThrmWdt : 1;
>
> + UINT32 AdrSrcMeUncErr : 1;
>
> + UINT32 AdrSrcAdrGpio : 1;
>
> + UINT32 AdrSrcOcwdtNoicc : 1;
>
> + UINT32 AdrSrcOcwdtIcc : 1;
>
> + UINT32 AdrSrcCseHecUncErr : 1;
>
> + UINT32 AdrSrcPmcSramUncErr : 1;
>
> + UINT32 AdrSrcPmcIromParity : 1;
>
> + UINT32 AdrSrcPmcRfFusaErr : 1;
>
> + UINT32 Reserved3 : 4;
>
> + UINT32 AdrSrcPpbrParityErr : 1;
>
> + UINT32 Reserved4 : 2;
>
> + } Field;
>
> + UINT32 Value;
>
> +} ADR_SOURCE_ENABLE;
>
> +
>
> +/**
>
> + ADR Configuration
>
> + <b>Revision 1</b>: - Initial version.
>
> +**/
>
> +typedef struct {
>
> + CONFIG_BLOCK_HEADER Header; ///< Config Block Header
>
> + UINT32 AdrEn : 2; ///< Determine if Adr is enabled - 0:
> PLATFORM_POR, 1: FORCE_ENABLE, 2: FORCE_DISABLE
>
> + UINT32 AdrTimerEn : 2; ///< Determine if Adr timer options are
> enabled - 0: PLATFORM_POR, 1: FORCE_ENABLE, 2: FORCE_DISABLE
>
> + UINT32 AdrTimer1Val : 2; ///< Determines the Timeout value used
> for the ADR timer 1. A value of zero bypasses the timer
>
> + UINT32 AdrMultiplier1Val : 8; ///< Specifies the tick frequency upon
> which the timer 1 will increment. ADR_TIMER_SCALE should be used to
> encode values
>
> + UINT32 AdrTimer2Val : 8; ///< Determines the Timeout value used
> for the ADR timer 2. A value of zero bypasses the timer
>
> + UINT32 AdrMultiplier2Val : 8; ///< Specifies the tick frequency upon
> which the timer 2 will increment. ADR_TIMER_SCALE should be used to
> encode values
>
> + UINT32 AdrHostPartitionReset : 2; ///< Determine if Host Partition
> Reset is enabled - 0: PLATFORM_POR, 1: FORCE_ENABLE, 2: FORCE_DISABLE
>
> + UINT32 AdrSrcOverride : 1; ///< Check if default ADR sources will be
> overriten with custom 0: Not overwritten, 1: Overwritten
>
> + UINT32 ReservedBits : 31;
>
> + ADR_SOURCE_ENABLE AdrSrcSel; ///< Determine which ADR
> sources are enabled - 0: Enabled, 1: Disabled
>
> +} ADR_CONFIG;
>
> +
>
> +#pragma pack (pop)
>
> +
>
> +#endif // _ADR_CONFIG_H_
>
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Pmc/PmConfig.h
> b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Pmc/PmConfig.h
> new file mode 100644
> index 0000000000..2f8e19b50b
> --- /dev/null
> +++
> b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Pmc/PmConfig.h
> @@ -0,0 +1,391 @@
> +/** @file
>
> + Power Management policy
>
> +
>
> + Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +**/
>
> +#ifndef _PM_CONFIG_H_
>
> +#define _PM_CONFIG_H_
>
> +
>
> +#include <ConfigBlock.h>
>
> +
>
> +#define PM_CONFIG_REVISION 2
>
> +extern EFI_GUID gPmConfigGuid;
>
> +
>
> +#pragma pack (push,1)
>
> +
>
> +/**
>
> + This structure allows to customize PCH wake up capability from S5 or
> DeepSx by WOL, LAN, PCIE wake events.
>
> +**/
>
> +typedef struct {
>
> + /**
>
> + Corresponds to the PME_B0_S5_DIS bit in the General PM Configuration
> B (GEN_PMCON_B) register.
>
> + When set to 1, this bit blocks wake events from PME_B0_STS in S5,
> regardless of the state of PME_B0_EN.
>
> + When cleared (default), wake events from PME_B0_STS are allowed in S5
> if PME_B0_EN = 1. <b>0: Disable</b>; 1: Enable.
>
> + **/
>
> + UINT32 PmeB0S5Dis : 1;
>
> + UINT32 WolEnableOverride : 1; ///< Corresponds to the "WOL Enable
> Override" bit in the General PM Configuration B (GEN_PMCON_B) register.
> 0: Disable; <b>1: Enable</b>.
>
> + UINT32 PcieWakeFromDeepSx : 1; ///< Determine if enable PCIe to
> wake from deep Sx. <b>0: Disable</b>; 1: Enable.
>
> + UINT32 WoWlanEnable : 1; ///< Determine if WLAN wake from Sx,
> corresponds to the "HOST_WLAN_PP_EN" bit in the PWRM_CFG3 register.
> <b>0: Disable</b>; 1: Enable.
>
> + UINT32 WoWlanDeepSxEnable : 1; ///< Determine if WLAN wake from
> DeepSx, corresponds to the "DSX_WLAN_PP_EN" bit in the PWRM_CFG3
> register. <b>0: Disable</b>; 1: Enable.
>
> + UINT32 LanWakeFromDeepSx : 1; ///< Determine if enable LAN to
> wake from deep Sx. 0: Disable; <b>1: Enable</b>.
>
> + UINT32 RsvdBits0 : 26;
>
> +} PCH_WAKE_CONFIG;
>
> +
>
> +typedef enum {
>
> + PchDeepSxPolDisable,
>
> + PchDpS5BatteryEn,
>
> + PchDpS5AlwaysEn,
>
> + PchDpS4S5BatteryEn,
>
> + PchDpS4S5AlwaysEn,
>
> + PchDpS3S4S5BatteryEn,
>
> + PchDpS3S4S5AlwaysEn
>
> +} PCH_DEEP_SX_CONFIG;
>
> +
>
> +typedef enum {
>
> + PchSlpS360us = 1,
>
> + PchSlpS31ms,
>
> + PchSlpS350ms,
>
> + PchSlpS32s
>
> +} PCH_SLP_S3_MIN_ASSERT;
>
> +
>
> +typedef enum {
>
> + PchSlpS4PchTime, ///< The time defined in PCH EDS Power Sequencing
> and Reset Signal Timings table
>
> + PchSlpS41s,
>
> + PchSlpS42s,
>
> + PchSlpS43s,
>
> + PchSlpS44s
>
> +} PCH_SLP_S4_MIN_ASSERT;
>
> +
>
> +typedef enum {
>
> + PchSlpSus0ms = 1,
>
> + PchSlpSus500ms,
>
> + PchSlpSus1s,
>
> + PchSlpSus4s,
>
> +} PCH_SLP_SUS_MIN_ASSERT;
>
> +
>
> +typedef enum {
>
> + PchSlpA0ms = 1,
>
> + PchSlpA4s,
>
> + PchSlpA98ms,
>
> + PchSlpA2s,
>
> +} PCH_SLP_A_MIN_ASSERT;
>
> +
>
> +typedef enum {
>
> + S0ixDisQNoChange,
>
> + S0ixDisQDciOob,
>
> + S0ixDisQUsb2Dbc,
>
> + S0ixDisQMax,
>
> +} S0IX_DISQ_PROBE_TYPE;
>
> +
>
> +/**
>
> + Low Power Mode Enable config.
>
> + Used to configure if respective S0i2/3 sub-states are to be supported
>
> + by the platform. Each bit corresponds to one LPM state - LPMx->BITx.
>
> + Some sub-states will require external FETs controlled by
> EXT_PWR_GATE#/EXT_PWR_GATE2# pins
>
> + to gate v1p05-PHY or v1p05-IS supplies
>
> +**/
>
> +typedef union {
>
> + struct {
>
> + UINT32 S0i2p0En : 1; ///< LPM0 - S0i2.0 Enable
>
> + UINT32 S0i2p1En : 1; ///< LPM1 - S0i2.1 Enable
>
> + /**
>
> + LPM2 - S0i2.2 Enable.
>
> + Requires EXT_PWR_GATE# controlled FET to gate v1p05 PHY.
>
> + Refer to V1p05PhyExtFetControlEn.
>
> + **/
>
> + UINT32 S0i2p2En : 1;
>
> + UINT32 S0i3p0En : 1; ///< LPM3 - S0i3.0 Enable
>
> + UINT32 S0i3p1En : 1; ///< LPM4 - S0i3.1 Enable
>
> + UINT32 S0i3p2En : 1; ///< LPM5 - S0i3.2 Enable
>
> + /**
>
> + LPM5 - S0i3.3 Enable.
>
> + Requires EXT_PWR_GATE# controlled FET to gate v1p05 PHY.
>
> + Refer to V1p05PhyExtFetControlEn.
>
> + **/
>
> + UINT32 S0i3p3En : 1;
>
> + /**
>
> + LPM7 - S0i3.4 Enable.
>
> + Requires EXT_PWR_GATE2# controlled FET to gate v1p05-SRAM/ISCLK.
>
> + Refer to V1p05IsExtFetControlEn.
>
> + **/
>
> + UINT32 S0i3p4En : 1;
>
> + UINT32 Reserved : 24; ///< Reserved
>
> + } Field;
>
> + UINT32 Val;
>
> +} PMC_LPM_S0IX_SUB_STATE_EN;
>
> +
>
> +/**
>
> + Description of Global Reset Trigger/Event Mask register
>
> +**/
>
> +typedef union {
>
> + struct {
>
> + UINT32 Reserved1 : 1;
>
> + UINT32 Pbo : 1;
>
> + UINT32 PmcUncErr : 1;
>
> + UINT32 PchThrm : 1;
>
> + UINT32 MePbo : 1;
>
> + UINT32 CpuThrm : 1;
>
> + UINT32 Megbl : 1;
>
> + UINT32 LtReset : 1;
>
> + UINT32 PmcWdt : 1;
>
> + UINT32 MeWdt : 1;
>
> + UINT32 PmcFw : 1;
>
> + UINT32 PchpwrFlr : 1;
>
> + UINT32 SyspwrFlr : 1;
>
> + UINT32 Reserved2 : 1;
>
> + UINT32 MiaUxsErr : 1;
>
> + UINT32 MiaUxErr : 1;
>
> + UINT32 CpuThrmWdt : 1;
>
> + UINT32 MeUncErr : 1;
>
> + UINT32 AdrGpio : 1;
>
> + UINT32 OcwdtNoicc : 1;
>
> + UINT32 OcwdtIcc : 1;
>
> + UINT32 CseHecUncErr : 1;
>
> + UINT32 PmcSramUncErr : 1;
>
> + UINT32 PmcIromParity : 1;
>
> + UINT32 PmcRfFusaErr : 1;
>
> + UINT32 Reserved3 : 4;
>
> + UINT32 PpbrParityErr : 1;
>
> + UINT32 Reserved4 : 2;
>
> + } Field;
>
> + UINT32 Value;
>
> +} PMC_GLOBAL_RESET_MASK;
>
> +
>
> +/**
>
> + The PCH_PM_CONFIG block describes expected miscellaneous power
> management settings.
>
> + The PowerResetStatusClear field would clear the Power/Reset status bits,
> please
>
> + set the bits if you want PCH Init driver to clear it, if you want to check the
>
> + status later then clear the bits.
>
> +
>
> + <b>Revision 1</b>:
>
> + - Initial version.
>
> + <b>Revision 2</b>
>
> + - Added C10DynamicThresholdAdjustment
>
> +**/
>
> +typedef struct {
>
> + CONFIG_BLOCK_HEADER Header; ///< Config Block Header
>
> +
>
> + PCH_WAKE_CONFIG WakeConfig; ///< Specify Wake Policy
>
> + UINT32 PchDeepSxPol : 4; ///< Deep Sx Policy. Refer to
> PCH_DEEP_SX_CONFIG for each value. Default is
> <b>PchDeepSxPolDisable</b>.
>
> + UINT32 PchSlpS3MinAssert : 4; ///< SLP_S3 Minimum
> Assertion Width Policy. Refer to PCH_SLP_S3_MIN_ASSERT for each value.
> Default is <b>PchSlpS350ms</b>.
>
> + UINT32 PchSlpS4MinAssert : 4; ///< SLP_S4 Minimum
> Assertion Width Policy. Refer to PCH_SLP_S4_MIN_ASSERT for each value.
> Default is <b>PchSlpS44s</b>.
>
> + UINT32 PchSlpSusMinAssert : 4; ///< SLP_SUS Minimum
> Assertion Width Policy. Refer to PCH_SLP_SUS_MIN_ASSERT for each value.
> Default is <b>PchSlpSus4s</b>.
>
> + UINT32 PchSlpAMinAssert : 4; ///< SLP_A Minimum
> Assertion Width Policy. Refer to PCH_SLP_A_MIN_ASSERT for each value.
> Default is <b>PchSlpA2s</b>.
>
> + UINT32 RsvdBits0 : 12;
>
> + /**
>
> + This member describes whether or not the LPC ClockRun feature of PCH
> should
>
> + be enabled. <b>0: Disable</b>; 1: Enable
>
> + **/
>
> + UINT32 SlpStrchSusUp : 1; ///< <b>0: Disable</b>; 1:
> Enable SLP_X Stretching After SUS Well Power Up
>
> + /**
>
> + Enable/Disable SLP_LAN# Low on DC Power. 0: Disable; <b>1:
> Enable</b>.
>
> + Configure On DC PHY Power Diable according to policy SlpLanLowDc.
>
> + When this is enabled, SLP_LAN# will be driven low when ACPRESENT is
> low.
>
> + This indicates that LAN PHY should be powered off on battery mode.
>
> + This will override the DC_PP_DIS setting by WolEnableOverride.
>
> + **/
>
> + UINT32 SlpLanLowDc : 1;
>
> + /**
>
> + PCH power button override period.
>
> + 000b-4s, 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s
>
> + <b>Default is 0: 4s</b>
>
> + **/
>
> + UINT32 PwrBtnOverridePeriod : 3;
>
> + /**
>
> + <b>(Test)</b>
>
> + Disable/Enable PCH to CPU enery report feature. <b>0: Disable</b>; 1:
> Enable.
>
> + Enery Report is must have feature. Wihtout Energy Report, the
> performance report
>
> + by workloads/benchmarks will be unrealistic because PCH's energy is not
> being accounted
>
> + in power/performance management algorithm.
>
> + If for some reason PCH energy report is too high, which forces CPU to try
> to reduce
>
> + its power by throttling, then it could try to disable Energy Report to do
> first debug.
>
> + This might be due to energy scaling factors are not correct or the LPM
> settings are not
>
> + kicking in.
>
> + **/
>
> + UINT32 DisableEnergyReport : 1;
>
> + /**
>
> + When set to Disable, PCH will internal pull down AC_PRESENT in deep SX
> and during G3 exit.
>
> + When set to Enable, PCH will not pull down AC_PRESENT.
>
> + This setting is ignored when DeepSx is not supported.
>
> + Default is <b>0:Disable</b>
>
> + **/
>
> + UINT32 DisableDsxAcPresentPulldown : 1;
>
> + /**
>
> + Power button native mode disable.
>
> + While FALSE, the PMC's power button logic will act upon the input value
> from the GPIO unit, as normal.
>
> + While TRUE, this will result in the PMC logic constantly seeing the power
> button as de-asserted.
>
> + <b>Default is FALSE.</b>
>
> + **/
>
> + UINT32 DisableNativePowerButton : 1;
>
> + UINT32 MeWakeSts : 1; ///< Clear the ME_WAKE_STS
> bit in the Power and Reset Status (PRSTS) register. 0: Disable; <b>1:
> Enable</b>.
>
> + UINT32 WolOvrWkSts : 1; ///< Clear the
> WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register. 0:
> Disable; <b>1: Enable</b>.
>
> + /*
>
> + Set true to enable TCO timer.
>
> + When FALSE, it disables PCH ACPI timer, and stops TCO timer.
>
> + @note: This will have significant power impact when it's enabled.
>
> + If TCO timer is disabled, uCode ACPI timer emulation must be enabled,
>
> + and WDAT table must not be exposed to the OS.
>
> + <b>0: Disable</b>, 1: Enable
>
> + */
>
> + UINT32 EnableTcoTimer : 1;
>
> + /*
>
> + When VRAlert# feature pin is enabled and its state is '0',
>
> + the PMC requests throttling to a T3 Tstate to the PCH throttling unit.
>
> + <b>0: Disable</b>; 1: Enable.
>
> + */
>
> + UINT32 VrAlert : 1;
>
> + /**
>
> + Decide if PS_ON is to be enabled. This is available on desktop only.
>
> + PS_ON is a new C10 state from the CPU on desktop SKUs that enables a
>
> + lower power target that will be required by the California Energy
>
> + Commission (CEC). When FALSE, PS_ON is to be disabled.}
>
> + <b>0: Disable</b>; 1: Enable.
>
> + **/
>
> + UINT32 PsOnEnable : 1;
>
> + /**
>
> + Enable/Disable platform support for CPU_C10_GATE# pin to control
> gating
>
> + of CPU VccIO and VccSTG rails instead of SLP_S0# pin. This policy needs
>
> + to be set if board design includes support for CPU_C10_GATE# pin.
>
> + 0: Disable; <b>1: Enable</b>
>
> + **/
>
> + UINT32 CpuC10GatePinEnable : 1;
>
> + /**
>
> + Control whether to enable PMC debug messages to Trace Hub.
>
> + When Enabled, PMC HW will send debug messages to trace hub;
>
> + When Disabled, PMC HW will never send debug meesages to trace hub.
>
> + @note: When enabled, system may not enter S0ix
>
> + <b>0: Disable</b>; 1: Enable.
>
> + **/
>
> + UINT32 PmcDbgMsgEn : 1;
>
> + /**
>
> + Enable/Disable ModPHY SUS Power Domain Dynamic Gating.
>
> + EXT_PWR_GATE# signal (if supported on platform) can be used to
>
> + control external FET for power gating ModPHY
>
> + @note: This setting is not supported and ignored on PCH-H
>
> + 0: Disable; <b>1: Enable</b>.
>
> + **/
>
> + UINT32 ModPhySusPgEnable : 1;
>
> + /**
>
> + <b>(Test)</b>
>
> + This policy option enables USB2 PHY SUS Well Power Gating functionality.
>
> + @note: This setting is not supported and ignored on PCH-H
>
> + 0: disable USB2 PHY SUS Well Power Gating
>
> + <b>1: enable USB2 PHY SUS Well Power Gating</b>
>
> + **/
>
> + UINT32 Usb2PhySusPgEnable : 1;
>
> + /**
>
> + Enable Os Idle Mode.
>
> + 0: Disable; <b>1: Enable</b>.
>
> + **/
>
> + UINT32 OsIdleEnable : 1;
>
> + /**
>
> + Enable control using EXT_PWR_GATE# pin of external FET
>
> + to power gate v1p05-PHY
>
> + <b>0: Disable</b>; 1: Enable.
>
> + **/
>
> + UINT32 V1p05PhyExtFetControlEn : 1;
>
> + /**
>
> + Enable control using EXT_PWR_GATE2# pin of external FET
>
> + to power gate v1p05-IS supply
>
> + <b>0: Disable</b>; 1: Enable.
>
> + **/
>
> + UINT32 V1p05IsExtFetControlEn : 1;
>
> + /**
>
> + Enable/Disable the Low Power Mode Host S0ix Auto-Demotion
>
> + feature. This feature enables the PMC to autonomously manage
>
> + the deepest allowed S0ix substate to combat thrashing between
>
> + power management states.
>
> + 0: Disable; <b>1: Enable</b>.
>
> + **/
>
> + UINT32 S0ixAutoDemotion : 1;
>
> + /**
>
> + Enable/Disable Latch Events C10 Exit. When this bit is set to 1,
>
> + SLP_S0# entry events in SLP_S0_DEBUG_REGx registers are captured
>
> + on C10 exit (instead of C10 entry which is default)
>
> + <b>0: Disable</b>; 1: Enable.
>
> + **/
>
> + UINT32 LatchEventsC10Exit : 1;
>
> + UINT32 RsvdBits1 : 10;
>
> + /*
>
> + Power button debounce configuration
>
> + Debounce time can be specified in microseconds. Only certain values
> according
>
> + to below formula are supported:
>
> + DebounceTime = (2 ^ PADCFG_DW2.DEBOUNCE)*(glitch filter clock
> period).
>
> + RTC clock with f = 32 KHz is used for glitch filter.
>
> + DebounceTime = (2 ^ PADCFG_DW2.DEBOUNCE)*(31.25 us).
>
> + Supported DebounceTime values are following:
>
> + DebounceTime = 0 -> Debounce feature disabled
>
> + DebounceTime > 0 && < 250us -> Not supported
>
> + DebounceTime = 250us - 1024000us -> Supported range (DebounceTime
> = 250us * 2^n)
>
> + For values not supported by HW, they will be rounded down to closest
> supported one
>
> + <b>Default is 0</b>
>
> + */
>
> + UINT32 PowerButtonDebounce;
>
> + /**
>
> + Reset Power Cycle Duration could be customized in the unit of second.
> Please refer to EDS
>
> + for all support settings. PCH HW default is 4 seconds, and range is 1~4
> seconds, where
>
> + <b>0 is default</b>, 1 is 1 second, 2 is 2 seconds, ... 4 is 4 seconds.
>
> + And make sure the setting correct, which never less than the following
> register.
>
> + - GEN_PMCON_B.SLP_S3_MIN_ASST_WDTH
>
> + - GEN_PMCON_B.SLP_S4_MIN_ASST_WDTH
>
> + - PWRM_CFG.SLP_A_MIN_ASST_WDTH
>
> + - PWRM_CFG.SLP_LAN_MIN_ASST_WDTH
>
> + **/
>
> + UINT8 PchPwrCycDur;
>
> + /**
>
> + Specifies the Pcie Pll Spread Spectrum Percentage
>
> + The value of this policy is in 1/10th percent units.
>
> + Valid spread range is 0-20. A value of 0xFF is reserved for AUTO.
>
> + A value of 0 is SSC of 0.0%. A value of 20 is SSC of 2.0%
>
> + The default is <b>0xFF: AUTO - No BIOS override</b>.
>
> + **/
>
> + UINT8 PciePllSsc;
>
> + /**
>
> + Tells BIOS to enable C10 dynamic threshold adjustment mode.
>
> + BIOS will only attemt to enable it on PCH SKUs which support it.
>
> + **/
>
> + UINT8 C10DynamicThresholdAdjustment;
>
> + UINT8 Rsvd0[1]; ///< Reserved bytes
>
> + /**
>
> + <b>(Test)</b>
>
> + Low Power Mode Enable/Disable config.
>
> + Configure if respective S0i2/3 sub-states are to be supported
>
> + by the platform. By default all sub-states are enabled but
>
> + for test purpose respective states can be disabled.
>
> + <b>Default is 0xFF</b>
>
> + **/
>
> + PMC_LPM_S0IX_SUB_STATE_EN LpmS0ixSubStateEnable;
>
> + /*
>
> + Set true to enable Timed GPIO 0 timer.
>
> + <b>0: Disable</b>, 1: Enable
>
> + */
>
> + UINT32 EnableTimedGpio0 : 1;
>
> + /*
>
> + Set true to enable Timed GPIO 1 timer.
>
> + <b>0: Disable</b>, 1: Enable
>
> + */
>
> + UINT32 EnableTimedGpio1 : 1;
>
> + UINT32 Rsvdbits : 30;
>
> +
>
> + /**
>
> + Set true to enable override of Global Reset Event/Trigger masks.
>
> + Values from GlobalResetTriggerMask and GlobalResetEventMask will
>
> + be used as override value.
>
> + <b>0: Disable</b>, 1: Enable
>
> + **/
>
> + UINT8 GlobalResetMasksOverride;
>
> + UINT8 Rsvd1[3]; ///< Reserved bytes
>
> + /*
>
> + Mask for enabling Global Reset Trigger prevention
>
> + */
>
> + PMC_GLOBAL_RESET_MASK GlobalResetTriggerMask;
>
> + /*
>
> + Mask for enabling Global Reset Event prevention
>
> + */
>
> + PMC_GLOBAL_RESET_MASK GlobalResetEventMask;
>
> +} PCH_PM_CONFIG;
>
> +
>
> +#pragma pack (pop)
>
> +
>
> +#endif // _PM_CONFIG_H_
>
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Psf/PsfConfig.h
> b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Psf/PsfConfig.h
> new file mode 100644
> index 0000000000..033e416b83
> --- /dev/null
> +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Psf/PsfConfig.h
> @@ -0,0 +1,32 @@
> +/** @file
>
> + Primary Sideband Fabric policy.
>
> +
>
> + Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +**/
>
> +
>
> +#ifndef _PSF_CONFIG_H_
>
> +#define _PSF_CONFIG_H_
>
> +
>
> +#define PSF_CONFIG_REVISION 1
>
> +extern EFI_GUID gPsfConfigGuid;
>
> +
>
> +#pragma pack (push,1)
>
> +
>
> +/**
>
> + The PSF_CONFIG block describes the expected configuration of the
> Primary
>
> + Sideband Fabric.
>
> +**/
>
> +typedef struct {
>
> + CONFIG_BLOCK_HEADER Header; ///< Config Block Header
>
> + /**
>
> + Psf Tcc (Time Coordinated Computing) Enable will decrease psf
> transaction latency by disable
>
> + some psf power management features. <b>0: Disable</b>; 1: Enable.
>
> + **/
>
> + UINT32 TccEnable : 1;
>
> + UINT32 RsvdBits0 : 31; ///< Reserved bits
>
> +} PSF_CONFIG;
>
> +
>
> +#pragma pack (pop)
>
> +
>
> +#endif // _PSF_CONFIG_H_
>
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Rst/RstConfig.h
> b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Rst/RstConfig.h
> new file mode 100644
> index 0000000000..469d46a205
> --- /dev/null
> +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Rst/RstConfig.h
> @@ -0,0 +1,82 @@
> +/** @file
>
> + Rst policy
>
> +
>
> + Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +**/
>
> +#ifndef _RST_CONFIG_H_
>
> +#define _RST_CONFIG_H_
>
> +#include <PchLimits.h>
>
> +#include <ConfigBlock.h>
>
> +
>
> +#define RST_CONFIG_REVISION 1
>
> +extern EFI_GUID gRstConfigGuid;
>
> +
>
> +#pragma pack (push,1)
>
> +
>
> +typedef enum {
>
> + SataOromDelay2sec,
>
> + SataOromDelay4sec,
>
> + SataOromDelay6sec,
>
> + SataOromDelay8sec
>
> +} SATA_OROM_DELAY;
>
> +
>
> +/**
>
> + This structure describes the details of Intel RST for PCIe Storage remapping
>
> + Note: In order to use this feature, Intel RST Driver is required
>
> +**/
>
> +typedef struct {
>
> + /**
>
> + This member describes whether or not the Intel RST for PCIe Storage
> remapping should be enabled. <b>0: Disable</b>; 1: Enable.
>
> + Note 1: If Sata Controller is disabled, PCIe Storage Remapping should be
> disabled as well
>
> + Note 2: If PCIe Storage remapping is enabled, the PCH integrated AHCI
> controllers Class Code is configured as RAID
>
> + **/
>
> + UINT32 Enable : 1;
>
> + /**
>
> + Intel RST for PCIe Storage remapping - PCIe Port Selection (1-based, <b>0
> = autodetect</b>)
>
> + The supported ports for PCIe Storage remapping is different depend on
> the platform and cycle router
>
> + **/
>
> + UINT32 RstPcieStoragePort : 5;
>
> + /**
>
> + PCIe Storage Device Reset Delay in milliseconds (ms), which it guarantees
> such delay gap is fulfilled
>
> + before PCIe Storage Device configuration space is accessed after an reset
> caused by the link disable and enable step.
>
> + Default value is <b>100ms</b>.
>
> + **/
>
> + UINT32 DeviceResetDelay : 8;
>
> + UINT32 RsvdBits0 : 18; ///< Reserved bits
>
> +
>
> +} RST_HARDWARE_REMAPPED_STORAGE_CONFIG;
>
> +
>
> +/**
>
> + Rapid Storage Technology settings.
>
> +
>
> + <b>Revision 1</b>:
>
> + - Initial version.
>
> +**/
>
> +typedef struct {
>
> + CONFIG_BLOCK_HEADER Header; ///< Config Block Header
>
> +
>
> + UINT32 Raid0 : 1; ///< 0 : Disable; <b>1 : Enable</b> RAID0
>
> + UINT32 Raid1 : 1; ///< 0 : Disable; <b>1 : Enable</b> RAID1
>
> + UINT32 Raid10 : 1; ///< 0 : Disable; <b>1 : Enable</b> RAID10
>
> + UINT32 Raid5 : 1; ///< 0 : Disable; <b>1 : Enable</b> RAID5
>
> + UINT32 Irrt : 1; ///< 0 : Disable; <b>1 : Enable</b> Intel Rapid
> Recovery Technology
>
> + UINT32 OromUiBanner : 1; ///< 0 : Disable; <b>1 : Enable</b>
> OROM UI and BANNER
>
> + UINT32 OromUiDelay : 2; ///< <b>00b : 2 secs</b>; 01b : 4 secs;
> 10b : 6 secs; 11 : 8 secs (see : SATA_OROM_DELAY)
>
> + UINT32 HddUnlock : 1; ///< 0 : Disable; <b>1 : Enable</b>.
> Indicates that the HDD password unlock in the OS is enabled
>
> + UINT32 LedLocate : 1; ///< 0 : Disable; <b>1 : Enable</b>.
> Indicates that the LED/SGPIO hardware is attached and ping to locate feature
> is enabled on the OS
>
> + UINT32 IrrtOnly : 1; ///< 0 : Disable; <b>1 : Enable</b>. Allow
> only IRRT drives to span internal and external ports
>
> + UINT32 SmartStorage : 1; ///< 0 : Disable; <b>1 : Enable</b> RST
> Smart Storage caching Bit
>
> + UINT32 LegacyOrom : 1; ///< <b>0 : Disable</b>; 1 : Enable RST
> Legacy OROM
>
> + UINT32 OptaneMemory : 1; ///< 0: Disable; <b>1: Enable</b> RST
> Optane(TM) Memory
>
> + UINT32 CpuAttachedStorage : 1; ///< 0: Disable; <b>1: Enable</b>
> CPU Attached Storage
>
> + UINT32 RsvdBits0 : 17; ///< Reserved Bits
>
> + /**
>
> + This member describes the details of implementation of Intel RST for PCIe
> Storage remapping (Intel RST Driver is required)
>
> + Note: RST for PCIe Sorage remapping is supported only for first SATA
> controller if more controllers are available
>
> + **/
>
> + RST_HARDWARE_REMAPPED_STORAGE_CONFIG
> HardwareRemappedStorageConfig[PCH_MAX_RST_PCIE_STORAGE_CR];
>
> +} RST_CONFIG;
>
> +
>
> +#pragma pack (pop)
>
> +#endif
>
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Rtc/RtcConfig.h
> b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Rtc/RtcConfig.h
> new file mode 100644
> index 0000000000..1f354c10ae
> --- /dev/null
> +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Rtc/RtcConfig.h
> @@ -0,0 +1,38 @@
> +/** @file
>
> + RTC policy
>
> +
>
> + Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +**/
>
> +#ifndef _RTC_CONFIG_H_
>
> +#define _RTC_CONFIG_H_
>
> +
>
> +#define RTC_CONFIG_REVISION 1
>
> +extern EFI_GUID gRtcConfigGuid;
>
> +
>
> +#pragma pack (push,1)
>
> +
>
> +/**
>
> + The RTC_CONFIG block describes the expected configuration of RTC
> configuration.
>
> +**/
>
> +typedef struct {
>
> + CONFIG_BLOCK_HEADER Header; ///< Config Block Header
>
> + /**
>
> + When set, prevents RTC TS (BUC.TS) from being changed.
>
> + This BILD bit has different function compared to LPC/eSPI, SPI.
>
> + 0: Disabled; <b>1: Enabled</b>
>
> + **/
>
> + UINT32 BiosInterfaceLock : 1;
>
> + /**
>
> + When set, bytes 38h-3Fh in the upper 128bytes bank of RTC RAM are
> locked
>
> + and cannot be accessed.
>
> + Writes will be droipped and reads will not return any guaranteed data.
>
> + 0: Disabled; <b>1: Enabled</b>
>
> + **/
>
> + UINT32 MemoryLock : 1;
>
> + UINT32 RsvdBits0 : 30;
>
> +} RTC_CONFIG;
>
> +
>
> +#pragma pack (pop)
>
> +
>
> +#endif // _RTC_CONFIG_H_
>
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Sata/SataConfig.h
> b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Sata/SataConfig.h
> new file mode 100644
> index 0000000000..c560fdd3ab
> --- /dev/null
> +++
> b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Sata/SataConfig.h
> @@ -0,0 +1,168 @@
> +/** @file
>
> + Sata policy
>
> +
>
> + Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +**/
>
> +#ifndef _SATA_CONFIG_H_
>
> +#define _SATA_CONFIG_H_
>
> +
>
> +#include <PchLimits.h>
>
> +
>
> +#define SATA_CONFIG_REVISION 1
>
> +extern EFI_GUID gSataConfigGuid;
>
> +
>
> +#pragma pack (push,1)
>
> +
>
> +typedef enum {
>
> + SataModeAhci,
>
> + SataModeRaid,
>
> + SataModeMax
>
> +} SATA_MODE;
>
> +
>
> +typedef enum {
>
> + SataSpeedDefault,
>
> + SataSpeedGen1,
>
> + SataSpeedGen2,
>
> + SataSpeedGen3
>
> +} SATA_SPEED;
>
> +
>
> +typedef enum {
>
> + SataRstMsix,
>
> + SataRstMsi,
>
> + SataRstLegacy
>
> +} SATA_RST_INTERRUPT;
>
> +
>
> +typedef enum {
>
> + SataRaidClient,
>
> + SataRaidAlternate,
>
> + SataRaidServer
>
> +} SATA_RAID_DEV_ID;
>
> +
>
> +/**
>
> + This structure configures the features, property, and capability for each
> SATA port.
>
> +**/
>
> +typedef struct {
>
> + /**
>
> + Enable SATA port.
>
> + It is highly recommended to disable unused ports for power savings
>
> + **/
>
> + UINT32 Enable : 1; ///< 0: Disable; <b>1: Enable</b>
>
> + UINT32 HotPlug : 1; ///< <b>0: Disable</b>; 1: Enable
>
> + UINT32 InterlockSw : 1; ///< <b>0: Disable</b>; 1: Enable
>
> + UINT32 External : 1; ///< <b>0: Disable</b>; 1: Enable
>
> + UINT32 SpinUp : 1; ///< <b>0: Disable</b>; 1: Enable the
> COMRESET initialization Sequence to the device
>
> + UINT32 SolidStateDrive : 1; ///< <b>0: HDD</b>; 1: SSD
>
> + UINT32 DevSlp : 1; ///< <b>0: Disable</b>; 1: Enable DEVSLP
> on the port
>
> + UINT32 EnableDitoConfig : 1; ///< <b>0: Disable</b>; 1: Enable
> DEVSLP Idle Timeout settings (DmVal, DitoVal)
>
> + UINT32 DmVal : 4; ///< DITO multiplier. Default is
> <b>15</b>.
>
> + UINT32 DitoVal : 10; ///< DEVSLP Idle Timeout (DITO), Default
> is <b>625</b>.
>
> + /**
>
> + Support zero power ODD <b>0: Disable</b>, 1: Enable.
>
> + This is also used to disable ModPHY dynamic power gate.
>
> + **/
>
> + UINT32 ZpOdd : 1;
>
> + UINT32 DevSlpResetConfig : 4; ///< 0: Hardware default; <b>0x01:
> GpioResumeReset</b>; 0x03: GpioHostDeepReset; 0x05:
> GpioPlatformReset; 0x07: GpioDswReset
>
> + UINT32 SataPmPtm : 1; ///< Deprecated
>
> + UINT32 RxPolarity : 1; ///< <b>0: Disable</b>; 1: Enable; Rx
> Polarity
>
> + UINT32 RsvdBits0 : 3; ///< Reserved fields for future
> expansion w/o protocol change
>
> +} PCH_SATA_PORT_CONFIG;
>
> +
>
> +/**
>
> + This structure lists PCH supported SATA thermal throttling register setting
> for customization.
>
> + The settings is programmed through SATA Index/Data registers.
>
> + When the SuggestedSetting is enabled, the customized values are ignored.
>
> +**/
>
> +typedef struct {
>
> + UINT32 P0T1M : 2; ///< Port 0 T1 Multipler
>
> + UINT32 P0T2M : 2; ///< Port 0 T2 Multipler
>
> + UINT32 P0T3M : 2; ///< Port 0 T3 Multipler
>
> + UINT32 P0TDisp : 2; ///< Port 0 Tdispatch
>
> +
>
> + UINT32 P1T1M : 2; ///< Port 1 T1 Multipler
>
> + UINT32 P1T2M : 2; ///< Port 1 T2 Multipler
>
> + UINT32 P1T3M : 2; ///< Port 1 T3 Multipler
>
> + UINT32 P1TDisp : 2; ///< Port 1 Tdispatch
>
> +
>
> + UINT32 P0Tinact : 2; ///< Port 0 Tinactive
>
> + UINT32 P0TDispFinit : 1; ///< Port 0 Alternate Fast Init Tdispatch
>
> + UINT32 P1Tinact : 2; ///< Port 1 Tinactive
>
> + UINT32 P1TDispFinit : 1; ///< Port 1 Alternate Fast Init Tdispatch
>
> + UINT32 SuggestedSetting : 1; ///< 0: Disable; <b>1: Enable</b>
> suggested representative values
>
> + UINT32 RsvdBits0 : 9; ///< Reserved bits
>
> +} SATA_THERMAL_THROTTLING;
>
> +
>
> +/**
>
> + The SATA_CONFIG block describes the expected configuration of the
> SATA controllers.
>
> +
>
> + <b>Revision 1</b>:
>
> + - Initial version.
>
> +**/
>
> +typedef struct {
>
> + CONFIG_BLOCK_HEADER Header; ///< Config Block Header
>
> + ///
>
> + /// This member describes whether or not the SATA controllers should be
> enabled. 0: Disable; <b>1: Enable</b>.
>
> + ///
>
> + UINT8 Enable;
>
> + UINT8 TestMode; ///< <b>(Test)</b> <b>0: Disable</b>; 1:
> Allow entrance to the PCH SATA test modes
>
> + UINT8 SalpSupport; ///< 0: Disable; <b>1: Enable</b>
> Aggressive Link Power Management
>
> + UINT8 PwrOptEnable; ///< 0: Disable; <b>1: Enable</b> SATA
> Power Optimizer on PCH side.
>
> + /**
>
> + EsataSpeedLimit
>
> + When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA
> port speed.
>
> + Please be noted, this setting could be cleared by HBA reset, which might
> be issued
>
> + by EFI AHCI driver when POST time, or by SATA inbox driver/RST driver
> after POST.
>
> + To support the Speed Limitation when POST, the EFI AHCI driver should
> preserve the
>
> + setting before and after initialization. For support it after POST, it's
> dependent on
>
> + driver's behavior.
>
> + <b>0: Disable</b>; 1: Enable
>
> + **/
>
> + UINT8 EsataSpeedLimit;
>
> + UINT8 LedEnable; ///< SATA LED indicates SATA controller
> activity. 0: Disable; <b>1: Enable</b> SATA LED.
>
> + /**
>
> + This option allows to configure SATA controller device ID while in RAID
> mode.
>
> + Refer to SATA_RAID_DEV_ID enumeration for supported options.
>
> + Choosing Client will allow RST driver loading, RSTe driver will not be able to
> load
>
> + Choosing Alternate will not allow RST inbox driver loading in Windows
>
> + Choosing Server will allow RSTe driver loading, RST driver will not load
>
> + <b>0: Client</b>; 1: Alternate; 2: Server
>
> + **/
>
> + UINT8 RaidDeviceId;
>
> + /**
>
> + Controlls which interrupts will be linked to SATA controller CAP list
>
> + This option will take effect only if SATA controller is in RAID mode
>
> + Default: <b>PchSataMsix</b>
>
> + **/
>
> + UINT8 SataRstInterrupt;
>
> +
>
> + /**
>
> + Determines the system will be configured to which SATA mode.
>
> + Refer to SATA_MODE enumeration for supported options. Default is
> <b>SataModeAhci</b>.
>
> + **/
>
> + UINT8 SataMode;
>
> + /**
>
> + Indicates the maximum speed the SATA controller can support.
>
> + Refer to SATA_SPEED enumeration for supported options.
>
> + <b>0h: SataSpeedDefault</b>; 1h: 1.5 Gb/s (Gen 1); 2h: 3 Gb/s(Gen 2);
> 3h: 6 Gb/s (Gen 1)
>
> + **/
>
> + UINT8 SpeedLimit;
>
> + UINT8 EnclosureSupport; ///< Enclosure Management
> Support. 0: Disable; 1: Enable
>
> + /**
>
> + Controlls whenever Serial GPIO support is enabled for controller
>
> + <b>0: Disable</b>; 1: Enable
>
> + **/
>
> + UINT8 SgpioSupport;
>
> + /**
>
> + This member configures the features, property, and capability for each
> SATA port.
>
> + **/
>
> + PCH_SATA_PORT_CONFIG PortSettings[PCH_MAX_SATA_PORTS];
>
> + /**
>
> + This field decides the settings of Sata thermal throttling. When the
> Suggested Setting
>
> + is enabled, PCH RC will use the suggested representative values.
>
> + **/
>
> + SATA_THERMAL_THROTTLING ThermalThrottling;
>
> +} SATA_CONFIG;
>
> +
>
> +#pragma pack (pop)
>
> +
>
> +#endif // _SATA_CONFIG_H_
>
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Scs/ScsConfig.h
> b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Scs/ScsConfig.h
> new file mode 100644
> index 0000000000..2ebc901896
> --- /dev/null
> +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Scs/ScsConfig.h
> @@ -0,0 +1,139 @@
> +/** @file
>
> + Scs policy
>
> +
>
> + Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +**/
>
> +#ifndef _SCS_CONFIG_H_
>
> +#define _SCS_CONFIG_H_
>
> +
>
> +#include <ConfigBlock.h>
>
> +#include <PchLimits.h>
>
> +
>
> +#define SCS_SDCARD_CONFIG_REVISION 1
>
> +#define SCS_EMMC_CONFIG_REVISION 1
>
> +#define SCS_EMMC_DXE_CONFIG_REVISION 1
>
> +#define SCS_SDCARD_MAX_DATA_GPIOS 4
>
> +#define SCS_EMMC_MAX_DATA_GPIOS 8
>
> +extern EFI_GUID gSdCardConfigGuid;
>
> +extern EFI_GUID gEmmcConfigGuid;
>
> +extern EFI_GUID gUfsConfigGuid;
>
> +extern EFI_GUID gEmmcDxeConfigGuid;
>
> +
>
> +#pragma pack (push,1)
>
> +
>
> +/**
>
> + This structre holds the DLL configuration
>
> + register values that will be programmed by RC
>
> + if EnableCustomDlls field is set to TRUE. Those
>
> + policies should be used by platform if default values
>
> + provided by RC are not sufficient to provide stable operation
>
> + at all supported spped modes. RC will blindly set the DLL values
>
> + as provided in this structre.
>
> +
>
> + For help with obtaining valid DLL values for your platform please
>
> + contact enabling support.
>
> +**/
>
> +typedef struct {
>
> + UINT32 TxCmdDelayControl; // Offset 820h: Tx CMD Delay Control
>
> + UINT32 TxDataDelayControl1; // Offset 824h: Tx Data Delay Control 1
>
> + UINT32 TxDataDelayControl2; // Offset 828h: Tx Data Delay Control 2
>
> + UINT32 RxCmdDataDelayControl1; // Offset 82Ch: Rx CMD + Data Delay
> Control 1
>
> + UINT32 RxCmdDataDelayControl2; // Offset 834h: Rx CMD + Data Delay
> Control 2
>
> + UINT32 RxStrobeDelayControl; // Offset 830h: Rx Strobe Delay Control,
> valid only for eMMC
>
> +} SCS_SD_DLL;
>
> +
>
> +/**
>
> + SD GPIO settings
>
> +**/
>
> +typedef struct {
>
> + /**
>
> + GPIO signals pin muxing settings. If signal can be enable only on a single
> pin
>
> + then this parameter should be set to 0. Refer to
> GPIO_*_MUXING_SDCARD_*x_* in GpioPins*.h
>
> + for supported settings on a given platform
>
> + **/
>
> + UINT32 PinMux;
>
> + /**
>
> + GPIO Pads Internal Termination.
>
> + For more information please see Platform Design Guide.
>
> + Check GPIO_ELECTRICAL_CONFIG for reference
>
> + **/
>
> + UINT32 PadTermination;
>
> +} MUX_GPIO_PARAM;
>
> +
>
> +typedef struct {
>
> + MUX_GPIO_PARAM PowerEnable;
>
> + MUX_GPIO_PARAM Cmd;
>
> + MUX_GPIO_PARAM Data[SCS_SDCARD_MAX_DATA_GPIOS];
>
> + MUX_GPIO_PARAM Cdb;
>
> + MUX_GPIO_PARAM Clk;
>
> + MUX_GPIO_PARAM Wp;
>
> +} SCS_SDCARD_GPIO_CONFIG;
>
> +
>
> +typedef struct {
>
> + MUX_GPIO_PARAM Cmd;
>
> + MUX_GPIO_PARAM Data[SCS_EMMC_MAX_DATA_GPIOS];
>
> + MUX_GPIO_PARAM Rclk;
>
> + MUX_GPIO_PARAM Clk;
>
> + MUX_GPIO_PARAM Resetb;
>
> +} SCS_EMMC_GPIO_CONFIG;
>
> +
>
> +typedef struct {
>
> + CONFIG_BLOCK_HEADER Header;
>
> +
>
> + UINT32 Enable : 1; ///< Enable/Disable SdCard 0: Disabled, <b>1:
> Enabled</b>
>
> + UINT32 PowerEnableActiveHigh : 1; ///< Determine SD_PWREN#
> polarity 0: Active low, <b>1: Active high</b>
>
> + UINT32 UseCustomDlls : 1; ///< Use tuned DLL values from policy
> <b>0: Use default DLL</b>, 1: Use values from TunedDllValues field
>
> + UINT32 Reserved : 29;
>
> + SCS_SD_DLL CustomDllValues; ///< Structure containing custom DLL
> values for SD card
>
> + SCS_SDCARD_GPIO_CONFIG GpioConfig;
>
> +} SCS_SDCARD_CONFIG;
>
> +
>
> +typedef struct {
>
> + UINT32 Hs400RxValue : 7; ///< Value of the tuned HS400 Rx value
>
> + UINT32 Hs400TxValue : 7; ///< Value of the tuned HS400 Tx value
>
> + UINT32 Reserved : 18;
>
> +} SCS_EMMC_TUNED_DLL;
>
> +
>
> +typedef struct {
>
> + CONFIG_BLOCK_HEADER Header;
>
> +
>
> + UINT32 Enable : 1; ///< Enable/Disable eMMC 0: Disabled, <b>1:
> Enabled</b>
>
> + UINT32 Hs400Supported : 1; ///< Enable/Disable eMMC HS400 support
> 0: Disabled, <b>1: Enabled</b>
>
> + UINT32 UseCustomDlls : 1; ///< Use custom DLL values from policy
> <b>0: Use default DLL</b>, 1: Use values from TunedDllValues field
>
> + UINT32 Reserved : 29;
>
> + SCS_SD_DLL CustomDllValues; ///< Structure containing custom DLL
> values for eMMC ///< Structure containing tuned DLL settings for
> eMMC
>
> + SCS_EMMC_GPIO_CONFIG GpioConfig;
>
> +} SCS_EMMC_CONFIG;
>
> +
>
> +typedef enum {
>
> + DriverStrength33Ohm = 0,
>
> + DriverStrength40Ohm,
>
> + DriverStrength50Ohm
>
> +} SCS_EMMC_DRIVER_STRENGTH;
>
> +
>
> +typedef struct {
>
> + UINT32 TuningSuccessful : 1; ///< Informs software tuning module about
> previous software tuning status.
>
> + UINT32 Hs400RxValue : 7; ///< Value of the tuned HS400 Rx value
> returned from software tuning module
>
> + UINT32 Hs400TxValue : 7; ///< Value of the tuned HS400 Tx value
> returned from software tuning module
>
> + UINT32 Reserved : 17;
>
> +} SCS_EMMC_SOFTWARE_TUNING_RESULTS;
>
> +
>
> +typedef struct {
>
> + CONFIG_BLOCK_HEADER Header;
>
> +
>
> + UINT32 EnableSoftwareHs400Tuning : 1; ///< Enable/Disable
> software eMMC HS400 tuning: <b>0 - Disable</b>, 1 - Enable
>
> + UINT32 DriverStrength : 2; ///< I/O driver strength: 0 - 33
> Ohm, <b>1 - 40 Ohm</b>, 2 - 50 Ohm
>
> + UINT32 Reserved : 29;
>
> + EFI_LBA TuningLba; ///< Specifies LBA which will be
> used during software tuning process.
>
> + SCS_EMMC_SOFTWARE_TUNING_RESULTS PreviousTuningResults; ///<
> Informes software tuning module about previous software tuning results.}
> SCS_EMMC_DXE_CONFIG;
>
> +} SCS_EMMC_DXE_CONFIG;
>
> +
>
> +typedef struct {
>
> + UINT32 Enable : 1; ///< Enable/Disable UFS controller 0: Disabled, <b>1:
> Enabled</b>
>
> + UINT32 Reserved : 31;
>
> +} SCS_UFS_CONTROLLER_CONFIG;
>
> +
>
> +#pragma pack (pop)
>
> +
>
> +#endif // _SCS_CONFIG_H_
>
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/SerialIo/SerialIoConfi
> g.h
> b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/SerialIo/SerialIoConfi
> g.h
> new file mode 100644
> index 0000000000..d76937cf59
> --- /dev/null
> +++
> b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/SerialIo/SerialIoConfi
> g.h
> @@ -0,0 +1,32 @@
> +/** @file
>
> + Serial IO policy
>
> +
>
> + Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +**/
>
> +#ifndef _SERIAL_IO_CONFIG_H_
>
> +#define _SERIAL_IO_CONFIG_H_
>
> +
>
> +#define SERIAL_IO_CONFIG_REVISION 1
>
> +extern EFI_GUID gSerialIoConfigGuid;
>
> +
>
> +#include <SerialIoDevices.h>
>
> +
>
> +#pragma pack (push,1)
>
> +
>
> +/**
>
> + The SERIAL_IO_CONFIG block provides the configurations to set the Serial
> IO controllers
>
> +
>
> + <b>Revision 1:</b>
>
> + - Inital version.
>
> +**/
>
> +typedef struct {
>
> + CONFIG_BLOCK_HEADER Header; ///< Config Block
> Header
>
> + SERIAL_IO_SPI_CONFIG
> SpiDeviceConfig[PCH_MAX_SERIALIO_SPI_CONTROLLERS]; ///< SPI
> Configuration
>
> + SERIAL_IO_I2C_CONFIG
> I2cDeviceConfig[PCH_MAX_SERIALIO_I2C_CONTROLLERS]; ///< I2C
> Configuration
>
> + SERIAL_IO_UART_CONFIG
> UartDeviceConfig[PCH_MAX_SERIALIO_UART_CONTROLLERS]; ///< UART
> Configuration
>
> +} SERIAL_IO_CONFIG;
>
> +
>
> +#pragma pack (pop)
>
> +
>
> +#endif // _SERIAL_IO_CONFIG_H_
>
> diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/SiConfig.h
> b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/SiConfig.h
> new file mode 100644
> index 0000000000..7ee4554b1d
> --- /dev/null
> +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/SiConfig.h
> @@ -0,0 +1,152 @@
> +/** @file
>
> + Si Config Block
>
> +
>
> + Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +**/
>
> +#ifndef _SI_CONFIG_H_
>
> +#define _SI_CONFIG_H_
>
> +
>
> +#define SI_CONFIG_REVISION 2
>
> +
>
> +extern EFI_GUID gSiConfigGuid;
>
> +
>
> +
>
> +#pragma pack (push,1)
>
> +
>
> +/**
>
> + The Silicon Policy allows the platform code to publish a set of configuration
>
> + information that the RC drivers will use to configure the silicon hardware.
>
> +
>
> + <b>Revision 1</b>:
>
> + - Initial version.
>
> + <b>Revision 2</b>:
>
> + - Added TraceHubMemBase
>
> +**/
>
> +typedef struct {
>
> + CONFIG_BLOCK_HEADER Header; ///< Offset 0 - 27 Config Block Header
>
> + //
>
> + // Platform specific common policies that used by several silicon
> components.
>
> + //
>
> + UINT8 CsmFlag; ///< CSM status flag.
>
> + /**
>
> + This is used to skip the SSID programming in silicon code.
>
> + When set to TRUE, silicon code will not do any SSID programming and
> platform code
>
> + needs to handle that by itself properly.
>
> + <b>0: FALSE</b>, 1: TRUE
>
> + **/
>
> + UINT8 SkipSsidProgramming;
>
> + UINT8 RsvdBytes0[2];
>
> + /**
>
> + When SkipSsidProgramming is FALSE, silicon code will use this as default
> value
>
> + to program the SVID for all internal devices.
>
> + <b>0: use silicon default SVID 0x8086 </b>, Non-zero: use customized
> SVID.
>
> + **/
>
> + UINT16 CustomizedSvid;
>
> + /**
>
> + When SkipSsidProgramming is FALSE, silicon code will use this as default
> value
>
> + to program the Sid for all internal devices.
>
> + <b>0: use silicon default SSID 0x7270 </b>, Non-zero: use customized
> SSID.
>
> + **/
>
> + UINT16 CustomizedSsid;
>
> + /**
>
> + SsidTablePtr contains the SVID_SID_INIT_ENTRY table.
>
> + This is valid when SkipSsidProgramming is FALSE;
>
> + It doesn't need to contain entries for all Intel internal devices.
>
> + It can only contains the SVID_SID_INIT_ENTRY entries for those Dev#
> Func# which needs
>
> + to be overridden.
>
> + In the enties, only Dev, Function, SubSystemVendorId, and SubSystemId
> are required.
>
> + <b>Default is NULL.</b>
>
> +
>
> + E.g. Platform only needs to override BDF 0:31:5 to AAAA:BBBB and BDF
> 0:31:3 to CCCC:DDDD,
>
> + it can be done in platform like this:
>
> + STATIC SVID_SID_INIT_ENTRY mSsidTablePtr[SI_MAX_DEVICE_COUNT] =
> {0};
>
> +
>
> + VOID SiPolicyUpdate () {
>
> + UINT32 EntryCount = 0;
>
> + SiPolicy->SkipSsidProgramming = FALSE;
>
> + SiPolicy->SsidTablePtr = mSsidTablePtr;
>
> +
>
> + mSsidTablePtr[EntryCount].Address.Bits.Device = SpiDeviceNumber ();
>
> + mSsidTablePtr[EntryCount].Address.Bits.Function = SpiFunctionNumber
> ();
>
> + mSsidTablePtr[EntryCount].SvidSidValue.SubSystemVendorId =
> 0xAAAA;
>
> + mSsidTablePtr[EntryCount].SvidSidValue.SubSystemId = 0xBBBB;
>
> + EntryCount ++;
>
> + mSsidTablePtr[EntryCount].Address.Bits.Device = HdaDevNumber ();
>
> + mSsidTablePtr[EntryCount].Address.Bits.Function = HdaFuncNumber ();
>
> + mSsidTablePtr[EntryCount].SvidSidValue.SubSystemVendorId = 0xCCCC;
>
> + mSsidTablePtr[EntryCount].SvidSidValue.SubSystemId = 0xDDDD;
>
> + EntryCount ++;
>
> + ASSERT (EntryCount < SI_MAX_DEVICE_COUNT);
>
> + SiPolicy->NumberOfSsidTableEntry = EntryCount;
>
> + }
>
> + **/
>
> + UINT32 *SsidTablePtr;
>
> + /**
>
> + Number of valid enties in SsidTablePtr.
>
> + This is valid when SkipSsidProgramming is FALSE;
>
> + <b>Default is 0.</b>
>
> + **/
>
> + UINT16 NumberOfSsidTableEntry;
>
> + UINT8 RsvdBytes1[2];
>
> + /**
>
> + If Trace Hub is enabled and trace to memory is desired, Platform code or
> BootLoader needs to allocate trace hub memory
>
> + as reserved, and save allocated memory base to TraceHubMemBase to
> ensure Trace Hub memory is configured properly.
>
> + To get total trace hub memory size please refer to
> TraceHubCalculateTotalBufferSize ()
>
> +
>
> + Noted: If EDKII memory service is used to allocate memory, it will require
> double memory size to support size-aligned memory allocation,
>
> + so Platform code or FSP Wrapper code should ensure enough memory
> available for size-aligned TraceHub memory allocation.
>
> + **/
>
> + UINT32 TraceHubMemBase; // Offset 58
>
> + /**
>
> + This is used to skip setting BIOS_DONE MSR during firmware update boot
> mode.
>
> + When set to TRUE and boot mode is BOOT_ON_FLASH_UPDATE,
>
> + skip setting BIOS_DONE MSR at EndofPei.
>
> + <b>0: FALSE</b>, 1: TRUE
>
> + **/
>
> + UINT8 SkipBiosDoneWhenFwUpdate;
>
> + UINT8 RsvdBytes2[3];
>
> +} SI_CONFIG;
>
> +
>
> +#pragma pack (pop)
>
> +
>
> +#define DEFAULT_SSVID 0x8086
>
> +#define DEFAULT_SSDID 0x7270
>
> +#define SI_MAX_DEVICE_COUNT 70
>
> +
>
> +///
>
> +/// Subsystem Vendor ID / Subsystem ID
>
> +///
>
> +typedef struct {
>
> + UINT16 SubSystemVendorId;
>
> + UINT16 SubSystemId;
>
> +} SVID_SID_VALUE;
>
> +
>
> +//
>
> +// Below is to match PCI_SEGMENT_LIB_ADDRESS () which can directly send
> to PciSegmentRead/Write functions.
>
> +//
>
> +typedef struct {
>
> + union {
>
> + struct {
>
> + UINT32 Register:12;
>
> + UINT32 Function:3;
>
> + UINT32 Device:5;
>
> + UINT32 Bus:8;
>
> + UINT32 Reserved1:4;
>
> + UINT32 Segment:16;
>
> + UINT32 Reserved2:16;
>
> + } Bits;
>
> + UINT64 SegBusDevFuncRegister;
>
> + } Address;
>
> + SVID_SID_VALUE SvidSidValue;
>
> + UINT32 Reserved;
>
> +} SVID_SID_INIT_ENTRY;
>
> +
>
> +
>
> +typedef struct {
>
> + UINT32 SkipBus;
>
> + UINT32 SkipDevice;
>
> + UINT32 SkipFunction;
>
> +} SVID_SID_SKIP_TABLE;
>
> +
>
> +#endif // _SI_CONFIG_H_
>
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/SiPreMemConfig.h
> b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/SiPreMemConfig.h
> new file mode 100644
> index 0000000000..4bf014e9ba
> --- /dev/null
> +++
> b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/SiPreMemConfig.h
> @@ -0,0 +1,67 @@
> +/** @file
>
> + Si Config Block PreMem
>
> +
>
> + Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +**/
>
> +#ifndef _SI_PREMEM_CONFIG_H_
>
> +#define _SI_PREMEM_CONFIG_H_
>
> +
>
> +#define SI_PREMEM_CONFIG_REVISION 1
>
> +
>
> +extern EFI_GUID gSiPreMemConfigGuid;
>
> +
>
> +typedef enum {
>
> + ProbeTypeDisabled = 0x00,
>
> + ProbeTypeDciOob = 0x02,
>
> + ProbeTypeUsb3Dbc = 0x03,
>
> + ProbeTypeXdp3 = 0x04,
>
> + ProbeTypeUsb2Dbc = 0x05,
>
> + ProbeType2WireDciOob = 0x06,
>
> + ProbeTypeManual = 0x07,
>
> + ProbeTypeMax
>
> +} PLATFORM_DEBUG_CONSENT_PROBE_TYPE;
>
> +
>
> +#pragma pack (push,1)
>
> +/**
>
> + The Silicon PreMem Policy allows the platform code to publish a set of
> configuration
>
> + information that the RC drivers will use to configure the silicon hardware.
>
> +
>
> + <b>Revision 1</b>:
>
> + - Initial version.
>
> +**/
>
> +typedef struct {
>
> + CONFIG_BLOCK_HEADER Header; ///< Offset 0 - 27 Config Block Header
>
> + /**
>
> + Platform Debug Consent
>
> + As a master switch to enable platform debug capability and relevant
> settings with specified probe type.
>
> + Manual: Do not use Platform Debug Consent to override other debug-
> relevant policies, but the user must set each debug option manually, aimed
> at advanced users.
>
> +
>
> + PDC-dependent policies are listed:
>
> + DciPreMemConfig->DciEn
>
> + DciPreMemConfig->DciDbcMode
>
> + CpuTraceHubConfig->EnableMode
>
> + CpuTraceHubConfig->CpuTraceHubMemReg0Size
>
> + CpuTraceHubConfig->CpuTraceHubMemReg1Size
>
> + PchTraceHubPreMemConfig->EnableMode
>
> + PchTraceHubPreMemConfig->MemReg0Size
>
> + PchTraceHubPreMemConfig->MemReg1Size
>
> +
>
> + Note: DCI OOB (aka BSSB) uses CCA probe.
>
> + Refer to definition of PLATFORM_DEBUG_CONSENT_PROBE_TYPE
>
> + <b>0:Disabled</b>; 2:DCI OOB; 3:USB3 DbC; 4:XDP3/MIPI60 5:USB2 DbC;
> 6:2-wire DCI OOB; 7:Manual
>
> + **/
>
> + UINT32 PlatformDebugConsent : 4;
>
> + UINT32 RsvdBits : 28;
>
> + /**
>
> + This is used to skip override boot mode during firmware update boot
> mode.
>
> + When set to TRUE and boot mode is BOOT_ON_FLASH_UPDATE,
>
> + skip setting boot mode to BOOT_WITH_FULL_CONFIGURATION in PEI
> memory init.
>
> + <b>0: FALSE</b>, 1: TRUE
>
> + **/
>
> + UINT8 SkipOverrideBootModeWhenFwUpdate;
>
> + UINT8 RsvdBytes[3];
>
> +} SI_PREMEM_CONFIG;
>
> +
>
> +#pragma pack (pop)
>
> +#endif // _SI_PREMEM_CONFIG_H_
>
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Smbus/SmbusConfig
> .h
> b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Smbus/SmbusConfig
> .h
> new file mode 100644
> index 0000000000..36f96a4f32
> --- /dev/null
> +++
> b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Smbus/SmbusConfig
> .h
> @@ -0,0 +1,50 @@
> +/** @file
>
> + Smbus policy
>
> +
>
> + Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +**/
>
> +#ifndef _SMBUS_CONFIG_H_
>
> +#define _SMBUS_CONFIG_H_
>
> +
>
> +#define SMBUS_PREMEM_CONFIG_REVISION 1
>
> +extern EFI_GUID gSmbusPreMemConfigGuid;
>
> +
>
> +#pragma pack (push,1)
>
> +
>
> +#define PCH_MAX_SMBUS_RESERVED_ADDRESS 128
>
> +
>
> +///
>
> +/// The SMBUS_CONFIG block lists the reserved addresses for non-ARP
> capable devices in the platform.
>
> +///
>
> +typedef struct {
>
> + /**
>
> + Revision 1: Init version
>
> + **/
>
> + CONFIG_BLOCK_HEADER Header; ///< Config Block Header
>
> + /**
>
> + This member describes whether or not the SMBus controller of PCH
> should be enabled.
>
> + 0: Disable; <b>1: Enable</b>.
>
> + **/
>
> + UINT32 Enable : 1;
>
> + UINT32 ArpEnable : 1; ///< Enable SMBus ARP support, <b>0:
> Disable</b>; 1: Enable.
>
> + UINT32 DynamicPowerGating : 1; ///< <b>(Test)</b> <b>Disable</b>
> or Enable Smbus dynamic power gating.
>
> + ///
>
> + /// <b>(Test)</b> SPD Write Disable, 0: leave SPD Write Disable bit; <b>1:
> set SPD Write Disable bit.</b>
>
> + /// For security recommendations, SPD write disable bit must be set.
>
> + ///
>
> + UINT32 SpdWriteDisable : 1;
>
> + UINT32 SmbAlertEnable : 1; ///< Enable SMBus Alert pin
> (SMBALERT#). 0: <b>Disabled<b>, 1: Enabled.
>
> + UINT32 RsvdBits0 : 27; ///< Reserved bits
>
> + UINT16 SmbusIoBase; ///< SMBUS Base Address (IO space).
> Default is <b>0xEFA0</b>.
>
> + UINT8 Rsvd0; ///< Reserved bytes
>
> + UINT8 NumRsvdSmbusAddresses; ///< The number of elements in
> the RsvdSmbusAddressTable.
>
> + /**
>
> + Array of addresses reserved for non-ARP-capable SMBus devices.
>
> + **/
>
> + UINT8
> RsvdSmbusAddressTable[PCH_MAX_SMBUS_RESERVED_ADDRESS];
>
> +} PCH_SMBUS_PREMEM_CONFIG;
>
> +
>
> +#pragma pack (pop)
>
> +
>
> +#endif // _SMBUS_CONFIG_H_
>
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Spi/SpiConfig.h
> b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Spi/SpiConfig.h
> new file mode 100644
> index 0000000000..f3e52ff453
> --- /dev/null
> +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Spi/SpiConfig.h
> @@ -0,0 +1,43 @@
> +/** @file
>
> + PCH SPI Flash Controller config block
>
> +
>
> + Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +**/
>
> +
>
> +#ifndef _SPI_CONFIG_H_
>
> +#define _SPI_CONFIG_H_
>
> +
>
> +#define SPI_CONFIG_REVISION 1
>
> +extern EFI_GUID gSpiConfigGuid;
>
> +
>
> +#pragma pack (push,1)
>
> +
>
> +/**
>
> + Basic configuration for option features of PCH SPI Flash controller
>
> +**/
>
> +typedef struct {
>
> + CONFIG_BLOCK_HEADER Header; ///< Config Block Header
>
> + /**
>
> + Enable extended BIOS Direct Read Region feature
>
> + Enabling this will make all memory accesses in a decode range to be
> translated
>
> + to BIOS region reads from SPI flash
>
> + <b>0: Disabled</b>, 1: Enabled
>
> + **/
>
> + UINT32 ExtendedBiosDecodeRangeEnable : 1;
>
> + UINT32 RsvdBits0 : 31; ///< Reserved bits
>
> + /**
>
> + Base address that will be used for Extended Decode Range.
>
> + This will be ignored when ExtendedBiosDecodeRangeEnable is set to 0.
>
> + **/
>
> + UINT32 ExtendedBiosDecodeRangeBase;
>
> + /**
>
> + Limit address that will be used for Extended Decode Range.
>
> + This will be ignored when ExtendedBiosDecodeRangeEnable is set to 0.
>
> + **/
>
> + UINT32 ExtendedBiosDecodeRangeLimit;
>
> +} SPI_CONFIG;
>
> +
>
> +#pragma pack (pop)
>
> +
>
> +#endif // _SPI_CONFIG_H_
>
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Tcss/TcssPeiConfig.h
> b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Tcss/TcssPeiConfig.h
> new file mode 100644
> index 0000000000..53af4ccd45
> --- /dev/null
> +++
> b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Tcss/TcssPeiConfig.h
> @@ -0,0 +1,145 @@
> +/** @file
>
> + TCSS PEI policy
>
> +
>
> + Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +**/
>
> +#ifndef _TCSS_PEI_CONFIG_H_
>
> +#define _TCSS_PEI_CONFIG_H_
>
> +
>
> +#include <ConfigBlock.h>
>
> +#include <UsbConfig.h>
>
> +#include <TcssInfo.h>
>
> +
>
> +#define TCSS_PEI_CONFIG_REVISION 2
>
> +extern EFI_GUID gTcssPeiConfigGuid;
>
> +
>
> +#pragma pack (push,1)
>
> +
>
> +
>
> +#define MAX_IOM_AUX_BIAS_COUNT 4
>
> +
>
> +///
>
> +/// The IOM_AUX_ORI_PAD_CONFIG describes IOM TypeC port map GPIO
> pin.
>
> +/// Those GPIO setting for DP Aux Orientation Bias Control when the TypeC
> port didn't have re-timer.
>
> +/// IOM needs know Pull-Up and Pull-Down pin for Bias control
>
> +///
>
> +typedef struct {
>
> + UINT32 GpioPullN; ///< GPIO Pull Up Ping number that is for IOM
> indecate the pull up pin from TypeC port.
>
> + UINT32 GpioPullP; ///< GPIO Pull Down Ping number that is for IOM
> indecate the pull down pin from TypeC port.
>
> +} IOM_AUX_ORI_PAD_CONFIG;
>
> +
>
> +///
>
> +/// The IOM_EC_INTERFACE_CONFIG block describes interaction between
> BIOS and IOM-EC.
>
> +///
>
> +
>
> +typedef struct {
>
> + UINT32 VccSt; ///< IOM VCCST request. (Not equal to actual VCCST
> value)
>
> + UINT32 UsbOverride; ///< IOM to override USB connection.
>
> + UINT32 D3ColdEnable; ///< Enable/disable D3 Cold support in TCSS
>
> + UINT32 D3HotEnable; ///< Enable/disable D3 Hot support in TCSS
>
> +} IOM_INTERFACE_CONFIG;
>
> +
>
> +///
>
> +/// The PMC_INTERFACE_CONFIG block describes interaction between
> BIOS and PMC
>
> +///
>
> +typedef struct {
>
> + UINT8 PmcPdEnable; ///< PMC PD Solution Enable
>
> + UINT8 Rsvd[3];
>
> +} PMC_INTERFACE_CONFIG;
>
> +
>
> +///
>
> +/// The SA XDCI INT Pin and IRQ number
>
> +///
>
> +typedef struct {
>
> + UINT8 IntPing; ///< Int Pin Number
>
> + UINT8 Irq; ///< Irq Number
>
> + UINT16 Rsvd;
>
> +} SA_XDCI_IRQ_INT_CONFIG;
>
> +
>
> +///
>
> +/// The TCSS_PCIE_PORT_POLICY block describes PCIe settings for TCSS.
>
> +///
>
> +typedef struct {
>
> + UINT8 AcsEnabled; ///< Indicate whether the ACS is enabled.
> 0: Disable; <b>1: Enable</b>.
>
> + UINT8 DpcEnabled; ///< Downstream Port Containment. 0:
> Disable; <b>1: Enable</b>
>
> + UINT8 RpDpcExtensionsEnabled; ///< RP Extensions for
> Downstream Port Containment. 0: Disable; <b>1: Enable</b>
>
> + UINT8 LtrEnable; ///< Latency Tolerance Reporting
> Mechanism. <b>0: Disable</b>; 1: Enable.
>
> + UINT8 PtmEnabled; ///< Enables PTM capability
>
> +
>
> + UINT8 Aspm; ///< The ASPM configuration of the root port
> (see: PCH_PCIE_ASPM_CONTROL). Default is <b>
>
> + UINT8 SlotNumber; ///< Indicates the slot number for the
> root port. Default is the value as root port index.
>
> + UINT8 SlotPowerLimitScale; ///< <b>(Test)</b> Specifies scale
> used for slot power limit value. Leave as 0 to set to default. Default is
> <b>zero</b>.
>
> + UINT16 SlotPowerLimitValue; ///< <b>(Test)</b> Specifies upper
> limit on power supplies by slot. Leave as 0 to set to default. Default is
> <b>zero</b>.
>
> +
>
> + UINT8 AdvancedErrorReporting; ///< Indicate whether the
> Advanced Error Reporting is enabled. <b>0: Disable</b>; 1: Enable.
>
> + UINT8 UnsupportedRequestReport; ///< Indicate whether the
> Unsupported Request Report is enabled. <b>0: Disable</b>; 1: Enable.
>
> + UINT8 FatalErrorReport; ///< Indicate whether the Fatal Error
> Report is enabled. <b>0: Disable</b>; 1: Enable.
>
> + UINT8 NoFatalErrorReport; ///< Indicate whether the No Fatal
> Error Report is enabled. <b>0: Disable</b>; 1: Enable.
>
> + UINT8 CorrectableErrorReport; ///< Indicate whether the
> Correctable Error Report is enabled. <b>0: Disable</b>; 1: Enable.
>
> + UINT8 SystemErrorOnFatalError; ///< Indicate whether the System
> Error on Fatal Error is enabled. <b>0: Disable</b>; 1: Enable.
>
> + UINT8 SystemErrorOnNonFatalError; ///< Indicate whether the
> System Error on Non Fatal Error is enabled. <b>0: Disable</b>; 1: Enable.
>
> + UINT8 SystemErrorOnCorrectableError; ///< Indicate whether the
> System Error on Correctable Error is enabled. <b>0: Disable</b>; 1: Enable.
>
> +
>
> + UINT16 LtrMaxSnoopLatency; ///< Latency Tolerance Reporting,
> Max Snoop Latency.
>
> + UINT16 LtrMaxNoSnoopLatency; ///< Latency Tolerance Reporting,
> Max Non-Snoop Latency.
>
> + UINT8 SnoopLatencyOverrideMode; ///< Latency Tolerance
> Reporting, Snoop Latency Override Mode.
>
> + UINT8 SnoopLatencyOverrideMultiplier; ///< Latency Tolerance
> Reporting, Snoop Latency Override Multiplier.
>
> + UINT16 SnoopLatencyOverrideValue; ///< Latency Tolerance
> Reporting, Snoop Latency Override Value.
>
> + UINT8 NonSnoopLatencyOverrideMode; ///< Latency Tolerance
> Reporting, Non-Snoop Latency Override Mode.
>
> + UINT8 NonSnoopLatencyOverrideMultiplier; ///< Latency Tolerance
> Reporting, Non-Snoop Latency Override Multiplier.
>
> + UINT16 NonSnoopLatencyOverrideValue; ///< Latency Tolerance
> Reporting, Non-Snoop Latency Override Value.
>
> + UINT8 ForceLtrOverride; ///< <b>0: Disable</b>; 1: Enable.
>
> + UINT8 LtrConfigLock; ///< <b>0: Disable</b>; 1: Enable.
>
> +} TCSS_PCIE_PORT_POLICY;
>
> +
>
> +///
>
> +/// TCSS_PCIE_PEI_POLICY describes PCIe port settings for TCSS.
>
> +///
>
> +typedef struct {
>
> + TCSS_PCIE_PORT_POLICY PciePortPolicy[MAX_ITBT_PCIE_PORT];
>
> +} TCSS_PCIE_PEI_POLICY;
>
> +
>
> +///
>
> +/// The TCSS_IOM_PEI_CONFIG block describes IOM Aux/HSL override
> settings for TCSS.
>
> +///
>
> +typedef struct {
>
> + UINT16 AuxOri; ///< Bits defining value for IOM Aux Orientation
> Register
>
> + UINT16 HslOri; ///< Bits defining value for IOM HSL Orientation Register
>
> +} TCSS_IOM_ORI_OVERRIDE;
>
> +
>
> +///
>
> +/// The TCSS_IOM_PEI_CONFIG block describes IOM settings for TCSS.
>
> +///
>
> +typedef struct {
>
> + IOM_AUX_ORI_PAD_CONFIG
> IomAuxPortPad[MAX_IOM_AUX_BIAS_COUNT]; ///< The
> IOM_AUX_ORI_BIAS_CTRL port config setting.
>
> + TCSS_IOM_ORI_OVERRIDE IomOverrides;
>
> + IOM_INTERFACE_CONFIG IomInterface; ///< Config
> settings are BIOS <-> IOM interface.
>
> + PMC_INTERFACE_CONFIG PmcInterface; ///< Config
> settings for BIOS <-> PMC interface
>
> + UINT8 TcStateLimit; ///< Tcss C-State deep stage
>
> + UINT8 Usb3ComplModeEnable;
>
> + UINT8 Reserved[2]; ///< Reserved bytes for future
> use
>
> +} TCSS_IOM_PEI_CONFIG;
>
> +
>
> +///
>
> +/// The TCSS_MISC_PEI_CONFIG block describes MISC settings for TCSS.
>
> +///
>
> +typedef struct {
>
> + SA_XDCI_IRQ_INT_CONFIG SaXdci; ///< System Agent Xdci Int Pin and
> Irq setting
>
> + UINT32 Rsvd; ///< Reserved bytes for future use, align to
> multiple 4
>
> +} TCSS_MISC_PEI_CONFIG;
>
> +
>
> +///
>
> +/// The TCSS_PEI_CONFIG block describes TCSS settings for SA.
>
> +///
>
> +typedef struct {
>
> + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
>
> + TCSS_PCIE_PEI_POLICY PciePolicy; ///< The PCIe Config
>
> + USB_CONFIG UsbConfig; ///< USB config is shared between PCH
> and SA.
>
> + TCSS_IOM_PEI_CONFIG IomConfig; ///< The Iom Config
>
> + TCSS_MISC_PEI_CONFIG MiscConfig; ///< The MISC Config
>
> +} TCSS_PEI_CONFIG;
>
> +
>
> +#pragma pack (pop)
>
> +
>
> +#endif /* _TCSS_PEI_CONFIG_H_ */
>
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Thc/ThcConfig.h
> b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Thc/ThcConfig.h
> new file mode 100644
> index 0000000000..23c3750216
> --- /dev/null
> +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Thc/ThcConfig.h
> @@ -0,0 +1,73 @@
> +/** @file
>
> + Touch Host Controller policy.
>
> +
>
> + Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +**/
>
> +
>
> +#ifndef _THC_CONFIG_H_
>
> +#define _THC_CONFIG_H_
>
> +
>
> +#define THC_CONFIG_REVISION 1
>
> +extern EFI_GUID gThcConfigGuid;
>
> +
>
> +#pragma pack (push,1)
>
> +
>
> +/**
>
> + Available Port Assignments
>
> +
>
> +**/
>
> +typedef enum {
>
> + ThcAssignmentNone, ///< None of the avaialbe controllers assigned
>
> + ThcAssignmentThc0, ///< Port assigned to THC0
>
> + ThcAssignmentThc1 ///< Port assigned to THC1
>
> +} THC_PORT_ASSIGNMENT;
>
> +
>
> +
>
> +/**
>
> + Port Configuration structure required for each Port that THC might use.
>
> +
>
> +**/
>
> +typedef struct {
>
> + UINT32 Assignment; ///< Sets THCx assignment see
> THC_PORT_ASSIGNMENT
>
> + UINT32 InterruptPinMuxing; ///< Each GPIO PORTx/SPIx INTB Pin has
> different muxing options refer to GPIO_*_MUXING_THC_SPIx_*
>
> +} THC_PORT;
>
> +
>
> +/**
>
> + THC_CONFIG block provides the configurations forTouch Host Controllers
>
> +
>
> + Assignment field in each THC port controlls the THC behavior.
>
> +
>
> + Available scenarios:
>
> + 1: Single Port 0 used by THC0
>
> + - THC0 Enabled
>
> + - Port0 assigned to THC0
>
> + - Port1 unassigned
>
> + - THC1 will be automatically Disabled.
>
> + 2: Both ports used by THC0
>
> + - THC0 Enabled
>
> + - Port0 assigned to THC0
>
> + - Port1 assigned to THC0
>
> + - THC1 will be automatically Disabled.
>
> + 3: Port 0 used by THC0 and Port 1 used by THC1
>
> + - THC0 Enabled
>
> + - Port0 assigned to THC0
>
> + - THC1 Enabled
>
> + - Port1 assigned to THC1.
>
> +<b>4: Both Ports unassigned.</b>
>
> + Both THC Controllers will be disabled in that case.
>
> +
>
> + @note
>
> + Invalid scenario that will cause ASSERT.
>
> + 1. Same port Number assigned to THC0 or THC1.
>
> + 2. Two Ports assigned to THC1.
>
> +
>
> +**/
>
> +typedef struct {
>
> + CONFIG_BLOCK_HEADER Header; ///< Config Block Header
>
> + THC_PORT ThcPort[2]; ///< Port Configuration
>
> +} THC_CONFIG;
>
> +
>
> +#pragma pack (pop)
>
> +
>
> +#endif // _THC_CONFIG_H_
>
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Thermal/ThermalCon
> fig.h
> b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Thermal/ThermalCo
> nfig.h
> new file mode 100644
> index 0000000000..a952f74238
> --- /dev/null
> +++
> b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Thermal/ThermalCo
> nfig.h
> @@ -0,0 +1,153 @@
> +/** @file
>
> + Thermal policy
>
> +
>
> + Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +**/
>
> +#ifndef _THERMAL_CONFIG_H_
>
> +#define _THERMAL_CONFIG_H_
>
> +
>
> +#define THERMAL_CONFIG_REVISION 1
>
> +extern EFI_GUID gThermalConfigGuid;
>
> +
>
> +#pragma pack (push,1)
>
> +
>
> +/**
>
> + This structure lists PCH supported throttling register setting for
> custimization.
>
> + When the SuggestedSetting is enabled, the customized values are ignored.
>
> +**/
>
> +typedef struct {
>
> + UINT32 T0Level : 9; ///< Custimized T0Level value. If
> SuggestedSetting is used, this setting is ignored.
>
> + UINT32 T1Level : 9; ///< Custimized T1Level value. If
> SuggestedSetting is used, this setting is ignored.
>
> + UINT32 T2Level : 9; ///< Custimized T2Level value. If
> SuggestedSetting is used, this setting is ignored.
>
> + UINT32 TTEnable : 1; ///< Enable the thermal throttle function. If
> SuggestedSetting is used, this settings is ignored.
>
> + /**
>
> + When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13
> will force at least T2 state.
>
> + If SuggestedSetting is used, this setting is ignored.
>
> + **/
>
> + UINT32 TTState13Enable : 1;
>
> + /**
>
> + When set to 1, this entire register (TL) is locked and remains locked until
> the next platform reset.
>
> + If SuggestedSetting is used, this setting is ignored.
>
> + **/
>
> + UINT32 TTLock : 1;
>
> + UINT32 SuggestedSetting : 1; ///< 0: Disable; <b>1: Enable</b>
> suggested representative values.
>
> + /**
>
> + ULT processors support thermal management and cross thermal throttling
> between the processor package
>
> + and LP PCH. The PMSYNC message from PCH to CPU includes specific bit
> fields to update the PCH
>
> + thermal status to the processor which is factored into the processor
> throttling.
>
> + Enable/Disable PCH Cross Throttling; 0: Disabled, 1: <b>Enabled</b>.
>
> + **/
>
> + UINT32 PchCrossThrottling : 1;
>
> + UINT32 Rsvd0; ///< Reserved bytes
>
> +} THERMAL_THROTTLE_LEVELS;
>
> +
>
> +//
>
> +// Supported Thermal Sensor Target Width
>
> +//
>
> +typedef enum {
>
> + DmiThermSensWidthX1 = 0,
>
> + DmiThermSensWidthX2 = 1,
>
> + DmiThermSensWidthX4 = 2,
>
> + DmiThermSensWidthX8 = 3,
>
> + DmiThermSensWidthX16 = 4
>
> +} DMI_THERMAL_SENSOR_TARGET_WIDTH;
>
> +
>
> +/**
>
> + This structure allows to customize DMI HW Autonomous Width Control for
> Thermal and Mechanical spec design.
>
> + When the SuggestedSetting is enabled, the customized values are ignored.
>
> + Look at DMI_THERMAL_SENSOR_TARGET_WIDTH for possible values
>
> +**/
>
> +typedef struct {
>
> + UINT32 DmiTsawEn : 1; ///< DMI Thermal Sensor Autonomous
> Width Enable
>
> + UINT32 SuggestedSetting : 1; ///< 0: Disable; <b>1: Enable</b>
> suggested representative values
>
> + UINT32 RsvdBits0 : 6; ///< Reserved bits
>
> + UINT32 TS0TW : 3; ///< Thermal Sensor 0 Target Width
> (<b>DmiThermSensWidthx8</b>)
>
> + UINT32 TS1TW : 3; ///< Thermal Sensor 1 Target Width
> (<b>DmiThermSensWidthx4</b>)
>
> + UINT32 TS2TW : 3; ///< Thermal Sensor 2 Target Width
> (<b>DmiThermSensWidthx2</b>)
>
> + UINT32 TS3TW : 3; ///< Thermal Sensor 3 Target Width
> (<b>DmiThermSensWidthx1</b>)
>
> + UINT32 RsvdBits1 : 12; ///< Reserved bits
>
> +} DMI_HW_WIDTH_CONTROL;
>
> +
>
> +/**
>
> + This structure configures PCH memory throttling thermal sensor GPIO PIN
> settings
>
> +**/
>
> +typedef struct {
>
> + /**
>
> + GPIO PM_SYNC enable, 0:Diabled, 1:<b>Enabled</b>
>
> + When enabled, RC will overrides the selected GPIO native mode.
>
> + For GPIO_C, PinSelection 0: CPU_GP_0 (default) or 1: CPU_GP_1
>
> + For GPIO_D, PinSelection 0: CPU_GP_3 (default) or 1: CPU_GP_2
>
> + For CNL: CPU_GP_0 is GPP_E3, CPU_GP_1 is GPP_E7, CPU_GP_2 is
> GPP_B3, CPU_GP_3 is GPP_B4.
>
> + **/
>
> + UINT32 PmsyncEnable : 1;
>
> + UINT32 C0TransmitEnable : 1; ///< GPIO Transmit enable in C0 state,
> 0:Disabled, 1:<b>Enabled</b>
>
> + UINT32 PinSelection : 1; ///< GPIO Pin assignment selection, <b>0:
> default</b>, 1: secondary
>
> + UINT32 RsvdBits0 : 29;
>
> +} TS_GPIO_PIN_SETTING;
>
> +
>
> +enum PCH_PMSYNC_GPIO_X_SELECTION {
>
> + TsGpioC,
>
> + TsGpioD,
>
> + MaxTsGpioPin
>
> +};
>
> +
>
> +/**
>
> + This structure supports an external memory thermal sensor (TS-on-DIMM
> or TS-on-Board).
>
> +**/
>
> +typedef struct {
>
> + /**
>
> + This will enable PCH memory throttling.
>
> + While this policy is enabled, must also enable EnableExtts in SA policy.
>
> + <b>0: Disable</b>; 1: Enable
>
> + **/
>
> + UINT32 Enable : 1;
>
> + UINT32 RsvdBits0 : 31;
>
> + /**
>
> + GPIO_C and GPIO_D selection for memory throttling.
>
> + It's strongly recommended to choose GPIO_C and GPIO_D for memory
> throttling feature,
>
> + and route EXTTS# accordingly.
>
> + **/
>
> + TS_GPIO_PIN_SETTING TsGpioPinSetting[2];
>
> +} PCH_MEMORY_THROTTLING;
>
> +
>
> +/**
>
> + The THERMAL_CONFIG block describes the expected configuration of the
> Thermal IP block.
>
> +**/
>
> +typedef struct {
>
> + CONFIG_BLOCK_HEADER Header; ///< Config Block Header
>
> + UINT32 PchHotEnable : 1; ///< Enable PCHHOT# pin assertion when
> temperature is higher than PchHotLevel. 0: <b>Disabled<b>, 1: Enabled.
>
> + UINT32 RsvdBits0 : 31;
>
> + /**
>
> + This field decides the settings of Thermal throttling. When the Suggested
> Setting
>
> + is enabled, PCH RC will use the suggested representative values.
>
> + **/
>
> + THERMAL_THROTTLE_LEVELS TTLevels;
>
> + /**
>
> + This field decides the settings of DMI throttling. When the Suggested
> Setting
>
> + is enabled, PCH RC will use the suggested representative values.
>
> + **/
>
> + DMI_HW_WIDTH_CONTROL DmiHaAWC;
>
> + /**
>
> + Memory Thermal Management settings
>
> + **/
>
> + PCH_MEMORY_THROTTLING MemoryThrottling;
>
> + /**
>
> + The recommendation is the same as Cat Trip point.
>
> + This field decides the temperature, default is <b>120</b>.
>
> + Temperature value used for PCHHOT# pin assertion based on 2s
> complement format
>
> + - 0x001 positive 1'C
>
> + - 0x000 0'C
>
> + - 0x1FF negative 1'C
>
> + - 0x1D8 negative 40'C
>
> + - and so on
>
> + **/
>
> + UINT16 PchHotLevel;
>
> + UINT8 Rsvd0[6];
>
> +
>
> +
>
> +} THERMAL_CONFIG;
>
> +
>
> +#pragma pack (pop)
>
> +
>
> +#endif // _THERMAL_CONFIG_H_
>
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/TraceHub/TraceHubC
> onfig.h
> b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/TraceHub/TraceHub
> Config.h
> new file mode 100644
> index 0000000000..9c315fb4a4
> --- /dev/null
> +++
> b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/TraceHub/TraceHub
> Config.h
> @@ -0,0 +1,101 @@
> +/** @file
>
> + Configurations for CPU and PCH trace hub
>
> +
>
> + Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +**/
>
> +#ifndef _TRACE_HUB_CONFIG_H_
>
> +#define _TRACE_HUB_CONFIG_H_
>
> +
>
> +#include <ConfigBlock.h>
>
> +
>
> +#define CPU_TRACEHUB_PREMEM_CONFIG_REVISION 1
>
> +#define PCH_TRACEHUB_PREMEM_CONFIG_REVISION 1
>
> +
>
> +extern EFI_GUID gPchTraceHubPreMemConfigGuid;
>
> +extern EFI_GUID gCpuTraceHubPreMemConfigGuid;
>
> +
>
> +typedef enum {
>
> + CpuTraceHub,
>
> + PchTraceHub
>
> +} TRACE_HUB_DEVICE;
>
> +///
>
> +/// The TRACE_HUB_ENABLE_MODE describes TraceHub mode of
> operation
>
> +///
>
> +typedef enum {
>
> + TraceHubModeDisabled = 0,
>
> + TraceHubModeTargetDebugger = 1,
>
> + TraceHubModeHostDebugger = 2,
>
> + TraceHubModeMax
>
> +} TRACE_HUB_ENABLE_MODE;
>
> +
>
> +///
>
> +/// The TRACE_BUFFER_SIZE describes the desired TraceHub buffer size
>
> +///
>
> +typedef enum {
>
> + TraceBufferNone,
>
> + TraceBuffer1M,
>
> + TraceBuffer8M,
>
> + TraceBuffer64M,
>
> + TraceBuffer128M,
>
> + TraceBuffer256M,
>
> + TraceBuffer512M,
>
> + TraceBufferMax
>
> +} TRACE_BUFFER_SIZE;
>
> +
>
> +#pragma pack (push,1)
>
> +///
>
> +/// TRACE_HUB_CONFIG block describes TraceHub settings
>
> +///
>
> +typedef struct {
>
> + /**
>
> + Trace hub mode. Default is disabled.
>
> + Target Debugger mode refers to debug tool running on target device itself
> and it works as a conventional PCI device;
>
> + Host Debugger mode refers to SUT debugged via probe on host,
> configured as ACPI device with PCI configuration sapce hidden.
>
> + <b>0 = Disable</b>; 1 = Target Debugger mode; 2 = Host Debugger mode
>
> + Refer to TRACE_HUB_ENABLE_MODE
>
> + **/
>
> + UINT8 EnableMode;
>
> + /**
>
> + Trace hub memory buffer region size policy.
>
> + The avaliable memory size options are: 0:0MB (none), 1:1MB,
> <b>2:8MB</b>, 3:64MB, 4:128MB, 5:256MB, 6:512MB.
>
> + Note : Limitation of total buffer size (CPU + PCH) is 512MB. If iTbt is
> enabled, the total size limits to 256 MB.
>
> + Refer to TRACE_BUFFER_SIZE
>
> + **/
>
> + UINT8 MemReg0Size;
>
> + UINT8 MemReg1Size;
>
> + /**
>
> + AET Trace. AET base address can be set to FW Base either from CPU trace
> hub or PCH one.
>
> + AetEnabled must be exclusive, if AetEnabled = 1 for CPU trace hub, must
> AetEnabled = 0 for PCH one.
>
> + The default is set to PCH.
>
> + CPU Trace Hub
>
> + <b>0 = Disabled</b>; 1 = Enabled
>
> + PCH Trace Hub
>
> + 0 = Disabled; <b>1 = Enabled</b>
>
> + **/
>
> + UINT8 AetEnabled;
>
> +} TRACE_HUB_CONFIG;
>
> +
>
> +/**
>
> + CPU Trace Hub PreMem Configuration
>
> + Contains Trace Hub settings for CPU side tracing
>
> + <b>Revision 1</b>: - Initial version.
>
> +**/
>
> +typedef struct {
>
> + CONFIG_BLOCK_HEADER Header; ///< Config Block Header
>
> + TRACE_HUB_CONFIG TraceHub; ///< Trace Hub Config
>
> +} CPU_TRACE_HUB_PREMEM_CONFIG;
>
> +
>
> +/**
>
> + PCH Trace Hub PreMem Configuration
>
> + Contains Trace Hub settings for PCH side tracing
>
> + <b>Revision 1</b>: - Initial version.
>
> +**/
>
> +typedef struct {
>
> + CONFIG_BLOCK_HEADER Header; ///< Config Block Header
>
> + TRACE_HUB_CONFIG TraceHub; ///< Trace Hub Config
>
> +} PCH_TRACE_HUB_PREMEM_CONFIG;
>
> +
>
> +#pragma pack (pop)
>
> +
>
> +#endif
>
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Usb/Usb2PhyConfig.
> h
> b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Usb/Usb2PhyConfig.
> h
> new file mode 100644
> index 0000000000..99063103c3
> --- /dev/null
> +++
> b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Usb/Usb2PhyConfig.
> h
> @@ -0,0 +1,81 @@
> +/** @file
>
> + USB2 PHY configuration policy
>
> +
>
> + Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +**/
>
> +#ifndef _USB2_PHY_CONFIG_H_
>
> +#define _USB2_PHY_CONFIG_H_
>
> +
>
> +#include <UsbConfig.h>
>
> +
>
> +#define USB2_PHY_CONFIG_REVISION 1
>
> +extern EFI_GUID gUsb2PhyConfigGuid;
>
> +
>
> +#pragma pack (push,1)
>
> +
>
> +/**
>
> + This structure configures per USB2 AFE settings.
>
> + It allows to setup the port electrical parameters.
>
> +**/
>
> +typedef struct {
>
> +/** Per Port HS Preemphasis Bias (PERPORTPETXISET)
>
> + 000b - 0mV
>
> + 001b - 11.25mV
>
> + 010b - 16.9mV
>
> + 011b - 28.15mV
>
> + 100b - 28.15mV
>
> + 101b - 39.35mV
>
> + 110b - 45mV
>
> + 111b - 56.3mV
>
> +**/
>
> + UINT8 Petxiset;
>
> +/** Per Port HS Transmitter Bias (PERPORTTXISET)
>
> + 000b - 0mV
>
> + 001b - 11.25mV
>
> + 010b - 16.9mV
>
> + 011b - 28.15mV
>
> + 100b - 28.15mV
>
> + 101b - 39.35mV
>
> + 110b - 45mV
>
> + 111b - 56.3mV
>
> +**/
>
> + UINT8 Txiset;
>
> +/**
>
> + Per Port HS Transmitter Emphasis (IUSBTXEMPHASISEN)
>
> + 00b - Emphasis OFF
>
> + 01b - De-emphasis ON
>
> + 10b - Pre-emphasis ON
>
> + 11b - Pre-emphasis & De-emphasis ON
>
> +**/
>
> + UINT8 Predeemp;
>
> +/**
>
> + Per Port Half Bit Pre-emphasis (PERPORTTXPEHALF)
>
> + 1b - half-bit pre-emphasis
>
> + 0b - full-bit pre-emphasis
>
> +**/
>
> + UINT8 Pehalfbit;
>
> +} USB2_PHY_PARAMETERS;
>
> +
>
> +/**
>
> + This structure holds info on how to tune electrical parameters of USB2
> ports based on board layout
>
> +
>
> + <b>Revision 1</b>:
>
> + - Initial version.
>
> +
>
> +**/
>
> +typedef struct {
>
> + CONFIG_BLOCK_HEADER Header; ///< Config Block Header
>
> + /**
>
> + This structure configures per USB2 port physical settings.
>
> + It allows to setup the port location and port length, and configures the
> port strength accordingly.
>
> + Changing this policy values from default ones may require disabling USB2
> PHY Sus Well Power Gating
>
> + through Usb2PhySusPgEnable on PCH-LP
>
> + **/
>
> + USB2_PHY_PARAMETERS Port[MAX_USB2_PORTS];
>
> +} USB2_PHY_CONFIG;
>
> +
>
> +#pragma pack (pop)
>
> +
>
> +#endif // _USB2_PHY_CONFIG_H_
>
> +
>
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Usb/Usb3HsioConfig.
> h
> b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Usb/Usb3HsioConfig
> .h
> new file mode 100644
> index 0000000000..da816b1378
> --- /dev/null
> +++
> b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Usb/Usb3HsioConfig
> .h
> @@ -0,0 +1,138 @@
> +/** @file
>
> + USB3 Mod PHY configuration policy
>
> +
>
> + Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +**/
>
> +
>
> +#ifndef _USB3_HSIO_CONFIG_H_
>
> +#define _USB3_HSIO_CONFIG_H_
>
> +
>
> +#include <UsbConfig.h>
>
> +
>
> +#define USB3_HSIO_CONFIG_REVISION 2
>
> +extern EFI_GUID gUsb3HsioConfigGuid;
>
> +
>
> +#pragma pack (push,1)
>
> +
>
> +/**
>
> + This structure describes USB3 Port N configuration parameters
>
> +**/
>
> +typedef struct {
>
> + /**
>
> + USB 3.0 TX Output Downscale Amplitude Adjustment (orate01margin)
>
> + HSIO_TX_DWORD8[21:16]
>
> + <b>Default = 00h</b>
>
> + **/
>
> + UINT8 HsioTxDownscaleAmp;
>
> + /**
>
> + USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting
> (ow2tapgen2deemph3p5)
>
> + HSIO_TX_DWORD5[21:16]
>
> + <b>Default = 29h</b> (approximately -3.5dB De-Emphasis)
>
> + **/
>
> + UINT8 HsioTxDeEmph;
>
> + /**
>
> + Signed Magnatude number added to the CTLE
> code.(ctle_adapt_offset_cfg_4_0)
>
> + HSIO_RX_DWORD25 [20:16]
>
> + Ex: -1 -- 1_0001. +1: 0_0001
>
> + <b>Default = 0h</b>
>
> + **/
>
> + UINT8 HsioCtrlAdaptOffsetCfg;
>
> + /**
>
> + LFPS filter select for n (filter_sel_n_2_0)
>
> + HSIO_RX_DWORD51 [29:27]
>
> + 0h:1.6ns
>
> + 1h:2.4ns
>
> + 2h:3.2ns
>
> + 3h:4.0ns
>
> + 4h:4.8ns
>
> + 5h:5.6ns
>
> + 6h:6.4ns
>
> + <b>Default = 0h</b>
>
> + **/
>
> + UINT8 HsioFilterSelN;
>
> + /**
>
> + LFPS filter select for p (filter_sel_p_2_0)
>
> + HSIO_RX_DWORD51 [26:24]
>
> + 0h:1.6ns
>
> + 1h:2.4ns
>
> + 2h:3.2ns
>
> + 3h:4.0ns
>
> + 4h:4.8ns
>
> + 5h:5.6ns
>
> + 6h:6.4ns
>
> + <b>Default = 0h</b>
>
> + **/
>
> + UINT8 HsioFilterSelP;
>
> + /**
>
> + Controls the input offset (olfpscfgpullupdwnres_sus_usb_2_0)
>
> + HSIO_RX_DWORD51 [2:0]
>
> + 000 Prohibited
>
> + 001 45K
>
> + 010 Prohibited
>
> + 011 31K
>
> + 100 36K
>
> + 101 36K
>
> + 110 36K
>
> + 111 36K
>
> + <b>Default = 3h</b>
>
> + **/
>
> + UINT8 HsioOlfpsCfgPullUpDwnRes;
>
> +
>
> + UINT8 HsioTxDeEmphEnable; ///< Enable the write to USB 3.0 TX
> Output -3.5dB De-Emphasis Adjustment, <b>0: Disable</b>; 1: Enable.
>
> + UINT8 HsioTxDownscaleAmpEnable; ///< Enable the write to USB 3.0
> TX Output Downscale Amplitude Adjustment, <b>0: Disable</b>; 1: Enable.
>
> + UINT8 HsioCtrlAdaptOffsetCfgEnable; ///< Enable the write to Signed
> Magnatude number added to the CTLE code, <b>0: Disable</b>; 1: Enable.
>
> + UINT8 HsioFilterSelNEnable; ///< Enable the write to LFPS filter select
> for n, <b>0: Disable</b>; 1: Enable.
>
> + UINT8 HsioFilterSelPEnable; ///< Enable the write to LFPS filter select
> for p, <b>0: Disable</b>; 1: Enable.
>
> + UINT8 HsioOlfpsCfgPullUpDwnResEnable; ///< Enable the write to
> olfpscfgpullupdwnres, <b>0: Disable</b>; 1: Enable.
>
> + /**
>
> + USB 3.0 TX Output - Unique Transition Bit Scale for rate 3
> (rate3UniqTranScale)
>
> + HSIO_TX_DWORD9[6:0]
>
> + <b>Default = 4Ch</b>
>
> + **/
>
> + UINT8 HsioTxRate3UniqTran;
>
> + /**
>
> + USB 3.0 TX Output -Unique Transition Bit Scale for rate 2
> (rate2UniqTranScale)
>
> + HSIO_TX_DWORD9[14:8]
>
> + <b>Default = 4Ch</b>
>
> + **/
>
> + UINT8 HsioTxRate2UniqTran;
>
> + /**
>
> + USB 3.0 TX Output - Unique Transition Bit Scale for rate 1
> (rate1UniqTranScale)
>
> + HSIO_TX_DWORD9[22:16]
>
> + <b>Default = 4Ch</b>
>
> + **/
>
> + UINT8 HsioTxRate1UniqTran;
>
> + /**
>
> + USB 3.0 TX Output - Unique Transition Bit Scale for rate 0
> (rate0UniqTranScale)
>
> + HSIO_TX_DWORD9[30:24]
>
> + <b>Default = 4Ch</b>
>
> + **/
>
> + UINT8 HsioTxRate0UniqTran;
>
> +
>
> + UINT8 HsioTxRate3UniqTranEnable; ///< Enable the write to USB 3.0 TX
> Unique Transition Bit Mode for rate 3, <b>0: Disable</b>; 1: Enable.
>
> + UINT8 HsioTxRate2UniqTranEnable; ///< Enable the write to USB 3.0 TX
> Unique Transition Bit Mode for rate 2, <b>0: Disable</b>; 1: Enable.
>
> + UINT8 HsioTxRate1UniqTranEnable; ///< Enable the write to USB 3.0 TX
> Unique Transition Bit Mode for rate 1, <b>0: Disable</b>; 1: Enable.
>
> + UINT8 HsioTxRate0UniqTranEnable; ///< Enable the write to USB 3.0 TX
> Unique Transition Bit Mode for rate 0, <b>0: Disable</b>; 1: Enable.
>
> +} HSIO_PARAMETERS;
>
> +
>
> +/**
>
> + Structure for holding USB3 tuning parameters
>
> +
>
> + <b>Revision 1</b>:
>
> + - Initial version.
>
> + <b>Revision 2</b>:
>
> + - USB 3.0 TX Output Unique Transition Bit Scale policies added
>
> +**/
>
> +typedef struct {
>
> + CONFIG_BLOCK_HEADER Header; ///< Config Block Header
>
> + /**
>
> + These members describe whether the USB3 Port N of PCH is enabled by
> platform modules.
>
> + **/
>
> + HSIO_PARAMETERS Port[MAX_USB3_PORTS];
>
> +} USB3_HSIO_CONFIG;
>
> +
>
> +#pragma pack (pop)
>
> +
>
> +#endif // _USB3_HSIO_CONFIG_H_
>
> +
>
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Usb/UsbConfig.h
> b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Usb/UsbConfig.h
> new file mode 100644
> index 0000000000..a1c7f0bb04
> --- /dev/null
> +++
> b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Usb/UsbConfig.h
> @@ -0,0 +1,149 @@
> +/** @file
>
> + Common USB policy shared between PCH and CPU
>
> + Contains general features settings for xHCI and xDCI
>
> +
>
> + Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +**/
>
> +#ifndef _USB_CONFIG_H_
>
> +#define _USB_CONFIG_H_
>
> +
>
> +#define USB_CONFIG_REVISION 2
>
> +extern EFI_GUID gUsbConfigGuid;
>
> +
>
> +#define MAX_USB2_PORTS 16
>
> +#define MAX_USB3_PORTS 10
>
> +
>
> +#pragma pack (push,1)
>
> +
>
> +typedef UINT8 USB_OVERCURRENT_PIN;
>
> +#define USB_OC_SKIP 0xFF
>
> +#define USB_OC_MAX_PINS 16 ///< Total OC pins number (both
> physical and virtual)
>
> +
>
> +/**
>
> + This structure configures per USB2.0 port settings like enabling and
> overcurrent protection
>
> +**/
>
> +typedef struct {
>
> + /**
>
> + These members describe the specific over current pin number of USB 2.0
> Port N.
>
> + It is SW's responsibility to ensure that a given port's bit map is set only for
>
> + one OC pin Description. USB2 and USB3 on the same combo Port must
> use the same OC pin.
>
> + **/
>
> + UINT32 OverCurrentPin : 8;
>
> + UINT32 Enable : 1; ///< 0: Disable; <b>1: Enable</b>.
>
> + UINT32 PortResetMessageEnable : 1; ///< 0: Disable USB2 Port Reset
> Message; 1: Enable USB2 Port Reset Message
>
> + UINT32 RsvdBits0 : 22; ///< Reserved bits
>
> +} USB2_PORT_CONFIG;
>
> +
>
> +/**
>
> + This structure configures per USB3.x port settings like enabling and
> overcurrent protection
>
> +**/
>
> +typedef struct {
>
> + /**
>
> + These members describe the specific over current pin number of USB 3.x
> Port N.
>
> + It is SW's responsibility to ensure that a given port's bit map is set only for
>
> + one OC pin Description. USB2 and USB3 on the same combo Port must
> use the same OC pin.
>
> + **/
>
> + UINT32 OverCurrentPin : 8;
>
> + UINT32 Enable : 1; ///< 0: Disable; <b>1: Enable</b>.
>
> + UINT32 RsvdBits0 : 23; ///< Reserved bits
>
> +} USB3_PORT_CONFIG;
>
> +
>
> +/**
>
> + The XDCI_CONFIG block describes the configurations
>
> + of the xDCI Usb Device controller.
>
> +**/
>
> +typedef struct {
>
> + /**
>
> + This member describes whether or not the xDCI controller should be
> enabled.
>
> + 0: Disable; <b>1: Enable</b>.
>
> + **/
>
> + UINT32 Enable : 1;
>
> + UINT32 RsvdBits0 : 31; ///< Reserved bits
>
> +} XDCI_CONFIG;
>
> +
>
> +
>
> +/**
>
> + This member describes the expected configuration of the USB controller,
>
> + Platform modules may need to refer Setup options, schematic, BIOS
> specification to update this field.
>
> + The Usb20OverCurrentPins and Usb30OverCurrentPins field must be
> updated by referring the schematic.
>
> +
>
> + <b>Revision 1</b>: - Initial version.
>
> + <b>Revision 2</b>: - Add USB3LinkSpeed
>
> +**/
>
> +typedef struct {
>
> + CONFIG_BLOCK_HEADER Header; ///< Config Block Header
>
> + /**
>
> + This policy option when set will make BIOS program Port Disable Override
> register during PEI phase.
>
> + When disabled BIOS will not program the PDO during PEI phase and leave
> PDO register unlocked for later programming.
>
> + If this is disabled, platform code MUST set it before booting into OS.
>
> + <b>1: Enable</b>
>
> + 0: Disable
>
> + **/
>
> + UINT32 PdoProgramming : 1;
>
> + /**
>
> + This option allows for control whether USB should program the
> Overcurrent Pins mapping into xHCI.
>
> + Disabling this feature will disable overcurrent detection functionality.
>
> + Overcurrent Pin mapping data is contained in respective port structures
> (i.e. USB30_PORT_CONFIG) in OverCurrentPin field.
>
> + By default this Overcurrent functionality should be enabled and disabled
> only for OBS debug usage.
>
> + <b>1: Will program USB OC pin mapping in respective xHCI controller
> registers</b>
>
> + 0: Will clear OC pin mapping allow for OBS usage of OC pins
>
> + **/
>
> + UINT32 OverCurrentEnable : 1;
>
> + /**
>
> + <b>(Test)</b>
>
> + If this policy option is enabled then BIOS will program OCCFDONE bit in
> xHCI meaning that OC mapping data will be
>
> + consumed by xHCI and OC mapping registers will be locked. OverCurrent
> mapping data is taken from respective port data
>
> + structure from OverCurrentPin field.
>
> + If EnableOverCurrent policy is enabled this also should be enabled,
> otherwise xHCI won't consume OC mapping data.
>
> + <b>1: Program OCCFDONE bit and make xHCI consume OverCurrent
> mapping data</b>
>
> + 0: Do not program OCCFDONE bit making it possible to use OBS debug on
> OC pins.
>
> + **/
>
> + UINT32 XhciOcLock : 1;
>
> + /**
>
> + Enabling this feature will allow for overriding LTR values for xHCI
> controller.
>
> + Values used for programming will be taken from this config block and
> BIOS will disregard recommended ones.
>
> + <b>0: disable - do not override recommended LTR values</b>
>
> + 1: enable - override recommended LTR values
>
> + **/
>
> + UINT32 LtrOverrideEnable : 1;
>
> + /**
>
> + This setting enable LBPM GEN1 speed
>
> + 0: GEN2;
>
> + 1: GEN1;
>
> + **/
>
> + UINT32 USB3LinkSpeed : 1;
>
> + UINT32 RsvdBits0 : 27; ///< Reserved bits
>
> + /**
>
> + High Idle Time Control override value
>
> + This setting is used only if LtrOverrideEnable is enabled
>
> + **/
>
> + UINT32 LtrHighIdleTimeOverride;
>
> + /**
>
> + Medium Idle Time Control override value
>
> + This setting is used only if LtrOverrideEnable is enabled
>
> + **/
>
> + UINT32 LtrMediumIdleTimeOverride;
>
> + /**
>
> + Low Idle Time Control override value
>
> + This setting is used only if LtrOverrideEnable is enabled
>
> + **/
>
> + UINT32 LtrLowIdleTimeOverride;
>
> + /**
>
> + These members describe whether the USB2 Port N of PCH is enabled by
> platform modules.
>
> + **/
>
> + USB2_PORT_CONFIG PortUsb20[MAX_USB2_PORTS];
>
> + /**
>
> + These members describe whether the USB3 Port N of PCH is enabled by
> platform modules.
>
> + **/
>
> + USB3_PORT_CONFIG PortUsb30[MAX_USB3_PORTS];
>
> + /**
>
> + This member describes whether or not the xDCI controller should be
> enabled.
>
> + **/
>
> + XDCI_CONFIG XdciConfig;
>
> +
>
> +} USB_CONFIG;
>
> +
>
> +#pragma pack (pop)
>
> +
>
> +#endif // _USB_CONFIG_H_
>
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/VoltageRegulator/Cp
> uPowerMgmtVrConfig.h
> b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/VoltageRegulator/Cp
> uPowerMgmtVrConfig.h
> new file mode 100644
> index 0000000000..8b01ecd262
> --- /dev/null
> +++
> b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/VoltageRegulator/Cp
> uPowerMgmtVrConfig.h
> @@ -0,0 +1,114 @@
> +/** @file
>
> + CPU Power Management VR Config Block.
>
> +
>
> + Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +**/
>
> +#ifndef _CPU_POWER_MGMT_VR_CONFIG_H_
>
> +#define _CPU_POWER_MGMT_VR_CONFIG_H_
>
> +
>
> +#define CPU_POWER_MGMT_VR_CONFIG_REVISION 7
>
> +
>
> +extern EFI_GUID gCpuPowerMgmtVrConfigGuid;
>
> +
>
> +#pragma pack (push,1)
>
> +
>
> +///
>
> +/// Defines the maximum number of VR domains supported.
>
> +/// @warning: Changing this define would cause DWORD alignment issues
> in policy structures.
>
> +///
>
> +#define MAX_NUM_VRS 5
>
> +
>
> +/**
>
> + CPU Power Management VR Configuration Structure.
>
> +
>
> + <b>Revision 1</b>:
>
> + - Initial version.
>
> + <b>Revision 2</b>:
>
> + - Updated Acoustic Noise Mitigation.
>
> + <b>Revision 3</b>:
>
> + - Deprecate PsysOffset and added PsysOffset1 for Psys Offset Correction
>
> + <b>Revision 4</b>:
>
> + - Deprecate TdcTimeWindow and added TdcTimeWindow1 for TDC Time
>
> + Added Irms support.
>
> + <b>Revision 5</b>:
>
> + - Add RfiMitigation.
>
> + <b>Revision 6</b>:
>
> + - Added an option to Enable/Disable FIVR Spread Spectrum
>
> + <b>Revision 7</b>:
>
> + - Add Dynamic Periodicity Alteration (DPA) tuning feature
>
> +**/
>
> +typedef struct {
>
> + CONFIG_BLOCK_HEADER Header; ///< Config Block Header
>
> + UINT32 AcousticNoiseMitigation : 1; ///< Enable or Disable Acoustic
> Noise Mitigation feature. <b>0: Disabled</b>; 1: Enabled
>
> + /**
>
> + VR specific mailbox commands.
>
> + <b>00b - no VR specific command sent.</b>
>
> + 01b - A VR mailbox command specifically for the MPS IMPV8 VR will be
> sent.
>
> + 10b - VR specific command sent for PS4 exit issue.
>
> + 11b - Reserved.
>
> + **/
>
> + UINT32 SendVrMbxCmd : 2;
>
> + UINT32 EnableMinVoltageOverride : 1; ///< Enable or disable
> Minimum Voltage override for minimum voltage runtime and minimum
> voltage C8. <b>0: Disabled</b> 1: Enabled.
>
> + UINT32 RfiMitigation : 1; ///< Enable or Disable RFI Mitigation.
> <b>0: Disable - DCM is the IO_N default</b>; 1: Enable - Enable IO_N
> DCM/CCM switching as RFI mitigation.
>
> + UINT32 RsvdBits : 27; ///< Reserved for future use.
>
> + UINT8 PsysSlope; ///< PCODE MMIO Mailbox: Platform
> Psys slope correction. <b>0: Auto</b> Specified in 1/100 increment values.
> Range is 0-200. 125 = 1.25.
>
> + UINT8 PsysOffset; ///< PCODE MMIO Mailbox: Platform
> Psys offset correction. <b>0: Auto</b> Units 1/4, Range 0-255. Value of 100 =
> 100/4 = 25 offset. Deprecated
>
> + UINT8 FivrSpreadSpectrum; ///< Set the Spread Spectrum
> Range. <b>1.5%</b>, Range: 0.5%, 1%, 1.5%, 2%, 3%, 4%, 5%, 6%. Each
> Range is translated to internally encoded values. 0.5% = 0, 1% = 3, 1.5% = 8,
> 2% = 18, 3% = 28, 4% = 34, 5% = 39, 6% = 44.
>
> + UINT8 RsvdBytes0;
>
> + /**
>
> + PCODE MMIO Mailbox: Set the desired RFI frequency, in increments of
> 100KHz.
>
> + <b>0: Auto</b>
>
> + Range varies based on XTAL clock:
>
> + - 0-1918 (Up to 191.8HMz) for 24MHz clock.
>
> + - 0-1535 (Up to 153.5MHz) for 19MHz clock.
>
> + **/
>
> + UINT16 FivrRfiFrequency;
>
> + UINT8 RsvdBytes1[2];
>
> + /** @name VR Settings
>
> + The VR related settings are sorted in an array where each index maps to
> the VR domain as defined below:
>
> + - 0 = System Agent VR
>
> + - 1 = IA Core VR
>
> + - 2 = Ring Vr
>
> + - 3 = GT VR
>
> + - 4 = FIVR VR
>
> +
>
> + The VR settings for a given domain must be populated in the appropriate
> index.
>
> + **/
>
> + ///@{
>
> + UINT16 TdcCurrentLimit[MAX_NUM_VRS]; ///< PCODE MMIO
> Mailbox: Thermal Design Current current limit. Specified in 1/8A units. Range
> is 0-4095. 1000 = 125A. <b>0: 0 Amps</b>
>
> + UINT16 AcLoadline[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox:
> AcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is 0-6249.
> <b>Intel Recommended Defaults vary by domain and SKU.</b>
>
> + UINT16 DcLoadline[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox:
> DcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is 0-
> 6249.<b>Intel Recommended Defaults vary by domain and SKU.</b>
>
> + UINT16 Psi1Threshold[MAX_NUM_VRS]; ///< PCODE MMIO
> Mailbox: Power State 1 current cuttof in 1/4 Amp increments. Range is 0-
> 128A.
>
> + UINT16 Psi2Threshold[MAX_NUM_VRS]; ///< PCODE MMIO
> Mailbox: Power State 2 current cuttof in 1/4 Amp increments. Range is 0-
> 128A.
>
> + UINT16 Psi3Threshold[MAX_NUM_VRS]; ///< PCODE MMIO
> Mailbox: Power State 3 current cuttof in 1/4 Amp increments. Range is 0-
> 128A.
>
> + INT16 ImonOffset[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox:
> Imon offset correction. Value is a 2's complement signed integer. Units
> 1/1000, Range 0-63999. For an offset = 12.580, use 12580. <b>0: Auto</b>
>
> + UINT16 IccMax[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox:
> VR Icc Max limit. 0-255A in 1/4 A units. 400 = 100A. <b>Default: 0 - Auto, no
> override</b>
>
> + UINT16 VrVoltageLimit[MAX_NUM_VRS]; ///< PCODE MMIO
> Mailbox: VR Voltage Limit. Range is 0-7999mV.
>
> + UINT16 ImonSlope[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox:
> Imon slope correction. Specified in 1/100 increment values. Range is 0-200.
> 125 = 1.25. <b>0: Auto</b>
>
> + UINT8 Psi3Enable[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox:
> Power State 3 enable/disable; 0: Disable; <b>1: Enable</b>.
>
> + UINT8 Psi4Enable[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox:
> Power State 4 enable/disable; 0: Disable; <b>1: Enable</b>.
>
> + UINT8 VrConfigEnable[MAX_NUM_VRS]; ///< Enable/Disable BIOS
> configuration of VR; 0: Disable; <b>1: Enable.</b>
>
> + UINT8 TdcEnable[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox:
> Thermal Design Current enable/disable; <b>0: Disable; </b>1: Enable
>
> + UINT8 TdcTimeWindow[MAX_NUM_VRS]; ///< @deprecated.
> PCODE MMIO Mailbox: Thermal Design Current time window. Defined in milli
> seconds. <b>1ms default</b>
>
> + UINT8 TdcLock[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox:
> Thermal Design Current Lock; <b>0: Disable</b>; 1: Enable.
>
> + UINT8 FastPkgCRampDisable[MAX_NUM_VRS]; ///< Disable Fast Slew
> Rate for Deep Package C States for VR IA,GT,SA,VLCC,FIVR domain based on
> Acoustic Noise Mitigation feature enabled. <b>0: False</b>; 1: True
>
> + UINT8 SlowSlewRate[MAX_NUM_VRS]; ///< Slew Rate
> configuration for Deep Package C States for VR VR IA,GT,SA,VLCC,FIVR
> domain based on Acoustic Noise Mitigation feature enabled. <b>0:
> Fast/2</b>; 1: Fast/4; 2: Fast/8; 3: Fast/16
>
> + ///@}
>
> + UINT16 MinVoltageRuntime; ///< PCODE MMIO Mailbox:
> Minimum voltage for runtime. Valid if EnableMinVoltageOverride = 1 .Range
> 0 to 1999mV. <b> 0: 0mV </b>
>
> + UINT16 MinVoltageC8; ///< PCODE MMIO Mailbox: Minimum
> voltage for C8. Valid if EnableMinVoltageOverride = 1. Range 0 to 1999mV.
> <b> 0: 0mV </b>
>
> + UINT16 PsysOffset1; ///< PCODE MMIO Mailbox: Platform
> Psys offset correction. <b>0: Auto</b> Units 1/1000, Range 0-63999. For an
> offset of 25.348, enter 25348.
>
> + UINT8 RsvdBytes2[2];
>
> + UINT32 TdcTimeWindow1[MAX_NUM_VRS]; ///< PCODE MMIO
> Mailbox: Thermal Design Current time window. Defined in milli seconds.
> <b>1ms default</b>
>
> + UINT8 Irms[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox:
> Current root mean square. <b>0: Disable</b>; 1: Enable.
>
> + UINT8 FivrSpectrumEnable; ///< Enable or Disable FIVR Spread
> Spectrum 0: Disable; <b> 1: Enable.</b>
>
> + UINT8 Rsvd1[2];
>
> + UINT8 PreWake; ///< PCODE MMIO Mailbox: Acoustic
> Noise Mitigation Range. This can be programmed only if
> AcousticNoiseMitigation is enabled.<b>Default Value = 0 micro ticks</b>
> Defines the max pre-wake randomization time in micro ticks. Range is 0-255.
>
> + UINT8 RampUp; ///< PCODE MMIO Mailbox: Acoustic
> Noise Mitigation Range. This can be programmed only if
> AcousticNoiseMitigation is enabled.<b>Default Value = 0 micro ticks</b>
> Defines the max ramp up randomization time in micro ticks. Range is 0-255.
>
> + UINT8 RampDown; ///< PCODE MMIO Mailbox: Acoustic
> Noise Mitigation Range. This can be programmed only if
> AcousticNoiseMitigation is enabled.<b>Default Value = 0 micro ticks</b>
> Defines the max ramp down randomization time in micro ticks. Range is 0-
> 255.
>
> + UINT8 Rsvd2[1];
>
> +} CPU_POWER_MGMT_VR_CONFIG;
>
> +
>
> +#pragma pack (pop)
>
> +
>
> +#endif // _CPU_POWER_MGMT_VR_CONFIG_H_
>
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Vtd/VtdConfig.h
> b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Vtd/VtdConfig.h
> new file mode 100644
> index 0000000000..74ca983a5d
> --- /dev/null
> +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Vtd/VtdConfig.h
> @@ -0,0 +1,64 @@
> +/** @file
>
> + VT-d policy definitions.
>
> +
>
> + Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +**/
>
> +#ifndef _VTD_CONFIG_H_
>
> +#define _VTD_CONFIG_H_
>
> +
>
> +#include <Library/VtdInfoLib.h>
>
> +#pragma pack(push, 1)
>
> +
>
> +#define VTD_CONFIG_REVISION 1
>
> +#define VTD_DXE_CONFIG_REVISION 2
>
> +
>
> +/**
>
> + The data elements should be initialized by a Platform Module.
>
> + The data structure is for VT-d driver initialization\n
>
> + <b>Revision 1</b>:
>
> + - Initial version.
>
> +**/
>
> +typedef struct {
>
> + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block
> Header
>
> + /**
>
> + Offset 28:
>
> + VT-D Support can be verified by reading CAP ID register as expalined in
> BIOS Spec.
>
> + This policy is for debug purpose only.
>
> + If VT-D is not supported, all other policies in this config block will be
> ignored.
>
> + <b>0 = To use Vt-d</b>;
>
> + 1 = Avoids programming Vtd bars, Vtd overrides and DMAR table.
>
> + **/
>
> + UINT8 VtdDisable;
>
> + UINT8 X2ApicOptOut; ///< Offset 29 :This field is used to enable the
> X2APIC_OPT_OUT bit in the DMAR table. 1=Enable/Set and
> <b>0=Disable/Clear</b>
>
> + UINT8 DmaControlGuarantee; ///< Offset 30 :This field is used to
> enable the DMA_CONTROL_GUARANTEE bit in the DMAR table.
> 1=Enable/Set and <b>0=Disable/Clear</b>
>
> + UINT8 VtdIgdEnable; ///< Offset 31 :This field is used to enable the
> VtdIgdEnable Policy. 1=Enable/Set and <b>0=Disable/Clear</b>
>
> + UINT8 VtdIpuEnable; ///< Offset 32 :This field is used to enable the
> VtdIpuEnable Policy. 1=Enable/Set and <b>0=Disable/Clear</b>
>
> + UINT8 VtdIopEnable; ///< Offset 33 :This field is used to enable the
> VtdIopEnable Policy. 1=Enable/Set and <b>0=Disable/Clear</b>
>
> + UINT8 VtdItbtEnable; ///< Offset 34 :This field is used to enable the
> VtdItbtEnable Policy. 1=Enable/Set and <b>0=Disable/Clear</b>
>
> + UINT8 PreBootDmaMask; ///< Offset 35 :Convey
> PcdVTdPolicyPropertyMask value from EDK2 IntelSiliconPkg
>
> + /**
>
> + Offset 36:
>
> + This field is used to describe the base addresses for VT-d function:\n
>
> + VTD BAR for Gfx if IGfx is supported : <b>BaseAddress[0]=0xFED90000,\n
>
> + VTD BAR for IPU if IPU is supporrted : BaseAddress[1]=0xFED92000,\n
>
> + VTD BAR for other DMA Agents (except Igfx and IPU) :
> BaseAddress[2]=0xFED91000,\n
>
> + VTD BAR for iTBT if iTBT is supported : BaseAddress[3]=0xFED84000,
> BaseAddress[4]=0xFED85000,
> BaseAddress[5]=0xFED86000,BaseAddress[6]=0xFED87000</b>
>
> + **/
>
> + UINT32 BaseAddress[VTD_ENGINE_NUMBER];
>
> + UINT32 DmaBufferSize; ///< Offset 64 :Protect Memory Region
> (PMR) DMA buffer size
>
> +
>
> +
>
> +} VTD_CONFIG;
>
> +
>
> +/**
>
> + The data structure is for VT-d driver initialization in DXE\n
>
> + <b>Revision 1</b>:
>
> + - Initial version.
>
> +**/
>
> +typedef struct {
>
> + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block
> Header
>
> +} VTD_DXE_CONFIG;
>
> +#pragma pack(pop)
>
> +
>
> +#endif // _VTD_CONFIG_H_
>
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Wdt/WatchDogConfi
> g.h
> b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Wdt/WatchDogConfi
> g.h
> new file mode 100644
> index 0000000000..8766762580
> --- /dev/null
> +++
> b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Wdt/WatchDogConfi
> g.h
> @@ -0,0 +1,31 @@
> +/** @file
>
> + WatchDog policy
>
> +
>
> + Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +**/
>
> +#ifndef _WATCH_DOG_CONFIG_H_
>
> +#define _WATCH_DOG_CONFIG_H_
>
> +
>
> +#define WATCH_DOG_PREMEM_CONFIG_REVISION 1
>
> +extern EFI_GUID gWatchDogPreMemConfigGuid;
>
> +
>
> +#pragma pack (push,1)
>
> +
>
> +/**
>
> + This policy clears status bits and disable watchdog, then lock the
>
> + WDT registers.
>
> + while WDT is designed to be disabled and locked by Policy,
>
> + bios should not enable WDT by WDT PPI. In such case, bios shows the
>
> + warning message but not disable and lock WDT register to make sure
>
> + WDT event trigger correctly.
>
> +**/
>
> +typedef struct {
>
> + CONFIG_BLOCK_HEADER Header; ///< Config Block Header
>
> + UINT32 DisableAndLock : 1; ///< <b>(Test)</b> Set 1 to clear WDT
> status, then disable and lock WDT registers. <b>0: Disable</b>; 1: Enable.
>
> + UINT32 RsvdBits : 31;
>
> +} PCH_WDT_PREMEM_CONFIG;
>
> +
>
> +#pragma pack (pop)
>
> +
>
> +#endif // _WATCH_DOG_CONFIG_H_
>
> diff --git a/Silicon/Intel/TigerlakeSiliconPkg/SiPkg.dec
> b/Silicon/Intel/TigerlakeSiliconPkg/SiPkg.dec
> new file mode 100644
> index 0000000000..0982758b77
> --- /dev/null
> +++ b/Silicon/Intel/TigerlakeSiliconPkg/SiPkg.dec
> @@ -0,0 +1,1208 @@
> +## @file
>
> +# Component description file for the Silicon Reference Code.
>
> +#
>
> +# Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
>
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +#
>
> +##
>
> +
>
> +
>
> +[Defines]
>
> +DEC_SPECIFICATION = 0x00010017
>
> +PACKAGE_NAME = SiPkg
>
> +PACKAGE_VERSION = 0.1
>
> +PACKAGE_GUID = F245E276-44A0-46b3-AEB5-9898BBCF008D
>
> +
>
> +[Includes.Common.Private]
>
> +
>
> +#
>
> +# TigerLake Fru
>
> +#
>
> +Fru/TglCpu/IncludePrivate
>
> +Fru/TglPch/IncludePrivate
>
> +
>
> +##
>
> +# IpBlock IncludePrivate
>
> +#
>
> +IpBlock/Psf/IncludePrivate
>
> +IpBlock/Pmc/IncludePrivate
>
> +IpBlock/Smbus/IncludePrivate
>
> +IpBlock/Graphics/IncludePrivate
>
> +IpBlock/CpuPcieRp/IncludePrivate
>
> +IpBlock/Hda/IncludePrivate
>
> +IpBlock/PchDmi/IncludePrivate
>
> +IpBlock/P2sb/IncludePrivate
>
> +IpBlock/Spi/IncludePrivate
>
> +IpBlock/Gpio/IncludePrivate
>
> +IpBlock/Cnvi/IncludePrivate
>
> +IpBlock/Gbe/IncludePrivate
>
> +IpBlock/PcieRp/IncludePrivate
>
> +IpBlock/Vtd/IncludePrivate
>
> +IpBlock/HostBridge/IncludePrivate
>
> +IpBlock/SerialIo/IncludePrivate
>
> +
>
> +SystemAgent/IncludePrivate
>
> +
>
> +Pch/IncludePrivate
>
> +
>
> +[Includes]
>
> +#
>
> +# TigerLake
>
> +#
>
> +Fru/TglCpu/Include
>
> +Fru/TglPch/Include
>
> +
>
> +# CPU PCIe
>
> +IpBlock/CpuPcieRp/Include
>
> +
>
> +IpBlock/Gpio/Include
>
> +
>
> +
>
> +##
>
> +#
>
> +# This section is for IP ConfigBlock versions control
>
> +#
>
> +# - Memory
>
> +Include/ConfigBlock/Memory/Ver2
>
> +#
>
> +# - Graphics
>
> +Include/ConfigBlock/Graphics/Gen12
>
> +#
>
> +# - CPU PCIe
>
> +Include/ConfigBlock/CpuPcieRp/Gen4
>
> +Include/ConfigBlock/CpuDmi
>
> +
>
> +# - Hybrid Graphics
>
> +Include/ConfigBlock/HybridGraphics
>
> +
>
> +Include
>
> +#
>
> +# SystemAgent
>
> +#
>
> +SystemAgent/Include
>
> +SystemAgent/AcpiTables
>
> +SystemAgent/AcpiTables/SaSsdt
>
> +Include/ConfigBlock/Vtd
>
> +Include/ConfigBlock/PcieRp
>
> +Include/ConfigBlock/Gna
>
> +Include/ConfigBlock/CpuPcieRp/Gen4
>
> +Include/ConfigBlock/CpuPcieRp/Gen3
>
> +Include/ConfigBlock/CpuDmi
>
> +Include/ConfigBlock/HybridGraphics
>
> +Include/ConfigBlock/HostBridge
>
> +#
>
> +# Cpu
>
> +#
>
> +Cpu/Include
>
> +Include/ConfigBlock/Overclocking
>
> +Include/ConfigBlock/VoltageRegulator
>
> +
>
> +#
>
> +# Pch
>
> +#
>
> +Pch/Include
>
> +Include/ConfigBlock/Thermal
>
> +Include/ConfigBlock/P2sb
>
> +Include/ConfigBlock/Ish
>
> +Include/ConfigBlock/Usb
>
> +Include/ConfigBlock/Espi
>
> +Include/ConfigBlock/Fivr
>
> +Include/ConfigBlock/Rtc
>
> +Include/ConfigBlock/Smbus
>
> +Include/ConfigBlock/Pmc
>
> +Include/ConfigBlock/Itss
>
> +Include/ConfigBlock/Scs
>
> +Include/ConfigBlock/Hda
>
> +Include/ConfigBlock/Sata
>
> +Include/ConfigBlock/Rst
>
> +Include/ConfigBlock/Ieh
>
> +Include/ConfigBlock/Me
>
> +Include/ConfigBlock/PchDmi
>
> +Include/ConfigBlock/Gpio
>
> +Include/ConfigBlock/Dci
>
> +Include/ConfigBlock/Cnvi
>
> +Include/ConfigBlock/Gbe
>
> +Include/ConfigBlock/TraceHub
>
> +Include/ConfigBlock/Thc
>
> +Include/ConfigBlock/Wdt
>
> +Include/ConfigBlock/PcieRp/PchPcieRp
>
> +Include/ConfigBlock/PcieRp
>
> +Include/ConfigBlock/Psf
>
> +Include/ConfigBlock/SerialIo
>
> +Include/ConfigBlock/HybridStorage
>
> +Include/ConfigBlock/Spi
>
> +
>
> +
>
> +#
>
> +# - Tcss
>
> +Include/ConfigBlock/Tcss
>
> +[Guids.common.Private]
>
> +#
>
> +# PCH
>
> +#
>
> +gPchDeviceTableHobGuid = { 0xb3e123d0, 0x7a1e, 0x4db4, { 0xaf, 0x66,
> 0xbe, 0xd4, 0x1e, 0x9c, 0x66, 0x38 }}
>
> +gWdtHobGuid = { 0x65675786, 0xacca, 0x4b11, { 0x8a, 0xb7, 0xf8,
> 0x43, 0xaa, 0x2a, 0x8b, 0xea }}
>
> +gPchConfigHobGuid = { 0x524ed3ca, 0xb250, 0x49f5, { 0x94, 0xd9,
> 0xa2, 0xba, 0xff, 0xc7, 0x0e, 0x14 }}
>
> +gGpioLibUnlockHobGuid = { 0xA7892E49, 0x0F9F, 0x4166, { 0xB8, 0xD6,
> 0x8A, 0x9B, 0xD9, 0x8B, 0x17, 0x38 }}
>
> +gSiScheduleResetHobGuid = { 0xEA0597FF, 0x8858, 0x41CA, { 0xBB, 0xC1,
> 0xFE, 0x18, 0xFC, 0xD2, 0x8E, 0x22 }}
>
> +gCnviConfigHobGuid = { 0xa8d6e4d9, 0x94b7, 0x4fc9, { 0x94, 0x3f, 0x7a,
> 0x9c, 0xb2, 0x31, 0x57, 0xce }}
>
> +
>
> +#
>
> +# CPU
>
> +#
>
> +gPeiAcpiCpuDataGuid = { 0x7682bbef, 0xb0b6, 0x4939, { 0xae, 0x66,
> 0x1b, 0x3d, 0xf2, 0xf6, 0xaa, 0xf3 }}
>
> +gCpuStatusCodeDataTypeExceptionHandlerGuid = { 0x3BC2BD12, 0xAD2E,
> 0x11D5, { 0x87, 0xDD, 0x00, 0x06, 0x29, 0x45, 0xC3, 0xB9 }}
>
> +
>
> +#
>
> +# SA
>
> +#
>
> +gSchemaListGuid = { 0x3047C2AC, 0x5E8E, 0x4C55, { 0xA1, 0xCB, 0xEA,
> 0xAD, 0x0A, 0x88, 0x86, 0x1B }}
>
> +gEqPhase3SchemaGuid = { 0x145AC084, 0x340E, 0x4777, { 0xBC, 0x75,
> 0xF8, 0x50, 0x5F, 0xFD, 0x50, 0x9D }}
>
> +gScoreSchemaGuid = { 0x8233A1BB, 0x58D5, 0x4F66, { 0xA1, 0x3F,
> 0x8A, 0xA3, 0xED, 0x6A, 0xF5, 0xA0 }}
>
> +gPortMarginGuid = { 0xD7154D12, 0x03B2, 0x4054, { 0x8C, 0xD2, 0x9F,
> 0x4B, 0x20, 0x90, 0xBE, 0xF7 }}
>
> +gJitterTolerenceGuid = { 0xB52A2E04, 0x45FF, 0x484E, { 0xB5, 0xFE,
> 0xEE, 0x47, 0x8F, 0x5F, 0x6C, 0x9B }}
>
> +gLaneMarginGuid = { 0x7AC0996D, 0xA601, 0x4210, { 0x94, 0x4E, 0x93,
> 0x4E, 0x51, 0x7B, 0x6C, 0x57 }}
>
> +gVocMarginGuid = { 0x3578349A, 0x9E98, 0x4F70, { 0x91, 0xCB, 0xE2,
> 0x5B, 0x98, 0x99, 0xBC, 0x16 }}
>
> +
>
> +[Guids]
>
> +gSmbiosProcessorInfoHobGuid = {0xe6d73d92, 0xff56, 0x4146, {0xaf,
> 0xac, 0x1c, 0x18, 0x81, 0x7d, 0x68, 0x71}}
>
> +gSmbiosCacheInfoHobGuid = {0xd805b74e, 0x1460, 0x4755, {0xbb,
> 0x36, 0x1e, 0x8c, 0x8a, 0xd6, 0x78, 0xd7}}
>
> +
>
> +##
>
> +## IntelFrameworkPkg
>
> +##
>
> +# MsegSmramPei.inf
>
> +gEfiSmmPeiSmramMemoryReserveGuid = {0x6dadf1d1, 0xd4cc, 0x4910,
> {0xbb, 0x6e, 0x82, 0xb1, 0xfd, 0x80, 0xff, 0x3d}}
>
> +##
>
> +## MdeModulePkg
>
> +##
>
> +gEfiMemoryTypeInformationGuid = {0x4c19049f, 0x4137, 0x4dd3, {0x9c,
> 0x10, 0x8b, 0x97, 0xa8, 0x3f, 0xfd, 0xfa}}
>
> +gEfiCapsuleVendorGuid = {0x711c703f, 0xc285, 0x4b10, {0xa3, 0xb0, 0x36,
> 0xec, 0xbd, 0x3c, 0x8b, 0xe2}}
>
> +gEfiConsoleOutDeviceGuid = { 0xd3b36f2c, 0xd551, 0x11d4, { 0x9a, 0x46,
> 0x0, 0x90, 0x27, 0x3f, 0xc1, 0x4d}}
>
> +##
>
> +## Common
>
> +##
>
> +## Include/ConfigBlock/SiConfig.h
>
> +gSiConfigGuid = {0x4ed6d282, 0x22f3, 0x4fe1, {0xa6, 0x61, 0x6, 0x1a, 0x97,
> 0x38, 0x59, 0xd8}}
>
> +##
>
> +gSiPreMemConfigGuid = {0xb94c004c, 0xa0ab, 0x40f0, {0x9b, 0x61, 0x0b,
> 0x25, 0x88, 0xbe, 0xfd, 0xc6}}
>
> +##
>
> +##
>
> +gPciePreMemConfigGuid = {0xd0f9c2a9, 0x7332, 0x4733, {0x8d, 0xb1, 0x98,
> 0x79, 0x27, 0x60, 0xda, 0xe6}}
>
> +##
>
> +gSiPkgTokenSpaceGuid = {0x977c97c1, 0x47e1, 0x4b6b, {0x96, 0x69, 0x43,
> 0x66, 0x99, 0xcb, 0xe4, 0x5b}}
>
> +## Include/SiConfigHob.h
>
> +gSiConfigHobGuid = {0xb3903068, 0x7482, 0x4424, {0xba, 0x4b, 0x40, 0x5f,
> 0x8f, 0xd7, 0x65, 0x4e}}
>
> +gBootMediaHobGuid = {0x8c7340ea, 0xde8b, 0x4e06, {0xa4, 0x78, 0xec,
> 0x8b, 0x62, 0xd7, 0xa, 0x8b}}
>
> +gEfiPramConfGuid = { 0xecb54cd9, 0xe5ae, 0x4fdc, { 0xa9, 0x71, 0xe8, 0x77,
> 0x75, 0x60, 0x68, 0xf7}}
>
> +##
>
> +##
>
> +## IPU's GUIDs
>
> +##
>
> +gIpuDataHobGuid = {0x61dd66, 0x212b, 0x4dae, {0x9b, 0xc0, 0x30, 0xe0,
> 0x2e, 0x3f, 0x40, 0xfd}}
>
> +gIpuConfigHobGuid = {0x446268e5, 0x8c30, 0x4e0a, {0x9b, 0x28, 0xa3, 0xe7,
> 0xf0, 0x4, 0x31, 0xd0}}
>
> +
>
> +## Include/FspErrorInfo.h
>
> +gFspErrorInfoHobGuid = {0x611e6a88, 0xadb7, 0x4301, {0x93, 0xff, 0xe4,
> 0x73, 0x04, 0xb4, 0x3d, 0xa6}}
>
> +gStatusCodeDataTypeFspErrorGuid = {0x611e6a88, 0xadb7, 0x4301, {0x93,
> 0xff, 0xe4, 0x73, 0x04, 0xb4, 0x3d, 0xa6}}
>
> +
>
> +##
>
> +##
>
> +## SystemAgent
>
> +##
>
> +gSaOverclockingPreMemConfigGuid = { 0x09ecc29d, 0xdbbe, 0x49fb, {
> 0xa6, 0x49, 0x4b, 0xf6, 0x40, 0xe2, 0xeb, 0xd6}}
>
> +gSaAcpiTableStorageGuid = {0x3c0ed5e2, 0x91ea, 0x4b94, { 0x82, 0xd,
> 0x9d, 0xaf, 0x9a, 0x3b, 0xb4, 0xa2}}
>
> +gSaDataHobGuid = {0xe07d0bda, 0xbf90, 0x46a9, { 0xb0, 0x0e, 0xb2, 0xc4,
> 0x4a, 0x0e, 0xd6, 0xd0}}
>
> +gPsmiDataHobGuid = {0xa9652bd, 0x6acd, 0x47e5, { 0x80, 0x3a, 0x9, 0x53,
> 0x7b, 0xd2, 0xa8, 0x48 }}
>
> +gSaConfigHobGuid = {0x762fa2e6, 0xea3b, 0x41c8, { 0x8c, 0x52, 0x63, 0x76,
> 0x6d, 0x70, 0x39, 0xe0}}
>
> +gCpuPcieHobGuid = {0x440ab2e5, 0xa3ea, 0x466f, { 0x84, 0x96, 0xdf, 0xb1,
> 0x3b, 0x75, 0x29, 0x95}}
>
> +gSaPegHobGuid = {0x5807c388, 0xfa06, 0x4683, { 0xab, 0xd3, 0x1b, 0x31,
> 0xbb, 0x81, 0x2d, 0x23}}
>
> +gHgAcpiTableStorageGuid = {0x8de8964f, 0x2939, 0x4b49, { 0xa3, 0x48,
> 0xf6, 0xb2, 0xb2, 0xde, 0x4a, 0x42}}
>
> +gSaSsdtAcpiTableStorageGuid = {0xca89914d, 0x2317, 0x452e, { 0xb2, 0x45,
> 0x36, 0xc6, 0xfb, 0x77, 0xa9, 0xc6}}
>
> +gSegSsdtAcpiTableStorageGuid = {0x10c3800d, 0xe225, 0x480e, { 0x85,
> 0xda, 0xbe, 0xed, 0xdb, 0x88, 0xe1, 0xc6}}
>
> +gHgAcpiTablePchStorageGuid = {0xe3164526, 0x690a, 0x4e0d, { 0xb0, 0x28,
> 0xae, 0xa1, 0x6f, 0xe2, 0xbc, 0xf3}}
>
> +gSaMiscPeiPreMemConfigGuid = {0x4a525577, 0x3469, 0x4f11, { 0x99, 0xcf,
> 0xfb, 0xcd, 0x5e, 0xf1, 0x84, 0xe4}}
>
> +gSaMiscPeiConfigGuid = {0x1def8e6, 0xe998, 0x4e27, { 0x89, 0x98, 0x9c,
> 0xfa, 0xb2, 0x92, 0xbc, 0x50}}
>
> +gCpuPciePeiPreMemConfigGuid = { 0x81baf3c9, 0xf295, 0x4572, { 0x8b,
> 0x21, 0x79, 0x3f, 0xa3, 0x1b, 0xa5, 0xdb}}
>
> +gCpuDmiPreMemConfigGuid = { 0x30d12ad5, 0xa3c6, 0x49c7, { 0xa2, 0xfd,
> 0x35, 0x5c, 0xcb, 0x61, 0xcb, 0xcf}}
>
> +gVmdPeiConfigGuid = { 0x79b52c74, 0xb9ba, 0x4f36, {0xa2, 0x40, 0xf2, 0x41,
> 0x0d, 0x20, 0x84, 0x8a}}
>
> +gVmdInfoHobGuid = { 0xccd0306e, 0x7fa1, 0x4df5, {0x99, 0x99, 0xc1,
> 0xf8, 0x9a, 0x1d, 0x1b, 0xa9}}
>
> +gEfiVmdFeatureVariableGuid = { 0x61a14fe8, 0x4dab, 0x4a19, {0xb1, 0xe3,
> 0x97, 0xfb, 0x23, 0xd0, 0x92, 0x12}}
>
> +gPramPreMemConfigGuid = { 0xcf0b9b31, 0xa1a6, 0x46d9, { 0x8d, 0x14,
> 0xe3, 0xac, 0x69, 0x0f, 0x52, 0x3a}}
>
> +gHybridGraphicsConfigGuid = { 0xc7956998, 0xc065, 0x46c4, { 0x8e, 0x2f,
> 0x58, 0x2b, 0x67, 0xeb, 0xbe, 0x2f}}
>
> +gHybridGraphicsInfoHobGuid = { 0x46cbed07, 0x717a, 0x4a75, { 0x85, 0xb3,
> 0xf4, 0xb6, 0xc4, 0xe2, 0x3a, 0x75}}
>
> +gMemoryConfigGuid = { 0x26cf084c, 0xc9db, 0x41bb, { 0x92, 0xc6, 0xd1,
> 0x97, 0xb8, 0xa1, 0xe4, 0xbf}}
>
> +gMemoryConfigNoCrcGuid = { 0xc56c73d0, 0x1cdb, 0x4c0c, { 0xa9, 0x57,
> 0xea, 0x62, 0xa9, 0xe6, 0xf5, 0x0c}}
>
> +gGnaConfigGuid = { 0x53e0ef18, 0xb8a8, 0x4795, { 0xa6, 0x6d, 0xe4, 0x77,
> 0x2c, 0xc3, 0xae, 0x82}}
>
> +gVtdDxeConfigGuid = {0xcbbf1996, 0x4a4c, 0x4dd9, {0xab, 0xbe, 0x83,
> 0x89, 0x73, 0xd, 0x48, 0xb0}}
>
> +gPcieDxeConfigGuid = {0x1ed2d6f1, 0xa9d2, 0x476e, {0x8e, 0x74, 0xad,
> 0xd9, 0x5b, 0x5, 0x10, 0x82}}
>
> +gMemoryDxeConfigGuid = {0xa5c7dda8, 0x686b, 0x404f, {0x86, 0x40, 0xf8,
> 0x2, 0xd, 0x84, 0x4c, 0x94}}
>
> +gFspReservedMemoryResourceHobTsegGuid = { 0xd038747c, 0xd00c,
> 0x4980, { 0xb3, 0x19, 0x49, 0x01, 0x99, 0xa4, 0x7d, 0x55}}
>
> +gCpuPcieRpPrememConfigGuid = { 0x41aef892, 0xc800, 0x4ac0, {0xa9, 0x30,
> 0x84, 0xac, 0x47, 0xca, 0xca, 0x7e}}
>
> +gCpuPcieRpConfigGuid = { 0x9749a5fb, 0x9130, 0x44f0, {0x8f, 0x61, 0xdb,
> 0xff, 0x8e, 0xf2, 0xca, 0xc7}}
>
> +## Include/Guid/AcpiS3Context.h
>
> +gEfiAcpiVariableGuid = {0xaf9ffd67, 0xec10, 0x488a, {0x9d, 0xfc, 0x6c, 0xbf,
> 0x5e, 0xe2, 0x2c, 0x2e}}
>
> +## IntelFsp2Pkg/IntelFsp2Pkg.dec gSiMemoryS3DataGuid is the same as
> gFspNonVolatileStorageHobGuid
>
> +gSiMemoryS3DataGuid = { 0x721acf02, 0x4d77, 0x4c2a, { 0xb3, 0xdc,
> 0x27, 0x0b, 0x7b, 0xa9, 0xe4, 0xb0 } }
>
> +gSiMemoryInfoDataGuid = { 0x9b2071d4, 0xb054, 0x4e0c, { 0x8d, 0x09,
> 0x11, 0xcf, 0x8b, 0x9f, 0x03, 0x23 } }
>
> +gSiMemoryPlatformDataGuid = { 0x6210d62f, 0x418d, 0x4999, { 0xa2, 0x45,
> 0x22, 0x10, 0x0a, 0x5d, 0xea, 0x44 } }
>
> +## Include/MrcRmtData.h
>
> +gEfiMemorySchemaGuid = { 0xCE3F6794, 0x4883, 0x492C, { 0x8D, 0xBA,
> 0x2F, 0xC0, 0x98, 0x44, 0x77, 0x10}}
>
> +gMrcSchemaListHobGuid = { 0x3047C2AC, 0x5E8E, 0x4C55, { 0xA1, 0xCB,
> 0xEA, 0xAD, 0x0A, 0x88, 0x86, 0x1B}}
>
> +gRmtResultMetadataGuid = { 0x02CB1552, 0xD659, 0x4232, { 0xB5, 0x1F,
> 0xCA, 0xB1, 0xE1, 0x1F, 0xCA, 0x87}}
>
> +gRmtResultColumnsGuid = { 0x0E60A1EB, 0x331F, 0x42A1, { 0x9D, 0xE7,
> 0x45, 0x3E, 0x84, 0x76, 0x11, 0x54}}
>
> +gMargin2DResultMetadataGuid = { 0x48265582, 0x8E49, 0x4AC7, { 0xAA,
> 0x06, 0xE1, 0xB9, 0xA7, 0x4C, 0x97, 0x16}}
>
> +gMargin2DResultColumnsGuid = { 0x91A449EC, 0x8A4A, 0x4736, { 0xAD,
> 0x71, 0xA3, 0xF6, 0xF6, 0xD7, 0x52, 0xD9}}
>
> +gSaFspErrorTypePeiGopInit = { 0x8106a5cc, 0x30ba, 0x41cf, { 0xa1, 0x78,
> 0x63, 0x38, 0x91, 0x11, 0xae, 0xb2}}
>
> +gSaFspErrorTypePeiGopGetMode = { 0x348cc7fe, 0x1e9a, 0x4c7a, { 0x86,
> 0x28, 0xae, 0x48, 0x5b, 0x42, 0x10, 0xf0}}
>
> +gSaFspErrorTypeCallerId = { 0x98230916, 0xe632, 0x49ff, { 0x81, 0x81, 0x55,
> 0xce, 0xe5, 0x10, 0x36, 0x89}}
>
> +gMrcFspErrorTypeCallerId = { 0x5a47c211, 0x642f, 0x4f92, { 0x9c, 0xb3, 0x7f,
> 0xeb, 0x93, 0xda, 0xdd, 0xba}}
>
> +gMrcFspErrorTypeMemoryInit = { 0x5de1c071, 0x2c9c, 0x4a53, { 0x80, 0x21,
> 0x4e, 0x80, 0xd2, 0x5d, 0x44, 0xa8}}
>
> +gSaPciePeiConfigGuid = { 0xdaa929a9, 0x5ec9, 0x486a, { 0xb0, 0xf7, 0x82,
> 0x3a, 0x55, 0xc7, 0xb5, 0xb3}}
>
> +gSaPciePeiPreMemConfigGuid = { 0xfc5e01a3, 0x69f6, 0x4e35, { 0x9f, 0xcf,
> 0x6, 0x68, 0x7b, 0xab, 0x31, 0xd7}}
>
> +
>
> +
>
> +#
>
> +# Host Bridge
>
> +#
>
> +gHostBridgePeiPreMemConfigGuid = {0xbdef6805, 0x2080, 0x44ad, { 0x93,
> 0x2e, 0x00, 0x04, 0xf5, 0x2c, 0xb7, 0xa1}}
>
> +gHostBridgePeiConfigGuid = {0x3b6d998e, 0x8b6e, 0x4f53, { 0xbe, 0x41,
> 0x7, 0x41, 0x95, 0x53, 0x8a, 0xaf}}
>
> +gHostBridgeDataHobGuid = {0x3b682d57, 0xd402, 0x40a6, { 0xb1, 0x34,
> 0xa0, 0xc4, 0xf6, 0x31, 0x1d, 0x9}}
>
> +
>
> +#
>
> +# Graphics
>
> +#
>
> +gGraphicsPeiPreMemConfigGuid = {0x0319c56b, 0xc43a, 0x42f1, { 0x80,
> 0xbe, 0xca, 0x5b, 0xd1, 0xd5, 0xc9, 0x28}}
>
> +gGraphicsPeiConfigGuid = {0x04249ac0, 0x0088, 0x439f, { 0xa7, 0x4e, 0xa7,
> 0x04, 0x2a, 0x06, 0x2f, 0x5d}}
>
> +gGraphicsDxeConfigGuid = {0x34d93161, 0xf78e, 0x4915, {0xad, 0xc4, 0xdb,
> 0x67, 0x16, 0x42, 0x39, 0x24}}
>
> +gGraphicsAcpiTableStorageGuid = {0xce9caa0e, 0x8248, 0x442c, { 0x9e,
> 0x57, 0x50, 0xf2, 0x12, 0xe2, 0xba, 0xed}}
>
> +## IpBlock/Graphics/IncludePrivate/GraphicsDataHob.h
>
> +gGraphicsDataHobGuid = { 0x48e6e20a, 0x9110, 0x4332, { 0x8c, 0x9f, 0x5f,
> 0x7c, 0xae, 0x76, 0xfc, 0xf3}}
>
> +
>
> +#
>
> +# IPU
>
> +#
>
> +gIpuPreMemConfigGuid = { 0x830a222b, 0x3ff5, 0x432e, { 0x9d, 0xd5,
> 0x4e, 0xe3, 0xfc, 0xa2, 0xaa, 0xa2}}
>
> +gIpuAcpiTableStorageGuid = {0x9b25dba6, 0x45b3, 0x4190, { 0x99, 0x8d,
> 0xaf, 0x31, 0xdc, 0x21, 0x78, 0x21}}
>
> +
>
> +## Include/SsaCommonConfig.h
>
> +gSsaPostcodeHookGuid = {0xADF0A27B, 0x61A6, 0x4F18, {0x9E, 0xAC, 0x46,
> 0x87, 0xE7, 0x9E, 0x6F, 0xBB}}
>
> +gSsaBiosVariablesGuid = {0x43eeffe8, 0xa978, 0x41dc, {0x9d, 0xb6, 0x54,
> 0xc4, 0x27, 0xf2, 0x7e, 0x2a}}
>
> +gSsaBiosResultsGuid = {0x8f4e928, 0xf5f, 0x46d4, {0x84, 0x10, 0x47, 0x9f,
> 0xda, 0x27, 0x9d, 0xb6}}
>
> +gHobUsageDataGuid = {0xc764a821, 0xec41, 0x450d, { 0x9c, 0x99, 0x27,
> 0x20, 0xfc, 0x7c, 0xe1, 0xf6 }}
>
> +##
>
> +## TBT
>
> +##
>
> +gPeiITbtConfigGuid = {0xd7e7e1e6, 0xcbec, 0x4f5f, {0xae, 0xd3, 0xfd,
> 0xc0, 0xa8, 0xb0, 0x7e, 0x25}}
>
> +gDxeITbtConfigGuid = {0x196bf9e3, 0x20d7, 0x4b7b, {0x89, 0xf9, 0x31,
> 0xc2, 0x72, 0x08, 0xc9, 0xb9}}
>
> +gITbtInfoHobGuid = {0x74a81eaa, 0x033c, 0x4783, {0xbe, 0x2b, 0x84,
> 0x85, 0x74, 0xa6, 0x97, 0xb7}}
>
> +
>
> +##
>
> +## TCSS
>
> +##
>
> +gTcssHobGuid = { 0x455702ce, 0x4adb, 0x45d9, { 0x8b, 0x27, 0xf7, 0xb0,
> 0xd9, 0x79, 0x8a, 0xe0}}
>
> +gTcssSsdtAcpiTableStorageGuid = { 0xbd53572c, 0x6486, 0x45e2, { 0x90,
> 0xe, 0xb9, 0x8a, 0xc1, 0xa8, 0x25, 0x45}}
>
> +gTcssPeiConfigGuid = { 0xfb631590, 0x79c9, 0x4f0d, { 0xa9, 0x96, 0xee,
> 0xe2, 0x98, 0x66, 0xfa, 0xfd}}
>
> +gTcssPeiPreMemConfigGuid = { 0x514ed829, 0xb2bb, 0x46be, { 0xa9, 0x78,
> 0x6d, 0xc, 0x91, 0xc1, 0xeb, 0xe4}}
>
> +gTcssSsidHobGuid = { 0x8903d47a, 0x8f82, 0x4063, { 0xa8, 0x40, 0x31, 0x68,
> 0x9c, 0x9e, 0x78, 0x20}}
>
> +##
>
> +## Telemetry
>
> +##
>
> +gTelemetryPeiConfigGuid = { 0x8ebf9fee, 0x7496, 0x42b4, { 0xa6, 0xf6,
> 0xcf, 0x2b, 0x33, 0x99, 0x30, 0xd6}}
>
> +gTelemetryPeiPreMemConfigGuid = { 0x422de269, 0xb2ef, 0x4829, { 0x93,
> 0x36, 0x0b, 0xe4, 0x98, 0xb5, 0x53, 0xb2}}
>
> +
>
> +##
>
> +## VTD
>
> +##
>
> +gVtdDataHobGuid = {0x1d60dce8, 0x503a, 0x44a8, { 0xb3, 0x2d, 0x56, 0xb3,
> 0x88, 0xf3, 0x4c, 0x55}}
>
> +gVtdConfigGuid = {0x03e5cf63, 0xbebb, 0x4041, { 0xb7, 0xe7, 0xbf, 0x54,
> 0x61, 0x20, 0xf1, 0xc5}}
>
> +
>
> +#
>
> +# TRACEHUB
>
> +#
>
> +gCpuTraceHubPreMemConfigGuid = { 0xf2e17477, 0x93f3, 0x430d, { 0x9e,
> 0x08, 0x3c, 0xcc, 0x6e, 0x2f, 0x6c, 0x4b}}
>
> +gTraceHubDataHobGuid = { 0xf1187e54, 0x995f, 0x49d9, { 0xac, 0xee,
> 0xc5, 0x34, 0xf4, 0x5a, 0x18, 0xc7}}
>
> +
>
> +##
>
> +## Cpu
>
> +##
>
> +gSmramCpuDataHeaderGuid = {0x5848fd2d, 0xd6af, 0x474b, {0x82, 0x75,
> 0x95, 0xdd, 0xe7, 0x0a, 0xe8, 0x23}}
>
> +gCpuAcpiTableStorageGuid = {0xc38fb0e2, 0x0c43, 0x49c9, {0xb5, 0x44,
> 0x9b, 0x17, 0xaa, 0x4d, 0xcb, 0xa3}}
>
> +gTxtInfoHobGuid = {0x2986883f, 0x88e0, 0x48d0, {0x4b, 0x82, 0x20, 0xc2,
> 0x69, 0x48, 0xdd, 0xac}}
>
> +gHtBistHobGuid = {0xbe644001, 0xe7d4, 0x48b1, {0xb0, 0x96, 0x8b, 0xa0,
> 0x47, 0xbc, 0x7a, 0xe7}}
>
> +gProcessorProducerGuid = {0x1bf06aea, 0x5bec, 0x4a8d, {0x95, 0x76, 0x74,
> 0x9b, 0x09, 0x56, 0x2d, 0x30}}
>
> +gCpuInitDataHobGuid = {0x266e31cc, 0x13c5, 0x4807, {0xb9, 0xdc, 0x39,
> 0xa6, 0xba, 0x88, 0xff, 0x1a}}
>
> +gBiosGuardHobGuid = {0x66f0c42d, 0x0d0e, 0x4c23, {0x93, 0xc0, 0x2d,
> 0x52, 0x95, 0xdc, 0x5e, 0x21}}
>
> +gCpuSecurityPreMemConfigGuid = {0xfd5c346, 0x8260, 0x4067, {0x94, 0x69,
> 0xcf, 0x91, 0x68, 0xa3, 0x42, 0x90}}
>
> +gCpuConfigLibPreMemConfigGuid = {0xfc1c0ec2, 0xc6b4, 0x4f05, {0xbb,
> 0x85, 0xc8, 0x0, 0x8d, 0x5b, 0x4a, 0xb7}}
>
> +gCpuTxtPreMemConfigGuid = {0x20b4db03, 0xd160, 0x4f83, {0xa4, 0x1,
> 0x9a, 0x8a, 0xa8, 0x88, 0x68, 0x14}}
>
> +gCpuTestConfigGuid = {0xd4dba957, 0xd9c, 0x4af2, {0x9d, 0x40, 0x35, 0xa8,
> 0x44, 0xe4, 0x93, 0xad}}
>
> +gBiosGuardConfigGuid = {0x762f9ddb, 0x1c89, 0x4612, {0x84, 0x6b, 0xee,
> 0xdc, 0x8f, 0x62, 0x25, 0x45}}
>
> +gCpuConfigGuid = {0x48c3aac9, 0xd66c, 0x42e4, {0x9b, 0x1d, 0x39, 0x4, 0x5f,
> 0x46, 0x53, 0x41}}
>
> +gCpuPidTestConfigGuid = {0x2511095f, 0xd49e, 0x4537, {0xa6, 0x60, 0x88,
> 0x71, 0x31, 0xd1, 0x53, 0xda}}
>
> +gCpuPowerMgmtBasicConfigGuid = {0xa021e31d, 0x7c14, 0x47da, {0xb5,
> 0xec, 0xca, 0xbb, 0x4d, 0x76, 0xed, 0xc8}}
>
> +gCpuPowerMgmtCustomConfigGuid = {0x562fa1c8, 0x55ee, 0x4e2f, {0x91,
> 0xca, 0x8d, 0x84, 0x50, 0x3, 0x2f, 0xe}}
>
> +gCpuPowerMgmtPsysConfigGuid = {0x4e7f850, 0x19b5, 0x47ba, {0x9d,
> 0x28, 0xb1, 0xe7, 0x5e, 0x1f, 0x48, 0x53}}
>
> +gCpuPowerMgmtTestConfigGuid = {0x5161ed3d, 0x90bf, 0x436f, {0xb8,
> 0x33, 0xd7, 0x17, 0x89, 0xb3, 0x48, 0xc1}}
>
> +gCpuPowerMgmtVrConfigGuid = {0x254766c9, 0x929d, 0x4eac, {0x9e, 0xec,
> 0xdf, 0xa2, 0x2, 0x44, 0xb5, 0xea}}
>
> +gTxtPrivateBaseHobGuid = {0x651EBDB4, 0x4E1D, 0x422A, {0x82, 0xFB, 0x1E,
> 0xDA, 0x66, 0x71, 0x6C, 0x0B}}
>
> +gTxtAcmInfoTableGuid = {0x7FC03AAA, 0x46A7, 0x18DB, {0x2E, 0xAC, 0x69,
> 0x8F, 0x8D, 0x41, 0x7F, 0x5A}}
>
> +gOverclockingPreMemConfigGuid = {0xad151bbc, 0xd5a0, 0x481e, {0x9d,
> 0x19, 0xf6, 0x7b, 0x79, 0xe9, 0x8f, 0x68}}
>
> +gCpuDataHobGuid = {0x1eec629f, 0xf3cf, 0x4b02, { 0xa9, 0xa5, 0x27, 0xa2,
> 0x33, 0x20, 0xbe, 0x5d}}
>
> +
>
> +##
>
> +## Me
>
> +##
>
> +gMePlatformReadyToBootGuid = {0x03fdf171, 0x1d67, 0x4ace, {0xa9, 0x04,
> 0x3e, 0x36, 0xd3, 0x38, 0xfa, 0x74}}
>
> +gMeSsdtAcpiTableStorageGuid = {0x9a8f82d5, 0x39b1, 0x48da, {0x92, 0xdc,
> 0xa2, 0x2d, 0xa8, 0x83, 0x4d, 0xf6}}
>
> +gMeDataHobGuid = {0x1e94f097, 0x5acd, 0x4089, {0xb2, 0xe3, 0xb9, 0xa5,
> 0xc8, 0x79, 0xa7, 0x0c}}
>
> +gMeEDebugHobGuid = {0x5f672ec1, 0xa8f6, 0x47d3, {0x9c, 0xd0, 0x92,
> 0xe9, 0xe9, 0xe0, 0xb3, 0x84}}
>
> +gPciImrHobGuid = {0x49b1eac3, 0x0cd6, 0x451e, {0x96, 0x30, 0x92, 0x4b,
> 0xc2, 0x69, 0x35, 0x86}}
>
> +gTpm2AcpiTableStorageGuid = {0x7d279373, 0xeecc, 0x4d4f, {0xae, 0x2f,
> 0xce, 0xc4, 0xb7, 0x06, 0xb0, 0x6a}}
>
> +gMeBiosPayloadHobGuid = {0x992c52c8, 0xbc01, 0x4ecd, {0x20, 0xbf, 0xf9,
> 0x57, 0x16, 0x0e, 0x9e, 0xf7}}
>
> +gEfiTouchPanelGuid = {0x91b1d27b, 0xe126, 0x48d1, {0x82, 0x34, 0xd2,
> 0x8b, 0x81, 0xc8, 0x83, 0x62}}
>
> +gMeFwHobGuid = {0x52885e62, 0x4c4d, 0x9546, {0x2d, 0xba, 0x2a, 0x84,
> 0x89, 0xee, 0xa8, 0xa3 }}
>
> +gMePeiPreMemConfigGuid = {0x67ed113b, 0xd4ab, 0x43f5, {0x9c, 0x3c,
> 0x35, 0x44, 0x15, 0xaa, 0x47, 0x5c}}
>
> +gMePeiConfigGuid = {0x9bad5628, 0x657b, 0x48e3, {0xb1, 0x11, 0xc3, 0xb9,
> 0xeb, 0xea, 0xee, 0x17}}
>
> +gMeDxeConfigGuid = {0xad08bacc, 0x4906, 0x4d9b, {0xbe, 0xd1, 0x81,
> 0xa5, 0x2c, 0x13, 0xdb, 0xf8}}
>
> +gIvmProtocolGuid = {0x3C4852D6, 0xD47B, 0x4F46, {0xB0, 0x5E, 0xB5, 0xED,
> 0xC1, 0xAA, 0x44, 0x0E}}
>
> +gSdmProtocolGuid = {0xDBA4D603, 0xD7ED, 0x4931, {0x88, 0x23, 0x17,
> 0xAD, 0x58, 0x57, 0x05, 0xD5}}
>
> +gRtmProtocolGuid = {0x5565A099, 0x7FE2, 0x45C1, {0xA2, 0x2B, 0xD7, 0xE9,
> 0xDF, 0xEA, 0x9A, 0x2E}}
>
> +gSvmProtocolGuid = {0xF47ACC04, 0xD94B, 0x49CA, {0x87, 0xA6, 0x7F,
> 0x7D, 0xC0, 0x3F, 0xBA, 0xF3}}
>
> +gMeEopDoneHobGuid = {0x247323af, 0xc8f1, 0x4b8c, {0x90, 0x87, 0xaa,
> 0x4b, 0xa7, 0xb7, 0x6d, 0x6a}}
>
> +gMePreMemPolicyHobGuid = {0xe6de74a5, 0x21b, 0x4f78, {0xa3, 0xcd,
> 0x34, 0xd6, 0x7e, 0xe4, 0x82, 0xbf}}
>
> +gMePolicyHobGuid = {0x0341cf17, 0xbc8f, 0x4a20, {0xac, 0x28, 0x6c, 0x3c,
> 0x32, 0x4c, 0xd4, 0x17}}
>
> +gMeFspErrorTypeEop = {0x948585c4, 0x76a4, 0x45bb, {0xbe, 0x6c, 0x39,
> 0x61, 0xc3, 0xab, 0xde, 0x15}}
>
> +gMeFspErrorTypeCallerId = {0x1f4dc7e9, 0x26ca, 0x4336, { 0x8c, 0xe3, 0x39,
> 0x31, 0x3, 0xb5, 0xf3, 0xd7}}
>
> +gMeConfigSpaceGuid = {0xcb405fd3, 0x4404, 0x4ccd, {0x85, 0x18, 0x0d,
> 0x03, 0x07, 0x48, 0xd0, 0xa6}}
>
> +gMeDidSentHobGuid = {0x4c3d3af1, 0x1720, 0x4c3f, {0xab, 0x7c, 0x36, 0x50,
> 0xbb, 0x5b, 0x85, 0x7e}}
>
> +gMeDisabledEventHobGuid = {0x1500b6a7, 0xb82f, 0x456b, {0xba, 0x2b,
> 0x4, 0x72, 0x41, 0x6, 0xf, 0x7}}
>
> +gMeSavedPmconHobGuid = {0xb8baee93, 0xea15, 0x4ddc, {0x90, 0xb8,
> 0x44, 0x12, 0xd2, 0xea, 0xcf, 0x4f}}
>
> +
>
> +##
>
> +## Amt
>
> +##
>
> +gAmtForcePushPetPolicyGuid = {0xacc8e1e4, 0x9f9f, 0x4e40, {0xa5, 0x7e,
> 0xf9, 0x9e, 0x52, 0xf3, 0x4c, 0xa5}}
>
> +gAmtForcePushPetVariableGuid = {0xd7ac94af, 0xa498, 0x45ec, {0xbf,
> 0xa2, 0xa5, 0x6e, 0x95, 0x34, 0x61, 0x8b}}
>
> +gMeBiosExtensionSetupGuid = {0xaf013532, 0xc828, 0x4fbd, {0x20, 0xae,
> 0xfe, 0xe6, 0xaf, 0xbe, 0xdd, 0x4e}}
>
> +gAmtPetQueueHobGuid = {0xca0801d3, 0xafb1, 0x4dec, {0x9b, 0x65, 0x93,
> 0x65, 0xec, 0xc7, 0x93, 0x6b}}
>
> +gAmtForcePushPetHobGuid = {0x4efa0db6, 0x26dc, 0x4bb1, {0xa7, 0x6f,
> 0x14, 0xbc, 0x63, 0x0c, 0x7b, 0x3c}}
>
> +gAmtPeiConfigGuid = {0x7254546a, 0xace3, 0x4a32, {0x9a, 0xc2, 0xf0, 0xcc,
> 0x28, 0x4e, 0x1e, 0x4d}}
>
> +gAmtDxeConfigGuid = {0x3f12ab6b, 0xb04d, 0x4824, {0xbf, 0xb6, 0x3e,
> 0xe7, 0x5d, 0x02, 0x0b, 0x84}}
>
> +gAmtPolicyHobGuid = {0x703eb2cd, 0x5ca8, 0x4233, {0x9d, 0xa3, 0x0d, 0x2d,
> 0x57, 0xe6, 0x73, 0x34}}
>
> +gAmtMebxDataGuid = { 0x912e1538, 0x371d, 0x4ea6, { 0xa8, 0x41, 0xd7,
> 0x6a, 0x8, 0x93, 0x3a, 0x70}}
>
> +
>
> +##
>
> +## PCH
>
> +##
>
> +gEfiSmbusArpMapGuid = {0x707be83e, 0x0bf6, 0x40a5, {0xbe, 0x64, 0x34,
> 0xc0, 0x3a, 0xa0, 0xb8, 0xe2}}
>
> +gIrmtAcpiTableStorageGuid = {0x6684d675, 0xee06, 0x49b2, {0x87, 0x6f,
> 0x79, 0xc5, 0x8f, 0xdd, 0xa5, 0xb7}}
>
> +gPchGlobalResetGuid = { 0x9db31b4c, 0xf5ef, 0x48bb, { 0x94, 0x2b, 0x18,
> 0x1f, 0x7e, 0x3a, 0x3e, 0x40 }}
>
> +gI2c0MasterGuid = {0xa121a5db, 0xb0cb, 0x46ec, {0xa0, 0xcb, 0x27, 0xf8,
> 0xda, 0x72, 0xd4, 0x0e}}
>
> +gI2c1MasterGuid = {0x55e3d0f9, 0xc954, 0x422d, {0x9c, 0x4c, 0xcc, 0x46,
> 0x12, 0x7c, 0x5b, 0xa8}}
>
> +gI2c2MasterGuid = {0x9289aa40, 0xdf32, 0x474e, {0xb0, 0x3a, 0xc7, 0x7f,
> 0x76, 0xd3, 0x45, 0x21}}
>
> +gI2c3MasterGuid = {0xd8b2c17f, 0x4117, 0x4166, {0x90, 0x17, 0x01, 0x68,
> 0xb4, 0x81, 0xac, 0x18}}
>
> +gI2c4MasterGuid = {0x513d943d, 0x15d9, 0x4bd0, {0xb1, 0x41, 0x14, 0x50,
> 0x2b, 0xbf, 0xa9, 0xf2}}
>
> +gI2c5MasterGuid = {0x50df382a, 0xb6bf, 0x4435, {0xae, 0xe6, 0x21, 0xf4,
> 0x85, 0x7c, 0xa8, 0xb4}}
>
> +gChipsetInitHobGuid = {0xc1392859, 0x1f75, 0x446e, {0xb3, 0xf5, 0x83,
> 0x35, 0xfc, 0xc8, 0xd1, 0xc4}}
>
> +
>
> +gPchGeneralPreMemConfigGuid = {0xC65F62FA, 0x52B9, 0x4837, {0x86,
> 0xEB, 0x1A, 0xFB, 0xD4, 0xAD, 0xBB, 0x3E}}
>
> +gDciPreMemConfigGuid = {0xAB4AF366, 0x2250, 0x40C3, {0x92, 0xDB,
> 0x36, 0x61, 0xC6, 0x71, 0x3C, 0x5A}}
>
> +gWatchDogPreMemConfigGuid = {0xFBCE08CC, 0x60F2, 0x4BDF, {0xB7,
> 0x88, 0x09, 0xBB, 0x81, 0x65, 0x52, 0x2B}}
>
> +gPchTraceHubPreMemConfigGuid = {0x8456c11, 0xdb85, 0x4914, {0x8d,
> 0x1a, 0xe5, 0xac, 0x64, 0x37, 0xe8, 0x96}}
>
> +gPcieRpPreMemConfigGuid = {0x8377AB38, 0xF8B0, 0x476A, { 0x9C, 0xA1,
> 0x68, 0xEA, 0x78, 0x57, 0xD8, 0x2A}}
>
> +gSmbusPreMemConfigGuid = {0x77A6E62C, 0x716B, 0x4386, {0x9E, 0x9C,
> 0x23, 0xA0, 0x2E, 0x13, 0x7B, 0x3A}}
>
> +gLpcPreMemConfigGuid = {0xA6E6032F, 0x1E58, 0x407E, {0x9A, 0xB8, 0xC6,
> 0x30, 0xC6, 0xC4, 0x11, 0x8E}}
>
> +gHsioPciePreMemConfigGuid = {0xE8FB0C12, 0x0DA1, 0x4A20, {0xB3, 0x36,
> 0xFB, 0x75, 0x93, 0x8C, 0xE0, 0x14}}
>
> +gHsioSataPreMemConfigGuid = {0x732260D0, 0xA5C1, 0x4119, {0xAA,
> 0x0C, 0x93, 0xDC, 0xAC, 0x67, 0x0A, 0x31}}
>
> +
>
> +gPchGeneralConfigGuid = {0x6ED94C8C, 0x25F7, 0x4686, {0xB2, 0x46, 0xCA,
> 0x4D, 0xE2, 0x95, 0x4B, 0x5D}}
>
> +gPchPcieConfigGuid = {0x0A53B507, 0x988B, 0x475C, {0xBF, 0x76, 0x33,
> 0xDE, 0x10, 0x6D, 0x94, 0x84}}
>
> +gPchPcieRpDxeConfigGuid = {0x475530EA, 0xBD72, 0x416F, {0x98,
> 0x9F,0x48, 0x70, 0x5F, 0x14, 0x4E, 0xD9}}
>
> +gSataConfigGuid = {0xF5F87B4F, 0xCC3C, 0x408D, {0x89, 0xE3, 0x61, 0xC5,
> 0x9C, 0x54, 0x07, 0xC4}}
>
> +gRstConfigGuid = {0x43B6F112, 0x3851, 0x4DDC, {0x81, 0xB9, 0xE4, 0x5A,
> 0x2B, 0xE, 0xB3, 0x25}}
>
> +gIoApicConfigGuid = {0x2873D0F1, 0x00F6, 0x40AB, {0xAC, 0x36, 0x9A,
> 0x68, 0xBA, 0x87, 0x3E, 0x6C}}
>
> +gPchDmiConfigGuid = {0xB3A61210, 0x1CD3, 0x4797, {0x8E, 0xE6, 0xD3,
> 0x42, 0x9C, 0x4F, 0x17, 0xBD}}
>
> +gFlashProtectionConfigGuid = {0xD0F71512, 0x9E32, 0x4CC9, {0xA5, 0xA3,
> 0xAD, 0x67, 0x9A, 0x06, 0x67, 0xB8}}
>
> +gHdAudioPreMemConfigGuid = {0xD38F1E2B, 0x21B3, 0x43D1, {0x9F, 0xA8,
> 0xA5, 0xE1, 0x78, 0x73, 0x1E, 0x88}}
>
> +gHdAudioConfigGuid = {0x7EB3CE7E, 0x82E0, 0x4CD7, {0xBD, 0xE5, 0xB2,
> 0xBF, 0x4E, 0x91, 0xC3, 0x4C}}
>
> +gHdAudioDxeConfigGuid = {0x22EFC2DE, 0x66EB, 0x412D, {0x97, 0x17,
> 0xE7, 0x7A, 0xA1, 0x4E, 0x87, 0x76}}
>
> +gInterruptConfigGuid = {0x09A2B815, 0xBE29, 0x45EF, {0xBF, 0xBF, 0x58,
> 0xEA, 0xAC, 0x5E, 0x29, 0x78}}
>
> +gIshPreMemConfigGuid = {0x7C24E649, 0xC1F0, 0x4CF9, {0x87, 0x96, 0xE7,
> 0xA0, 0xEE, 0x34, 0x43, 0xF8}}
>
> +gIshConfigGuid = {0x433AE2AA, 0xC5A6, 0x46ED, {0x94, 0x19, 0x1E, 0x5D,
> 0xB8, 0x1C, 0x57, 0x40}}
>
> +gGbeConfigGuid = {0x4B2DE99E, 0x7517, 0x4D04, {0x8C, 0x02, 0xF1, 0x1A,
> 0x59, 0x2B, 0x14, 0x2F}}
>
> +gTsnConfigGuid = {0x9E9A93CB, 0x0F4E, 0x4E56, {0x90, 0x2D, 0x6C, 0x76,
> 0xDE, 0x90, 0xF7, 0x71}}
>
> +gLockDownConfigGuid = {0x8A838E0A, 0xA639, 0x46F0, {0xA9, 0xCE, 0x70,
> 0xC4, 0x85, 0xFB, 0xA8, 0x0D}}
>
> +gP2sbConfigGuid = {0x2474DCB8, 0x4BB4, 0x49DA, {0x87, 0x83, 0x7C, 0xD3,
> 0xD3, 0x85, 0xFF, 0x07}}
>
> +gPmConfigGuid = {0x93826157, 0xDC85, 0x4E34, {0xAE, 0xD9, 0x6E, 0xA1,
> 0x0D, 0xF9, 0xE3, 0xA7}}
>
> +gScsConfigGuid = {0xF4DE6D52, 0xB5C9, 0x48C0, {0xA0, 0x4A, 0x68, 0x54,
> 0x20, 0x94, 0x05, 0xD0}}
>
> +gScsInfoHobGuid = {0x94C5E85B, 0xAA6D, 0x481D, {0x8B, 0xBD, 0x54, 0xAA,
> 0xE2, 0x99, 0x78, 0xB2}}
>
> +gSdCardConfigGuid = {0xD6A3038E, 0x50AE, 0x44B0, {0x93, 0xE2, 0xF7, 0x93,
> 0xF5, 0x90, 0x50, 0x27}}
>
> +gEmmcConfigGuid = {0xE0C6FB5D, 0x5696, 0x47F3, {0x84, 0xE8, 0xCC, 0x6C,
> 0x68, 0xA4, 0xB2, 0x1D}}
>
> +gUfsConfigGuid = {0x3AF25C55, 0x76B4, 0x4367, {0x85, 0xEF, 0x9D, 0x51,
> 0x2F, 0x2F, 0x8F, 0xA7}}
>
> +gEmmcDxeConfigGuid = {0x59440AA6, 0xEB45, 0x4E36, {0xBC, 0x90, 0xBE,
> 0xF9, 0x0C, 0xB0, 0xC8, 0x18}}
>
> +gSerialIoConfigGuid = {0x6CC06EBF, 0x0D34, 0x4340, {0xBC, 0x16, 0xDA,
> 0x09, 0xE5, 0x78, 0x3A, 0xDB}}
>
> +gSerialIrqConfigGuid = {0x251701E7, 0xE266, 0x4623, {0x99, 0x68, 0x73,
> 0x8C, 0xD2, 0x23, 0x10, 0x96}}
>
> +gSpiConfigGuid = {0x150360EF, 0x99BE, 0x4E43, {0x94, 0xBB, 0xBD, 0x40,
> 0x26, 0xCA, 0x34, 0x57}}
>
> +gEspiConfigGuid = {0x60FBF3B8, 0x96D4, 0x4187, {0x84, 0x9E, 0xAA, 0xF7,
> 0x5C, 0x4B, 0xE1, 0xE3}}
>
> +gThermalConfigGuid = {0x4416506D, 0x1197, 0x4722, {0xA5, 0xB4, 0x46,
> 0x11, 0xF9, 0x23, 0x9E, 0xAE}}
>
> +gUsbConfigGuid = {0xB2DA9CCD, 0x6A8C, 0x4BB6, {0xB3, 0xE6, 0xCD, 0xFB,
> 0xB7, 0x66, 0x8B, 0xDE}}
>
> +gUsb2PhyConfigGuid = {0x576C1134, 0x2E0C, 0xCB7D, {0xCD, 0x3F, 0xAC,
> 0x68, 0x2D, 0xAE, 0xD3, 0xF2}}
>
> +gUsb3HsioConfigGuid = {0xF8AFC238, 0xF176, 0x12CE, {0xBE, 0xF4, 0x69,
> 0xF9, 0xB1, 0xAC, 0x40, 0xD5}}
>
> +gPchPcieStorageDetectHobGuid = {0xC682F3F4, 0x2F46, 0x495E, {0x98,
> 0xAA, 0x43, 0x14, 0x4B, 0xA5, 0xA4, 0x85}}
>
> +gCnviConfigGuid = {0xE53EBEF7, 0x103D, 0x4A70, {0x9B, 0x6A, 0x73, 0xEE,
> 0x5F, 0x4C, 0x8D, 0xF5}}
>
> +gHsioConfigGuid = {0xE53EBEE7, 0x103D, 0x4A71, {0x9B, 0x6A, 0x74, 0xEE,
> 0x5F, 0x4C, 0x8D, 0xF5}}
>
> +gPchRstHobGuid = {0x4ECA680C, 0x660D, 0x48F8, {0xAA, 0xD8, 0x94, 0xD6,
> 0x56, 0x10, 0xF9, 0x86}}
>
> +gPchInfoHobGuid = {0x99FD5E18, 0xE262, 0x4E6A, {0x82, 0x66, 0x77, 0xD0,
> 0x36, 0x5F, 0xD6, 0x3E}}
>
> +gGpioDxeConfigGuid = {0x06985984, 0xAFA3, 0x429C, {0x80, 0xCD, 0x69,
> 0x43, 0xF3, 0x38, 0x31, 0x4D}}
>
> +gFivrConfigGuid = {0x68EE8BD4, 0x05F2, 0x4656, {0xAE, 0xE4, 0xAD, 0x10,
> 0xC7, 0x22, 0xC3, 0x4F}}
>
> +gThcConfigGuid = {0x1B318AD1, 0xAA0D, 0x4764, {0x99, 0xFD, 0xBB, 0x2B,
> 0xF4, 0x7F, 0x7E, 0xD6}}
>
> +gIehConfigGuid = {0x42C4D7F3, 0x981D, 0x4475, {0xA2, 0xAE, 0xAD, 0xCD,
> 0xD5, 0xCE, 0x87, 0x1E}}
>
> +gRtcConfigGuid = {0x0E9259B8, 0x3DDE, 0x40C7, {0xAA, 0x5F, 0x94, 0x82,
> 0x9A, 0x86, 0x8F, 0xAF}}
>
> +gCnviConfigGuid = {0xa660970e, 0x511b, 0x46bb, {0xa7, 0xb8, 0xec, 0xdd,
> 0xf5, 0xe2, 0x2d, 0x73}}
>
> +gGpioCheckConflictHobGuid = {0x5603f872, 0xefac, 0x40ae, {0xb9, 0x7e,
> 0x13, 0xb2, 0xf8, 0x07, 0x80, 0x21}}
>
> +gPsfConfigGuid = {0x49B12CF6, 0x0A56, 0x4B9F, {0xA8, 0x4C, 0xF5, 0x7D,
> 0x21, 0x23, 0x8C, 0x77}}
>
> +gHybridStorageConfigGuid = {0x265CE069, 0xD8CF, 0x48BE, {0xAE, 0x12,
> 0x02, 0x4C, 0x25, 0x12, 0xFA, 0xF8}}
>
> +gHybridStorageHobGuid = {0xFF91F620, 0x069E, 0x4191, {0x83, 0x73, 0x11,
> 0x60, 0x9F, 0x24, 0x90, 0xEB}}
>
> +gAdrConfigGuid = {0x5B36A07C, 0x3BBF, 0x4D53, {0x8A, 0x2D, 0xE1, 0xCF,
> 0x97, 0x39, 0x0C, 0x65}}
>
> +gSpiConfigGuid = {0xD61A6A07, 0xAD25, 0xBFC2, {0x8C, 0x60, 0xD0, 0xD1,
> 0xF4, 0x13, 0x14, 0xBC}}
>
> +
>
> +##
>
> +## Fusa
>
> +##
>
> +gFusaConfigGuid = {0xF9225896, 0xA9C8, 0x4543, {0xBA, 0x9E, 0x53, 0x32,
> 0xD7, 0xBF, 0x8C, 0x2B}}
>
> +gSiFusaInfoGuid = {0xcc7876ba, 0xee7b, 0x4bd4, {0x99, 0x4b, 0x7e, 0xc9,
> 0x74, 0xc9, 0xd8, 0x43}}
>
> +
>
> +##
>
> +## SecurityPkg
>
> +##
>
> +## GUID used to "Tcg2PhysicalPresence" variable and
> "Tcg2PhysicalPresenceFlags" variable for TPM2 request and response.
>
> +# Include/Guid/Tcg2PhysicalPresenceData.h
>
> +gEfiTcg2PhysicalPresenceGuid = { 0xaeb9c5c1, 0x94f1, 0x4d02, { 0xbf,
> 0xd9, 0x46, 0x2, 0xdb, 0x2d, 0x3c, 0x54 }}
>
> +gEfiTrEEPhysicalPresenceGuid = {0xf24643c2, 0xc622, 0x494e, {0x8a,
> 0x0d, 0x46, 0x32, 0x57, 0x9c, 0x2d, 0x5b}}
>
> +gTcoWdtHobGuid = { 0x3e405418, 0x0d8c, 0x4f1a, { 0xb0, 0x55,
> 0xbe, 0xf9, 0x08, 0x41, 0x46, 0x8d }}
>
> +
>
> +##
>
> +## UEFI Variable Support (Direct SPI and UFS)
>
> +##
>
> +gCseVariableStoragePpiInstanceGuid = { 0x9513730d, 0x06ce, 0x4cf6, {
> 0x9d, 0x95, 0xb0, 0x76, 0x31, 0xbc, 0xd5, 0xa9}}
>
> +gFvbVariableStoragePpiInstanceGuid = { 0x5067b88a, 0xaa37, 0x414d, {
> 0xa3, 0xca, 0xc8, 0x37, 0xfc, 0xec, 0xd6, 0xf3}}
>
> +gCseVariableStorageProtocolInstanceGuid = { 0x5d5ede0b, 0x5d93,
> 0x4aae, { 0xa8, 0xec, 0x08, 0x41, 0xd0, 0x53, 0x85, 0xc4}}
>
> +gFvbVariableStorageProtocolInstanceGuid = { 0xe98252e8, 0xf209, 0x4ef5,
> { 0xab, 0x7e, 0x12, 0x69, 0x45, 0x14, 0x47, 0xbe}}
>
> +gPeiVariableCacheHobGuid = { 0x35212b29, 0x128a, 0x4754, { 0xb9,
> 0x96, 0x62, 0x45, 0xcc, 0xa8, 0xa0, 0x66}}
>
> +gCseVariableStorageSecurePreMemoryDataGuid = { 0xa1749e1e, 0x8ce1,
> 0x4310, { 0xbd, 0x3f, 0x64, 0xc9, 0x01, 0xc6, 0x13, 0xc2}}
>
> +gCseVariableStorageGeneralDataAreaGuid = { 0x6d7a6128, 0x685b,
> 0x4f75, { 0x87, 0x87, 0xba, 0x93, 0x08, 0x60, 0x75, 0x0c}}
>
> +gCseVariableStorageFileSystemGuid = { 0xdb798aca, 0x3533, 0x41c7, {
> 0x9a, 0x98, 0x00, 0x31, 0x1b, 0x66, 0x0a, 0x15}}
>
> +gBugCheckVariableGuid = { 0xba57e015, 0x65b3, 0x4c3c, { 0xb2,
> 0x74, 0x65, 0x91, 0x92, 0xf6, 0x99, 0xe3}}
>
> +
>
> +##
>
> +## PreMem Performance
>
> +##
>
> +gPerfPchPrePolicyGuid = {0x3112356F, 0xCC77, 0x4E82, {0x86, 0xD5, 0x3E,
> 0x25, 0xEE, 0x81, 0x92, 0xA4}}
>
> +gPerfSiValidateGuid = {0x681F96E6, 0xF9CF, 0x464D, {0x97, 0x9A, 0xB1,
> 0x11, 0x33, 0xDE, 0x37, 0xA9}}
>
> +gPerfPchValidateGuid = {0xD0FF37D6, 0xA569, 0x4058, {0xB3, 0xDA, 0x29,
> 0x0B, 0x38, 0xC5, 0x32, 0x25}}
>
> +gPerfAmtValidateGuid = {0x9E949422, 0x4A7A, 0x4E41, {0xB0, 0xAB,
> 0x3C, 0x0D, 0x88, 0x0A, 0x00, 0xFF}}
>
> +gPerfCpuValidateGuid = {0xB760CFCC, 0xDEEF, 0x4C7E, {0x99, 0x5B, 0xED,
> 0xFE, 0xF2, 0x23, 0xB2, 0x09}}
>
> +gPerfMeValidateGuid = {0x8CF7A498, 0x588D, 0x4D39, {0xBD, 0xAC,
> 0x51, 0x0C, 0x31, 0xAF, 0x45, 0xD0}}
>
> +gPerfSaValidateGuid = {0xA73B382B, 0x62D4, 0x4A19, {0xBB, 0xF9, 0x09,
> 0x3E, 0xC5, 0xA5, 0x93, 0x11}}
>
> +gPerfHeciPreMemGuid = {0xD815D922, 0x4994, 0x40B3, {0x97, 0xCC,
> 0x07, 0xF3, 0x7D, 0x42, 0xE7, 0x97}}
>
> +gPerfPchPreMemGuid = {0xBB73E2B1, 0xB9FD, 0x4A80, {0xB8, 0x1A,
> 0x52, 0x39, 0xE9, 0x4D, 0x06, 0x2E}}
>
> +gPerfCpuPreMemGuid = {0xAC5FCBC6, 0x084D, 0x445D, {0xB3, 0xF3,
> 0xCA, 0x16, 0xDE, 0xE9, 0xBB, 0x47}}
>
> +gPerfMePreMemGuid = {0x6051338E, 0x0FFA, 0x40F7, {0xAF, 0xEF,
> 0xAB, 0x86, 0x7A, 0x38, 0xCC, 0xF3}}
>
> +gPerfAmtPreMemGuid = {0xDB732D50, 0x9BB8, 0x489A, {0xA1, 0xD1,
> 0xDD, 0xD2, 0x16, 0x1D, 0x72, 0xB8}}
>
> +gPerfAmtPostMemGuid = {0x0329D610, 0x4269, 0xD28F, {0x61, 0xBF,
> 0xB9, 0xA2, 0xD9, 0xFA, 0x96, 0x93}}
>
> +gPerfSaPreMemGuid = {0x76F18BDA, 0x2195, 0x4FB6, {0x9A, 0x94,
> 0x0E, 0x0B, 0xAC, 0xDE, 0xEC, 0xAB}}
>
> +gPerfEvlGuid = {0x8221518B, 0xAC19, 0x4E32, {0xAB, 0x5F, 0x00, 0x47,
> 0x0A, 0x50, 0x69, 0x40}}
>
> +gPerfMemGuid = {0x2B57B316, 0x5CF7, 0x4847, {0xB0, 0x76, 0x6B,
> 0x5D, 0x23, 0xC3, 0xAA, 0x3E}}
>
> +
>
> +##
>
> +## PostMem Performance
>
> +##
>
> +gPerfPchPostMemGuid = {0x70B67A99, 0x5556, 0x4315, {0xB3, 0x05,
> 0xD5, 0xDC, 0x4A, 0x35, 0x63, 0x70}}
>
> +gPerfSaPostMemGuid = {0x9FF0CE92, 0x883F, 0x43DC, {0x8A, 0x07,
> 0xE0, 0xCB, 0x6D, 0x56, 0x7D, 0xE0}}
>
> +gPerfS3CpuInitPostMemGuid = {0x976262C2, 0xD202, 0x4D12, {0x82, 0xAD,
> 0xF4, 0xA9, 0x8F, 0x9B, 0x96, 0x01}}
>
> +gPerfSaSecLockPostMemGuid = {0x272AC110, 0x0B60, 0x4D07, {0xA5, 0x58,
> 0x6D, 0x73, 0xE2, 0x43, 0x85, 0x95}}
>
> +gPerfCpuStrapPostMemGuid = {0x8EF4372B, 0x68F0, 0x4957, {0xBC, 0x4D,
> 0x7E, 0x5C, 0xFE, 0xDA, 0xB6, 0x3E}}
>
> +gPerfMpPostMemGuid = {0xA59BAC5B, 0xC6A4, 0x4AEB, {0x84, 0x32,
> 0x7A, 0x8B, 0x6B, 0x68, 0x5F, 0x37}}
>
> +gPerfCpuPostMemGuid = {0xE2FE5ED3, 0x1417, 0x451A, {0x95, 0xC9,
> 0xD0, 0xB2, 0xB9, 0x7B, 0xE0, 0x54}}
>
> +gPerfSaResetPostMemGuid = {0xBE152BEE, 0xFD19, 0x4274, {0xA8, 0xBA,
> 0xFB, 0x31, 0x42, 0xB5, 0xB5, 0xC3}}
>
> +gPerfCpuPowerMgmtGuid = {0x9ED307D6, 0x4AEB, 0x44A9, {0x9B, 0x11,
> 0xD8, 0x21, 0x84, 0x9A, 0xCB, 0xF7}}
>
> +gPerfMePostMemGuid = {0x2CC8626D, 0x3387, 0x4817, {0xAB, 0xF6,
> 0x86, 0x9A, 0xF5, 0xF0, 0x51, 0xAA}}
>
> +gPerfHdaPostMemGuid = {0xB31883B7, 0x5A05, 0x4040, {0x40, 0x80,
> 0x66, 0x8D, 0x29, 0x13, 0xD7, 0x84}}
>
> +
>
> +##
>
> +## Dp-In Guid
>
> +##
>
> +## Include/DpInDataHob.h
>
> +gDpInHobGuid = {0x3e110a83, 0xb94b, 0x4648, {0xa2, 0x26, 0x50, 0x9b,
> 0xd5, 0x55, 0xe3, 0x6b}}
>
> +## Include/ConfigBlock/Tcss/DpInPreMemConfig.h
>
> +gDpInPreMemConfigGuid = {0x80c14ba, 0xcc84, 0x4746, {0xbf, 0x6b, 0xd1,
> 0xf1, 0x8e, 0xaa, 0xe8, 0x35}}
>
> +
>
> +[Protocols.common.Private]
>
> +##
>
> +## SA
>
> +##
>
> +gSaIotrapSmiProtocolGuid = { 0x1861e089, 0xcaa3, 0x473e, { 0x84, 0x32,
> 0xdc, 0x1f, 0x94, 0xc6, 0xc1, 0xa6 }}
>
> +gCpuPcieIoTrapProtocolGuid = { 0xda904080, 0x33ab, 0x48ca, { 0x97, 0x5b,
> 0x5f, 0x2f, 0x23, 0x8a, 0x41, 0xb4 }}
>
> +
>
> +gPchPcieIoTrapProtocolGuid = { 0xd66a1cf, 0x79ad, 0x494b, { 0x97, 0x8b,
> 0xb2, 0x59, 0x81, 0x68, 0x93, 0x34 }}
>
> +
>
> +[Protocols]
>
> +##
>
> +## MdeModulePkg
>
> +##
>
> +gEfiSmmVariableProtocolGuid = {0xed32d533, 0x99e6, 0x4209, {0x9c, 0xc0,
> 0x2d, 0x72, 0xcd, 0xd9, 0x98, 0xa7}}
>
> +gEdkiiPlatformSpecificResetFilterProtocolGuid = { 0x695d7835, 0x8d47,
> 0x4c11, { 0xab, 0x22, 0xfa, 0x8a, 0xcc, 0xe7, 0xae, 0x7a } }
>
> +gEdkiiPlatformSpecificResetHandlerProtocolGuid = { 0x2df6ba0b, 0x7092,
> 0x440d, { 0xbd, 0x4, 0xfb, 0x9, 0x1e, 0xc3, 0xf3, 0xc1 } }
>
> +
>
> +##
>
> +## SystemAgent
>
> +##
>
> +gBdatAccessGuid = {0x9477482c, 0x8717, 0x4725, {0x98, 0x28, 0x7b,
> 0xd8, 0xc9, 0xa3, 0x75, 0x6a}}
>
> +gIgdOpRegionProtocolGuid = {0x9e67aecf, 0x4fbb, 0x4c84, {0x99, 0xa5,
> 0x10, 0x73, 0x40, 0x7, 0x6d, 0xb4}}
>
> +gMemInfoProtocolGuid = {0xd4d2f201, 0x50e8, 0x4d45, {0x8e, 0x5,
> 0xfd, 0x49, 0xa8, 0x2a, 0x15, 0x69}}
>
> +gSaPolicyProtocolGuid = {0xc6aa1f27, 0x5597, 0x4802, {0x9f, 0x63,
> 0xd6, 0x28, 0x36, 0x59, 0x86, 0x35}}
>
> +gSaNvsAreaProtocolGuid = {0x149a10a5, 0x9d06, 0x4c6b, {0xbe, 0x44,
> 0x08, 0x92, 0xce, 0x20, 0x61, 0xac}}
>
> +gGopPolicyProtocolGuid = {0xec2e931b, 0x3281, 0x48a5, {0x81, 0x07,
> 0xdf, 0x8a, 0x8b, 0xed, 0x3c, 0x5d}}
>
> +gGen12PolicyProtocolGuid = {0x40f60ea0, 0x6c96, 0x4ed3, {0x96, 0xe5,
> 0xba, 0x6f, 0x6d, 0x66, 0x28, 0x9f}}
>
> +gGen9PolicyProtocolGuid = {0xeaaed1ba, 0xf15c, 0x4112, {0xb5, 0x82,
> 0x90, 0x63, 0xac, 0xa0, 0x7f, 0x06}}
>
> +gGopComponentName2ProtocolGuid = {0x651b7ebd, 0xce13, 0x41d0,
> {0x82, 0xe5, 0xa0, 0x63, 0xab, 0xbe, 0x9b, 0xb6}}
>
> +gGopOverrideProtocolGuid = {0x4a89a16e, 0x67b8, 0x4429, {0x8c, 0x47,
> 0x43, 0x67, 0x90, 0xf2, 0xf2, 0x69}}
>
> +gMemoryAddressEncodeDecodeProtocolGuid = {0x603df7ca, 0x1ba8,
> 0x4c12, {0xa9, 0x8a, 0x49, 0x6d, 0xfe, 0x77, 0xeb, 0xdf}}
>
> +
>
> +##
>
> +## TBT
>
> +##
>
> +gITbtPolicyProtocolGuid = {0xb0563c42, 0x28ea, 0x40e6, {0x99, 0x84,
> 0xd5, 0xbf, 0xf8, 0xb0, 0x40, 0x56}}
>
> +gITbtNvsAreaProtocolGuid = {0xdabf85bd, 0xfbdc, 0x4ed2, {0xb1, 0x0d,
> 0xc9, 0x08, 0xd0, 0x8c, 0xee, 0xe8}}
>
> +gDisableITbtBmeProtocolGuid = {0x89a9adc3, 0x9b7c, 0x4b53, {0x82,
> 0xbf, 0x78, 0x72, 0x6b, 0x91, 0x4f, 0x9f}}
>
> +
>
> +##
>
> +## Cpu
>
> +##
>
> +gCpuInfoProtocolGuid = {0xe223cf65, 0xf6ce, 0x4122, {0xb3, 0xaf, 0x4b,
> 0xd1, 0x8a, 0xff, 0x40, 0xa1}}
>
> +gSmmBiosGuardProtocolGuid = {0x17565311, 0x4b71, 0x4340, {0x88, 0xaa,
> 0xdc, 0x9f, 0x44, 0x22, 0xe5, 0x3a}}
>
> +gCpuNvsAreaProtocolGuid = {0xb9cf3f43, 0xbe3e, 0x4e45, {0xa0, 0xbe,
> 0x1a, 0x4, 0x89, 0xdf, 0x1a, 0xc9}}
>
> +gDxeCpuPolicyProtocolGuid = {0x8282b977, 0x22f9, 0x4134, {0x99, 0x43,
> 0x7b, 0xcc, 0x5f, 0x40, 0x33, 0x52}}
>
> +gBiosGuardNvsAreaProtocolGuid = {0x5df588da, 0x991e, 0x4a7f, {0x80,
> 0x51, 0x70, 0xc7, 0x12, 0xb7, 0xba, 0xb0}}
>
> +gSmmResourceConfigProtocolGuid = {0xA37FC2D2, 0x822D, 0x4A63, {0x9C,
> 0x42, 0xBE, 0xB1, 0xD6, 0xEE, 0x85, 0x39}}
>
> +
>
> +##
>
> +## Me
>
> +##
>
> +gActiveManagementProtocolGuid = {0xd25dc167, 0xeb6a, 0x432d, {0x65,
> 0x91, 0xbf, 0x80, 0x29, 0xb0, 0x05, 0xbb}}
>
> +gAlertStandardFormatProtocolGuid = {0x45de9920, 0xcd54, 0x446a, {0xa0,
> 0x3c, 0x22, 0xe6, 0xfb, 0xb4, 0x51, 0xe4}}
>
> +gHeciProtocolGuid = {0x3c7bc880, 0x41f8, 0x4869, {0xae, 0xfc, 0x87,
> 0x0a, 0x3e, 0xd2, 0x82, 0x99}}
>
> +gHeciFlowProtocolGuid = {0x1498d127, 0x123c, 0x4e52, {0x84, 0x00,
> 0xcc, 0x3c, 0x9f, 0x79, 0xc4, 0x0e}}
>
> +gMebxProtocolGuid = {0x01ab1829, 0xcecd, 0x4cfa, {0xa1, 0x8c,
> 0xea, 0x75, 0xd6, 0x6f, 0x3e, 0x74}}
>
> +gDxeMePolicyGuid = {0xa0b5dc52, 0x4f34, 0x3990, {0xd4, 0x91,
> 0x10, 0x8b, 0xe8, 0xba, 0x75, 0x42}}
>
> +gMeInfoProtocolGuid = {0x7523c8e4, 0x4fbe, 0x9661, {0x29, 0x96,
> 0x14, 0x97, 0xff, 0x36, 0x2f, 0x3b}}
>
> +gPlatformMeHookProtocolGuid = {0xbc52476e, 0xf67e, 0x4301, {0xb2,
> 0x62, 0x36, 0x9c, 0x48, 0x78, 0xaa, 0xc2}}
>
> +gMeNvsAreaProtocolGuid = {0x3bffecfd, 0xd75f, 0x4975, {0xb8, 0x88,
> 0x39, 0x02, 0xbd, 0x69, 0x00, 0x2b}}
>
> +gJhiProtocolGuid = {0xccba3051, 0xa574, 0x4f9d, {0x96, 0xf4, 0xec,
> 0x0d, 0x4a, 0x87, 0xbc, 0x5a}}
>
> +gIntegratedTouchHidProtocolGuid = {0x3d0479c1, 0x6b19, 0x4191, {0xb8,
> 0x09, 0x60, 0x08, 0xdd, 0x07, 0x97, 0x55}}
>
> +gIntegratedTouchProtocolGuid = {0x2b12e46f, 0x3c24, 0x47ff, {0x8b,
> 0x89, 0xc0, 0x60, 0x2c, 0x1c, 0x61, 0x42}}
>
> +gMeEopDoneProtocolGuid = {0x8d9b3387, 0x73db, 0x456f, {0x88,
> 0x9d, 0x6f, 0xfe, 0x90, 0x82, 0x64, 0x09}}
>
> +gMeSendEopInFspProtocolGuid = {0xcecdba92, 0x76c6, 0x4063, {0xaa,
> 0x6b, 0x19, 0xfc, 0x60, 0x5c, 0x70, 0xff}}
>
> +
>
> +gHeciAccessProtocolGuid = {0x3a5aab32, 0xd5a7, 0x4ce8, {0x88, 0xe2,
> 0xed, 0x8f, 0x7b, 0x43, 0x23, 0x9d}}
>
> +gHeciTransportProtocolGuid = {0x9fc932b9, 0x8851, 0x43f7, {0x8a, 0x58,
> 0xa8, 0xd9, 0x04, 0x01, 0xcd, 0x78}}
>
> +gHeciControlProtocolGuid = {0xd86381d8, 0xff7e, 0x462e, {0x9b, 0x55,
> 0x02, 0x0a, 0x64, 0x1b, 0xe3, 0x4f}}
>
> +gHeciAccessSmmProtocolGuid = {0x5da6182c, 0xf679, 0x49eb, {0x96,
> 0xf5, 0xe6, 0x24, 0x9b, 0x54, 0x0b, 0x96}}
>
> +gHeciTransportSmmProtocolGuid = {0xf5f7b292, 0xbb38, 0x4e59, {0xa1,
> 0x6e, 0x0f, 0x27, 0x15, 0xd4, 0xb7, 0xf4}}
>
> +gHeciControlSmmProtocolGuid = {0x7e1e508d, 0x7def, 0x4d69, {0xa9,
> 0xb3, 0xa5, 0x23, 0xe8, 0x48, 0xc6, 0x98}}
>
> +
>
> +##
>
> +## Amt
>
> +##
>
> +gAmtSaveMebxProtocolGuid = {0x86682c04, 0xea42, 0x49e5, {0x96,
> 0x81, 0xe3, 0x32, 0xaa, 0xb0, 0x9e, 0xd7}}
>
> +gDxeAmtPolicyGuid = {0x6725e645, 0x4a7f, 0x9969, {0x82, 0xec,
> 0xd1, 0x87, 0x21, 0xde, 0x5a, 0x57}}
>
> +gAmtReadyToBootProtocolGuid = {0xcc9d5c0b, 0x9010, 0x45f1, {0x99,
> 0x3c, 0x83, 0x27, 0x67, 0xf1, 0x67, 0x77}}
>
> +gMeSmbiosTablesUpdateProtocolGuid = {0x5054ee06, 0x4ce0, 0x4acc,
> {0x9a, 0x80, 0xdf, 0x73, 0xbf, 0xa5, 0x38, 0xdd}}
>
> +gOneClickRecoveryProtocolGuid = {0x93598eac, 0xc62b, 0x4dbb, {0x96,
> 0x76, 0xe0, 0x5e, 0x8c, 0xc3, 0x84, 0x44}}
>
> +
>
> +##
>
> +## PCH
>
> +##
>
> +gThcProtocolGuid = {0x00860921, 0x7B9B, 0x4EA8, {0xAD, 0x23, 0x3C, 0xCA,
> 0x33, 0x9E, 0x7D, 0xFE}}
>
> +gPchSpiProtocolGuid = {0xc7d289, 0x1347, 0x4de0, {0xbf, 0x42, 0xe, 0x26,
> 0x9d, 0xe, 0xf3, 0x4a}}
>
> +gWdtProtocolGuid = {0xb42b8d12, 0x2acb, 0x499a, {0xa9, 0x20, 0xdd, 0x5b,
> 0xe6, 0xcf, 0x09, 0xb1}}
>
> +gPchSerialIoUartDebugInfoProtocolGuid = {0x2fd2b1bd, 0x0387, 0x4ec6,
> {0x94, 0x1f, 0xf1, 0x4b, 0x7f, 0x1c, 0x94, 0xb6}}
>
> +gEfiSmmSmbusProtocolGuid = {0x72e40094, 0x2ee1, 0x497a, {0x8f, 0x33,
> 0x4c, 0x93, 0x4a, 0x9e, 0x9c, 0x0c}}
>
> +gPchSmmSpiProtocolGuid = {0x56521f06, 0xa62, 0x4822, {0x99, 0x63, 0xdf,
> 0x1, 0x9d, 0x72, 0xc7, 0xe1}}
>
> +gPchSmmIoTrapControlGuid = {0x514d2afd, 0x2096, 0x4283, {0x9d, 0xa6,
> 0x70, 0x0c, 0xd2, 0x7d, 0xc7, 0xa5}}
>
> +gPchTcoSmiDispatchProtocolGuid = {0x9e71d609, 0x6d24, 0x47fd, {0xb5,
> 0x72, 0x61, 0x40, 0xf8, 0xd9, 0xc2, 0xa4}}
>
> +gPchPcieSmiDispatchProtocolGuid = {0x3e7d2b56, 0x3f47, 0x42aa, {0x8f,
> 0x6b, 0x22, 0xf5, 0x19, 0x81, 0x8d, 0xab}}
>
> +gPchAcpiSmiDispatchProtocolGuid = {0xd52bb262, 0xf022, 0x49ec, {0x86,
> 0xd2, 0x7a, 0x29, 0x3a, 0x7a, 0x05, 0x4b}}
>
> +gPchSmiDispatchProtocolGuid = {0xE6A81BBF, 0x873D, 0x47FD, {0xB6,
> 0xBE, 0x61, 0xB3, 0xE5, 0x72, 0x09, 0x93}}
>
> +gPchNvsAreaProtocolGuid = {0x2e058b2b, 0xedc1, 0x4431, {0x87, 0xd9,
> 0xc6, 0xc4, 0xea, 0x10, 0x2b, 0xe3}}
>
> +gPchEspiSmiDispatchProtocolGuid = {0xB3C14FF3, 0xBAE8, 0x456C, {0x86,
> 0x31, 0x27, 0xFE, 0x0C, 0xEB, 0x34, 0x0C}}
>
> +gPchSmmPeriodicTimerControlGuid = {0x6906E93B, 0x603B, 0x4A0F, {0x86,
> 0x92, 0x83, 0x20, 0x04, 0xAA, 0xF2, 0xDB}}
>
> +gIoTrapExDispatchProtocolGuid = {0x5B48E913, 0x707B, 0x4F9D, {0xAF,
> 0x2E, 0xEE, 0x03, 0x5B, 0xCE, 0x39, 0x5D}}
>
> +gPchPolicyProtocolGuid = {0x543d5c93, 0x6a28, 0x4513, {0x85, 0x9a,
> 0x82, 0xa7, 0xb9, 0x12, 0xcb, 0xbe}}
>
> +gScsEmmcSoftwareTuningProtocolGuid = {0x972215b2, 0x9616, 0x4de4,
> {0xa9, 0x75, 0xb0, 0x74, 0x3e, 0xe1, 0x78, 0x54}}
>
> +
>
> +##
>
> +## Hsti
>
> +##
>
> +## HstiSiliconDxe Driver Entry Point
>
> +gHstiProtocolGuid = { 0x1b05de41, 0xc93b, 0x4bb4, { 0xad, 0x47, 0x2a, 0x78,
> 0xac, 0xf, 0xc9, 0xe4 }}
>
> +## Handler to gather and publish HSTI results on ReadyToBootEvent
>
> +gHstiPublishCompleteProtocolGuid = {0x0f500be6, 0xece4, 0x4ed8, { 0x90,
> 0x81, 0x9a, 0xa9, 0xa5, 0x23, 0xfb, 0x7b}}
>
> +gEfiAdapterInformationProtocolGuid = { 0xE5DD1403, 0xD622, 0xC24E,
> {0x84, 0x88, 0xC7, 0x1B, 0x17, 0xF5, 0xE8, 0x02 }}
>
> +
>
> +##
>
> +## Silicon Policy
>
> +##
>
> +## Include/Protocol/SiPolicyProtocol.h
>
> +gDxeSiPolicyProtocolGuid = { 0xeca27516, 0x306c, 0x4e28, { 0x8c, 0x94,
> 0x4e, 0x52, 0x10, 0x96, 0x69, 0x5e }}
>
> +
>
> +##
>
> +## DGR
>
> +##
>
> +gEfiSpaLogOutputProtocolGuid = { 0x1d10d46b, 0x0306, 0x454a, { 0x90,
> 0x8c, 0x93, 0x65, 0xb3, 0x8a, 0x90, 0x26 }}
>
> +
>
> +[Ppis.common.Private]
>
> +gPchHsioChipsetInitSusTblDataPpiGuid = { 0x97ed4e5d, 0x01a5, 0x4a3c, {
> 0xb7, 0xe9, 0x1a, 0x4e, 0xa3, 0xdd, 0x23, 0xce }}
>
> +gHybridStorageCfgPpiGuid = {0x8557e481, 0xc00e, 0x4929, {0xb4, 0x53,
> 0xf6, 0xc2, 0x53, 0x79, 0xb0, 0x13}}
>
> +
>
> +[Ppis]
>
> +##
>
> +## MdeModulePkg
>
> +##
>
> +gPeiCapsulePpiGuid = {0x3acf33ee, 0xd892, 0x40f4, {0xa2, 0xfc, 0x38, 0x54,
> 0xd2, 0xe1, 0x32, 0x3d}}
>
> +gPeiSmmControlPpiGuid = {0x61c68702, 0x4d7e, 0x4f43, {0x8d, 0xef, 0xa7,
> 0x43, 0x05, 0xce, 0x74, 0xc5}}
>
> +gEdkiiPlatformSpecificResetFilterPpiGuid = { 0x8c9f4de3, 0x7b90, 0x47ef, {
> 0x93, 0x8, 0x28, 0x7c, 0xec, 0xd6, 0x6d, 0xe8 } }
>
> +gEdkiiPlatformSpecificResetNotificationPpiGuid = { 0xe09f355d, 0xdae8,
> 0x4910, { 0xb1, 0x4a, 0x92, 0x78, 0xf, 0xdc, 0xf7, 0xcb } }
>
> +gEdkiiPlatformSpecificResetHandlerPpiGuid = { 0x75cf14ae, 0x3441, 0x49dc,
> { 0xaa, 0x10, 0xbb, 0x35, 0xa7, 0xba, 0x8b, 0xab } }
>
> +
>
> +##
>
> +## SecurityPkg
>
> +##
>
> +gPeiTpmInitializedPpiGuid = {0xe9db0d58, 0xd48d, 0x47f6, {0x9c, 0x6e,
> 0x6f, 0x40, 0xe8, 0x6c, 0x7b, 0x41}}
>
> +gPeiTpmInitializationDonePpiGuid = {0xa030d115, 0x54dd, 0x447b, { 0x90,
> 0x64, 0xf2, 0x6, 0x88, 0x3d, 0x7c, 0xcc}}
>
> +##
>
> +## Common
>
> +##
>
> +## Include/Ppi/SiPolicy.h
>
> +gSiPolicyPpiGuid = {0xaebffa01, 0x7edc, 0x49ff, {0x8d, 0x88, 0xcb, 0x84,
> 0x8c, 0x5e, 0x86, 0x70}}
>
> +## Include/Ppi/SiPolicy.h
>
> +gSiPreMemPolicyPpiGuid = {0xc133fe57, 0x17c7, 0x4b09, {0x8b, 0x3c, 0x97,
> 0xc1, 0x89, 0xd0, 0xab, 0x8d}}
>
> +gFspApiModePpiGuid = {0xa1eeab87, 0xc859, 0x479d, {0x89, 0xb5,
> 0x14, 0x61, 0xf4, 0x06, 0x1a, 0x3e}}
>
> +## Silicon Initialization PPI is used to export End of Silicon init.
>
> +gEndOfSiInitPpiGuid = {0xE2E3D5D1, 0x8356, 0x4F96, {0x9C, 0x9E, 0x2E,
> 0xC3, 0x48, 0x1D, 0xEA, 0x88}}
>
> +gEfiEndOfPeiSignal2PpiGuid = {0x22918381, 0xd018, 0x4d7c, {0x9d, 0x62,
> 0xf5, 0xa5, 0x70, 0x1c, 0x66, 0x80}}
>
> +gFspTempRamExitPpiGuid = {0xbc1cfbdb, 0x7e50, 0x42be, {0xb4, 0x87,
> 0x22, 0xe0, 0xa9, 0x0c, 0xb0, 0x52}}
>
> +gFspmArchConfigPpiGuid = {0x824d5a3a, 0xaf92, 0x4c0c, {0x9f, 0x19,
> 0x19, 0x52, 0x6d, 0xca, 0x4a, 0xbb}}
>
> +gSiPreMemDefaultPolicyInitPpiGuid = {0xfec36242, 0xf8d8, 0x4b43, {0x87,
> 0x94, 0x4f, 0x1f, 0x9f, 0x63, 0x8d, 0xdc}}
>
> +gSiPreMemPolicyReadyPpiGuid = {0x85270bef, 0x6984, 0x4375, {0xa6, 0xea,
> 0xb5, 0xaa, 0x90, 0x6e, 0xdd, 0x4a}}
>
> +gSiDefaultPolicyInitPpiGuid = {0xf69abf86, 0x4048, 0x44ef, { 0xa8, 0xef,
> 0x6c, 0x7f, 0x20, 0x4a, 0xc8, 0xda}}
>
> +gSiPolicyReadyPpiGuid = {0xd570de8c, 0xb9c4, 0x4ffa, {0xad, 0xee, 0xa5,
> 0x82, 0x7c, 0xe3, 0x17, 0x79}}
>
> +
>
> +##
>
> +## UEFI Variable Support (Override Until BP1.5)
>
> +##
>
> +gEdkiiVariableStoragePpiGuid = { 0x90d915c5, 0xe4c1, 0x4da8, {0xa7, 0x6f,
> 0x9, 0xe5, 0x78, 0x91, 0x65, 0x48}}
>
> +gEdkiiVariableStorageSelectorPpiGuid = { 0x782546d1, 0x03ab, 0x41e4,
> {0xa0, 0x1d, 0x7a, 0x9b, 0x22, 0xba, 0x2e, 0x1e}}
>
> +gReadOnlyVariablePreMemoryDescriptorPpiGuid = { 0xbe136fc9, 0xc277,
> 0x4dd1, {0xbe, 0x42, 0xce, 0xf0, 0x9f, 0xf4, 0x3f, 0x55}}
>
> +gEfiReadyToInstallEndOfPei2PpiGuid = {0xeef72924, 0x2db2, 0x4569, { 0x86,
> 0x3f, 0xd4, 0x86, 0xae, 0x7a, 0xe4, 0x12}}
>
> +
>
> +##
>
> +## SystemAgent
>
> +##
>
> +gSsaBiosCallBacksPpiGuid = {0x99b56126, 0xe16c, 0x4d9b, {0xbb, 0x71,
> 0xaa, 0x35, 0x46, 0x1a, 0x70, 0x2f}}
>
> +gSsaBiosServicesPpiGuid = {0x55750d10, 0x6d3d, 0x4bf5, {0x89, 0xd8,
> 0xe3, 0x5e, 0xf0, 0xb0, 0x90, 0xf4}}
>
> +gEnablePeiGraphicsPpiGuid = {0x8e3bb474, 0x545, 0x4902, {0x86, 0xb0,
> 0x6c, 0xb5, 0xe2, 0x64, 0xb4, 0xa5}}
>
> +gPeiGraphicsFramebufferReadyPpiGuid = {0x590ad868, 0xb0b1, 0x4d20,
> {0x91, 0xff, 0xc2, 0xa9, 0xd6, 0x88, 0x81, 0x94}}
>
> +gMrcMemoryInitDonePpiGuid = {0x0ff07255, 0x67c2, 0x456d, {0x9a, 0x95,
> 0xc9, 0x16, 0x2c, 0x23, 0x86, 0x8d}}
>
> +## X Compatibility support PPI
>
> +gCompatibleMemoryInitPpiGuid = {0xca311f82, 0xf490, 0x4b12, {0x9e, 0xe1,
> 0x2b, 0x66, 0xa3, 0x6c, 0x3e, 0xa}}
>
> +gVmdInitDonePpiGuid = {0x42a187c8, 0xca0a, 0x4750, {0x82, 0xfd, 0xc9,
> 0xa0, 0xd5, 0x9, 0xfe, 0xd1}}
>
> +
>
> +##
>
> +## TwoLm
>
> +##
>
> +gMrcMemoryInitDonePpiGuid = { 0x598907f5, 0xd5fc, 0x435c, { 0x8a, 0x7f,
> 0x53, 0xc5, 0xa4, 0xb5, 0x31, 0xc4}}
>
> +
>
> +##
>
> +## Nvdimm Cache Info
>
> +##
>
> +gNvdimmCachePpiGuid = { 0x1bbc5601, 0xe571, 0x4ae0, { 0xbc, 0x38, 0xb8,
> 0x65, 0x0d, 0x50, 0x6f, 0x5b}}
>
> +
>
> +##
>
> +## Cpu
>
> +##
>
> +gPeiCachePpiGuid = {0x09be4bc2, 0x790e, 0x4dea, {0x8b, 0xdc, 0x38, 0x05,
> 0x16, 0x98, 0x39, 0x44}}
>
> +gPeiTxtMemoryUnlockedPpiGuid = {0x38cdd10b, 0x767d, 0x4f6e, {0xa7,
> 0x44, 0x67, 0xee, 0x1d, 0xfe, 0x2f, 0xa5}}
>
> +gPeiTxtReadyToRunMemoryInitPpiGuid = {0x9ecafd30, 0x29e2, 0x42f6,
> {0xba, 0xf3, 0x8b, 0x7d, 0xb8, 0xfe, 0x1f, 0x22}}
>
> +gPeiReadyToInstallMpPpiGuid = { 0x1a266768, 0xfd43, 0x4e18, { 0xa8, 0x8a,
> 0x35, 0xc7, 0x94, 0xc3, 0x91, 0x0e }}
>
> +##
>
> +## Me
>
> +##
>
> +gHeciPpiGuid = {0xd14319e2, 0x407a, 0x9580, {0x8d, 0xe5, 0x51, 0xa8, 0xff,
> 0xc6, 0xd7, 0xd7}}
>
> +gMbpSensitivePpiGuid = {0xed7c9ce9, 0x5912, 0x4807, {0xec, 0x90, 0x22,
> 0x18, 0xbc, 0x7b, 0xfc, 0x6c}}
>
> +gHeci3IntegratedTouchControllerGuid = {0x3e8d0870, 0x271a, 0x4208,
> {0x8e, 0xb5, 0x9a, 0xcb, 0x94, 0x02, 0xae, 0x04}}
>
> +gSiNvmOwnershipAcquiredPpiGuid = {0xe5db3d8c, 0xefa4, 0x4308, {0x9a,
> 0xab, 0x6b, 0x97, 0x81, 0x09, 0x98, 0xa0}}
>
> +gHeciAccessPpiGuid = {0x3a5aab32, 0xd5a7, 0x4ce8, {0x88, 0xe2, 0xed, 0x8f,
> 0x7b, 0x43, 0x23, 0x9d}}
>
> +gHeciTransportPpiGuid = {0x9fc932b9, 0x8851, 0x43f7, {0x8a, 0x58, 0xa8,
> 0xd9, 0x04, 0x01, 0xcd, 0x78}}
>
> +gHeciControlPpiGuid = {0xd86381d8, 0xff7e, 0x462e, {0x9b, 0x55, 0x02,
> 0x0a, 0x64, 0x1b, 0xe3, 0x4f}}
>
> +gMeBeforeDidSentPpiGuid = {0xd497b143, 0xf3ef, 0x4192, {0xa8, 0xc5,
> 0x5e, 0xf6, 0xcd, 0x6e, 0x4c, 0x87}}
>
> +
>
> +##
>
> +## PCH
>
> +##
>
> +gWdtPpiGuid = {0xf38d1338, 0xaf7a, 0x4fb6, {0x91, 0xdb, 0x1a, 0x9c, 0x21,
> 0x83, 0x57, 0x0d}}
>
> +gPchSpiPpiGuid = {0xdade7ce3, 0x6971, 0x4b75, {0x82, 0x5e, 0xe, 0xe0,
> 0xeb, 0x17, 0x72, 0x2d}}
>
> +gPeiSmbusPolicyPpiGuid = {0x63b6e435, 0x32bc, 0x49c6, {0x81, 0xbd, 0xb7,
> 0xa1, 0xa0, 0xfe, 0x1a, 0x6c}}
>
> +
>
> +##
>
> +## TCSS
>
> +##
>
> +gTcssPeiInitDonePpiGuid = {0x5ad291b8, 0xace4, 0x416a, {0xb7, 0x50, 0x7,
> 0x63, 0x59, 0xfc, 0xc1, 0x5b}}
>
> +
>
> +[LibraryClasses]
>
> +## @libraryclass
>
> +## Common
>
> +##
>
> +MmPciLib|Include/Library/MmPciLib.h
>
> +
>
> +## @libraryclass
>
> +## SampleCode
>
> +##
>
> +## CPU
>
> +##
>
> +CpuPolicyLib|Cpu/Include/Library/CpuPolicyLib.h
>
> +
>
> +## @libraryclass
>
> +## Me
>
> +##
>
> +
>
> +MeChipsetLib|Me/Include/Library/MeChipsetLib.h
>
> +
>
> +PeiMePolicyLib|Me/Include/Library/PeiMePolicyLib.h
>
> +PttHciLib|Me/Include/Library/PttHciLib.h
>
> +PttHeciLib|Me/Include/Library/PttHeciLib.h
>
> +## @libraryclass
>
> +## Pch
>
> +##
>
> +GpioLib|Include/Library/GpioLib.h
>
> +GpioLib|Include/Library/GpioNativeLib.h
>
> +PchCycleDecodingLib|Pch/Include/Library/PchCycleDecodingLib.h
>
> +EspiLib|Include/Library/PchEspiLib.h
>
> +GbeLib|Include/Library/GbeLib.h
>
> +GbeMdiLib|IpBlock/Gbe/IncludePrivate/Library/GbeMdiLib.h
>
> +PchHsioLib|Pch/IncludePrivate/PchHsio.h
>
> +PchInfoLib|Pch/Include/Library/PchInfoLib.h
>
> +PchP2sbLib|Pch/Include/Library/PchP2sbLib.h
>
> +PchPcieRpLib|Pch/Include/Library/PchPcieRpLib.h
>
> +PchPcrLib|Pch/Include/Library/PchPcrLib.h
>
> +PchPolicyLib|Pch/Include/Library/PchPolicyLib.h
>
> +PchSbiAccessLib|Pch/IncludePrivate/Library/PchSbiAccessLib.h
>
> +SerialIoAccessLib|Include/Library/SerialIoAccessLib.h
>
> +DxePchPolicyLib|Pch/Include/Library/DxePchPolicyLib.h
>
> +
>
> +## @libraryclass
>
> +## Sa
>
> +##
>
> +DxeSaPolicyLib|SystemAgent/Include/Library/DxeSaPolicyLib.h
>
> +SaPlatformLib|SystemAgent/Include/Library/SaPlatformLib.h
>
> +Include/Library/VoltageRegulatorCommands.h
>
> +
>
> +[PcdsFixedAtBuild]
>
> +## From MdeModulePkg.dec
>
> +## Progress Code for S3 Suspend start.
>
> +## PROGRESS_CODE_S3_SUSPEND_START =
> (EFI_SOFTWARE_SMM_DRIVER | (EFI_OEM_SPECIFIC | 0x00000000)) =
> 0x03078000
>
> +gSiPkgTokenSpaceGuid.PcdProgressCodeS3SuspendStart|0x03078000|UIN
> T32|0x30001032
>
> +## Progress Code for S3 Suspend end.
>
> +## PROGRESS_CODE_S3_SUSPEND_END = (EFI_SOFTWARE_SMM_DRIVER
> | (EFI_OEM_SPECIFIC | 0x00000001)) = 0x03078001
>
> +gSiPkgTokenSpaceGuid.PcdProgressCodeS3SuspendEnd|0x03078001|UINT
> 32|0x30001033
>
> +##
>
> +## PcdNemCodeCacheBase is usally the same as PEI FV Base address,
>
> +## FLASH_BASE+FLASH_REGION_FV_RECOVERY_OFFSET from
> PlatformPkg.fdf.
>
> +##
>
> +## Restriction:
>
> +## 1) PcdNemCodeCacheBase - (PcdTemporaryRamBase +
> PcdTemporaryRamSize) >= 4K
>
> +## 2) PcdTemporaryRamBase >= 4G - 64M
>
> +##
>
> +gSiPkgTokenSpaceGuid.PcdNemCodeCacheBase|0xFFF80000|UINT32|0x20
> 000009
>
> +##
>
> +## NemCodeCacheSize is usally the same as PEI FV Size,
>
> +## FLASH_REGION_FV_RECOVERY_SIZE from PlatformPkg.fdf.
>
> +##
>
> +## Restriction:
>
> +## 1) PcdNemTotalCacheSize = NemCodeCacheSize +
> PcdTemporaryRamSize
>
> +## <= Maximun CPU NEM total size (Code + Data)
>
> +## = LLC size - 0.5M
>
> +## 2) PcdTemporaryRamSize <= Maximum CPU NEM data size
>
> +## = MLC size
>
> +## NOTE: The size restriction may be changed in next generation processor.
>
> +## Please refer to Processor BWG for detail.
>
> +##
>
> +gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress|0xFF800000|UINT32|0x1
> 0000001
>
> +gSiPkgTokenSpaceGuid.PcdBiosSize|0x00800000|UINT32|0x10000002
>
> +gSiPkgTokenSpaceGuid.PcdTemporaryRamBase|0xfef00000|UINT32|0x000
> 10028
>
> +gSiPkgTokenSpaceGuid.PcdTemporaryRamSize|0x2000|UINT32|0x0001002
> 9
>
> +gSiPkgTokenSpaceGuid.PcdTopMemoryCacheSize|0x0|UINT32|0x0001002
> A
>
> +gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase|0xFFE60000|UINT32|0x
> 30000004
>
> +gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize|0x000A0000|UINT32|0x3
> 0000005
>
> +gSiPkgTokenSpaceGuid.PcdFlashMicrocodeOffset|0x00000060|UINT32|0x3
> 0000013
>
> +gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset|0x00660000|UINT32|0
> x30000006
>
> +##
>
> +## The CPU Trace Hub's BARs base and size
>
> +##
>
> +gSiPkgTokenSpaceGuid.PcdCpuTraceHubMtbBarBase|0xfad00000|UINT32|
> 0x30000007
>
> +gSiPkgTokenSpaceGuid.PcdCpuTraceHubMtbBarSize|0x100000|UINT32|0x
> 30000008
>
> +gSiPkgTokenSpaceGuid.PcdCpuTraceHubSwBarBase|0xfc000000|UINT32|0
> x30000009
>
> +gSiPkgTokenSpaceGuid.PcdCpuTraceHubSwBarSize|0x800000|UINT32|0x30
> 00000A
>
> +gSiPkgTokenSpaceGuid.PcdCpuTraceHubRtitBarBase|0xfacfc000|UINT32|0
> x3000000B
>
> +gSiPkgTokenSpaceGuid.PcdCpuTraceHubRtitBarSize|0x4000|UINT32|0x300
> 0000C
>
> +gSiPkgTokenSpaceGuid.PcdCpuTraceHubFwBarBase|0xfae00000|UINT32|0
> x3000000D
>
> +gSiPkgTokenSpaceGuid.PcdCpuTraceHubFwBarSize|0x200000|UINT32|0x30
> 00000E
>
> +
>
> +gSiPkgTokenSpaceGuid.PcdFspWrapperEnable
> |FALSE|BOOLEAN|0x3000000F
>
> +gSiPkgTokenSpaceGuid.PcdFspBinaryEnable|FALSE|BOOLEAN|0x30000010
>
> +gSiPkgTokenSpaceGuid.PcdEmbeddedEnable|0x0|UINT8|0x30000012
>
> +
>
> +##
>
> +## PcdEfiGcdAllocateType is using for EFI_GCD_ALLOCATE_TYPE selection
>
> +## value of the struct
>
> +## 0x00 EfiGcdAllocateAnySearchBottomUp
>
> +## 0x01 EfiGcdAllocateMaxAddressSearchBottomUp
>
> +## 0x03 EfiGcdAllocateAnySearchTopDown
>
> +## 0x04 EfiGcdAllocateMaxAddressSearchTopDown
>
> +##
>
> +## below value should not using in this situation
>
> +## 0x05 EfiGcdMaxAllocateType : design for max value of struct
>
> +## 0x02 EfiGcdAllocateAddress : design for speccification address allocate
>
> +##
>
> +gSiPkgTokenSpaceGuid.PcdEfiGcdAllocateType|0x01|UINT8|0x40000000
>
> +
>
> +##
>
> +## Handshake register value driven to DMA controller PCIE venodr specific
> configuration register from FW
>
> +## (LC/CM to host)
>
> +##
>
> +gSiPkgTokenSpaceGuid.PcdITbtToPcieRegister|0xEC|UINT8|0x40000003
>
> +##
>
> +## Handshake register value driven from DMA controller PCIE venodr
> specific configuration register to FW
>
> +## (HOST to LC/CM)
>
> +##
>
> +gSiPkgTokenSpaceGuid.PcdPcieToITbtRegister|0xF0|UINT8|0x40000004
>
> +
>
> +gSiPkgTokenSpaceGuid.PcdAbove4GBMmioBase|0x0000004000000000|UIN
> T64|0x40000005
>
> +gSiPkgTokenSpaceGuid.PcdAbove4GBMmioSize|0x0000004000000000|UIN
> T64|0x40000006
>
> +
>
> +gSiPkgTokenSpaceGuid.PcdSmmEntryPointBinFile|{ 0x52, 0xce, 0xc8, 0xe0,
> 0x51, 0x2b, 0xc2, 0x4c, 0xb3, 0xc7, 0xd2, 0x11, 0xa6, 0x25, 0xc1, 0xba
> }|VOID*|0x40000007
>
> +gSiPkgTokenSpaceGuid.PcdSpsBinFile|{ 0xEE, 0xE3, 0x34, 0x71, 0xA6, 0x7F,
> 0x89, 0x44, 0x87, 0xA7, 0xAE, 0x38, 0x98, 0x4E, 0xAE, 0xD8
> }|VOID*|0x40000008
>
> +gSiPkgTokenSpaceGuid.PcdSpsSmmEntryPointBinFile|{ 0x5B, 0x63, 0x7D,
> 0x7C, 0x9C, 0x8B, 0x3C, 0x46, 0x9F, 0x7F, 0x91, 0xF6, 0x09, 0x06, 0x84, 0x8F
> }|VOID*|0x40000009
>
> +gSiPkgTokenSpaceGuid.PcdSpaBinFile|{ 0xE1, 0x19, 0xB7, 0x7B, 0x2A, 0x53,
> 0x40, 0x7B, 0xA3, 0x4C, 0xC4, 0xF9, 0xE2, 0x6C, 0x27, 0x74
> }|VOID*|0x4000000A
>
> +gSiPkgTokenSpaceGuid.PcdSpaSmmEntryPointBinFile|{ 0xD7, 0xAD, 0xB2,
> 0x9F, 0x4D, 0x53, 0x4B, 0xA6, 0x8D, 0x55, 0x5D, 0x28, 0x91, 0x60, 0x10, 0x19
> }|VOID*|0x4000000B
>
> +
>
> +##
>
> +## - DpIn Silicon Feature
>
> +##
>
> +# Note: PcdDpInEnable is Default Disable. Override it based on Platform/
> CPU
>
> +gSiPkgTokenSpaceGuid.PcdDpInEnable|FALSE|BOOLEAN|0x4000000C
>
> +# Note: For PcdMaxDpInExtPortSupported, we can have Maximum value
> of 0x08.
>
> +# Please Don't exceed beyond that. As it will cause boundary overflow.
>
> +# Currently hadrware wise maximum Dp-In External Port supported is 4.
>
> +# And it will never exceed the value of 0x08. That's why we don't support
>
> +# PcdMaxDpInExtPortSupported value more than 0x08
>
> +gSiPkgTokenSpaceGuid.PcdMaxDpInExtPortSupported|0x4|UINT8|0x4000
> 000D
>
> +
>
> +gSiPkgTokenSpaceGuid.VtdEngine1BaseAddeess|0xFED90000|UINT32|0x5
> 0000001
>
> +gSiPkgTokenSpaceGuid.VtdEngine2BaseAddeess|0xFED92000|UINT32|0x5
> 0000002
>
> +gSiPkgTokenSpaceGuid.VtdEngine3BaseAddeess|0xFED91000|UINT32|0x5
> 0000003
>
> +gSiPkgTokenSpaceGuid.VtdEngine4BaseAddeess|0xFED84000|UINT32|0x5
> 0000004
>
> +gSiPkgTokenSpaceGuid.VtdEngine5BaseAddeess|0xFED85000|UINT32|0x5
> 0000005
>
> +gSiPkgTokenSpaceGuid.VtdEngine6BaseAddeess|0xFED86000|UINT32|0x5
> 0000006
>
> +gSiPkgTokenSpaceGuid.VtdEngine7BaseAddeess|0xFED87000|UINT32|0x5
> 0000007
>
> +##
>
> +## Those PCDs are used to control build process.
>
> +##
>
> +gSiPkgTokenSpaceGuid.PcdTraceHubEnable
> |FALSE|BOOLEAN|0xF0000001
>
> +gSiPkgTokenSpaceGuid.PcdSmmVariableEnable
> |FALSE|BOOLEAN|0xF0000002
>
> +gSiPkgTokenSpaceGuid.PcdAtaEnable
> |FALSE|BOOLEAN|0xF0000004
>
> +gSiPkgTokenSpaceGuid.PcdAcpiEnable |TRUE
> |BOOLEAN|0xF0000009
>
> +gSiPkgTokenSpaceGuid.PcdSourceDebugEnable
> |FALSE|BOOLEAN|0xF000000B
>
> +gSiPkgTokenSpaceGuid.PcdPpmEnable |TRUE
> |BOOLEAN|0xF000000C
>
> +gSiPkgTokenSpaceGuid.PcdIntegratedTouchEnable
> |FALSE|BOOLEAN|0xF000000F
>
> +gSiPkgTokenSpaceGuid.PcdPttEnable
> |FALSE|BOOLEAN|0xF0000011
>
> +gSiPkgTokenSpaceGuid.PcdJhiEnable
> |FALSE|BOOLEAN|0xF0000012
>
> +gSiPkgTokenSpaceGuid.PcdSoftwareGuardEnable
> |FALSE|BOOLEAN|0xF0000013
>
> +gSiPkgTokenSpaceGuid.PcdSmbiosEnable |TRUE
> |BOOLEAN|0xF0000014
>
> +gSiPkgTokenSpaceGuid.PcdS3Enable |TRUE
> |BOOLEAN|0xF0000015
>
> +gSiPkgTokenSpaceGuid.PcdOverclockEnable
> |FALSE|BOOLEAN|0xF0000016
>
> +gSiPkgTokenSpaceGuid.PcdCpuPowerOnConfigEnable
> |FALSE|BOOLEAN|0xF0000017
>
> +gSiPkgTokenSpaceGuid.PcdSsaFlagEnable
> |FALSE|BOOLEAN|0xF0000018
>
> +gSiPkgTokenSpaceGuid.PcdEvLoaderEnable
> |FALSE|BOOLEAN|0xF0000019
>
> +gSiPkgTokenSpaceGuid.PcdIgdEnable |TRUE
> |BOOLEAN|0xF000001A
>
> +gSiPkgTokenSpaceGuid.PcdPegEnable |TRUE
> |BOOLEAN|0xF000001B
>
> +gSiPkgTokenSpaceGuid.PcdSaDmiEnable |TRUE
> |BOOLEAN|0xF000001C
>
> +gSiPkgTokenSpaceGuid.PcdGnaEnable |FALSE
> |BOOLEAN|0xF000001E
>
> +gSiPkgTokenSpaceGuid.PcdVtdEnable |TRUE
> |BOOLEAN|0xF0000020
>
> +gSiPkgTokenSpaceGuid.PcdBiosGuardEnable
> |FALSE|BOOLEAN|0xF0000021
>
> +gSiPkgTokenSpaceGuid.PcdSimicsEnable
> |FALSE|BOOLEAN|0xF0000022
>
> +gSiPkgTokenSpaceGuid.PcdBdatEnable
> |FALSE|BOOLEAN|0xF0000023
>
> +gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable |TRUE
> |BOOLEAN|0xF0000024
>
> +gSiPkgTokenSpaceGuid.PcdPeiDisplayEnable |TRUE
> |BOOLEAN|0xF0000025
>
> +gSiPkgTokenSpaceGuid.PcdOcWdtEnable
> |FALSE|BOOLEAN|0xF0000029
>
> +gSiPkgTokenSpaceGuid.PcdMinTreeEnable
> |FALSE|BOOLEAN|0xF000002A # To separate modules used in mininal
> source tree and advanced features
>
> +gSiPkgTokenSpaceGuid.PcdBootGuardEnable
> |FALSE|BOOLEAN|0xF0000030
>
> +gSiPkgTokenSpaceGuid.PcdSerialIoUartEnable
> |FALSE|BOOLEAN|0xF0000033
>
> +gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable
> |FALSE|BOOLEAN|0xF0000037
>
> +gSiPkgTokenSpaceGuid.PcdBfxEnable
> |FALSE|BOOLEAN|0xF000003A
>
> +gSiPkgTokenSpaceGuid.PcdThcEnable
> |FALSE|BOOLEAN|0xF000003B
>
> +
>
> +gSiPkgTokenSpaceGuid.PcdPpamEnable
> |FALSE|BOOLEAN|0xF000003F
>
> +gSiPkgTokenSpaceGuid.PcdPsmiEnable
> |FALSE|BOOLEAN|0xF0000042
>
> +gSiPkgTokenSpaceGuid.PcdCpuPcieEnable |TRUE
> |BOOLEAN|0xF0000043
>
> +gSiPkgTokenSpaceGuid.PcdHybridStorageSupport
> |FALSE|BOOLEAN|0xF0000044
>
> +gSiPkgTokenSpaceGuid.PcdMrcTraceMessageSupported |TRUE
> |BOOLEAN|0xF0000045
>
> +gSiPkgTokenSpaceGuid.PcdTmeLibSupported
> |FALSE|BOOLEAN|0xF0000046
>
> +gSiPkgTokenSpaceGuid.PcdAdlLpSupport
> |FALSE|BOOLEAN|0xF0000047
>
> +gSiPkgTokenSpaceGuid.PcdSpsStateSaveEnable
> |FALSE|BOOLEAN|0xF0000048
>
> +gSiPkgTokenSpaceGuid.PcdSpaEnable
> |FALSE|BOOLEAN|0xF0000049
>
> +
>
> +## PCD for TraceHub
>
> +[PcdsDynamic, PcdsPatchableInModule]
>
> +## From MdeModulePkg.dec
>
> +## Default OEM ID for ACPI table creation, its length must be 0x6 bytes to
> follow ACPI specification.
>
> +gSiPkgTokenSpaceGuid.PcdAcpiDefaultOemId|"INTEL "|VOID*|0x30001034
>
> +## Default OEM Table ID for ACPI table creation, it is "EDK2 ".
>
> +gSiPkgTokenSpaceGuid.PcdAcpiDefaultOemTableId|0x20202020324B4445|
> UINT64|0x30001035
>
> +## Default OEM Revision for ACPI table creation.
>
> +gSiPkgTokenSpaceGuid.PcdAcpiDefaultOemRevision|0x00000002|UINT32|
> 0x30001036
>
> +## Default Creator ID for ACPI table creation.
>
> +gSiPkgTokenSpaceGuid.PcdAcpiDefaultCreatorId|0x20202020|UINT32|0x30
> 001037
>
> +## Default Creator Revision for ACPI table creation.
>
> +gSiPkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision|0x01000013|UINT3
> 2|0x30001038
>
> +## ME HECI interface configuration
>
> +gMeConfigSpaceGuid.PcdHeciDumpsEnabled|TRUE|BOOLEAN|0x50000001
>
> +gMeConfigSpaceGuid.PcdHeciTimeoutsEnabled|TRUE|BOOLEAN|0x500000
> 02
>
> +
>
> +
>
> +[PcdsFixedAtBuild, PcdsPatchableInModule]
>
> +## This value is used to set the base address of PCH devices
>
> +gSiPkgTokenSpaceGuid.PcdSmbusBaseAddress|0x0000EFA0|UINT16|0x000
> 10031
>
> +gSiPkgTokenSpaceGuid.PcdTcoBaseAddress|0x0400|UINT16|0x00010033
>
> +gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress|0x1800|UINT16|0x00010035
>
> +
>
> +
>
> +## Stack size in the temporary RAM.
>
> +## 0 means half of TemporaryRamSize.
>
> +gSiPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0|UINT32|0x00010
> 036
>
> +##
>
> +## PcdFviSmbiosType determines the SMBIOS OEM type (0x80 to 0xFF)
> defined in SMBIOS,
>
> +## values 0-0x7F will be treated as disable FVI reporting.
>
> +## FVI structure uses it as SMBIOS OEM type to provide version
> information.
>
> +##
>
> +gSiPkgTokenSpaceGuid.PcdFviSmbiosType|0xDD|UINT8|0x00010037
>
> +gSiPkgTokenSpaceGuid.PcdSaPciPrint|FALSE|BOOLEAN|0x00010039
>
> +##
>
> +## SMBIOS defaults
>
> +##
>
> +gSiPkgTokenSpaceGuid.PcdSmbiosDefaultSocketDesignation|"U3E1"|VOID
> *|0x0001003a
>
> +gSiPkgTokenSpaceGuid.PcdSmbiosDefaultSerialNumber|"To Be Filled By
> O.E.M."|VOID*|0x0001003b
>
> +gSiPkgTokenSpaceGuid.PcdSmbiosDefaultAssetTag|"To Be Filled By
> O.E.M."|VOID*|0x0001003c
>
> +gSiPkgTokenSpaceGuid.PcdSmbiosDefaultPartNumber|"To Be Filled By
> O.E.M."|VOID*|0x0001003d
>
> +
>
> +##
>
> +## Allocate 56 KB [0x2000..0xFFFF] of I/O space for Pci Devices
>
> +## If PcdPciReservedMemLimit =0 Pci Reserved default MMIO Limit is
> 0xE0000000 else use PcdPciReservedMemLimit .
>
> +##
>
> +gSiPkgTokenSpaceGuid.PcdPciReservedIobase |0x2000
> |UINT16|0x00010041
>
> +gSiPkgTokenSpaceGuid.PcdPciReservedIoLimit |0xFFFF
> |UINT16|0x00010042
>
> +gSiPkgTokenSpaceGuid.PcdPciReservedMemLimit |0x0000
> |UINT32|0x00010043
>
> +gSiPkgTokenSpaceGuid.PcdPciDmaAbove4G |FALSE
> |BOOLEAN|0x00010044
>
> +gSiPkgTokenSpaceGuid.PcdPciNoExtendedConfigSpace|FALSE
> |BOOLEAN|0x00010045
>
> +
>
> +##
>
> +## Default 8MB TSEG for Release build BIOS when IED disabled (Also a
> default)
>
> +##
>
> +gSiPkgTokenSpaceGuid.PcdTsegSize|0x00800000|UINT32|0x00010046
>
> +##
>
> +## gSiPkgTokenSpaceGuid.PcdFwStsSmbiosType determines the SMBIOS
> OEM type (0x80 to 0xFF) defined
>
> +## in SMBIOS, values 0-0x7F will be treated as disable FWSTS SMBIOS
> reporting.
>
> +## FWSTS structure uses it as SMBIOS OEM type to provide FWSTS
> information.
>
> +##
>
> +gSiPkgTokenSpaceGuid.PcdFwStsSmbiosType|0xDB|UINT8|0x00010047
>
> +
>
> +##
>
> +## Maximum Address the AP Wakeup Buffer can start.
>
> +##
>
> +gSiPkgTokenSpaceGuid.PcdCpuApWakeupBufferMaxAddr|0x58000|UINT3
> 2|0x00010048
>
> +
>
> +##
>
> +## Silicon Reference Code versions
>
> +##
>
> +##Revision:Weekly build number
>
> +gSiPkgTokenSpaceGuid.PcdSiliconInitVersionRevision|0x33|UINT8|0x00010
> 051
>
> +
>
> +##Build[7:4]:Daily build number.
>
> +##Build[3:0]:Patch build number.
>
> +
>
> +##
>
> +## Temp MEM IO resource
>
> +##
>
> +gSiPkgTokenSpaceGuid.PcdSiliconInitTempPciBusMin |2 |UINT8
> |0x00010053
>
> +gSiPkgTokenSpaceGuid.PcdSiliconInitTempPciBusMax |10 |UINT8
> |0x00010054
>
> +gSiPkgTokenSpaceGuid.PcdSiliconInitTempMemBaseAddr
> |0xFE600000|UINT32|0x00010055
>
> +gSiPkgTokenSpaceGuid.PcdSiliconInitTempMemSize
> |0x00200000|UINT32|0x00010056
>
> +
>
> +##
>
> +## This PCD specifies the base address of the HPET timer.
>
> +## The acceptable values are 0xFED00000, 0xFED01000, 0xFED02000, and
> 0xFED03000
>
> +##
>
> +gSiPkgTokenSpaceGuid.PcdSiHpetBaseAddress
> |0xFED00000|UINT32|0x00010057
>
> +##
>
> +## This PCD specifies the base address of the IO APIC.
>
> +## The acceptable values are 0xFECxx000.
>
> +##
>
> +gSiPkgTokenSpaceGuid.PcdSiIoApicBaseAddress
> |0xFEC00000|UINT32|0x00010058
>
> +
>
> +
>
> +##
>
> +## VTD Base Addresses
>
> +##
>
> +
>
> +## Null-terminated string of the Version of Physical Presence interface
> supported by platform.
>
> +# @Prompt Version of Physical Presence interface supported by platform.
>
> +gSiPkgTokenSpaceGuid.PcdTcgPhysicalPresenceInterfaceVer|"1.3"|VOID*|
> 0x00000008
>
> +
>
> +## This PCD specifies Master of TraceHub device
>
> +gSiPkgTokenSpaceGuid.PcdTraceHubDebugLibMaster|0x0|UINT32|0x0001
> 1000
>
> +## This PCD specifies Channel of TraceHub device
>
> +gSiPkgTokenSpaceGuid.PcdTraceHubDebugLibChannel|0x0|UINT32|0x0001
> 1001
>
> +
>
> +
>
> +[PcdsPatchableInModule, PcdsFixedAtBuild]
>
> +## This value is used to set the base address of MCH
>
> +gSiPkgTokenSpaceGuid.PcdMchBaseAddress|0xFEDC0000|UINT64|0x00010
> 030
>
> +## 128KB window
>
> +gSiPkgTokenSpaceGuid.PcdMchMmioSize|0x20000|UINT32|0x50000000
>
> +gSiPkgTokenSpaceGuid.PcdSiliconInitVersionMajor
> |0x0A|UINT8|0x00010049
>
> +gSiPkgTokenSpaceGuid.PcdSiliconInitVersionValue
> |0x0000000800260020|UINT64|0x00010077
>
> +
>
> +##Minor:the program that supported by same core generation.
>
> +gSiPkgTokenSpaceGuid.PcdSiliconInitVersionMinor
> |0x00|UINT8|0x00010050
>
> +
>
> +gSiPkgTokenSpaceGuid.PcdSiliconInitVersionBuild
> |0x10|UINT8|0x00010052
>
> +gSiPkgTokenSpaceGuid.PcdRegBarBaseAddress|0xFB000000|UINT32|0x000
> 10059
>
> +[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]
>
> +##
>
> +## SerialIo Uart Configuration
>
> +##
>
> +gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugEnable |0 |UINT8
> |0x00210001 # 0:Disable, 1:Enable and Initialize, 2:Enable without Initializing
>
> +gSiPkgTokenSpaceGuid.PcdSerialIoUartNumber |2 |UINT8
> |0x00210002
>
> +gSiPkgTokenSpaceGuid.PcdSerialIoUartMode |2 |UINT8
> |0x00210003 # 0:Disabled, 1:Enabled, 2:Hidden, 3:COM, 4:SkipInit
>
> +gSiPkgTokenSpaceGuid.PcdSerialIoUartBaudRate |115200
> |UINT32|0x00210004 # 0:Default, Max:6000000
>
> +gSiPkgTokenSpaceGuid.PcdSerialIoUartParity |1 |UINT8
> |0x00210008 # 0:DefaultParity, 1:NoParity, 2:EvenParity, 3:OddParity
>
> +gSiPkgTokenSpaceGuid.PcdSerialIoUartDataBits |8 |UINT8
> |0x00210009 # 0:Default, 5,6,7,8
>
> +gSiPkgTokenSpaceGuid.PcdSerialIoUartStopBits |1 |UINT8
> |0x0021000A # 0:DefaultStopBits, 1:OneStopBit, 2:OneFiveStopBits,
> 3:TwoStopBits
>
> +gSiPkgTokenSpaceGuid.PcdSerialIoUartAutoFlow |0 |UINT8
> |0x0021000B # 0:No HW flow control, Only RX/TX Enabled; 1:HW Flow Control
> On, Rts/Cts lines enabled;
>
> +gSiPkgTokenSpaceGuid.PcdSerialIoUartRxPinMux |0x0
> |UINT32|0x0021000C # Pin muxing config for UART Rx pin
>
> +gSiPkgTokenSpaceGuid.PcdSerialIoUartTxPinMux |0x0
> |UINT32|0x00210010 # Pin muxing config for UART Tx pin
>
> +gSiPkgTokenSpaceGuid.PcdSerialIoUartRtsPinMux |0x0
> |UINT32|0x00210014 # Pin muxing config for UART Rts pin
>
> +gSiPkgTokenSpaceGuid.PcdSerialIoUartCtsPinMux |0x0
> |UINT32|0x00210018 # Pin muxing config for UART Cts pin
>
> +gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugMmioBase |0xFE036000
> |UINT32|0x0021001C # PcdSerialIoUartMode = Enabled, need to assign
> MMIO Resource in SEC/PEI Phase
>
> +
>
> +gSiPkgTokenSpaceGuid.PcdLpcUartDebugEnable |0x1 |UINT8
> |0x00210026 # 0:Disable, 1:Enable
>
> +gSiPkgTokenSpaceGuid.PcdDebugInterfaceFlags |0x12 |UINT8
> |0x00210027 # BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-
> TraceHub, BIT2 - Not used.
>
> +gSiPkgTokenSpaceGuid.PcdSerialDebugLevel |0x3 |UINT8
> |0x00210028 # {0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error
> Warnings and Info, 4:Load Error Warnings and Info, 5:Load Error Warnings
> Info and Verbose
>
> +gSiPkgTokenSpaceGuid.PcdIsaSerialUartBase |0x0 |UINT8
> |0x00210029 # 0:0x3F8, 1:0x2F8
>
> +
>
> +## UART Lib TimeOut
>
> +gSiPkgTokenSpaceGuid.PcdSerialIoUartTimeOut |1000000 |UINT32
> |0x00210020 # Write TimeOut in Micro Seconds - 0 = disabbled, default 1
> second,
>
> +gSiPkgTokenSpaceGuid.PcdSerialIoUartLibSkipMmioCheck |FALSE
> |BOOLEAN|0x00210024 # If TRUE MMIO sanity checks are skipped
>
> +
>
> +## UART Dxe Driver IgnoreBaudRateSet
>
> +## TRUE - Blocks changing BaudRate, so that driver will not override UART's
> initial configuration.
>
> +## Required to support redirection on higher BaudRates.
>
> +## FALSE - Allows for UART settings to be changed through the Serial Io
> Protocol
>
> +##
>
> +gSiPkgTokenSpaceGuid.PcdSerialIoUartDriverIgnoreBaudRateSet|FALSE|B
> OOLEAN|0x00210025
>
> +
>
> +##
>
> +## SerialIo 2nd Uart Configuration
>
> +##
>
> +gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartEnable |0 |UINT8
> |0x0021002A # 0:Disable, 1:Enable and Initialize, 2:Enable without Initializing
>
> +gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartNumber |2 |UINT8
> |0x0021002B
>
> +gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartMode |2 |UINT8
> |0x0021002C # 0:Disabled, 1:Enabled, 2:Hidden, 3:COM, 4:SkipInit
>
> +gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartBaudRate |115200
> |UINT32|0x0021002D # 0:Default, Max:6000000
>
> +gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartParity |1 |UINT8
> |0x00210031 # 0:DefaultParity, 1:NoParity, 2:EvenParity, 3:OddParity
>
> +gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartDataBits |8 |UINT8
> |0x00210032 # 0:Default, 5,6,7,8
>
> +gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartStopBits |1 |UINT8
> |0x00210033 # 0:DefaultStopBits, 1:OneStopBit, 2:OneFiveStopBits,
> 3:TwoStopBits
>
> +gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartAutoFlow |0 |UINT8
> |0x00210034 # 0:No HW flow control, Only RX/TX Enabled; 1:HW Flow Control
> On, Rts/Cts lines enabled;
>
> +gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartRxPinMux |0x0
> |UINT32|0x00210035 # Pin muxing config for UART Rx pin
>
> +gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartTxPinMux |0x0
> |UINT32|0x00210039 # Pin muxing config for UART Tx pin
>
> +gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartRtsPinMux |0x0
> |UINT32|0x0021003D # Pin muxing config for UART Rts pin
>
> +gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartCtsPinMux |0x0
> |UINT32|0x00210041 # Pin muxing config for UART Cts pin
>
> +gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartMmioBase |0xFE034000
> |UINT32|0x00210045 # PcdSerialIoUartMode = Enabled, need to assign
> MMIO Resource in SEC/PEI Phase
>
> +
>
> +##
>
> +## PCI Express MMIO region length
>
> +## Valid settings: 0x20000000/512MB, 0x10000000/256MB,
> 0x8000000/128MB, 0x4000000/64MB
>
> +##
>
> +gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000|UINT32|0
> x00200001
>
> +##
>
> +## Typically this should be the same with
> gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress.
>
> +## This PCD is added for supporting different PCD type in different phases.
>
> +##
>
> +gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress
> |0xC0000000|UINT64|0x00200002
>
> +##
>
> +## PCI Express MMIO temporary region length in SEC phase.
>
> +## Valid settings: 0x20000000/512MB, 0x10000000/256MB,
> 0x8000000/128MB, 0x4000000/64MB
>
> +##
>
> +gSiPkgTokenSpaceGuid.PcdTemporaryPciExpressRegionLength|0x10000000
> |UINT32|0x00200005
>
> +
>
> +## Specifies the SMRR2 base address.<BR><BR>
>
> +# @Prompt SMRR2 base address.
>
> +# @Expression 0x80000001 |
> (gSiPkgTokenSpaceGuid.PcdCpuSmmSmrr2Base & 0xfff) == 0
>
> +gSiPkgTokenSpaceGuid.PcdCpuSmmSmrr2Base|0|UINT32|0x20000002
>
> +
>
> +## Specifies the SMRR2 range size.<BR><BR>
>
> +# @Prompt SMRR2 range size.
>
> +# @Expression 0x80000001 |
> (gSiPkgTokenSpaceGuid.PcdCpuSmmSmrr2Size & 0xfff) == 0
>
> +gSiPkgTokenSpaceGuid.PcdCpuSmmSmrr2Size|0|UINT32|0x20000003
>
> +
>
> +## Specifies the SMRR2 range cache type.
>
> +# If SMRR2 is used to map a flash/ROM based handler, it would be
> configured as WP.<BR><BR>
>
> +# 5: WP(Write Protect).<BR>
>
> +# 6: WB(Write Back).<BR>
>
> +# @Prompt SMRR2 range cache type.
>
> +gSiPkgTokenSpaceGuid.PcdCpuSmmSmrr2CacheType|5|UINT8|0x20000004
>
> +
>
> +## Indidates if SMM PROT MODE feature is supported.<BR><BR>
>
> +# TRUE - SMM PROT MODE feature is supported.<BR>
>
> +# FALSE - SMM PROT MODE feature is not supported.<BR>
>
> +# @Prompt SMM PROT MODE feature.
>
> +gSiPkgTokenSpaceGuid.PcdCpuSmmProtectedModeEnable|FALSE|BOOLEA
> N|0x20000008
>
> +
>
> +## Specifies the a size of memory region to reserve in SMM for testing only.
>
> +# One can look in BIOS serial log for PCD to get region base address.
>
> +# Note: A different region may be allocated in release build than debug
> build.
>
> +# @Prompt SMM test region size.\r
>
> +gSiPkgTokenSpaceGuid.PcdSmmTestRsvMemorySize|0x0|UINT32|0x20000
> 00E
>
> +
>
> +[PcdsDynamic]
>
> +
>
> +## Indidates if SMM Code Access Check feature is supported.<BR><BR>
>
> +# TRUE - SMM Code Access Check feature is supported.<BR>
>
> +# FALSE - SMM Code Access Check feature is not supported.<BR>
>
> +# @Prompt SMM Code Access Check feature.
>
> +gSiPkgTokenSpaceGuid.PcdCpuSmmCodeAccessCheckEnable|TRUE|BOOLE
> AN|0x001000D
>
> +
>
> +## Causes all UEFI variables to be treated as volatile and hence never
> written to non-volatile
>
> +## storage.
>
> +## This is useful in cases such as a simulation environment that does not
> emulate a non-volatile
>
> +## storage device or in recovery scenarios where system errors prevent
> non-volatile storage from being accessed
>
> +gSiPkgTokenSpaceGuid.PcdNvVariableEmulationMode|FALSE|BOOLEAN|0
> x0010000E
>
> +
>
> +## Enables or disables storage of UEFI variables using the CSE Variable
> Storage drivers
>
> +## If disabled at runtime, it must be set before the CSE Variable Storage
> driver loads.
>
> +gSiPkgTokenSpaceGuid.PcdEnableCseVariableStorage|FALSE|BOOLEAN|0x
> 0010000F
>
> +
>
> +## Enables or disables storage of UEFI variables using the FVB Variable
> Storage drivers
>
> +## If disabled at runtime, it must be set before the FVB Variable Storage
> driver loads.
>
> +gSiPkgTokenSpaceGuid.PcdEnableFvbVariableStorage|TRUE|BOOLEAN|0x0
> 0100010
>
> +
>
> --
> 2.24.0.windows.2
prev parent reply other threads:[~2021-02-04 3:51 UTC|newest]
Thread overview: 81+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-01 1:36 [PATCH 01/40] TigerlakeSiliconPkg: Add package and Include/ConfigBlock headers Heng Luo
2021-02-01 1:36 ` [PATCH 02/40] TigerlakeSiliconPkg/Include: Add Library, PPI and Protocol include headers Heng Luo
2021-02-04 3:51 ` Nate DeSimone
2021-02-01 1:36 ` [PATCH 03/40] TigerlakeSiliconPkg/Include: Add Pins, Register and other " Heng Luo
2021-02-04 3:52 ` Nate DeSimone
2021-02-01 1:36 ` [PATCH 04/40] TigerlakeSiliconPkg/Cpu: Add Include headers Heng Luo
2021-02-04 3:53 ` Nate DeSimone
2021-02-01 1:36 ` [PATCH 05/40] TigerlakeSiliconPkg/Pch: Add include headers Heng Luo
2021-02-04 3:53 ` Nate DeSimone
2021-02-01 1:36 ` [PATCH 06/40] TigerlakeSiliconPkg/Pch: Add IncludePrivate headers Heng Luo
2021-02-04 3:53 ` Nate DeSimone
2021-02-01 1:36 ` [PATCH 07/40] TigerlakeSiliconPkg/SystemAgent: Add include headers Heng Luo
2021-02-04 3:53 ` Nate DeSimone
2021-02-01 1:36 ` [PATCH 08/40] TigerlakeSiliconPkg/SystemAgent: Add IncludePrivate headers Heng Luo
2021-02-04 3:53 ` Nate DeSimone
2021-02-01 1:36 ` [PATCH 09/40] TigerlakeSiliconPkg/Fru: Add TglCpu/Include headers Heng Luo
2021-02-04 3:53 ` Nate DeSimone
2021-02-01 1:36 ` [PATCH 10/40] TigerlakeSiliconPkg/Fru: Add TglCpu/IncludePrivate headers Heng Luo
2021-02-04 3:53 ` Nate DeSimone
2021-02-01 1:36 ` [PATCH 11/40] TigerlakeSiliconPkg/Fru: Add TglPch/Include headers Heng Luo
2021-02-04 3:53 ` Nate DeSimone
2021-02-01 1:36 ` [PATCH 12/40] TigerlakeSiliconPkg/Fru: Add TglPch/IncludePrivate headers Heng Luo
2021-02-04 3:53 ` Nate DeSimone
2021-02-01 1:36 ` [PATCH 13/40] TigerlakeSiliconPkg/IpBlock: Add Cnvi component Heng Luo
2021-02-04 3:53 ` Nate DeSimone
2021-02-01 1:36 ` [PATCH 14/40] TigerlakeSiliconPkg/IpBlock: Add CpuPcieRp component Heng Luo
2021-02-04 3:53 ` Nate DeSimone
2021-02-01 1:36 ` [PATCH 15/40] TigerlakeSiliconPkg/IpBlock: Add Espi component Heng Luo
2021-02-04 3:54 ` Nate DeSimone
2021-02-01 1:36 ` [PATCH 16/40] TigerlakeSiliconPkg/IpBlock: Add Gbe component Heng Luo
2021-02-04 3:54 ` Nate DeSimone
2021-02-01 1:36 ` [PATCH 17/40] TigerlakeSiliconPkg/IpBlock: Add Gpio component Heng Luo
2021-02-04 3:54 ` Nate DeSimone
2021-02-01 1:36 ` [PATCH 18/40] TigerlakeSiliconPkg/IpBlock: Add Graphics component Heng Luo
2021-02-04 3:54 ` Nate DeSimone
2021-02-01 1:36 ` [PATCH 19/40] TigerlakeSiliconPkg/IpBlock: Add Hda component Heng Luo
2021-02-04 3:54 ` Nate DeSimone
2021-02-01 1:36 ` [PATCH 20/40] TigerlakeSiliconPkg/IpBlock: Add HostBridge component Heng Luo
2021-02-04 3:54 ` Nate DeSimone
2021-02-01 1:36 ` [PATCH 21/40] TigerlakeSiliconPkg/IpBlock: Add P2sb component Heng Luo
2021-02-04 3:54 ` Nate DeSimone
2021-02-01 1:36 ` [PATCH 22/40] TigerlakeSiliconPkg/IpBlock: Add PchDmi component Heng Luo
2021-02-04 3:54 ` Nate DeSimone
2021-02-01 1:36 ` [PATCH 23/40] TigerlakeSiliconPkg/IpBlock: Add PcieRp component Heng Luo
2021-02-04 3:55 ` Nate DeSimone
2021-02-01 1:36 ` [PATCH 24/40] TigerlakeSiliconPkg/IpBlock: Add Pmc component Heng Luo
2021-02-04 3:56 ` Nate DeSimone
2021-02-01 1:36 ` [PATCH 25/40] TigerlakeSiliconPkg/IpBlock: Add Psf component Heng Luo
2021-02-04 3:56 ` Nate DeSimone
2021-02-01 1:36 ` [PATCH 26/40] TigerlakeSiliconPkg/IpBlock: Add Sata component Heng Luo
2021-02-04 3:56 ` Nate DeSimone
2021-02-01 1:36 ` [PATCH 27/40] TigerlakeSiliconPkg/IpBlock: Add SerialIo component Heng Luo
2021-02-04 3:56 ` Nate DeSimone
2021-02-01 1:36 ` [PATCH 28/40] TigerlakeSiliconPkg/IpBlock: Add Smbus component Heng Luo
2021-02-04 3:56 ` Nate DeSimone
2021-02-01 1:36 ` [PATCH 29/40] TigerlakeSiliconPkg/IpBlock: Add Spi component Heng Luo
2021-02-04 3:56 ` Nate DeSimone
2021-02-01 1:36 ` [PATCH 30/40] TigerlakeSiliconPkg/IpBlock: Add Vtd component Heng Luo
2021-02-04 3:56 ` Nate DeSimone
2021-02-01 1:36 ` [PATCH 31/40] TigerlakeSiliconPkg/Library: Add package common library instances Heng Luo
2021-02-04 3:56 ` Nate DeSimone
2021-02-01 1:36 ` [PATCH 32/40] TigerlakeSiliconPkg/Pch: Add Pch " Heng Luo
2021-02-04 3:56 ` Nate DeSimone
2021-02-01 1:36 ` [PATCH 33/40] TigerlakeSiliconPkg/Pch: Add Pch private " Heng Luo
2021-02-04 3:56 ` Nate DeSimone
2021-02-01 1:36 ` [PATCH 34/40] TigerlakeSiliconPkg/SystemAgent: Add Acpi Tables and " Heng Luo
2021-02-04 3:56 ` Nate DeSimone
2021-02-01 1:36 ` [PATCH 35/40] TigerlakeSiliconPkg/Fru/TglCpu: Add CpuPcieRp and Vtd " Heng Luo
2021-02-04 3:56 ` Nate DeSimone
2021-02-01 1:36 ` [PATCH 36/40] TigerlakeSiliconPkg/Pch: Add Pch modules Heng Luo
2021-02-04 3:56 ` Nate DeSimone
2021-02-01 1:36 ` [PATCH 37/40] TigerlakeSiliconPkg/SystemAgent: Add SystemAgent modules Heng Luo
2021-02-04 3:56 ` Nate DeSimone
2021-02-01 1:36 ` [PATCH 38/40] TigerlakeSiliconPkg/Fru: Add Fru DSC files Heng Luo
2021-02-04 3:56 ` Nate DeSimone
2021-02-01 1:36 ` [PATCH 39/40] TigerlakeSiliconPkg: Add package " Heng Luo
2021-02-04 3:56 ` Nate DeSimone
2021-02-01 1:36 ` [PATCH 40/40] Maintainers.txt: Add TigerlakeSiliconPkg maintainers Heng Luo
2021-02-04 3:51 ` Nate DeSimone
2021-02-04 8:24 ` Heng Luo
2021-02-04 3:51 ` Nate DeSimone [this message]
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