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Thu, 4 Feb 2021 03:51:20 +0000 From: "Nate DeSimone" To: "Luo, Heng" , "devel@edk2.groups.io" CC: "Chaganty, Rangasai V" Subject: Re: [PATCH 01/40] TigerlakeSiliconPkg: Add package and Include/ConfigBlock headers Thread-Topic: [PATCH 01/40] TigerlakeSiliconPkg: Add package and Include/ConfigBlock headers Thread-Index: AQHW+DrIQmJ4POcerkeo7qGceEZVWKpHVwzw Date: Thu, 4 Feb 2021 03:51:19 +0000 Message-ID: References: <20210201013657.1833-1-heng.luo@intel.com> In-Reply-To: <20210201013657.1833-1-heng.luo@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-reaction: no-action dlp-version: 11.5.1.3 dlp-product: dlpe-windows authentication-results: intel.com; dkim=none (message not signed) header.d=none;intel.com; dmarc=none action=none header.from=intel.com; x-originating-ip: [50.53.190.176] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 0659fec4-8c50-49b9-3052-08d8c8c0221b x-ms-traffictypediagnostic: BN6PR11MB1329: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:10000; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hi Heng, CpuPcieConfigGen3.h is only used on Rocket Lake boards for backwards socket= compatibility with Comet Lake. It is not needed for Tiger Lake. Please rem= ove it. Also, there are some fields missing from CPU_PCIE_CONFIG, please se= e inline. Thanks, Nate > -----Original Message----- > From: Luo, Heng > Sent: Sunday, January 31, 2021 5:36 PM > To: devel@edk2.groups.io > Cc: Chaganty, Rangasai V ; Desimone, > Nathaniel L > Subject: [PATCH 01/40] TigerlakeSiliconPkg: Add package and > Include/ConfigBlock headers >=20 > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3171 >=20 > Create the TigerlakeSiliconPkg to provide an initial package for > silicon initialization code for Tiger Lake (TGL) products. >=20 > * Major areas of functionality are categorized into CPU, IpBlock, Fru, > Platform Controller Hub (PCH), and System Agent subdirectories. > * Common libraries and headers are kept at the root of the package. >=20 > Cc: Sai Chaganty > Cc: Nate DeSimone > Signed-off-by: Heng Luo > --- > Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Cnvi/CnviConfig.h > | 67 ++++++++++++++++++++++++++++++++++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/CpuDmi/CpuDmiPreM > emConfig.h | 86 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/CpuPcieRp/Gen3/CpuP > cieConfigGen3.h | 347 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/CpuPcieRp/Gen4/CpuP > cieConfig.h | 490 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Dci/DciConfig.h > | 72 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Espi/EspiConfig.h > | 61 ++++++++++++++++++++++++++++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Fivr/FivrConfig.h > | 170 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Gbe/GbeConfig.h > | 33 +++++++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Gna/GnaConfig.h > | 31 +++++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Gpio/GpioDevConfig= .h > | 37 ++++++++++++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Graphics/Gen12/Grap= h > icsConfig.h | 211 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Hda/HdAudioConfig.= h > | 227 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++++++++++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/HostBridge/HostBrid= ge > Config.h | 62 > ++++++++++++++++++++++++++++++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/HybridGraphics/Hybr= id > GraphicsConfig.h | 66 > +++++++++++++++++++++++++++++++++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/HybridStorage/Hybri= dS > torageConfig.h | 36 +++++++++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Ieh/IehConfig.h > | 34 ++++++++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Ish/IshConfig.h > | 134 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Itss/InterruptConf= ig.h > | 58 ++++++++++++++++++++++++++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Itss/IoApicConfig.= h > | 60 +++++++++++++++++++++++++++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Me/MePeiConfig.h > | 117 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Memory/Ver2/Memor > yConfig.h | 478 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Overclocking/Overcl= oc > kingConfig.h | 236 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++ > Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/P2sb/P2sbConfig.h > | 34 ++++++++++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/PchDmi/PchDmiConfig= . > h | 44 +++++++++++++++++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/PcieRp/PchPcieRp/Pc= h > PcieRpConfig.h | 368 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/PcieRp/PcieConfig.= h > | 213 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Pmc/AdrConfig.h > | 86 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++ > Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Pmc/PmConfig.h > | 391 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > + > Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Psf/PsfConfig.h > | 32 ++++++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Rst/RstConfig.h > | 82 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++ > Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Rtc/RtcConfig.h > | 38 +++++++++++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Sata/SataConfig.h > | 168 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Scs/ScsConfig.h > | 139 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/SerialIo/SerialIoCo= nfig. > h | 32 ++++++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/SiConfig.h > | 152 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++++++++++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/SiPreMemConfig.h > | 67 ++++++++++++++++++++++++++++++++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Smbus/SmbusConfig.= h > | 50 ++++++++++++++++++++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Spi/SpiConfig.h > | 43 ++++++++++++++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Tcss/TcssPeiConfig= .h > | 145 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Thc/ThcConfig.h > | 73 > +++++++++++++++++++++++++++++++++++++++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Thermal/ThermalConf= i > g.h | 153 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/TraceHub/TraceHubCo > nfig.h | 101 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Usb/Usb2PhyConfig.= h > | 81 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++ > Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Usb/Usb3HsioConfig= .h > | 138 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Usb/UsbConfig.h > | 149 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++++++++++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/VoltageRegulator/Cp= u > PowerMgmtVrConfig.h | 114 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Vtd/VtdConfig.h > | 64 ++++++++++++++++++++++++++++++++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Wdt/WatchDogConfig. > h | 31 +++++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/SiPkg.dec = | 1208 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++ > 49 files changed, 7309 insertions(+) >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Cnvi/CnviConfig.h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Cnvi/CnviConfig.h > new file mode 100644 > index 0000000000..de1f4159f0 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Cnvi/CnviConfig.h > @@ -0,0 +1,67 @@ > +/** @file >=20 > + CNVi policy >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _CNVI_CONFIG_H_ >=20 > +#define _CNVI_CONFIG_H_ >=20 > + >=20 > +#define CNVI_CONFIG_REVISION 1 >=20 > +extern EFI_GUID gCnviConfigGuid; >=20 > + >=20 > +#pragma pack (push,1) >=20 > + >=20 > +/** >=20 > + CNVi Mode options >=20 > +**/ >=20 > +typedef enum { >=20 > + CnviModeDisabled =3D 0, >=20 > + CnviModeAuto >=20 > +} CNVI_MODE; >=20 > + >=20 > + >=20 > +/** >=20 > + CNVi signals pin muxing settings. If signal can be enable only on a si= ngle pin >=20 > + then this parameter is ignored by RC. Refer to GPIO_*_MUXING_CNVI_* > in GpioPins*.h >=20 > + for supported settings on a given platform >=20 > +**/ >=20 > +typedef struct { >=20 > + UINT32 RfReset; ///< RF_RESET# Pin mux configuration. Refer to > GPIO_*_MUXING_CNVI_RF_RESET_* >=20 > + UINT32 Clkreq; ///< CLKREQ Pin mux configuration. Refer to > GPIO_*_MUXING_CNVI_*_CLKREQ_* >=20 > +} CNVI_PIN_MUX; >=20 > + >=20 > +/** >=20 > + The CNVI_CONFIG block describes the expected configuration of the CNVi > IP. >=20 > + >=20 > + Revision 1: >=20 > + - Initial version. >=20 > +**/ >=20 > +typedef struct { >=20 > + CONFIG_BLOCK_HEADER Header; ///< Config Block Header >=20 > + /** >=20 > + This option allows for automatic detection of Connectivity Solution. >=20 > + Auto Detection assumes that CNVi will be enabled when available; >=20 > + Disable allows for disabling CNVi. >=20 > + CnviModeDisabled =3D Disabled, >=20 > + CnviModeAuto =3D Auto Detection >=20 > + **/ >=20 > + UINT32 Mode : 1; >=20 > + UINT32 BtCore : 1; ///< The option to turn ON or OFF t= he BT Core. > 0: Disabled, 1: Enabled >=20 > + /** >=20 > + The option to enable or disable BT Audio Offload. >=20 > + 0: Disabled, 1: Enabled >=20 > + @note This feature only support with Intel(R) Wireless-AX 22560 >=20 > + **/ >=20 > + UINT32 BtAudioOffload : 1; >=20 > + UINT32 RsvdBits : 29; >=20 > + /** >=20 > + CNVi PinMux Configuration >=20 > + RESET#/CLKREQ to CRF, can have two alternative mappings, depending o= n > board routing requirements. >=20 > + **/ >=20 > + CNVI_PIN_MUX PinMux; >=20 > +} CNVI_CONFIG; >=20 > + >=20 > +#pragma pack (pop) >=20 > + >=20 > +#endif // _CNVI_CONFIG_H_ >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/CpuDmi/CpuDmiPre > MemConfig.h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/CpuDmi/CpuDmiPre > MemConfig.h > new file mode 100644 > index 0000000000..527febb0a4 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/CpuDmi/CpuDmiPre > MemConfig.h > @@ -0,0 +1,86 @@ > +/** @file >=20 > + DMI policy >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _CPU_DMI_PREMEM_CONFIG_H_ >=20 > +#define _CPU_DMI_PREMEM_CONFIG_H_ >=20 > + >=20 > +#include >=20 > +#include >=20 > + >=20 > +#define DMI_CONFIG_REVISION 1 >=20 > + >=20 > +#define CPU_DMI_HWEQ_COEFFS_MAX 8 >=20 > + >=20 > +#pragma pack (push,1) >=20 > +/// >=20 > +/// The values before AutoConfig match the setting of PCI Express Base > Specification 1.1, please be careful for adding new feature >=20 > +/// >=20 > +typedef enum { >=20 > + DmiAspmDisabled, >=20 > + DmiAspmL0s, >=20 > + DmiAspmL1, >=20 > + DmiAspmL0sL1, >=20 > + DmiAspmAutoConfig, >=20 > + DmiAspmMax >=20 > +} DMI_ASPM; >=20 > + >=20 > + >=20 > +/** >=20 > + The CPU_DMI_CONFIG block describes the expected configuration of the > CPU for DMI. >=20 > + Revision 1: >=20 > + - Initial version. >=20 > +**/ >=20 > +typedef struct { >=20 > + CONFIG_BLOCK_HEADER Header; ///< Config Block Header >=20 > + >=20 > +/** >=20 > + - Auto (0x0) : Maximum possible link speed (Default) >=20 > + - Gen1 (0x1) : Limit Link to Gen1 Speed >=20 > + - Gen2 (0x2) : Limit Link to Gen2 Speed CpuDmiPreMemConfig >=20 > + - Gen3 (0x3) : Limit Link to Gen3 Speed >=20 > + **/ >=20 > + UINT8 DmiMaxLinkSpeed; >=20 > + /** >=20 > + (Test) DMI Equalization Phase 2 Enable Control >=20 > + - Disabled (0x0) : Disable phase 2 >=20 > + - Enabled (0x1) : Enable phase 2 >=20 > + - Auto (0x2) : Use the current default method (Default) >=20 > + **/ >=20 > + UINT8 DmiGen3EqPh2Enable; >=20 > + /** >=20 > + (Test) Selects the method for performing Phase3 of Gen3 > Equalization on DMI >=20 > + - Auto (0x0) : Use the current default method (Default) >=20 > + - HwEq (0x1) : Use Adaptive Hardware Equalization >=20 > + - SwEq (0x2) : Use Adaptive Software Equalization (Implemented= in > BIOS Reference Code) >=20 > + - Static (0x3) : Use the Static EQs provided in DmiGen3EndPointP= reset > array for Phase1 AND Phase3 (Instead of just Phase1) >=20 > + - Disabled (0x4) : Bypass Equalization Phase 3 >=20 > + **/ >=20 > + UINT8 DmiGen3EqPh3Method; >=20 > + /** >=20 > + (Test) Program DMI Gen3 EQ Phase1 Static Presets >=20 > + - Disabled (0x0) : Disable EQ Phase1 Static Presets Programmin= g >=20 > + - Enabled (0x1) : Enable EQ Phase1 Static Presets Programmin= g > (Default) >=20 > + **/ >=20 > + UINT8 DmiGen3ProgramStaticEq; >=20 > + UINT8 DmiDeEmphasis; //= /< DeEmphasis control > for DMI (-6 dB and -3.5 dB are the options) >=20 > + UINT8 DmiAspm; >=20 > + UINT8 DmiAspmCtrl; //= /< ASPM configuration on > the CPU side of the DMI/OPI Link. Default is DmiAspmAutoConfig >=20 > + UINT8 DmiAspmL1ExitLatency; //= /< ASPM > configuration on the CPU side of the DMI/OPI Link. Default is > DmiAspmAutoConfig >=20 > + UINT8 DmiGen3RootPortPreset[SA_DMI_MAX_LANE]; //= /< > Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is > default for each lane >=20 > + UINT8 DmiGen3EndPointPreset[SA_DMI_MAX_LANE]; //= /< > Used for programming DMI Gen3 preset values per lane. Range: 0-9, 7 is > default for each lane >=20 > + UINT8 DmiGen3EndPointHint[SA_DMI_MAX_LANE]; //= /< Hint > value per lane for the DMI Gen3 End Point. Range: 0-6, 2 is default for e= ach > lane >=20 > + >=20 > + /** >=20 > + DMI Gen3 RxCTLEp per-Bundle control. The range of the setting is (0-1= 5). > This setting >=20 > + has to be specified based upon platform design and must follow the > guideline. Default is 12. >=20 > + **/ >=20 > + >=20 > + UINT8 DmiGen3RxCtlePeaking[SA_DMI_MAX_BUNDLE]; >=20 > +} CPU_DMI_PREMEM_CONFIG; >=20 > + >=20 > +#pragma pack (pop) >=20 > + >=20 > +#endif // _CPU_DMI_CONFIG_H_ >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/CpuPcieRp/Gen3/Cp > uPcieConfigGen3.h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/CpuPcieRp/Gen3/Cp > uPcieConfigGen3.h > new file mode 100644 > index 0000000000..593e63b4f1 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/CpuPcieRp/Gen3/Cp > uPcieConfigGen3.h > @@ -0,0 +1,347 @@ > +/** @file >=20 > +Pcie root port policy >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +#ifndef _CPU_PCIE_CONFIG_GEN3_H_ >=20 > +#define _CPU_PCIE_CONFIG_GEN3_H_ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +#pragma pack(push, 1) >=20 > + >=20 > +#define CPU_PCIE_PEI_PREMEM_CONFIG_GEN3_REVISION 1 >=20 > + >=20 > +#define L0_SET BIT0 >=20 > +#define L1_SET BIT1 >=20 > + >=20 > + >=20 > +/// >=20 > +/// SA GPIO Data Structure >=20 > +/// >=20 > +typedef struct { >=20 > + GPIO_PAD GpioPad; ///< Offset 0: GPIO Pad >=20 > + UINT8 Value; ///< Offset 4: GPIO Value >=20 > + UINT8 Rsvd0[3]; ///< Offset 5: Reserved for 4 bytes alig= nment >=20 > + UINT32 Active : 1; ///< Offset 8: 0=3DActive Low; 1=3DActiv= e High >=20 > + UINT32 RsvdBits0 : 31; >=20 > +} SA_GPIO_INFO_PCIE; >=20 > + >=20 > +/// >=20 > +/// SA Board PEG GPIO Info >=20 > +/// >=20 > +typedef struct { >=20 > + SA_GPIO_INFO_PCIE SaPeg0ResetGpio; ///< Offset 0: PEG0 PERST# > GPIO assigned, must be a PCH GPIO pin >=20 > + SA_GPIO_INFO_PCIE SaPeg3ResetGpio; ///< Offset 12: PEG3 PERST# > GPIO assigned, must be a PCH GPIO pin >=20 > + BOOLEAN GpioSupport; ///< Offset 24: 1=3DSupported; = 0=3DNot > Supported >=20 > + UINT8 Rsvd0[3]; ///< Offset 25: Reserved for 4 = bytes alignment >=20 > +} PEG_GPIO_DATA; >=20 > + >=20 > +/** >=20 > +PCI Express and DMI controller configuration\n >=20 > +@note Optional. These policies will be ignored if there is no PEG > port present on board. >=20 > +Revision 1: >=20 > +- Initial version. >=20 > +**/ >=20 > +typedef struct { >=20 > + CONFIG_BLOCK_HEADER Header; //= /< Offset 0-27 > Config Block Header >=20 > + /** >=20 > + Offset 28:0 : >=20 > + (Test) DMI Link Speed Control >=20 > + - Auto (0x0) : Maximum possible link speed (Default) >=20 > + - Gen1 (0x1) : Limit Link to Gen1 Speed >=20 > + - Gen2 (0x2) : Limit Link to Gen2 Speed >=20 > + - Gen3 (0x3) : Limit Link to Gen3 Speed >=20 > + **/ >=20 > + UINT8 DmiMaxLinkSpeed; >=20 > + /** >=20 > + Offset 28:2 : >=20 > + (Test) DMI Equalization Phase 2 Enable Control >=20 > + - Disabled (0x0) : Disable phase 2 >=20 > + - Enabled (0x1) : Enable phase 2 >=20 > + - Auto (0x2) : Use the current default method (Default) >=20 > + **/ >=20 > + UINT8 DmiGen3EqPh2Enable; >=20 > + /** >=20 > + Offset 28:4 : >=20 > + (Test) Selects the method for performing Phase3 of Gen3 > Equalization on DMI >=20 > + - Auto (0x0) : Use the current default method (Default) >=20 > + - HwEq (0x1) : Use Adaptive Hardware Equalization >=20 > + - SwEq (0x2) : Use Adaptive Software Equalization (Implemented= in > BIOS Reference Code) >=20 > + - Static (0x3) : Use the Static EQs provided in DmiGen3EndPointP= reset > array for Phase1 AND Phase3 (Instead of just Phase1) >=20 > + - Disabled (0x4) : Bypass Equalization Phase 3 >=20 > + **/ >=20 > + UINT8 DmiGen3EqPh3Method; >=20 > + /** >=20 > + Offset 28:7 : >=20 > + (Test) Program DMI Gen3 EQ Phase1 Static Presets >=20 > + - Disabled (0x0) : Disable EQ Phase1 Static Presets Programmin= g >=20 > + - Enabled (0x1) : Enable EQ Phase1 Static Presets Programmin= g > (Default) >=20 > + **/ >=20 > + UINT8 DmiGen3ProgramStaticEq; >=20 > + >=20 > + /** >=20 > + Offset 28:8 to 28:15 : >=20 > + (Test) PEG Enable Control >=20 > + - Disabled (0x0) : Disable PEG Port >=20 > + - Enabled (0x1) : Enable PEG Port (If Silicon SKU permits it) >=20 > + - Auto (0x2) : If an endpoint is present, enable the PEG Port, > Disable otherwise (Default) >=20 > + **/ >=20 > + UINT8 Peg0Enable; ///< Enable/Disable PEG 0:1:= 0 Root Port >=20 > + UINT8 Peg1Enable; ///< (Test) Enable/Di= sable PEG > 0:1:1 Root Port >=20 > + UINT8 Peg2Enable; ///< (Test) Enable/Di= sable PEG > 0:1:2 Root Port >=20 > + UINT8 Peg3Enable; ///< (Test) Enable/Di= sable PEG > 0:6:0 Root Port. Applicable on certain CNL- SKUs and newer silicon. >=20 > + >=20 > + /** >=20 > + Offset 28:16 : >=20 > + (Test) PCIe Link Speed Control >=20 > + - Auto (0x0) : Maximum possible Link speed (Default) >=20 > + - Gen1 (0x1) : Limit Link to Gen1 Speed >=20 > + - Gen2 (0x2) : Limit Link to Gen2 Speed >=20 > + - Gen3 (0x3) : Limit Link to Gen3 Speed >=20 > + **/ >=20 > + UINT8 Peg0MaxLinkSpeed; ///< PCIe Link Speed C= ontrol for > PEG 0:1:0 Root Port. >=20 > + UINT8 Peg1MaxLinkSpeed; ///< (Test) PCI= e Link > Speed Control for PEG 0:1:1 Root Port. >=20 > + UINT8 Peg2MaxLinkSpeed; ///< (Test) PCI= e Link > Speed Control for PEG 0:1:2 Root Port. >=20 > + UINT8 Peg3MaxLinkSpeed; ///< (Test) PCI= e Link > Speed Control for PEG 0:6:0 Root Port. Applicable on certain CNL- SKUs an= d > newer silicon. >=20 > + >=20 > + /** >=20 > + Offset 32:0 : >=20 > + (Test) PCIe Link Width Control >=20 > + - Auto (0x0) : Maximum possible Link width (Default) >=20 > + - X1 (0x1) : Limit Link to X1 Width >=20 > + - X2 (0x2) : Limit Link to X2 Width >=20 > + - X4 (0x3) : Limit Link to X4 Width >=20 > + - X8 (0x4) : Limit Link to X8 Width >=20 > + **/ >=20 > + UINT8 Peg0MaxLinkWidth; ///< PCIe Link Width C= ontrol for > PEG 0:1:0 Root Port. >=20 > + UINT8 Peg1MaxLinkWidth; ///< (Test) PCI= e Link Width > Control for PEG 0:1:1 Root Port. >=20 > + UINT8 Peg2MaxLinkWidth; ///< (Test) PCI= e Link Width > Control for PEG 0:1:2 Root Port. >=20 > + UINT8 Peg3MaxLinkWidth; ///< (Test) PCI= e Link Width > Control for PEG 0:6:0 Root Port. Applicable on certain CNL- SKUs and newe= r > silicon. >=20 > + /** >=20 > + Offset 32:12 to 32:15 : >=20 > + Power down unused lanes on the PEG Root Port. >=20 > + - Disabled (0x0) : No power saving. >=20 > + - Auto (0x1) : Bios will power down unused lanes based on the > max possible link width >=20 > + **/ >=20 > + UINT8 Peg0PowerDownUnusedLanes; ///< Power dow= n > unused lanes on the PEG 0:1:0 Root Port. >=20 > + UINT8 Peg1PowerDownUnusedLanes; ///< Power dow= n > unused lanes on the PEG 0:1:1 Root Port. >=20 > + UINT8 Peg2PowerDownUnusedLanes; ///< Power dow= n > unused lanes on the PEG 0:1:2 Root Port. >=20 > + UINT8 Peg3PowerDownUnusedLanes; ///< Power dow= n > unused lanes on the PEG 0:6:0 Root Port. Applicable on certain CNL- SKUs > and newer silicon. >=20 > + >=20 > + /** >=20 > + Offset 32:16 to 32:23 : >=20 > + (Test) PCIe Equalization Phase 2 Enable Control >=20 > + - Disabled (0x0) : Disable phase 2 >=20 > + - Enabled (0x1) : Enable phase 2 >=20 > + - Auto (0x2) : Use the current default method (Default) >=20 > + **/ >=20 > + UINT8 Peg0Gen3EqPh2Enable; ///< Phase2 EQ enab= le on the > PEG 0:1:0 Root Port. >=20 > + UINT8 Peg1Gen3EqPh2Enable; ///< (Test) = Phase2 EQ > enable on the PEG 0:1:1 Root Port. >=20 > + UINT8 Peg2Gen3EqPh2Enable; ///< (Test) = Phase2 EQ > enable on the PEG 0:1:2 Root Port. >=20 > + UINT8 Peg3Gen3EqPh2Enable; ///< (Test) = Phase2 EQ > enable on the PEG 0:6:0 Root Port. Applicable on certain CNL- SKUs and > newer silicon. >=20 > + >=20 > + /** >=20 > + Offset 36:0 to 36:11 : >=20 > + (Test) Select the method for performing Phase3 of Gen3 > Equalization. >=20 > + - Auto (0x0) : Use the current default method (Default) >=20 > + - HwEq (0x1) : Use Adaptive Hardware Equalization >=20 > + - SwEq (0x2) : Use Adaptive Software Equalization (Implemented= in > BIOS Reference Code) >=20 > + - Static (0x3) : Use the Static EQs provided in PegGen3EndPointP= reset > array for Phase1 AND Phase3 (Instead of just Phase1) >=20 > + - Disabled (0x4) : Bypass Equalization Phase 3 >=20 > + **/ >=20 > + UINT8 Peg0Gen3EqPh3Method; ///< Phase3 EQ meth= od on > the PEG 0:1:0 Root Port. >=20 > + UINT8 Peg1Gen3EqPh3Method; ///< (Test) = Phase3 > EQ method on the PEG 0:1:1 Root Port. >=20 > + UINT8 Peg2Gen3EqPh3Method; ///< (Test) = Phase3 > EQ method on the PEG 0:1:2 Root Port. >=20 > + UINT8 Peg3Gen3EqPh3Method; ///< (Test) = Phase3 > EQ method on the PEG 0:6:0 Root Port. Applicable on certain CNL- SKUs and > newer silicon. >=20 > + /** >=20 > + Offset 36:12 : >=20 > + (Test) Program PEG Gen3 EQ Phase1 Static Presets >=20 > + - Disabled (0x0) : Disable EQ Phase1 Static Presets Programmin= g >=20 > + - Enabled (0x1) : Enable EQ Phase1 Static Presets Programmin= g > (Default) >=20 > + **/ >=20 > + UINT8 PegGen3ProgramStaticEq; >=20 > + /** >=20 > + Offset 36:13 : >=20 > + (Test) Always Attempt Gen3 Software Equalization >=20 > + >=20 > + When enabled, Gen3 Software Equalization will be executed every boot. > When disabled, it will be only executed if the CPU >=20 > + or EP is changed, otherwise it is skipped and the previous EQ value wi= ll be > re-used. >=20 > + >=20 > + This setting will only have an effect if Software Equalization is enab= led and > OEM Platform Code implements >=20 > + save/restore of the PegDataPtr data (see below). If PegDataPtr is not > saved/restored RC forces this to be enabled. >=20 > + >=20 > + - Disabled (0x0) : Reuse EQ settings saved/restored from NVRAM > whenever possible (Default) >=20 > + - Enabled (0x1) : Re-test and generate new EQ values every bo= ot, not > recommended >=20 > + **/ >=20 > + UINT8 Gen3SwEqAlwaysAttempt; >=20 > + /** >=20 > + Offset 36:14 to 36:16 : >=20 > + (Test) Select number of TxEq presets to test in the PCIe/DMI > Software Equalization Algorithm >=20 > + - P7,P3,P5,P8 (0x0) : Test Presets 7, 3, 5, and 8 >=20 > + - P0-P9 (0x1) : Test Presets 0-9 >=20 > + - Auto (0x2) : Use the current default method (Default) >=20 > + Auto will test Presets 7, 3, 5, and 8. It is possible for this defaul= t to change > over time; >=20 > + using "Auto" will ensure Reference Code always uses the latest default > settings. >=20 > + @warning Do not change from the default. Hard to detect issues are li= kely. >=20 > + **/ >=20 > + UINT8 Gen3SwEqNumberOfPresets; >=20 > + /** >=20 > + Offset 36:17 to 36:18: >=20 > + (Test) Offset 36 Enable use of the Voltage Offset and Centering > Test in the PCIe Software Equalization Algorithm >=20 > + - Disabled (0x0) : Disable VOC Test >=20 > + - Enabled (0x1) : Enable VOC Test >=20 > + - Auto (0x2) : Use the current default (Default) >=20 > + **/ >=20 > + UINT8 Gen3SwEqEnableVocTest; >=20 > + /** >=20 > + Offset 36:19 : >=20 > + Select when PCIe ASPM programming will happen in relation to the Oprom >=20 > + - Before (0x0) : Do PCIe ASPM programming before Oprom. > (Default) >=20 > + - After (0x1) : Do PCIe ASPM programming after Oprom. This wil= l > require an SMI handler to save/restore ASPM settings. >=20 > + **/ >=20 > + UINT8 InitPcieAspmAfterOprom; >=20 > + /** >=20 > + Offset 36:20 : >=20 > + (Test) PCIe Rx Compliance Testing Mode >=20 > + - Disabled (0x0) : Normal Operation - Disable PCIe = Rx > Compliance testing (Default) >=20 > + - Enabled (0x1) : PCIe Rx Compliance Test Mode - PEG controlle= r is in Rx > Compliance Testing Mode; it should only be set when doing PCIe compliance > testing >=20 > + **/ >=20 > + UINT8 PegRxCemTestingMode; >=20 > + >=20 > + /** >=20 > + Offset 36:21 to 36:24 : >=20 > + (Test) PCIe Rx Compliance Loopback Lane >=20 > + >=20 > + When PegRxCemTestingMode is Enabled, the specificied Lane (0 - 15) wil= l > be >=20 > + used for RxCEMLoopback. >=20 > + >=20 > + Default is Lane 0. >=20 > + **/ >=20 > + UINT8 PegRxCemLoopbackLane; >=20 > + /** >=20 > + Offset 36:25 to 36:28 : >=20 > + (Test) Generate PCIe BDAT Margin Table. Set this policy to enab= le > the generation and addition of PCIe margin data to the BDAT table. >=20 > + - Disabled (0x0) : Normal Operation - Disable PCIe BDA= T > margin data generation (Default) >=20 > + - PortData (0x1) : Port Data - Generate PCIe BD= AT margin data >=20 > + **/ >=20 > + UINT8 PegGenerateBdatMarginTable; >=20 > + /** >=20 > + Offset 36:29 : >=20 > + (Test) PCIe Non-Protocol Awareness for Rx Compliance Testing >=20 > + - Disabled (0x0) : Normal Operation - Disable no= n-protocol > awareness (Default) >=20 > + - Enabled (0x1) : Non-Protocol Awareness Enabled - Enable non= - > protocol awareness for compliance testing >=20 > + **/ >=20 > + UINT8 PegRxCemNonProtocolAwareness; >=20 > + /** >=20 > + Offset 36:30 : >=20 > + (Test) PCIe Disable Spread Spectrum Clocking. This feature shou= ld > be TRUE only for compliance testing >=20 > + - False (0x0) : Normal Operation - SSC= enabled > (Default) >=20 > + - True (0x1) : Disable SSC - Dis= able SSC for compliance > testing >=20 > + **/ >=20 > + UINT8 PegDisableSpreadSpectrumClocking; >=20 > + >=20 > + UINT8 DmiGen3RootPortPreset[SA_DMI_MAX_LANE_VER1]; > ///< Offset 40 Used for programming DMI Gen3 preset values per lane. > Range: 0-9, 8 is default for each lane >=20 > + UINT8 DmiGen3EndPointPreset[SA_DMI_MAX_LANE_VER1]; > ///< Offset 44 Used for programming DMI Gen3 preset values per lane. > Range: 0-9, 7 is default for each lane >=20 > + UINT8 DmiGen3EndPointHint[SA_DMI_MAX_LANE_VER1]; > ///< Offset 48 Hint value per lane for the DMI Gen3 End Point. Range: 0-6= , 2 is > default for each lane >=20 > + /** >=20 > + Offset 48/60 : >=20 > + DMI Gen3 RxCTLEp per-Bundle control. The range of the setting is (0-15= ). > This setting >=20 > + has to be specified based upon platform design and must follow the > guideline. Default is 12. >=20 > + **/ >=20 > + >=20 > + UINT8 DmiGen3RxCtlePeaking[SA_DMI_MAX_BUNDLE_VER1]; >=20 > + >=20 > + UINT8 PegGen3RootPortPreset[SA_PEG_MAX_LANE_GEN3]; > ///< Offset 54 (Test) Used for programming PEG Gen3 preset values > per lane. Range: 0-9, 8 is default for each lane >=20 > + UINT8 PegGen3EndPointPreset[SA_PEG_MAX_LANE_GEN3]; > ///< Offset 70 (Test) Used for programming PEG Gen3 preset values > per lane. Range: 0-9, 7 is default for each lane >=20 > + UINT8 PegGen3EndPointHint[SA_PEG_MAX_LANE_GEN3]; > ///< Offset 86 (Test) Hint value per lane for the PEG Gen3 End Poi= nt. > Range: 0-6, 2 is default for each lane >=20 > + /** >=20 > + Offset 102: >=20 > + PCIe Gen3 RxCTLEp per-Bundle control. The range of the setting is (0-1= 5). > This setting >=20 > + has to be specified based upon platform design and must follow the > guideline. Default is 12. >=20 > + **/ >=20 > + UINT8 PegGen3RxCtlePeaking[SA_PEG_MAX_BUNDLE_GEN3]; >=20 > + /** >=20 > + Offset 110: >=20 > + (Test)Used for PCIe Gen3 Software Equalization. Range: 0-65535, > default is 1000. >=20 > + @warning Do not change from the default. Hard to detect issues are li= kely. >=20 > + @note An attack on this policy could result in an apparent hang, >=20 > + but the system will eventually boot. This variable should be protecte= d. >=20 > + **/ >=20 > + UINT16 Gen3SwEqJitterDwellTime; >=20 > + /** >=20 > + Offset 112: >=20 > + This is a memory data pointer for saved preset search results. The > reference code will store >=20 > + the Gen3 Preset Search results in the SaPegHob. In order to skip the G= en3 >=20 > + preset search on boots where the PEG card configuration has not change= d > since the previous boot, >=20 > + platform code can save the contents of the SaPegHob in DXE (When it > present and for size reported by Header.HobLength) >=20 > + and provide a pointer to a restored copy of that data. Default value i= s > NULL, which results in a full >=20 > + preset search every boot. >=20 > + >=20 > + @note An attack on this policy could prevent the PCIe display from > working until a boot when >=20 > + PegDataPtr is NULL or Gen3SwEqAlwaysAttempt is enabled. The variable > used to save the >=20 > + preset search results should be protected in a way that it can only be > modified by the >=20 > + platform manufacturer. >=20 > + **/ >=20 > + VOID *PegDataPtr; >=20 > + /** >=20 > + Offset 116: >=20 > + (Test)Used for PCIe Gen3 Software Equalization. Range: 0-65535, > default is 1. >=20 > + @warning Do not change from the default. Hard to detect issues are li= kely. >=20 > + **/ >=20 > + UINT16 Gen3SwEqJitterErrorTarget; >=20 > + >=20 > + /** >=20 > + Offset 118: >=20 > + (Test)Used for PCIe Gen3 Software Equalization. Range: 0-65535, > default is 10000. >=20 > + @warning Do not change from the default. Hard to detect issues are li= kely. >=20 > + @note An attack on this policy could result in an apparent hang, >=20 > + but the system will eventually boot. This variable should be protecte= d. >=20 > + **/ >=20 > + UINT16 Gen3SwEqVocDwellTime; >=20 > + >=20 > + /** >=20 > + Offset 120: >=20 > + (Test)Used for PCIe Gen3 Software Equalization. Range: 0-65535, > default is 2. >=20 > + @warning Do not change from the default. Hard to detect issues are li= kely. >=20 > + **/ >=20 > + UINT16 Gen3SwEqVocErrorTarget; >=20 > + /** >=20 > + Offset 122: >=20 > + PCIe Hot Plug Enable/Disable. It has 2 policies. >=20 > + - Disabled (0x0) : No hotplug. >=20 > + - Enabled (0x1) : Bios assist hotplug. >=20 > + **/ >=20 > + UINT8 PegRootPortHPE[SA_PEG_MAX_FUN_GEN3]; >=20 > + UINT8 DmiDeEmphasis; //= /< Offset 125 This field is > used to describe the DeEmphasis control for DMI (-6 dB and -3.5 dB are th= e > options) >=20 > + UINT8 Rsvd0[3]; //= /< Offset 126 >=20 > + /** >=20 > + Offset 128: >=20 > + This contains the PCIe PERST# GPIO information. This structure is req= uired >=20 > + for PCIe Gen3 operation. The reference code will use the information i= n > this structure in >=20 > + order to reset PCIe Gen3 devices during equalization, if necessary. R= efer > to the Platform >=20 > + Developer's Guide (PDG) for additional details. >=20 > + **/ >=20 > + PEG_GPIO_DATA PegGpioData; >=20 > + >=20 > + /** >=20 > + Offset 156 >=20 > + (Test) PCIe Override RxCTLE. This feature should only be true t= o > disable RxCTLE adaptive behavior for compliance testing >=20 > + - False (0x0) : Normal Operation - RxC= TLE adaptive > behavior enabled (Default) >=20 > + - True (0x1) : Override RxCTLE - Dis= able RxCTLE adaptive > behavior to keep the configured RxCTLE peak values unmodified >=20 > + From CFL onwards, modularity is introduced to this setup option so tha= t > the RxCTLE adaptive behavior could be controlled at the controller level. >=20 > + Making this variable a UINT8 to accomodate the values of all controlle= rs as > bit definition >=20 > + **/ >=20 > + UINT8 PegGen3RxCtleOverride; >=20 > + >=20 > +} PCIE_PEI_PREMEM_CONFIG_GEN3; >=20 > + >=20 > +#pragma pack (pop) >=20 > + >=20 > +#endif // _CPU_PCIE_CONFIG_GEN3_H_ >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/CpuPcieRp/Gen4/Cp > uPcieConfig.h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/CpuPcieRp/Gen4/Cp > uPcieConfig.h > new file mode 100644 > index 0000000000..5941b6ad4a > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/CpuPcieRp/Gen4/Cp > uPcieConfig.h > @@ -0,0 +1,490 @@ > +/** @file >=20 > + Pcie root port policy >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +#ifndef _CPU_PCIE_CONFIG_H_ >=20 > +#define _CPU_PCIE_CONFIG_H_ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +#pragma pack(push, 1) >=20 > + >=20 > +#define CPU_PCIE_PEI_PREMEM_CONFIG_REVISION 1 >=20 > +#define CPU_PCIE_RP_PREMEM_CONFIG_REVISION 4 >=20 > + >=20 > +/** >=20 > + Making any setup structure change after code frozen >=20 > + will need to maintain backward compatibility, bump up >=20 > + structure revision and update below history table\n >=20 > + Revision 1: - Initial version. >=20 > + Revision 2: - Add Gen3TxOverride and Gen4TxOverride >=20 > + Revision 3: - Deprecate Dekel Suqelch Workaround Setup > Variable >=20 > + Revision 4: - Add FOMS Control Policy Setup Variable >=20 > + Revision 5: - Add Gen3HwEqOverride and Gen4HwEqOverride >=20 > + Revision 6: - Align revision with CPU_PCIE_RP_CONFIG_REVISION > value >=20 > +**/ >=20 > + >=20 > +#define CPU_PCIE_RP_CONFIG_REVISION 6 >=20 > + >=20 > +#define L0_SET BIT0 >=20 > +#define L1_SET BIT1 >=20 > + >=20 > + >=20 > + >=20 > + >=20 > +/** >=20 > + PCI Express and DMI controller configuration\n >=20 > + @note Optional. These policies will be ignored if there is no PE= G > port present on board. >=20 > + Revision 1: >=20 > + - Initial version. >=20 > +**/ >=20 > +typedef struct { >=20 > + CONFIG_BLOCK_HEADER Header; //= /< Offset 0-27 > Config Block Header >=20 > + /** >=20 > + Offset 28:0 : >=20 > + (Test) DMI Link Speed Control >=20 > + - Auto (0x0) : Maximum possible link speed (Default) >=20 > + - Gen1 (0x1) : Limit Link to Gen1 Speed >=20 > + - Gen2 (0x2) : Limit Link to Gen2 Speed >=20 > + - Gen3 (0x3) : Limit Link to Gen3 Speed >=20 > + **/ >=20 > + UINT32 DmiMaxLinkSpeed : 2; >=20 > + /** >=20 > + Offset 28:2 : >=20 > + (Test) DMI Equalization Phase 2 Enable Control >=20 > + - Disabled (0x0) : Disable phase 2 >=20 > + - Enabled (0x1) : Enable phase 2 >=20 > + - Auto (0x2) : Use the current default method (Default) >=20 > + **/ >=20 > + UINT32 DmiGen3EqPh2Enable : 2; >=20 > + /** >=20 > + Offset 28:4 : >=20 > + (Test) Selects the method for performing Phase3 of Gen3 > Equalization on DMI >=20 > + - Auto (0x0) : Use the current default method (Default) >=20 > + - HwEq (0x1) : Use Adaptive Hardware Equalization >=20 > + - SwEq (0x2) : Use Adaptive Software Equalization (Implemented= in > BIOS Reference Code) >=20 > + - Static (0x3) : Use the Static EQs provided in DmiGen3EndPointP= reset > array for Phase1 AND Phase3 (Instead of just Phase1) >=20 > + - Disabled (0x4) : Bypass Equalization Phase 3 >=20 > + **/ >=20 > + UINT32 DmiGen3EqPh3Method : 3; >=20 > + /** >=20 > + Offset 28:7 : >=20 > + (Test) Program DMI Gen3 EQ Phase1 Static Presets >=20 > + - Disabled (0x0) : Disable EQ Phase1 Static Presets Programmin= g >=20 > + - Enabled (0x1) : Enable EQ Phase1 Static Presets Programmin= g > (Default) >=20 > + **/ >=20 > + UINT32 DmiGen3ProgramStaticEq : 1; >=20 > + UINT32 RsvdBits0 : 24; /= //< Offset 28:8 :Reserved > for future use >=20 > + >=20 > + /** >=20 > + Offset 32:0 : >=20 > + Select when PCIe ASPM programming will happen in relation to the Oprom >=20 > + - Before (0x0) : Do PCIe ASPM programming before Oprom. > (Default) >=20 > + - After (0x1) : Do PCIe ASPM programming after Oprom. This wil= l > require an SMI handler to save/restore ASPM settings. >=20 > + **/ >=20 > + UINT32 InitPcieAspmAfterOprom : 1; >=20 > + UINT32 RsvdBits1 : 31; ///< Offset 32:1 :Reserv= ed for future use >=20 > + >=20 > + UINT8 DmiGen3RootPortPreset[SA_DMI_MAX_LANE]; //= /< > Offset 36 Used for programming DMI Gen3 preset values per lane. Range: 0- > 9, 8 is default for each lane >=20 > + UINT8 DmiGen3EndPointPreset[SA_DMI_MAX_LANE]; //= /< > Offset 40/44 Used for programming DMI Gen3 preset values per lane. Range: > 0-9, 7 is default for each lane >=20 > + UINT8 DmiGen3EndPointHint[SA_DMI_MAX_LANE]; //= /< > Offset 44/52 Hint value per lane for the DMI Gen3 End Point. Range: 0-6, = 2 is > default for each lane >=20 > + /** >=20 > + Offset 48/60 : >=20 > + DMI Gen3 RxCTLEp per-Bundle control. The range of the setting is (0-1= 5). > This setting >=20 > + has to be specified based upon platform design and must follow the > guideline. Default is 12. >=20 > + **/ >=20 > + >=20 > + UINT8 DmiGen3RxCtlePeaking[SA_DMI_MAX_BUNDLE]; >=20 > + >=20 > + UINT8 DmiDeEmphasis; //= /< Offset 64 This field is > used to describe the DeEmphasis control for DMI (-6 dB and -3.5 dB are th= e > options) >=20 > + UINT8 Rsvd0[3]; //= /< Offset 65 >=20 > +} PCIE_PEI_PREMEM_CONFIG; >=20 > + >=20 > + >=20 > +/** >=20 > + CPU PCIe Root Port Pre-Memory Configuration >=20 > + Contains Root Port settings and capabilities >=20 > + Revision 1: - Initial version. >=20 > + Revision 2: - Adding Dekel Suqelch Workaround Setup Variable >=20 > + Revision 3: - Deprecate Dekel Suqelch Workaround Setup > Variable >=20 > + Revision 4: - Adding CDR Relock Setup Variable >=20 > +**/ >=20 > +typedef struct { >=20 > + CONFIG_BLOCK_HEADER Header; ///< Conf= ig Block > Header >=20 > + /** >=20 > + Root Port enabling mask. >=20 > + Bit0 presents RP1, Bit1 presents RP2, and so on. >=20 > + 0: Disable; 1: Enable. >=20 > + **/ >=20 > + UINT32 RpEnabledMask; >=20 > + /** >=20 > + Assertion on Link Down GPIOs >=20 > + - Disabled (0x0) : Disable assertion on Link Down GPIOs(Default= ) >=20 > + - Enabled (0x1) : Enable assertion on Link Down GPIOs >=20 > + **/ >=20 > + UINT8 LinkDownGpios; >=20 > + /** >=20 > + Enable ClockReq Messaging >=20 > + - Disabled (0x0) : Disable ClockReq Messaging(Default) >=20 > + - Enabled (0x1) : Enable ClockReq Messaging >=20 > + **/ >=20 > + UINT8 ClkReqMsgEnable; >=20 > + /** >=20 > + Dekel Recipe Workaround >=20 > + 2 >=20 > + 1=3DMinimal, 9=3DMaximum, >=20 > + **/ >=20 > + UINT8 DekelSquelchWa; // Deprecated variable >=20 > + UINT8 Rsvd0[1]; >=20 > + /** >=20 > + Determines each PCIE Port speed capability. >=20 > + 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3; 4: Gen4 (see: > CPU_PCIE_SPEED) >=20 > + **/ >=20 > + UINT8 PcieSpeed[CPU_PCIE_MAX_ROOT_PORTS]; >=20 > + /** >=20 > + To Enable/Disable CDR Relock >=20 > + 0: Disable; 1: Enable >=20 > + **/ >=20 > + UINT8 CdrRelock[CPU_PCIE_MAX_ROOT_PORTS]; >=20 > + /** >=20 > + This policy is used while programming DEKEL Recipe >=20 > + 0: Disable; 1: Enable >=20 > + **/ >=20 > + UINT8 Xl1el[CPU_PCIE_MAX_ROOT_PORTS]; >=20 > + >=20 > +} CPU_PCIE_RP_PREMEM_CONFIG; >=20 > + >=20 > +typedef enum { >=20 > + CpuPcieOverrideDisabled =3D 0, >=20 > + CpuPcieL1L2Override =3D 0x01, >=20 > + CpuPcieL1SubstatesOverride =3D 0x02, >=20 > + CpuPcieL1L2AndL1SubstatesOverride =3D 0x03, >=20 > + CpuPcieLtrOverride =3D 0x04 >=20 > +} CPU_PCIE_OVERRIDE_CONFIG; >=20 > + >=20 > +/** >=20 > + PCIe device table entry entry >=20 > + >=20 > + The PCIe device table is being used to override PCIe device ASPM setti= ngs. >=20 > + To take effect table consisting of such entries must be instelled as P= PI >=20 > + on gPchPcieDeviceTablePpiGuid. >=20 > + Last entry VendorId must be 0. >=20 > +**/ >=20 > +typedef struct { >=20 > + UINT16 VendorId; ///< The vendor Id of Pci Express= card ASPM > setting override, 0xFFFF means any Vendor ID >=20 > + UINT16 DeviceId; ///< The Device Id of Pci Express= card ASPM > setting override, 0xFFFF means any Device ID >=20 > + UINT8 RevId; ///< The Rev Id of Pci Express ca= rd ASPM setting > override, 0xFF means all steppings >=20 > + UINT8 BaseClassCode; ///< The Base Class Code of Pci E= xpress card > ASPM setting override, 0xFF means all base class >=20 > + UINT8 SubClassCode; ///< The Sub Class Code of Pci Ex= press card > ASPM setting override, 0xFF means all sub class >=20 > + UINT8 EndPointAspm; ///< Override device ASPM (see: > CPU_PCIE_ASPM_CONTROL) >=20 > + ///< Bit 1 must be set in Overrid= eConfig for this field to > take effect >=20 > + UINT16 OverrideConfig; ///< The override config bitmap (= see: > CPU_PCIE_OVERRIDE_CONFIG). >=20 > + /** >=20 > + The L1Substates Capability Offset Override. (applicable if bit 2 is = set in > OverrideConfig) >=20 > + This field can be zero if only the L1 Substate value is going to be = override. >=20 > + **/ >=20 > + UINT16 L1SubstatesCapOffset; >=20 > + /** >=20 > + L1 Substate Capability Mask. (applicable if bit 2 is set in Override= Config) >=20 > + Set to zero then the L1 Substate Capability [3:0] is ignored, and on= ly L1s > values are override. >=20 > + Only bit [3:0] are applicable. Other bits are ignored. >=20 > + **/ >=20 > + UINT8 L1SubstatesCapMask; >=20 > + /** >=20 > + L1 Substate Port Common Mode Restore Time Override. (applicable if b= it > 2 is set in OverrideConfig) >=20 > + L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid > value of 0, but not the L1sTpowerOnValue. >=20 > + If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime, > L1sTpowerOnScale, and L1sTpowerOnValue are ignored, >=20 > + and only L1SubstatesCapOffset is override. >=20 > + **/ >=20 > + UINT8 L1sCommonModeRestoreTime; >=20 > + /** >=20 > + L1 Substate Port Tpower_on Scale Override. (applicable if bit 2 is s= et in > OverrideConfig) >=20 > + L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid > value of 0, but not the L1sTpowerOnValue. >=20 > + If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime, > L1sTpowerOnScale, and L1sTpowerOnValue are ignored, >=20 > + and only L1SubstatesCapOffset is override. >=20 > + **/ >=20 > + UINT8 L1sTpowerOnScale; >=20 > + /** >=20 > + L1 Substate Port Tpower_on Value Override. (applicable if bit 2 is s= et in > OverrideConfig) >=20 > + L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid > value of 0, but not the L1sTpowerOnValue. >=20 > + If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime, > L1sTpowerOnScale, and L1sTpowerOnValue are ignored, >=20 > + and only L1SubstatesCapOffset is override. >=20 > + **/ >=20 > + UINT8 L1sTpowerOnValue; >=20 > + >=20 > + /** >=20 > + SnoopLatency bit definition >=20 > + Note: All Reserved bits must be set to 0 >=20 > + >=20 > + BIT[15] - When set to 1b, indicates that the values in bits 9:0 = are valid >=20 > + When clear values in bits 9:0 will be ignored >=20 > + BITS[14:13] - Reserved >=20 > + BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in= these bits >=20 > + 000b - 1 ns >=20 > + 001b - 32 ns >=20 > + 010b - 1024 ns >=20 > + 011b - 32,768 ns >=20 > + 100b - 1,048,576 ns >=20 > + 101b - 33,554,432 ns >=20 > + 110b - Reserved >=20 > + 111b - Reserved >=20 > + BITS[9:0] - Snoop Latency Value. The value in these bits will be m= ultiplied > with >=20 > + the scale in bits 12:10 >=20 > + >=20 > + This field takes effect only if bit 3 is set in OverrideConfig. >=20 > + **/ >=20 > + UINT16 SnoopLatency; >=20 > + /** >=20 > + NonSnoopLatency bit definition >=20 > + Note: All Reserved bits must be set to 0 >=20 > + >=20 > + BIT[15] - When set to 1b, indicates that the values in bits 9:0 = are valid >=20 > + When clear values in bits 9:0 will be ignored >=20 > + BITS[14:13] - Reserved >=20 > + BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in= these bits >=20 > + 000b - 1 ns >=20 > + 001b - 32 ns >=20 > + 010b - 1024 ns >=20 > + 011b - 32,768 ns >=20 > + 100b - 1,048,576 ns >=20 > + 101b - 33,554,432 ns >=20 > + 110b - Reserved >=20 > + 111b - Reserved >=20 > + BITS[9:0] - Non Snoop Latency Value. The value in these bits will = be > multiplied with >=20 > + the scale in bits 12:10 >=20 > + >=20 > + This field takes effect only if bit 3 is set in OverrideConfig. >=20 > + **/ >=20 > + UINT16 NonSnoopLatency; >=20 > + >=20 > + /** >=20 > + Forces LTR override to be permanent >=20 > + The default way LTR override works is: >=20 > + rootport uses LTR override values provided by BIOS until connected > device sends an LTR message, then it will use values from the message >=20 > + This settings allows force override of LTR mechanism. If it's enable= d, then: >=20 > + rootport will use LTR override values provided by BIOS forever; LT= R > messages sent from connected device will be ignored >=20 > + **/ >=20 > + UINT8 ForceLtrOverride; >=20 > + UINT8 Reserved[3]; >=20 > +} CPU_PCIE_DEVICE_OVERRIDE; >=20 > + >=20 > +enum CPU_PCIE_SPEED { >=20 > + CpuPcieAuto, >=20 > + CpuPcieGen1, >=20 > + CpuPcieGen2, >=20 > + CpuPcieGen3, >=20 > + CpuPcieGen4, >=20 > + CpuPcieGen5 >=20 > +}; >=20 > + >=20 > +/// >=20 > +/// The values before AutoConfig match the setting of PCI Express Base > Specification 1.1, please be careful for adding new feature >=20 > +/// >=20 > +typedef enum { >=20 > + CpuPcieAspmDisabled, >=20 > + CpuPcieAspmL0s, >=20 > + CpuPcieAspmL1, >=20 > + CpuPcieAspmL0sL1, >=20 > + CpuPcieAspmAutoConfig, >=20 > + CpuPcieAspmMax >=20 > +} CPU_PCIE_ASPM_CONTROL; >=20 > + >=20 > +/** >=20 > + Refer to SA EDS for the SA implementation values corresponding >=20 > + to below PCI-E spec defined ranges >=20 > +**/ >=20 > +typedef enum { >=20 > + CpuPcieL1SubstatesDisabled, >=20 > + CpuPcieL1SubstatesL1_1, >=20 > + CpuPcieL1SubstatesL1_1_2, >=20 > + CpuPcieL1SubstatesMax >=20 > +} CPU_PCIE_L1SUBSTATES_CONTROL; >=20 > + >=20 > +enum CPU_PCIE_MAX_PAYLOAD { >=20 > + CpuPcieMaxPayload128 =3D 0, >=20 > + CpuPcieMaxPayload256, >=20 > + CpuPcieMaxPayload512, >=20 > + CpuPcieMaxPayloadMax >=20 > +}; >=20 > + >=20 > +enum CPU_PCIE_COMPLETION_TIMEOUT { >=20 > + CpuPcieCompletionTO_Default, >=20 > + CpuPcieCompletionTO_50_100us, >=20 > + CpuPcieCompletionTO_1_10ms, >=20 > + CpuPcieCompletionTO_16_55ms, >=20 > + CpuPcieCompletionTO_65_210ms, >=20 > + CpuPcieCompletionTO_260_900ms, >=20 > + CpuPcieCompletionTO_1_3P5s, >=20 > + CpuPcieCompletionTO_4_13s, >=20 > + CpuPcieCompletionTO_17_64s, >=20 > + CpuPcieCompletionTO_Disabled >=20 > +}; >=20 > + >=20 > + >=20 > +enum CPU_PCIE_GEN3_PRESET_COEFF_SELECTION { >=20 > + CpuPcieGen3PresetSelection, >=20 > + CpuPcieGen3CoefficientSelection >=20 > +}; >=20 > + >=20 > +enum CPU_PCIE_GEN4_PRESET_COEFF_SELECTION { >=20 > + CpuPcieGen4PresetSelection, >=20 > + CpuPcieGen4CoefficientSelection >=20 > +}; >=20 > + >=20 > +typedef enum { >=20 > + CpuPcieEqDefault =3D 0, ///< @deprecated since revision 3. Behav= es as > PchPcieEqHardware. >=20 > + CpuPcieEqHardware =3D 1, ///< Hardware equalization >=20 > + CpuPcieEqStaticCoeff =3D 4 ///< Fixed equalization (requires Coeffi= cient > settings per lane) >=20 > +} CPU_PCIE_EQ_METHOD; >=20 > + >=20 > + >=20 > +/** >=20 > + Represent lane specific PCIe Gen3 equalization parameters. >=20 > +**/ >=20 > +typedef struct { >=20 > + UINT8 Cm; ///< Coefficient C-1 >=20 > + UINT8 Cp; ///< Coefficient C+1 >=20 > + UINT8 PegGen3RootPortPreset; ///< (Test) = Used for > programming PEG Gen3 preset values per lane. Range: 0-9, 8 is default for > each lane >=20 > + UINT8 PegGen3EndPointPreset; ///< (Test) = Used for > programming PEG Gen3 preset values per lane. Range: 0-9, 7 is default for > each lane >=20 > + UINT8 PegGen3EndPointHint; ///< (Test) = Hint value > per lane for the PEG Gen3 End Point. Range: 0-6, 2 is default for each la= ne >=20 > + UINT8 PegGen4RootPortPreset; ///< (Test) = Used for > programming PEG Gen4 preset values per lane. Range: 0-9, 8 is default for > each lane >=20 > + UINT8 PegGen4EndPointPreset; ///< (Test) = Used for > programming PEG Gen4 preset values per lane. Range: 0-9, 7 is default for > each lane >=20 > + UINT8 PegGen4EndPointHint; ///< (Test) = Hint value > per lane for the PEG Gen4 End Point. Range: 0-6, 2 is default for each la= ne >=20 > +} CPU_PCIE_EQ_LANE_PARAM; >=20 > + >=20 > +/** >=20 > + The CPU_PCI_ROOT_PORT_CONFIG describe the feature and capability of > each CPU PCIe root port. >=20 > +**/ >=20 > +typedef struct { >=20 > + >=20 > + UINT32 ExtSync : 1; ///< Indicate whether = the extended > synch is enabled. 0: Disable; 1: Enable. >=20 > + UINT32 VcEnabled : 1; ///< Virtual Channel. = 0: Disable; 1: > Enable >=20 > + UINT32 MultiVcEnabled : 1; ///< Multiple Virtual = Channel. 0: > Disable; 1: Enable >=20 > + UINT32 PeerToPeer : 1; ///< Peer to Peer Mode= . 0: > Disable; 1: Enable. >=20 > + UINT32 RsvdBits0 : 28; ///< Reserved bits >=20 > + /** >=20 > + PCIe Gen4 Equalization Method >=20 > + - HwEq (0x1) : Hardware Equalization (Default) >=20 > + - StaticEq (0x2) : Static Equalization >=20 > + **/ >=20 > + UINT8 Gen4EqPh3Method; >=20 > + UINT8 FomsCp; ///< FOM Score Board C= ontrol Policy >=20 > + UINT8 RsvdBytes0[2]; ///< Reserved bytes >=20 > + >=20 > + // >=20 > + // Gen3 Equalization settings >=20 > + // >=20 > + UINT32 Gen3Uptp : 4; ///< (Test) Ups= tream Port > Transmitter Preset used during Gen3 Link Equalization. Used for all lanes= . > Default is 7. >=20 > + UINT32 Gen3Dptp : 4; ///< (Test) Dow= nstream Port > Transmiter Preset used during Gen3 Link Equalization. Used for all lanes. > Default is 7. >=20 > + // >=20 > + // Gen4 Equalization settings >=20 > + // >=20 > + UINT32 Gen4Uptp : 4; ///< (Test) Ups= tream Port > Transmitter Preset used during Gen4 Link Equalization. Used for all lanes= . > Default is 7. >=20 > + UINT32 Gen4Dptp : 4; ///< (Test) Dow= nstream Port > Transmiter Preset used during Gen4 Link Equalization. Used for all lanes. > Default is 7. >=20 > + // >=20 > + // Gen5 Equalization settings >=20 > + // >=20 > + UINT32 Gen5Uptp : 4; ///< (Test) Ups= tream Port > Transmitter Preset used during Gen5 Link Equalization. Used for all lanes= . > Default is 7. >=20 > + UINT32 Gen5Dptp : 4; ///< (Test) Dow= nstream Port > Transmiter Preset used during Gen5 Link Equalization. Used for all lanes. > Default is 7. >=20 > + UINT32 RsvdBits1 : 8; ///< Reserved Bits >=20 > + >=20 > + PCIE_ROOT_PORT_COMMON_CONFIG PcieRpCommonConfig; > ///< (Test) Includes policies which are common to both SA and PCH > RootPort >=20 > + >=20 > +} CPU_PCIE_ROOT_PORT_CONFIG; >=20 > + >=20 > +/** >=20 > + The CPU_PCIE_CONFIG block describes the expected configuration of the > CPU PCI Express controllers >=20 > + Revision 1< / b>: >=20 > + -Initial version. >=20 > + Revision 2: >=20 > + - SlotSelection policy added >=20 > + Revision 3 >=20 > + - Deprecate PegGen3ProgramStaticEq and PegGen4ProgramStaticEq >=20 > + Revision 4: >=20 > + - Deprecating SetSecuredRegisterLock >=20 > + Revision 5: >=20 > + - Adding Serl >=20 > +**/ >=20 > +typedef struct { >=20 > + CONFIG_BLOCK_HEADER Header; ///< Confi= g Block Header >=20 > + /// >=20 > + /// These members describe the configuration of each SA PCIe root port= . >=20 > + /// >=20 > + CPU_PCIE_ROOT_PORT_CONFIG > RootPort[CPU_PCIE_MAX_ROOT_PORTS]; >=20 > + /// >=20 > + /// Gen3 Equalization settings for physical PCIe lane, index 0 represe= nts > PCIe lane 1, etc. >=20 > + /// Corresponding entries are used when root port EqPh3Method is > PchPcieEqStaticCoeff (default). >=20 > + /// >=20 > + CPU_PCIE_EQ_LANE_PARAM > EqPh3LaneParam[SA_PEG_MAX_LANE]; >=20 > + /// >=20 > + /// List of coefficients used during equalization (applicable to both > software and hardware EQ) >=20 > + /// >=20 > + PCIE_EQ_PARAM > HwEqGen4CoeffList[PCIE_HWEQ_COEFFS_MAX]; // Deprecated Policy >=20 > + >=20 > + PCIE_COMMON_CONFIG PcieCommonConfig; /// < > (Test) Includes policies which are common to both SA and PCH PCIe >=20 > + >=20 > + UINT32 FiaProgramming : 1; /// < Skip Fia Co= nfiguration and > lock if enable >=20 > + /// >=20 > + /// This member describes whether the PCI Express Clock Gating for eac= h > root port >=20 > + /// is enabled by platform modules. 0: Disable; 1: Enable. >=20 > + /// >=20 > + UINT32 ClockGating : 1; >=20 > + /// >=20 > + /// This member describes whether the PCI Express Power Gating for eac= h > root port >=20 > + /// is enabled by platform modules. 0: Disable; 1: Enable. >=20 > + /// >=20 > + UINT32 PowerGating : 1; >=20 > + // Deprecated Policy >=20 > + /** >=20 > + (Test) Program PEG Gen3 EQ Phase1 Static Presets >=20 > + - Disabled (0x0) : Disable EQ Phase1 Static Presets Programmin= g >=20 > + - Enabled (0x1) : Enable EQ Phase1 Static Presets Programmin= g > (Default) >=20 > + **/ >=20 > + UINT32 PegGen3ProgramStaticEq : 1; >=20 > + >=20 > + // Deprecated Policy >=20 > + /** >=20 > + (Test) Program PEG Gen4 EQ Phase1 Static Presets >=20 > + - Disabled (0x0) : Disable EQ Phase1 Static Presets Programmin= g >=20 > + - Enabled (0x1) : Enable EQ Phase1 Static Presets Programmin= g > (Default) >=20 > + **/ >=20 > + UINT32 PegGen4ProgramStaticEq : 1; >=20 > + /** >=20 > + (Test) Cpu Pcie Secure Register Lock >=20 > + - Disabled (0x0) >=20 > + - Enabled (0x1) >=20 > + **/ >=20 > + UINT32 SetSecuredRegisterLock : 1; // Deprecated Policy >=20 > + /// >=20 > + /// This member allows to select between the PCI Express M2 or CEMx4 > slot 1: PCIe M2; 0: CEMx4 slot. >=20 > + /// >=20 > + UINT32 SlotSelection : 1; >=20 > + /// >=20 > + /// Set/Clear Serl(Secure Equalization Register Lock) >=20 > + /// >=20 > + UINT32 Serl : 1; >=20 > + >=20 > + UINT32 RsvdBits0 : 24; >=20 > + >=20 > + /** >=20 > + PCIe device override table >=20 > + The PCIe device table is being used to override PCIe device ASPM > settings. >=20 > + This is a pointer points to a 32bit address. And it's only used in P= ostMem > phase. >=20 > + Please refer to PCH_PCIE_DEVICE_OVERRIDE structure for the table. >=20 > + Last entry VendorId must be 0. >=20 > + The prototype of this policy is: >=20 > + CPU_PCIE_DEVICE_OVERRIDE *PcieDeviceOverrideTablePtr; >=20 > + **/ >=20 > + UINT32 PcieDeviceOverrideTablePtr; >=20 > + } CPU_PCIE_CONFIG; There are two fields missing from this definition: CPU_PCIE_ROOT_PORT_CONFIG2 RootPort2[CPU_PCIE_MAX_ROOT_PORTS]; PCIE_COMMON_CONFIG2 PcieCommonConfig2; >=20 > + >=20 > +#pragma pack (pop) >=20 > + >=20 > +#endif // _CPU_PCIE_CONFIG_H_ >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Dci/DciConfig.h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Dci/DciConfig.h > new file mode 100644 > index 0000000000..445642da1f > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Dci/DciConfig= .h > @@ -0,0 +1,72 @@ > +/** @file >=20 > + Dci policy >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _DCI_CONFIG_H_ >=20 > +#define _DCI_CONFIG_H_ >=20 > + >=20 > +#define DCI_PREMEM_CONFIG_REVISION 2 >=20 > +extern EFI_GUID gDciPreMemConfigGuid; >=20 > + >=20 > +#pragma pack (push,1) >=20 > + >=20 > +typedef enum { >=20 > + DciDbcDisabled =3D 0x0, >=20 > + DciDbcUsb2 =3D 0x1, >=20 > + DciDbcUsb3 =3D 0x2, >=20 > + DciDbcBoth =3D 0x3, >=20 > + DciDbcNoChange =3D 0x4, >=20 > + DciDbcMax >=20 > +} DCI_DBC_MODE; >=20 > + >=20 > +typedef enum { >=20 > + Usb3TcDbgDisabled =3D 0x0, >=20 > + Usb3TcDbgEnabled =3D 0x1, >=20 > + Usb3TcDbgNoChange =3D 0x2, >=20 > + Usb3TcDbgMax >=20 > +} DCI_USB3_TYPE_C_DEBUG_MODE; >=20 > + >=20 > +/** >=20 > + The PCH_DCI_PREMEM_CONFIG block describes policies related to Direct > Connection Interface (DCI) >=20 > + >=20 > + Revision 1: >=20 > + - Initial version. >=20 > + Revision 2: >=20 > + - Added DciModphyPg >=20 > + - change to use data in byte unit rather than bit-field >=20 > +**/ >=20 > +typedef struct { >=20 > + CONFIG_BLOCK_HEADER Header; ///< Config Block Header >=20 > + /** >=20 > + DCI enable. >=20 > + Determine if to enable DCI debug from host. >=20 > + 0:Disabled; 1:Enabled >=20 > + **/ >=20 > + UINT8 DciEn; >=20 > + /** >=20 > + USB DbC enable mode. >=20 > + Disabled: Clear both USB2/3DBCEN; USB2: Set USB2DBCEN; USB3: Set > USB3DBCEN; Both: Set both USB2/3DBCEN; No Change: Comply with HW > value >=20 > + Refer to definition of DCI_USB_DBC_MODE for supported settings. >=20 > + 0:Disabled; 1:USB2; 2:USB3; 3:Both; 4:No Change >=20 > + **/ >=20 > + UINT8 DciDbcMode; >=20 > + /** >=20 > + Enable Modphy power gate when DCI is enable. It must be disabled for= 4- > wire DCI OOB. Set default to HW default : Disabled >=20 > + 0:Disabled; 1:Enabled >=20 > + **/ >=20 > + UINT8 DciModphyPg; >=20 > + /** >=20 > + USB3 Type-C UFP2DFP kenel / platform debug support. No change will d= o > nothing to UFP2DFP configuration. >=20 > + When enabled, USB3 Type C UFP (upstream-facing port) may switch to > DFP (downstream-facing port) for first connection. >=20 > + It must be enabled for USB3 kernel(kernel mode debug) and platform > debug(DFx, DMA, Trace) over UFP Type-C receptacle. >=20 > + Refer to definition of DCI_USB_TYPE_C_DEBUG_MODE for supported > settings. >=20 > + 0:Disabled; 1:Enabled; 2:No Change >=20 > + **/ >=20 > + UINT8 DciUsb3TypecUfpDbg; >=20 > +} PCH_DCI_PREMEM_CONFIG; >=20 > + >=20 > +#pragma pack (pop) >=20 > + >=20 > +#endif // _DCI_CONFIG_H_ >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Espi/EspiConfig.h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Espi/EspiConfig.h > new file mode 100644 > index 0000000000..260b582702 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Espi/EspiConfig.h > @@ -0,0 +1,61 @@ > +/** @file >=20 > + Espi policy >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _ESPI_CONFIG_H_ >=20 > +#define _ESPI_CONFIG_H_ >=20 > + >=20 > +#define ESPI_CONFIG_REVISION 2 >=20 > +extern EFI_GUID gEspiConfigGuid; >=20 > + >=20 > +#pragma pack (push,1) >=20 > + >=20 > +/** >=20 > + This structure contains the policies which are related to ESPI. >=20 > + >=20 > + Revision 1: >=20 > + - Initial revision >=20 > + Revision 2: >=20 > + - Added LockLinkConfiguration field to config block >=20 > +**/ >=20 > +typedef struct { >=20 > + CONFIG_BLOCK_HEADER Header; ///< Config Block Head= er >=20 > + /** >=20 > + LPC (eSPI) Memory Range Decode Enable. When TRUE, then the range >=20 > + specified in PCLGMR[31:16] is enabled for decoding to LPC (eSPI). >=20 > + 0: FALSE, 1: TRUE >=20 > + **/ >=20 > + UINT32 LgmrEnable : 1; >=20 > + /** >=20 > + eSPI Master and Slave BME settings. >=20 > + When TRUE, then the BME bit enabled in eSPI Master and Slave. >=20 > + 0: FALSE, 1: TRUE >=20 > + **/ >=20 > + UINT32 BmeMasterSlaveEnabled : 1; >=20 > + /** >=20 > + Master HOST_C10 (Virtual Wire) to Slave Enable (VWHC10OE) >=20 > + 0b: Disable HOST_C10 reporting (HOST_C10 indication from PMC is > ignored) >=20 > + 1b: Enable HOST_C10 reporting to Slave via eSPI Virtual Wire (upon > receiving a HOST_C10 indication from PMC) >=20 > + **/ >=20 > + UINT32 HostC10ReportEnable : 1; >=20 > + /** >=20 > + eSPI Link Configuration Lock (SBLCL) >=20 > + If set to TRUE then communication through SET_CONFIG/GET_CONFIG >=20 > + to eSPI slaves addresses from range 0x0 - 0x7FF >=20 > + 1: TRUE, 0: FALSE >=20 > + **/ >=20 > + UINT32 LockLinkConfiguration : 1; >=20 > + /** >=20 > + Hardware Autonomous Enable (HAE) >=20 > + If set to TRUE, then the IP may request a PG whenever it is idle >=20 > + **/ >=20 > + UINT32 EspiPmHAE : 1; >=20 > + UINT32 RsvdBits : 27; ///< Reserved bits >=20 > +} PCH_ESPI_CONFIG; >=20 > + >=20 > +#pragma pack (pop) >=20 > + >=20 > +#endif // _ESPI_CONFIG_H_ >=20 > + >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Fivr/FivrConfig.h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Fivr/FivrConfig.h > new file mode 100644 > index 0000000000..0df2755280 > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Fivr/FivrConf= ig.h > @@ -0,0 +1,170 @@ > +/** @file >=20 > + PCH FIVR policy >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _FIVR_CONFIG_H_ >=20 > +#define _FIVR_CONFIG_H_ >=20 > + >=20 > +#define FIVR_CONFIG_REVISION 1 >=20 > +extern EFI_GUID gFivrConfigGuid; >=20 > + >=20 > +#pragma pack (push,1) >=20 > + >=20 > +/** >=20 > + Rail support in S0ix and Sx >=20 > + Settings other than FivrRailDisabled can be OR'ed >=20 > +**/ >=20 > +typedef enum { >=20 > + FivrRailDisabled =3D 0, >=20 > + FivrRailInS0i1S0i2 =3D BIT0, >=20 > + FivrRailInS0i3 =3D BIT1, >=20 > + FivrRailInS3 =3D BIT2, >=20 > + FivrRailInS4 =3D BIT3, >=20 > + FivrRailInS5 =3D BIT4, >=20 > + FivrRailInS0ix =3D FivrRailInS0i1S0i2 | FivrRailInS0i3, >=20 > + FivrRailInSx =3D FivrRailInS3 | FivrRailInS4 | FivrRailInS5, >=20 > + FivrRailAlwaysOn =3D FivrRailInS0ix | FivrRailInSx >=20 > +} FIVR_RAIL_SX_STATE; >=20 > + >=20 > +typedef enum { >=20 > + FivrRetentionActive =3D BIT0, >=20 > + FivrNormActive =3D BIT1, >=20 > + FivrMinActive =3D BIT2, >=20 > + FivrMinRetention =3D BIT3 >=20 > +} FIVR_RAIL_SUPPORTED_VOLTAGE; >=20 > + >=20 > +/** >=20 > + Structure for V1p05/Vnn VR rail configuration >=20 > +**/ >=20 > +typedef struct { >=20 > + /** >=20 > + Mask to enable the usage of external VR rail in specific S0ix or Sx = states >=20 > + Use values from FIVR_RAIL_SX_STATE >=20 > + The default is FivrRailDisabled. >=20 > + **/ >=20 > + UINT32 EnabledStates : 5; >=20 > + >=20 > + /** >=20 > + VR rail voltage value that will be used in S0i2/S0i3 states. >=20 > + This value is given in 2.5mV increments (0=3D0mV, 1=3D2.5mV, 2=3D5mV= ...) >=20 > + The default for Vnn is set to 420 - 1050 mV. >=20 > + **/ >=20 > + UINT32 Voltage : 11; >=20 > + /** >=20 > + @deprecated >=20 > + THIS POLICY IS DEPRECATED, PLEASE USE IccMaximum INSTEAD >=20 > + VR rail Icc Max Value >=20 > + Granularity of this setting is 1mA and maximal possible value is 500= mA >=20 > + The default is 0mA . >=20 > + **/ >=20 > + UINT32 IccMax : 8; >=20 > + >=20 > + /** >=20 > + This register holds the control hold off values to be used when >=20 > + changing the rail control for external bypass value in us >=20 > + **/ >=20 > + UINT32 CtrlRampTmr : 8; >=20 > + >=20 > + /** >=20 > + Mask to set the supported configuration in VR rail. >=20 > + Use values from FIVR_RAIL_SUPPORTED_VOLTAGE >=20 > + **/ >=20 > + UINT32 SupportedVoltageStates : 4; >=20 > + >=20 > + /** >=20 > + VR rail Icc Maximum Value >=20 > + Granularity of this setting is 1mA and maximal possible value is 500= mA >=20 > + The default is 0mA . >=20 > + **/ >=20 > + UINT32 IccMaximum : 16; >=20 > + >=20 > + UINT32 RsvdBits1 : 12; >=20 > + >=20 > +} FIVR_EXT_RAIL_CONFIG; >=20 > + >=20 > + >=20 > +/** >=20 > + Structure for VCCIN_AUX voltage rail configuration >=20 > +**/ >=20 > +typedef struct { >=20 > + /** >=20 > + Transition time in microseconds from Low Current Mode Voltage to High > Current Mode Voltage. >=20 > + Voltage transition time required by motherboard voltage regulator when > PCH changes >=20 > + the VCCIN_AUX regulator set point from the low current mode voltage > and high current mode voltage. >=20 > + This field has 1us resolution. >=20 > + When value is 0 PCH will not transition VCCIN_AUX to low current mode > voltage. >=20 > + The default is 0xC . >=20 > + **/ >=20 > + UINT8 LowToHighCurModeVolTranTime; >=20 > + >=20 > + /** >=20 > + Transition time in microseconds from Retention Mode Voltage to High > Current Mode Voltage. >=20 > + Voltage transition time required by motherboard voltage regulator when > PCH changes >=20 > + the VCCIN_AUX regulator set point from the retention mode voltage to > high current mode voltage. >=20 > + This field has 1us resolution. >=20 > + When value is 0 PCH will not transition VCCIN_AUX to retention voltage= . >=20 > + The default is 0x36 . >=20 > + **/ >=20 > + UINT8 RetToHighCurModeVolTranTime; >=20 > + >=20 > + /** >=20 > + Transition time in microseconds from Retention Mode Voltage to Low > Current Mode Voltage. >=20 > + Voltage transition time required by motherboard voltage regulator when > PCH changes >=20 > + the VCCIN_AUX regulator set point from the retention mode voltage to > low current mode voltage. >=20 > + This field has 1us resolution. >=20 > + When value is 0 PCH will not transition VCCIN_AUX to retention voltage= . >=20 > + The default is 0x2B . >=20 > + **/ >=20 > + UINT8 RetToLowCurModeVolTranTime; >=20 > + UINT8 RsvdByte1; >=20 > + /** >=20 > + Transition time in microseconds from Off (0V) to High Current Mode > Voltage. >=20 > + Voltage transition time required by motherboard voltage regulator when > PCH changes >=20 > + the VCCIN_AUX regulator set point from 0V to the high current mode > voltage. >=20 > + This field has 1us resolution. >=20 > + 0 =3D Transition to 0V is disabled >=20 > + Setting this field to 0 sets VCCIN_AUX as a fixed rail that stays on >=20 > + in all S0 & Sx power states after initial start up on G3 exit >=20 > + The default is 0x96 . >=20 > + **/ >=20 > + UINT32 OffToHighCurModeVolTranTime : 11; >=20 > + UINT32 RsvdBits1 : 21; >=20 > +} FIVR_VCCIN_AUX_CONFIG; >=20 > + >=20 > +/** >=20 > + The PCH_FIVR_CONFIG block describes FIVR settings. >=20 > +**/ >=20 > +typedef struct { >=20 > + CONFIG_BLOCK_HEADER Header; ///< Config Block Header >=20 > + /** >=20 > + External V1P05 VR rail configuration. >=20 > + **/ >=20 > + FIVR_EXT_RAIL_CONFIG ExtV1p05Rail; >=20 > + /** >=20 > + External Vnn VR rail configuration. >=20 > + **/ >=20 > + FIVR_EXT_RAIL_CONFIG ExtVnnRail; >=20 > + /** >=20 > + Additional External Vnn VR rail configuration that will get applied >=20 > + in Sx entry SMI callback. Required only if External Vnn VR >=20 > + needs different settings for Sx than those specified in ExtVnnRail. >=20 > + **/ >=20 > + FIVR_EXT_RAIL_CONFIG ExtVnnRailSx; >=20 > + /** >=20 > + VCCIN_AUX voltage rail configuration. >=20 > + **/ >=20 > + FIVR_VCCIN_AUX_CONFIG VccinAux; >=20 > + >=20 > + /** >=20 > + Enable/Disable FIVR Dynamic Power Management >=20 > + Default is 1 . >=20 > + **/ >=20 > + UINT32 FivrDynPm : 1; >=20 > + UINT32 RsvdBits2 : 31; >=20 > +} PCH_FIVR_CONFIG; >=20 > + >=20 > +#pragma pack (pop) >=20 > + >=20 > +#endif // _FIVR_CONFIG_H_ >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Gbe/GbeConfig.h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Gbe/GbeConfig.h > new file mode 100644 > index 0000000000..cb9411f9e8 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Gbe/GbeConfig.h > @@ -0,0 +1,33 @@ > +/** @file >=20 > + Gigabit Ethernet policy >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _GBE_CONFIG_H_ >=20 > +#define _GBE_CONFIG_H_ >=20 > + >=20 > +#define GBE_CONFIG_REVISION 1 >=20 > +extern EFI_GUID gGbeConfigGuid; >=20 > + >=20 > +#pragma pack (push,1) >=20 > + >=20 > +/** >=20 > + PCH intergrated GBE controller configuration settings. >=20 > +**/ >=20 > +typedef struct { >=20 > + CONFIG_BLOCK_HEADER Header; ///< Config Block Header >=20 > + /** >=20 > + Determines if enable PCH internal GBE, 0: Disable; 1: Enable. >=20 > + When Enable is changed (from disabled to enabled or from enabled to > disabled), >=20 > + it needs to set LAN Disable regsiter, which might be locked by FDSWL > register. >=20 > + So it's recommendated to issue a global reset when changing the stat= us > for PCH Internal LAN. >=20 > + **/ >=20 > + UINT32 Enable : 1; >=20 > + UINT32 LtrEnable : 1; ///< 0: Disable; 1: Enable LTR c= apabilty of > PCH internal LAN. >=20 > + UINT32 RsvdBits0 : 30; ///< Reserved bits >=20 > +} GBE_CONFIG; >=20 > + >=20 > +#pragma pack (pop) >=20 > + >=20 > +#endif // _GBE_CONFIG_H_ >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Gna/GnaConfig.h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Gna/GnaConfig.h > new file mode 100644 > index 0000000000..87649253c6 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Gna/GnaConfig.h > @@ -0,0 +1,31 @@ > +/** @file >=20 > + Policy definition for GNA Config Block >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _GNA_CONFIG_H_ >=20 > +#define _GNA_CONFIG_H_ >=20 > +#pragma pack(push, 1) >=20 > + >=20 > +#define GNA_CONFIG_REVISION 1 >=20 > +/** >=20 > + GNA config block for configuring GNA.\n >=20 > + Revision 1: >=20 > + - Initial version. >=20 > +**/ >=20 > +typedef struct { >=20 > + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27= Config > Block Header >=20 > + /** >=20 > + Offset 28:0 >=20 > + This policy enables the GNA Device (SA Device 8) if supported. >=20 > + If FALSE, all other policies in this config block will be ignored. >=20 > + 1=3DTRUE; >=20 > + 0=3DFALSE. >=20 > + **/ >=20 > + UINT32 GnaEnable : 1; >=20 > + UINT32 RsvdBits0 : 31; ///< Offset 28:1 :Reserved= for future use >=20 > +} GNA_CONFIG; >=20 > +#pragma pack(pop) >=20 > + >=20 > +#endif // _GNA_CONFIG_H_ >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Gpio/GpioDevConfi= g > .h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Gpio/GpioDevConfi= g > .h > new file mode 100644 > index 0000000000..1a724f14da > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Gpio/GpioDevConfi= g > .h > @@ -0,0 +1,37 @@ > +/** @file >=20 > + GPIO device policy >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _GPIO_DEV_CONFIG_H_ >=20 > +#define _GPIO_DEV_CONFIG_H_ >=20 > + >=20 > +extern EFI_GUID gGpioDxeConfigGuid; >=20 > + >=20 > +#define GPIO_DXE_CONFIG_REVISION 1 >=20 > + >=20 > +#pragma pack (push,1) >=20 > + >=20 > +/** >=20 > + This structure contains the DXE policies which are related to GPIO dev= ice. >=20 > + >=20 > + Revision 1: >=20 > + - Inital version. >=20 > +**/ >=20 > +typedef struct { >=20 > + CONFIG_BLOCK_HEADER Header; ///< Config Block Header >=20 > + /** >=20 > + If GPIO ACPI device is not used by OS it can be hidden. In such case >=20 > + no other device exposed to the system can reference GPIO device in o= ne >=20 > + of its resources through GpioIo(..) or GpioInt(..) ACPI descriptors. >=20 > + 0: Disable; 1: Enable >=20 > + **/ >=20 > + UINT32 HideGpioAcpiDevice : 1; >=20 > + UINT32 RsvdBits : 31; ///< Reserved bits >=20 > + >=20 > +} GPIO_DXE_CONFIG; >=20 > + >=20 > +#pragma pack (pop) >=20 > + >=20 > +#endif // _GPIO_DEV_CONFIG_H_ >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Graphics/Gen12/Gr= a > phicsConfig.h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Graphics/Gen12/Gr= a > phicsConfig.h > new file mode 100644 > index 0000000000..c3b134b830 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Graphics/Gen12/Gr= a > phicsConfig.h > @@ -0,0 +1,211 @@ > +/** @file >=20 > + Policy definition for Internal Graphics Config Block. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _GRAPHICS_CONFIG_H_ >=20 > +#define _GRAPHICS_CONFIG_H_ >=20 > +#pragma pack(push, 1) >=20 > + >=20 > +#define GRAPHICS_PEI_PREMEM_CONFIG_REVISION 3 >=20 > +#define GRAPHICS_PEI_CONFIG_REVISION 7 >=20 > +#define GRAPHICS_DXE_CONFIG_REVISION 1 >=20 > + >=20 > +#define DDI_DEVICE_NUMBER 4 >=20 > +#define MAX_BCLM_ENTRIES 20 >=20 > + >=20 > + >=20 > +// >=20 > +// DDI defines >=20 > +// >=20 > +typedef enum { >=20 > + DdiDisable =3D 0x00, >=20 > + DdiDdcEnable =3D 0x01, >=20 > +} DDI_DDC_TBT_VAL; >=20 > + >=20 > +typedef enum { >=20 > + DdiHpdDisable =3D 0x00, >=20 > + DdiHpdEnable =3D 0x01, >=20 > +} DDI_HPD_VAL; >=20 > + >=20 > +typedef enum { >=20 > + DdiPortDisabled =3D 0x00, >=20 > + DdiPortEdp =3D 0x01, >=20 > + DdiPortMipiDsi =3D 0x02, >=20 > +} DDI_PORT_SETTINGS; >=20 > + >=20 > +/** >=20 > + This structure configures the Native GPIOs for DDI port per VBT settin= gs. >=20 > +**/ >=20 > +typedef struct { >=20 > + UINT8 DdiPortAConfig; /// The Configuration of DDI port A, this settin= gs > must match VBT's settings. DdiPortDisabled - No LFP is connected on > DdiPortA, DdiPortEdp - Set DdiPortA to eDP, DdiPortMipiDsi - Set > DdiPortA to MIPI DSI >=20 > + UINT8 DdiPortBConfig; /// The Configuration of DDI port B, this settin= gs > must match VBT's settings. DdiPortDisabled - No LFP is connected on > DdiPortB, DdiPortEdp - Set DdiPortB to eDP, DdiPortMipiDsi - Set > DdiPortB to MIPI DSI >=20 > + UINT8 DdiPortAHpd; /// The HPD setting of DDI Port A, this settings= must > match VBT's settings. DdiHpdDisable - Disable HPD, DdiHpdEnable - > Enable HPD >=20 > + UINT8 DdiPortBHpd; /// The HPD setting of DDI Port B, this settings= must > match VBT's settings. DdiHpdDisable - Disable HPD, DdiHpdEnable - > Enable HPD >=20 > + UINT8 DdiPortCHpd; /// The HPD setting of DDI Port C, this settings= must > match VBT's settings. DdiHpdDisable - Disable HPD, DdiHpdEnable - > Enable HPD >=20 > + UINT8 DdiPort1Hpd; /// The HPD setting of DDI Port 1, this settings= must > match VBT's settings. DdiHpdDisable - Disable HPD, DdiHpdEnable - > Enable HPD >=20 > + UINT8 DdiPort2Hpd; /// The HPD setting of DDI Port 2, this settings= must > match VBT's settings. DdiHpdDisable - Disable HPD, DdiHpdEnable - > Enable HPD >=20 > + UINT8 DdiPort3Hpd; /// The HPD setting of DDI Port 3, this settings= must > match VBT's settings. DdiHpdDisable - Disable HPD, DdiHpdEnable - > Enable HPD >=20 > + UINT8 DdiPort4Hpd; /// The HPD setting of DDI Port 4, this settings= must > match VBT's settings. DdiHpdDisable - Disable HPD, DdiHpdEnable - > Enable HPD >=20 > + UINT8 DdiPortADdc; /// The DDC setting of DDI Port A, this settings= must > match VBT's settings. DdiDisable - Disable DDC, DdiDdcEnable - > Enable DDC >=20 > + UINT8 DdiPortBDdc; /// The DDC setting of DDI Port B, this settings= must > match VBT's settings. DdiDisable - Disable DDC, DdiDdcEnable - Enable > DDC >=20 > + UINT8 DdiPortCDdc; /// The DDC setting of DDI Port C, this settings= must > match VBT's settings. DdiDisable - Disable DDC, DdiDdcEnable - > Enable DDC >=20 > + UINT8 DdiPort1Ddc; /// The DDC setting of DDI Port 1, this settings= must > match VBT's settings. DdiDisable - Disable DDC, DdiDdcEnable - > Enable DDC >=20 > + UINT8 DdiPort2Ddc; /// The DDC setting of DDI Port 2, this settings= must > match VBT's settings. DdiDisable - Disable DDC, DdiDdcEnable - > Enable DDC >=20 > + UINT8 DdiPort3Ddc; /// The DDC setting of DDI Port 3, this settings= must > match VBT's settings. DdiDisable - Disable DDC, DdiDdcEnable - > Enable DDC >=20 > + UINT8 DdiPort4Ddc; /// The DDC setting of DDI Port 4, this settings= must > match VBT's settings. DdiDisable - Disable DDC, DdiDdcEnable - > Enable DDC >=20 > +} DDI_CONFIGURATION; >=20 > + >=20 > +/** >=20 > + This Configuration block is to configure GT related PreMem > data/variables.\n >=20 > + Revision 1: >=20 > + - Initial version. >=20 > + Revision 2: >=20 > + - Added DfdRestoreEnable. >=20 > + Revision 3: >=20 > + - Added DdiConfiguration. >=20 > + Revision 4: >=20 > + - Added GmAdr64 and made GmAdr obselete >=20 > +**/ >=20 > +typedef struct { >=20 > + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Confi= g Block > Header >=20 > + /** >=20 > + Offset 28 >=20 > + Selection of the primary display device: 0=3DiGFX, 1=3DPEG, 2=3DPCIe= Graphics > on PCH, 3=3DAUTO, 4=3DSwitchable Graphics\n >=20 > + When AUTO mode selected, the priority of display devices is: PCIe > Graphics on PCH > PEG > iGFX >=20 > + **/ >=20 > + UINT8 PrimaryDisplay; >=20 > + /** >=20 > + Offset 29 >=20 > + Intel Gfx Support. It controls enabling/disabling iGfx device. >=20 > + When AUTO mode selected, iGFX will be turned off when external > graphics detected. >=20 > + If FALSE, all other polices can be ignored. >=20 > + 2 =3D AUTO; >=20 > + 0 =3D FALSE; >=20 > + 1 =3D TRUE. >=20 > + **/ >=20 > + UINT8 InternalGraphics; >=20 > + /** >=20 > + Offset 30 >=20 > + Pre-allocated memory for iGFX\n >=20 > + 0 =3D 0MB,1 or 247 =3D 32MB,\n >=20 > + 2 =3D 64MB,\n >=20 > + 240 =3D 4MB, 241 =3D 8MB,\n >=20 > + 242 =3D 12MB, 243 =3D 16MB,\n >=20 > + 244 =3D 20MB, 245 =3D 24MB,\n >=20 > + 246 =3D 28MB, 248 =3D 36MB,\n >=20 > + 249 =3D 40MB, 250 =3D 44MB,\n >=20 > + 251 =3D 48MB, 252 =3D 52MB,\n >=20 > + 253 =3D 56MB, 254 =3D 60MB,\n >=20 > + Note: enlarging pre-allocated memory for iGFX may need to reduce > MmioSize because of 4GB boundary limitation >=20 > + **/ >=20 > + UINT16 IgdDvmt50PreAlloc; >=20 > + UINT8 PanelPowerEnable; ///< Offset 32 :(Test) Control > for enabling/disabling VDD force bit (Required only for early enabling of= eDP > panel): 0=3DFALSE, 1=3DTRUE >=20 > + UINT8 ApertureSize; ///< Offset 33 :Graphics ape= rture size > (256MB is the recommended size as per BWG) : 0=3D128MB, > 1=3D256MB, 3=3D512MB, 7=3D1024MB, 15=3D2048MB. >=20 > + UINT8 GtPsmiSupport; ///< Offset 34 :PSMI support= On/Off: > 0=3DFALSE, 1=3DTRUE >=20 > + UINT8 PsmiRegionSize; ///< Offset 35 :Psmi region = size: > 0=3D32MB, 1=3D288MB, 2=3D544MB, 3=3D800MB, 4=3D1056MB >=20 > + UINT8 DismSize; ///< Offset 36 :DiSM Size fo= r 2LM Sku: > 0=3D0GB, 1=3D1GB, 2=3D2GB, 3=3D3GB, 4=3D4GB, 5=3D5GB, 6=3D6GB, 7= =3D7GB >=20 > + UINT8 DfdRestoreEnable; ///< Offset 37 :Display memo= ry map > programming for DFD Restore 0- Disable, 1- Enable >=20 > + UINT16 GttSize; ///< Offset 38 :Selection of= iGFX GTT Memory > size: 1=3D2MB, 2=3D4MB, 3=3D8MB >=20 > + /** >=20 > + Offset 40 >=20 > + Temp Address of System Agent GTTMMADR: Default is > 0xAF000000 >=20 > + **/ >=20 > + UINT32 GttMmAdr; >=20 > + UINT32 GmAdr; ///< Offset 44 Obsolete not = to be used, use > GmAdr64 >=20 > + DDI_CONFIGURATION DdiConfiguration; ///< Offset 48 DDI > configuration, need to match with VBT settings. >=20 > + >=20 > + UINT8 GtClosEnable; ///< Offset 50 Gt ClOS >=20 > + UINT8 Rsvd0[7]; ///< Offset 51 Reserved for = 4 bytes of > alignment >=20 > + /** >=20 > + Offset 58 >=20 > + Temp Address of System Agent GMADR: Default is 0xB0000000 >=20 > + **/ >=20 > + UINT64 GmAdr64; >=20 > +} GRAPHICS_PEI_PREMEM_CONFIG; >=20 > + >=20 > +/** >=20 > + This configuration block is to configure IGD related variables used in > PostMem PEI. >=20 > + If Intel Gfx Device is not supported, all policies can be ignored. >=20 > + Revision 1: >=20 > + - Initial version. >=20 > + Revision 2: >=20 > + - Removed DfdRestoreEnable. >=20 > + Revision 3: >=20 > + - Removed DdiConfiguration. >=20 > + Revision 4: >=20 > + - Added new CdClock frequency >=20 > + Revision 5: >=20 > + - Added GT Chicket bits >=20 > + Revision 6: >=20 > + - Added LogoPixelHeight and LogoPixelWidth >=20 > + Revision 7: >=20 > + - Added SkipFspGop >=20 > + >=20 > +**/ >=20 > +typedef struct { >=20 > + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Blo= ck > Header >=20 > + UINT8 RenderStandby; ///< Offset 28 :(Test) This field > is used to enable or disable RC6 (Render Standby): 0=3DFALSE, 1=3DTRUE= >=20 > + UINT8 PmSupport; ///< Offset 29 :(Test) IGD PM > Support TRUE/FALSE: 0=3DFALSE, 1=3DTRUE >=20 > + /** >=20 > + Offset 30 >=20 > + CdClock Frequency select\n >=20 > + 0xFF =3D Auto. Max CdClock freq based on Reference Clk \n >=20 > + 0: 192 Mhz, 1: 307.2 Mhz, 2: 312 Mhz, 3: 324 Mhz, 4: 326.4 Mhz, 5: = 552 > Mhz, 6: 556.8 Mhz, 7: 648 Mhz, 8: 652.8 Mhz >=20 > + >=20 > + **/ >=20 > + UINT16 CdClock; >=20 > + UINT8 PeiGraphicsPeimInit; ///< Offset 32 : This polic= y is used to > enable/disable Intel Gfx PEIM.0- Disable, 1- Enable >=20 > + UINT8 CdynmaxClampEnable; ///< Offset 33 : This polic= y is used to > enable/disable CDynmax Clamping Feature (CCF) 1- Enable, 0- > Disable >=20 > + UINT16 GtFreqMax; ///< Offset 34 : (Test)<= /b> Max GT > frequency limited by user in multiples of 50MHz: Default value which > indicates normal frequency is 0xFF >=20 > + UINT8 DisableTurboGt; ///< Offset 36 : This polic= y is used to > enable/disable DisableTurboGt 0- Disable, 1- Enable >=20 > + UINT8 SkipCdClockInit; ///< Offset 37 : SKip full = CD clock > initialization. 0- Disable, 1- Enable >=20 > + UINT8 RC1pFreqEnable; ///< Offset 38 : This polic= y is used to > enable/disable RC1p Frequency. 0- Disable, 1- Enable >=20 > + UINT8 PavpEnable; ///< Offset 39 :IGD PAVP TR= UE/FALSE: > 0=3DFALSE, 1=3DTRUE >=20 > + VOID* LogoPtr; ///< Offset 40 Address of I= ntel Gfx PEIM > Logo to be displayed >=20 > + UINT32 LogoSize; ///< Offset 44 Intel Gfx PE= IM Logo Size >=20 > + VOID* GraphicsConfigPtr; ///< Offset 48 Address of t= he Graphics > Configuration Table >=20 > + VOID* BltBufferAddress; ///< Offset 52 Address of B= lt buffer for > PEIM Logo use >=20 > + UINT32 BltBufferSize; ///< Offset 56 The size for= Blt Buffer, > calculating by PixelWidth * PixelHeight * 4 bytes (the size of > EFI_GRAPHICS_OUTPUT_BLT_PIXEL) >=20 > + UINT8 ProgramGtChickenBits; ///< Offset 60 Program GT C= hicket > bits in GTTMMADR + 0xD00 BITS [3:1]. >=20 > + UINT8 SkipFspGop; ///< Offset 61 This policy = is used to skip > PEIM GOP in FSP.0- Use FSP provided GOP driver, 1- Skip FSP > provided GOP driver >=20 > + UINT8 Rsvd1[2]; ///< Offset 62 Reserved for= 4 bytes > alignment >=20 > + UINT32 LogoPixelHeight; ///< Offset 64 Address of > LogoPixelHeight for PEIM Logo use >=20 > + UINT32 LogoPixelWidth; ///< Offset 68 Address of > LogoPixelWidth for PEIM Logo use >=20 > +} GRAPHICS_PEI_CONFIG; >=20 > + >=20 > +/** >=20 > + This configuration block is to configure IGD related variables used in= DXE. >=20 > + If Intel Gfx Device is not supported or disabled, all policies will be= ignored. >=20 > + The data elements should be initialized by a Platform Module.\n >=20 > + Revision 1: >=20 > + - Initial version. >=20 > +**/ >=20 > +typedef struct { >=20 > + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27: Conf= ig Block > Header >=20 > + UINT32 Size; ///< Offset 28 - 31: T= his field gives the size of > the GOP VBT Data buffer >=20 > + EFI_PHYSICAL_ADDRESS VbtAddress; ///< Offset 32 - 39: T= his field > points to the GOP VBT data buffer >=20 > + UINT8 PlatformConfig; ///< Offset 40: This f= ield gives the > Platform Configuration Information (0=3DPlatform is S0ix Capable for ULT = SKUs > only, 1=3DPlatform is not S0ix Capable, 2=3DForce Platform is S0ix > Capable for All SKUs) >=20 > + UINT8 AlsEnable; ///< Offset 41: Ambien= t Light Sensor > Enable: 0=3DDisable, 2=3DEnable >=20 > + UINT8 BacklightControlSupport; ///< Offset 42: Backli= ght Control > Support: 0=3DPWM Inverted, 2=3DPWM Normal >=20 > + UINT8 IgdBootType; ///< Offset 43: IGD Bo= ot Type CMOS > option: 0=3DDefault, 0x01=3DCRT, 0x04=3DEFP, 0x08=3DLFP, 0x20=3DEF= P3, > 0x40=3DEFP2, 0x80=3DLFP2 >=20 > + UINT32 IuerStatusVal; ///< Offset 44 - 47: O= ffset 16 This field > holds the current status of all the supported Ultrabook events (Intel(R) > Ultrabook Event Status bits) >=20 > + CHAR16 GopVersion[0x10]; ///< Offset 48 - 79:Th= is field holds > the GOP Driver Version. It is an Output Protocol and updated by the Silic= on > code >=20 > + /** >=20 > + Offset 80: IGD Panel Type CMOS option\n >=20 > + 0=3DDefault, 1=3D640X480LVDS, 2=3D800X600LVDS, 3=3D1024X768LV= DS, > 4=3D1280X1024LVDS, 5=3D1400X1050LVDS1\n >=20 > + 6=3D1400X1050LVDS2, 7=3D1600X1200LVDS, 8=3D1280X768LVDS, > 9=3D1680X1050LVDS, 10=3D1920X1200LVDS, 13=3D1600X900LVDS\n >=20 > + 14=3D1280X800LVDS, 15=3D1280X600LVDS, 16=3D2048X1536LVDS, > 17=3D1366X768LVDS >=20 > + **/ >=20 > + UINT8 IgdPanelType; >=20 > + UINT8 IgdPanelScaling; ///< Offset 81: IGD Pa= nel Scaling: > 0=3DAUTO, 1=3DOFF, 6=3DForce scaling >=20 > + UINT8 IgdBlcConfig; ///< Offset 82: Backli= ght Control > Support: 0=3DPWM Inverted, 2=3DPWM Normal >=20 > + UINT8 IgdDvmtMemSize; ///< Offset 83: IGD DV= MT Memory > Size: 1=3D128MB, 2=3D256MB, 3=3DMAX >=20 > + UINT8 GfxTurboIMON; ///< Offset 84: IMON C= urrent Value: > 14=3DMinimal, 31=3DMaximum >=20 > + UINT8 Reserved[3]; ///< Offset 85: Reserv= ed for DWORD > alignment. >=20 > + UINT16 BCLM[MAX_BCLM_ENTRIES]; ///< Offset 88: IGD Ba= cklight > Brightness Level Duty cycle Mapping Table. >=20 > +} GRAPHICS_DXE_CONFIG; >=20 > +#pragma pack(pop) >=20 > + >=20 > +#endif // _GRAPHICS_CONFIG_H_ >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Hda/HdAudioConfig= . > h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Hda/HdAudioConfig= . > h > new file mode 100644 > index 0000000000..a2e0a65e45 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Hda/HdAudioConfig= . > h > @@ -0,0 +1,227 @@ > +/** @file >=20 > + HDAUDIO policy >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _HDAUDIO_CONFIG_H_ >=20 > +#define _HDAUDIO_CONFIG_H_ >=20 > + >=20 > +#include >=20 > +#include >=20 > + >=20 > +#define HDAUDIO_PREMEM_CONFIG_REVISION 2 >=20 > +#define HDAUDIO_CONFIG_REVISION 1 >=20 > +#define HDAUDIO_DXE_CONFIG_REVISION 1 >=20 > + >=20 > +extern EFI_GUID gHdAudioPreMemConfigGuid; >=20 > +extern EFI_GUID gHdAudioConfigGuid; >=20 > +extern EFI_GUID gHdAudioDxeConfigGuid; >=20 > + >=20 > +#pragma pack (push,1) >=20 > + >=20 > +/// >=20 > +/// The PCH_HDAUDIO_CONFIG block describes the expected configuration > of the Intel HD Audio feature. >=20 > +/// >=20 > + >=20 > +#define HDAUDIO_VERB_TABLE_VIDDID(Vid,Did) > (UINT32)((UINT16)Vid | ((UINT16)Did << 16)) >=20 > +#define HDAUDIO_VERB_TABLE_RID_SDI_SIZE(Rid,Sdi,VerbTableSize) > (UINT32)((UINT8)Rid | ((UINT8)Sdi << 8) | ((UINT16)VerbTableSize << 16)) >=20 > +#define HDAUDIO_VERB_TABLE_CMD_SIZE(VerbTable) ((sizeof > (VerbTable) - sizeof (HDA_VERB_TABLE_HEADER)) / (sizeof (UINT32))) >=20 > + >=20 > +/// >=20 > +/// Use this macro to create HDAUDIO_VERB_TABLE and populate size > automatically >=20 > +/// >=20 > +#define HDAUDIO_VERB_TABLE_INIT(Vid,Did,Rid,Sdi,...) \ >=20 > +{ \ >=20 > + { Vid, Did, Rid, Sdi, (sizeof((UINT32[]){__VA_ARGS__})/sizeof(UINT32))= }, \ >=20 > + { __VA_ARGS__ } \ >=20 > +} >=20 > + >=20 > + >=20 > +/** >=20 > + Azalia verb table header >=20 > + Every verb table should contain this defined header and followed by az= alia > verb commands. >=20 > +**/ >=20 > +typedef struct { >=20 > + UINT16 VendorId; ///< Codec Vendor ID >=20 > + UINT16 DeviceId; ///< Codec Device ID >=20 > + UINT8 RevisionId; ///< Revision ID of the codec. 0xFF matc= hes any > revision. >=20 > + UINT8 SdiNum; ///< SDI number, 0xFF matches any SDI. >=20 > + UINT16 DataDwords; ///< Number of data DWORDs following the > header. >=20 > +} HDA_VERB_TABLE_HEADER; >=20 > + >=20 > +#ifdef _MSC_VER >=20 > +// >=20 > +// Disable "zero-sized array in struct/union" extension warning. >=20 > +// Used for neater verb table definitions. >=20 > +// >=20 > +#pragma warning (push) >=20 > +#pragma warning (disable: 4200) >=20 > +#endif >=20 > +typedef struct { >=20 > + HDA_VERB_TABLE_HEADER Header; >=20 > + UINT32 Data[]; >=20 > +} HDAUDIO_VERB_TABLE; >=20 > +#ifdef _MSC_VER >=20 > +#pragma warning (pop) >=20 > +#endif >=20 > + >=20 > +typedef struct { >=20 > + UINT32 ClkA; ///< Pin mux configuration. Refer to > GPIO_*_MUXING_DMIC*_CLKA_* >=20 > + UINT32 ClkB; ///< Pin mux configuration. Refer to > GPIO_*_MUXING_DMIC*_CLKB_* >=20 > + UINT32 Data; ///< Pin mux configuration. Refer to > GPIO_*_MUXING_DMIC*_DATA_* >=20 > +} HDA_DMIC_PIN_MUX; >=20 > + >=20 > +/** >=20 > + HD Audio Link Policies >=20 > +**/ >=20 > +typedef struct { >=20 > + UINT32 Enable : 1; ///< HDA interface enable. When enabled relat= ed > pins will be switched to native mode: 0: Disable; 1: Enable. >=20 > + UINT32 RsvdBits0 : 31; >=20 > + UINT8 SdiEnable[PCH_MAX_HDA_SDI]; ///< HDA SDI signal enable. > When enabled related SDI pins will be switched to appropriate native mode= : > 0: Disable; 1: Enable >=20 > + UINT8 Reserved[(4 - (PCH_MAX_HDA_SDI % 4)) % 4]; ///< Padding for > SDI enable table. >=20 > +} HDA_LINK_HDA; >=20 > + >=20 > +/** >=20 > + HD Audio DMIC Interface Policies >=20 > +**/ >=20 > +typedef struct { >=20 > + UINT32 Enable : 1; ///< HDA DMIC interface enab= le. When > enabled related pins will be switched to native mode: 0: Disable; = 1: > Enable. >=20 > + UINT32 DmicClockSelect : 2; ///< DMIC link clock select:= 0: > Both, 1: ClkA, 2: ClkB; default is "Both" >=20 > + UINT32 RsvdBits0 : 29; >=20 > + HDA_DMIC_PIN_MUX PinMux; ///< Pin mux configuration. >=20 > +} HDA_LINK_DMIC; >=20 > + >=20 > +/** >=20 > + HD Audio SSP Interface Policies >=20 > +**/ >=20 > +typedef struct { >=20 > + UINT32 Enable : 1; ///< HDA SSP interface enable. Whe= n enabled > related pins will be switched to native mode: 0: Disable; 1: Enabl= e. >=20 > + UINT32 RsvdBits0 : 31; >=20 > +} HDA_LINK_SSP; >=20 > + >=20 > +/** >=20 > + HD Audio SNDW Interface Policies >=20 > +**/ >=20 > +typedef struct { >=20 > + UINT32 Enable : 1; ///< HDA SNDW interface enable. Wh= en > enabled related pins will be switched to native mode: 0: Disable; = 1: > Enable. >=20 > + UINT32 RsvdBits0 : 31; >=20 > +} HDA_LINK_SNDW; >=20 > + >=20 > + >=20 > +/** >=20 > + This structure contains the policies which are related to HD Audio dev= ice > (cAVS). >=20 > + >=20 > + Revision 1: >=20 > + - Inital version. >=20 > + >=20 > +**/ >=20 > +typedef struct { >=20 > + CONFIG_BLOCK_HEADER Header; ///< Config Block Header >=20 > + UINT32 Pme : 1; ///< Azalia wake-on-ring, 0:= Disable; 1: > Enable >=20 > + UINT32 CodecSxWakeCapability : 1; ///< Capability to detect wake > initiated by a codec in Sx (eg by modem codec), 0: Disable; 1: Ena= ble >=20 > + UINT32 HdAudioLinkFrequency : 4; ///< HDA-Link frequency > (PCH_HDAUDIO_LINK_FREQUENCY enum): 2: 24MHz, 1: 12MHz, 0: > 6MHz >=20 > + UINT32 RsvdBits0 : 26; ///< Reserved bits 0 >=20 > + /** >=20 > + Number of the verb table entry defined in VerbTablePtr. >=20 > + Each entry points to a verb table which contains HDAUDIO_VERB_TABLE > structure and verb command blocks. >=20 > + **/ >=20 > + UINT8 VerbTableEntryNum; >=20 > + UINT8 Rsvd0[3]; ///< Reserved bytes, align t= o multiple 4 >=20 > + /** >=20 > + Pointer to a verb table array. >=20 > + This pointer points to 32bits address, and is only eligible and cons= umed in > post mem phase. >=20 > + Each entry points to a verb table which contains HDAUDIO_VERB_TABLE > structure and verb command blocks. >=20 > + The prototype of this is: >=20 > + HDAUDIO_VERB_TABLE **VerbTablePtr; >=20 > + **/ >=20 > + UINT32 VerbTablePtr; >=20 > +} HDAUDIO_CONFIG; >=20 > + >=20 > +/** >=20 > + This structure contains the premem policies which are related to HD Au= dio > device (cAVS). >=20 > + >=20 > + Revision 1: >=20 > + - Inital version. >=20 > + Revision 2: >=20 > + - Add DmicClockSelect >=20 > +**/ >=20 > +typedef struct { >=20 > + CONFIG_BLOCK_HEADER Header; ///< Config Block Header >=20 > + UINT32 Enable : 1; ///< Intel HD Audio (Azalia) en= ablement: 0: > Disable, 1: Enable >=20 > + UINT32 DspEnable : 1; ///< DSP enablement: 0: Disable= ; 1: > Enable >=20 > + UINT32 VcType : 1; ///< Virtual Channel Type Selec= t: 0: > VC0, 1: VC1 >=20 > + /** >=20 > + Universal Audio Architecture compliance for DSP enabled system: >=20 > + 0: Not-UAA Compliant (Intel SST driver supported only), >=20 > + 1: UAA Compliant (HDA Inbox driver or SST driver supported) >=20 > + **/ >=20 > + UINT32 DspUaaCompliance : 1; >=20 > + UINT32 IDispLinkFrequency : 4; ///< iDisp-Link frequency > (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz >=20 > + UINT32 IDispLinkTmode : 3; ///< iDisp-Link T-Mode > (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 1: 1T, 2: 4T, 3: 8T, 4: > 16T >=20 > + UINT32 IDispCodecDisconnect : 1; ///< iDisplay Audio Codec > disconnection, 0: Not disconnected, enumerable; 1: Disconnected > SDI, not enumerable >=20 > + UINT32 PowerGatingSupported : 1; ///< Power Gating supported: 0: > Not supported, 1: Supported >=20 > + UINT32 RsvdBits : 19; ///< Reserved bits 0 >=20 > + >=20 > + /** >=20 > + Audio Link Mode configuration bitmask. >=20 > + Allows to configure enablement of the following interfaces: HDA-Link= , > DMIC, SSP, SoundWire. >=20 > + **/ >=20 > + >=20 > + HDA_LINK_HDA AudioLinkHda; ///< HDA-Link enablement: 0: > Disable; 1: Enable. >=20 > + /** >=20 > + DMIC link enablement: 0: Disable; 1: Enable. >=20 > + DMIC0 LKF: Muxed with SNDW2/SNDW4. >=20 > + **/ >=20 > + HDA_LINK_DMIC AudioLinkDmic [2]; >=20 > + /** >=20 > + I2S/SSP link enablement: 0: Disable; 1: Enable. >=20 > + SSP0/1 LKF: Muxed with HDA. >=20 > + @note Since the I2S/SSP2 pin set contains pads which are also used f= or > CNVi purpose, enabling AudioLinkSsp2 >=20 > + is exclusive with CNVi is present. >=20 > + **/ >=20 > + HDA_LINK_SSP AudioLinkSsp [PCH_MAX_HDA_SSP_LINK_NUM]; >=20 > + /** >=20 > + SoundWire link enablement: 0: Disable; 1: Enable. >=20 > + SNDW2 LKF: Muxed with DMIC0/DMIC1. >=20 > + SNDW3 LKF: Muxed with DMIC1. >=20 > + SNDW4 LKF: Muxed with DMIC0. >=20 > + **/ >=20 > + HDA_LINK_SNDW AudioLinkSndw > [PCH_MAX_HDA_SNDW_LINK_NUM]; >=20 > + >=20 > + >=20 > + UINT16 ResetWaitTimer; ///< (Test) The delay= timer > after Azalia reset, the value is number of microseconds. Default is > 600. >=20 > + UINT8 Rsvd0[2]; ///< Reserved bytes, align t= o multiple 4 >=20 > + >=20 > +} HDAUDIO_PREMEM_CONFIG; >=20 > + >=20 > +typedef struct { >=20 > + UINT32 AutonomousClockStop : 1; ///< SoundWire1 link > autonomous clock stop capability: 0: Disable; 1: Enable >=20 > + UINT32 DataOnActiveIntervalSelect : 2; ///< SoundWire1 link data = on > active interval select 0: 3 clock periods; 1: 4 clock periods; 2: = 5 clock > periods; 3: 6 clock periods >=20 > + UINT32 DataOnDelaySelect : 1; ///< SoundWire1 link data = on delay > select 0: 2 clock periods; 1: 3 clock periods >=20 > + UINT32 RsvdBits1 : 28; ///< Reserved bits 1 >=20 > +} HDAUDIO_SNDW_CONFIG; >=20 > + >=20 > +/** >=20 > + This structure contains the DXE policies which are related to HD Audio > device (cAVS). >=20 > + Revision 1: >=20 > + - Inital version. >=20 > +**/ >=20 > +typedef struct { >=20 > + CONFIG_BLOCK_HEADER Header; ///< Config Block Header >=20 > + /** >=20 > + SNDW configuration for exposed via SNDW ACPI tables: >=20 > + **/ >=20 > + HDAUDIO_SNDW_CONFIG > SndwConfig[PCH_MAX_HDA_SNDW_LINK_NUM]; >=20 > + /** >=20 > + Bitmask of supported DSP features: >=20 > + [BIT0] - WoV; [BIT1] - BT Sideband; [BIT2] - Codec VAD; [BIT5] - BT = Intel > HFP; [BIT6] - BT Intel A2DP >=20 > + [BIT7] - DSP based speech pre-processing disabled; [BIT8] - 0: Intel= WoV, > 1: Windows Voice Activation >=20 > + Default is zero. >=20 > + **/ >=20 > + UINT32 DspFeatureMask; >=20 > +} HDAUDIO_DXE_CONFIG; >=20 > + >=20 > +#pragma pack (pop) >=20 > + >=20 > +#endif // _HDAUDIO_CONFIG_H_ >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/HostBridge/HostBr= id > geConfig.h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/HostBridge/HostBr= id > geConfig.h > new file mode 100644 > index 0000000000..67335be92e > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/HostBridge/HostBr= id > geConfig.h > @@ -0,0 +1,62 @@ > +/** @file >=20 > + Configurations for HostBridge >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _HOST_BRIDGE_CONFIG_H_ >=20 > +#define _HOST_BRIDGE_CONFIG_H_ >=20 > + >=20 > +#include >=20 > + >=20 > +#define HOST_BRIDGE_PREMEM_CONFIG_REVISION 1 >=20 > +#define HOST_BRIDGE_PEI_CONFIG_REVISION 1 >=20 > + >=20 > +extern EFI_GUID gHostBridgePeiPreMemConfigGuid; >=20 > +extern EFI_GUID gHostBridgePeiConfigGuid; >=20 > + >=20 > +#pragma pack (push,1) >=20 > + >=20 > +/** >=20 > + This configuration block describes HostBridge settings in PreMem.\n >=20 > + Revision 1: >=20 > + - Initial version. >=20 > +**/ >=20 > +typedef struct { >=20 > + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Blo= ck > Header >=20 > + UINT32 MchBar; ///< Offset 28 Address of S= ystem Agent > MCHBAR: 0xFEDC0000(TGL)/0xFED10000(RKL)/0xFEA80000(JSL) >=20 > + UINT32 DmiBar; ///< Offset 32 Address of S= ystem Agent > DMIBAR: 0xFEDA0000 >=20 > + UINT32 EpBar; ///< Offset 36 Address of S= ystem Agent > EPBAR: 0xFEDA1000 >=20 > + UINT32 GdxcBar; ///< Offset 40 Address of S= ystem Agent > GDXCBAR: 0xFED84000 >=20 > + UINT32 RegBar; ///< Offset 44 Address of S= ystem Agent > REGBAR: 0xFB000000 >=20 > + UINT32 EdramBar; ///< Offset 48 Address of S= ystem Agent > EDRAMBAR: 0xFED80000 >=20 > + /** >=20 > + Offset 52 : >=20 > + Size of reserved MMIO space for PCI devices\n >=20 > + 0=3DAUTO, 512=3D512MB, 768=3D768MB, 1024=3D1024MB, 1280=3D128= 0MB, > 1536=3D1536MB, 1792=3D1792MB, >=20 > + 2048=3D2048MB, 2304=3D2304MB, 2560=3D2560MB, 2816=3D2816MB, > 3072=3D3072MB\n >=20 > + When AUTO mode selected, the MMIO size will be calculated by require= d > MMIO size from PCIe devices detected. >=20 > + **/ >=20 > + UINT32 MmioSize; >=20 > + UINT32 MmioSizeAdjustment; ///< Offset 56 Increase (gi= ven > positive value) or Decrease (given negative value) the Reserved MMIO size > when Dynamic Tolud/AUTO mode enabled (in MBs): 0=3Dno > adjustment >=20 > + UINT8 EnableAbove4GBMmio; ///< Offset 60 Enable/disab= le > above 4GB MMIO resource support: 0=3DDisable, 1=3DEnable >=20 > + UINT8 Reserved[3]; ///< Offset 61 Reserved for= future use. >=20 > +} HOST_BRIDGE_PREMEM_CONFIG; >=20 > + >=20 > + >=20 > +/** >=20 > + This configuration block describes HostBridge settings in Post-Mem.\n >=20 > + Revision 1: >=20 > + - Initial version. >=20 > +**/ >=20 > +typedef struct { >=20 > + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Blo= ck > Header >=20 > + UINT8 Device4Enable; ///< Offser 28 :This policy= is used to > control enable or disable System Agent Thermal device (0,4,0). > 0=3DFALSE, 1=3DTRUE. >=20 > + UINT8 ChapDeviceEnable; ///< Offset 29 :(Test)This > policy is used to control enable or disable System Agent Chap device (0,7= ,0). > 0=3DFALSE, 1=3DTRUE. >=20 > + UINT8 SkipPamLock; ///< Offset 30 :To skip PAM= register > locking. @note It is still recommended to set PCI Config space B0: D0: F0= : > Offset 80h[0]=3D1 in platform code even Silicon code skipped this.\n 0= =3DAll > PAM registers will be locked in Silicon code, 1=3DSkip lock PAM regis= ters in > Silicon code. >=20 > + UINT8 EdramTestMode; ///< Offset 28 :EDRAM Test = Mode. For > EDRAM stepping - 0- EDRAM SW Disable, 1- EDRAM SW Enable, 2- > EDRAM HW Mode >=20 > +} HOST_BRIDGE_PEI_CONFIG; >=20 > + >=20 > +#pragma pack (pop) >=20 > + >=20 > +#endif >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/HybridGraphics/Hy= br > idGraphicsConfig.h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/HybridGraphics/Hy= br > idGraphicsConfig.h > new file mode 100644 > index 0000000000..3f420aed48 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/HybridGraphics/Hy= br > idGraphicsConfig.h > @@ -0,0 +1,66 @@ > +/** @file >=20 > + Hybrid Graphics policy definitions >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _HYBRID_GRAPHICS_CONFIG_H_ >=20 > +#define _HYBRID_GRAPHICS_CONFIG_H_ >=20 > + >=20 > +#define HYBRID_GRAPHICS_CONFIG_REVISION 2 >=20 > + >=20 > +#pragma pack(push, 1) >=20 > +/// >=20 > +/// GPIO Support >=20 > +/// >=20 > +typedef enum { >=20 > + NotSupported =3D 0, >=20 > + PchGpio, >=20 > + I2CGpio, >=20 > +} GPIO_SUPPORT; >=20 > + >=20 > +/// >=20 > +/// CPU PCIe GPIO Data Structure >=20 > +/// >=20 > +typedef struct { >=20 > + UINT8 ExpanderNo; ///< Offset 0 Expander No For I2C based GPIO >=20 > + BOOLEAN Active; ///< Offset 1 0=3DActive Low; 1=3DActive High >=20 > + UINT8 Rsvd0[2]; ///< Offset 2 Reserved >=20 > + UINT32 GpioNo; ///< Offset 4 GPIO pad >=20 > +} CPU_PCIE_GPIO_INFO; >=20 > + >=20 > +/** >=20 > + CPU PCIE RTD3 GPIO Data Structure >=20 > +**/ >=20 > +typedef struct { >=20 > + CPU_PCIE_GPIO_INFO HoldRst; ///< Offset 0 This field contain PCI= e HLD > RESET GPIO value and level information >=20 > + CPU_PCIE_GPIO_INFO PwrEnable; ///< Offset 8 This field contain PCI= e > PWR Enable GPIO value and level information >=20 > + UINT32 WakeGpioNo; ///< Offset 16 This field contain PC= Ie RTD3 > Device Wake GPIO Number >=20 > + UINT8 GpioSupport; ///< Offset 20 Depends on board desi= gn the > GPIO configuration may be different: 0=3DNot Supported, 1=3DPCH > Based, 2=3DI2C based >=20 > + UINT8 Rsvd0[3]; ///< Offset 21 >=20 > +} CPU_PCIE_RTD3_GPIO; >=20 > + >=20 > +/** >=20 > + This Configuration block configures CPU PCI Express 0/1/2 RTD3 GPIOs & > Root Port. >=20 > + Hybrid Gfx uses the same GPIOs & Root port as PCI Express 0/1/2 RTD3. >=20 > + Revision 1: >=20 > + - Initial version. >=20 > + Revision 2: >=20 > + - Add HgSlot Policy: PEG or PCH Slot Slection for Hybrid Graphics >=20 > +**/ >=20 > +typedef struct { >=20 > + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Blo= ck > Header >=20 > + CPU_PCIE_RTD3_GPIO CpuPcie0Rtd3Gpio; ///< Offset 28 RTD3 GPIOs > used for PCIe >=20 > + UINT8 RootPortIndex; ///< Offset 52 Root Port In= dex number > used for HG >=20 > + UINT8 HgMode; ///< Offset 53 HgMode: > 0=3DDisabled, 1=3DHG Muxed, 2=3DHG Muxless, 3=3DPEG >=20 > + UINT16 HgSubSystemId; ///< Offset 54 Hybrid Graph= ics > Subsystem ID: 2212 >=20 > + UINT16 HgDelayAfterPwrEn; ///< Offset 56 Dgpu Delay a= fter > Power enable using Setup option: 0=3DMinimal, 1000=3DMaximum, 300=3D30= 0 > microseconds >=20 > + UINT16 HgDelayAfterHoldReset; ///< Offset 58 Dgpu Delay a= fter > Hold Reset using Setup option: 0=3DMinimal, 1000=3DMaximum, 100=3D100 > microseconds >=20 > + CPU_PCIE_RTD3_GPIO CpuPcie1Rtd3Gpio; ///< Offset 60 RTD3 GPIOs > used for PCIe >=20 > + CPU_PCIE_RTD3_GPIO CpuPcie2Rtd3Gpio; ///< Offset 84 RTD3 GPIOs > used for PCIe >=20 > + CPU_PCIE_RTD3_GPIO CpuPcie3Rtd3Gpio; ///< Offset 108 RTD3 GPIOs > used for PCIe >=20 > + UINT8 HgSlot; ///< Offset 132 Slot select= ion between PEG > and PCH >=20 > + UINT8 Rsvd0[3]; ///< Offset 133 Reserved By= tes >=20 > +} HYBRID_GRAPHICS_CONFIG; >=20 > +#pragma pack(pop) >=20 > +#endif // _HYBRID_GRAPHICS_CONFIG_H_ >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/HybridStorage/Hyb= ri > dStorageConfig.h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/HybridStorage/Hyb= ri > dStorageConfig.h > new file mode 100644 > index 0000000000..705fe43751 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/HybridStorage/Hyb= ri > dStorageConfig.h > @@ -0,0 +1,36 @@ > +/** @file >=20 > + Hybrid Storage policy >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _HYBRID_STORAGE_CONFIG_H_ >=20 > +#define _HYBRID_STORAGE_CONFIG_H_ >=20 > + >=20 > +#include >=20 > + >=20 > +#define HYBRID_STORAGE_CONFIG_REVISION 1 >=20 > + >=20 > +extern EFI_GUID gHybridStorageConfigGuid; >=20 > + >=20 > +#pragma pack (push,1) >=20 > + >=20 > +/** >=20 > + The HYBRID_STORAGE_CONFIG block describes the expected > configuration for Hybrid Storage device >=20 > + >=20 > + Revision 1: >=20 > + - Init version >=20 > +**/ >=20 > +typedef struct { >=20 > + CONFIG_BLOCK_HEADER Header; ///< Config Block Head= er >=20 > + /** >=20 > + Hybrid Storage Mode >=20 > + 0: Disable, 1: Enable Dynamic Configuration >=20 > + **/ >=20 > + UINT8 HybridStorageMode; >=20 > + UINT8 RsvdBytes[3]; >=20 > +} HYBRID_STORAGE_CONFIG; >=20 > + >=20 > +#pragma pack (pop) >=20 > + >=20 > +#endif // _HYBRID_STORAGE_CONFIG_H_ >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Ieh/IehConfig.h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Ieh/IehConfig.h > new file mode 100644 > index 0000000000..a9275152f5 > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Ieh/IehConfig= .h > @@ -0,0 +1,34 @@ > +/** @file >=20 > + Integrated Error Handler policy. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +#ifndef _IEH_CONFIG_H_ >=20 > +#define _IEH_CONFIG_H_ >=20 > + >=20 > +#define IEH_MODE_BYPASS 0 >=20 > +#define IEH_MODE_ENABLE 1 >=20 > + >=20 > +#define IEH_CONFIG_REVISION 1 >=20 > +extern EFI_GUID gIehConfigGuid; >=20 > + >=20 > +#pragma pack (push,1) >=20 > + >=20 > +/** >=20 > + The IEH_CONFIG block describes the expected configuration of the PCH >=20 > + Integrated Error Handler. >=20 > +**/ >=20 > +typedef struct { >=20 > + CONFIG_BLOCK_HEADER Header; ///< Config Block Header >=20 > + /** >=20 > + IEH mode 0: Bypass Mode; 1: Enable >=20 > + **/ >=20 > + UINT32 Mode : 1; >=20 > + UINT32 RsvdBits0 : 31; ///< Reserved bits >=20 > +} IEH_CONFIG; >=20 > + >=20 > +#pragma pack (pop) >=20 > + >=20 > +#endif // _IEH_CONFIG_H_ >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Ish/IshConfig.h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Ish/IshConfig.h > new file mode 100644 > index 0000000000..75a11e3052 > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Ish/IshConfig= .h > @@ -0,0 +1,134 @@ > +/** @file >=20 > + ISH policy >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _ISH_CONFIG_H_ >=20 > +#define _ISH_CONFIG_H_ >=20 > + >=20 > +#define ISH_PREMEM_CONFIG_REVISION 1 >=20 > +#define ISH_CONFIG_REVISION 1 >=20 > +extern EFI_GUID gIshPreMemConfigGuid; >=20 > +extern EFI_GUID gIshConfigGuid; >=20 > + >=20 > +#pragma pack (push,1) >=20 > + >=20 > +/** >=20 > + ISH GPIO settings >=20 > +**/ >=20 > +typedef struct { >=20 > + /** >=20 > + GPIO signals pin muxing settings. If signal can be enable only on a = single > pin >=20 > + then this parameter should be set to 0. Refer to > GPIO_*_MUXING_ISH_*x_* in GpioPins*.h >=20 > + for supported settings on a given platform >=20 > + **/ >=20 > + UINT32 PinMux; ///< GPIO Pin mux configuration.= Refer to > GPIO_*_MUXING_ISH_*x_MOSI_* >=20 > + /** >=20 > + GPIO Pads Internal Termination. >=20 > + For more information please see Platform Design Guide. >=20 > + Check GPIO_ELECTRICAL_CONFIG for reference >=20 > + **/ >=20 > + UINT32 PadTermination; >=20 > +} ISH_GPIO_CONFIG; >=20 > + >=20 > +/** >=20 > + SPI signals settings. >=20 > +**/ >=20 > +typedef struct { >=20 > + ISH_GPIO_CONFIG Mosi; ///< MOSI Pin configura= tion. >=20 > + ISH_GPIO_CONFIG Miso; ///< MISO Pin configura= tion. >=20 > + ISH_GPIO_CONFIG Clk; ///< CLK Pin configura= tion. >=20 > + ISH_GPIO_CONFIG Cs[PCH_MAX_ISH_SPI_CS_PINS]; ///< CS Pin > configuration. >=20 > +} ISH_SPI_PIN_CONFIG; >=20 > + >=20 > + >=20 > +/** >=20 > + UART signals settings. >=20 > +**/ >=20 > +typedef struct { >=20 > + ISH_GPIO_CONFIG Rx; ///< RXD Pin configuration. >=20 > + ISH_GPIO_CONFIG Tx; ///< TXD Pin configuration. >=20 > + ISH_GPIO_CONFIG Rts; ///< RTS Pin configuration. >=20 > + ISH_GPIO_CONFIG Cts; ///< CTS Pin configuration. >=20 > +} ISH_UART_PIN_CONFIG; >=20 > + >=20 > + >=20 > +/** >=20 > + I2C signals settings. >=20 > +**/ >=20 > +typedef struct { >=20 > + ISH_GPIO_CONFIG Sda; ///< SDA Pin configuration. >=20 > + ISH_GPIO_CONFIG Scl; ///< SCL Pin configuration. >=20 > +} ISH_I2C_PIN_CONFIG; >=20 > + >=20 > + >=20 > +/** >=20 > + Struct contains GPIO pins assigned and signal settings of SPI >=20 > +**/ >=20 > +typedef struct { >=20 > + UINT8 Enable; ///< ISH SPI GP= IO pins assigned: 0: > False 1: True >=20 > + UINT8 CsEnable[PCH_MAX_ISH_SPI_CS_PINS]; ///< ISH SPI CS= pins > assigned: 0: False 1: True >=20 > + UINT16 RsvdField0; ///< Reserved f= ield >=20 > + ISH_SPI_PIN_CONFIG PinConfig; >=20 > +} ISH_SPI; >=20 > + >=20 > + >=20 > +/** >=20 > + Struct contains GPIO pins assigned and signal settings of UART >=20 > +**/ >=20 > +typedef struct { >=20 > + UINT32 Enable : 1; ///< ISH UART GPIO pins assign= ed: 0: > False 1: True >=20 > + UINT32 RsvdBits0 : 31; ///< Reserved Bits >=20 > + ISH_UART_PIN_CONFIG PinConfig; >=20 > +} ISH_UART; >=20 > + >=20 > +/** >=20 > + Struct contains GPIO pins assigned and signal settings of I2C >=20 > +**/ >=20 > +typedef struct { >=20 > + UINT32 Enable : 1; ///< ISH I2C GPIO pins assigne= d: 0: > False 1: True >=20 > + UINT32 RsvdBits0 : 31; ///< Reserved Bits >=20 > + ISH_I2C_PIN_CONFIG PinConfig; >=20 > +} ISH_I2C; >=20 > + >=20 > +/** >=20 > + Struct contains GPIO pins assigned and signal settings of GP >=20 > +**/ >=20 > +typedef struct { >=20 > + UINT32 Enable : 1; ///< ISH GP GPIO pins assigned: <= b>0: > False 1: True >=20 > + UINT32 RsvdBits0 : 31; ///< Reserved Bits >=20 > + ISH_GPIO_CONFIG PinConfig; >=20 > +} ISH_GP; >=20 > + >=20 > +/// >=20 > +/// The ISH_CONFIG block describes Integrated Sensor Hub device. >=20 > +/// >=20 > +typedef struct { >=20 > + CONFIG_BLOCK_HEADER Header; ///< Config Block Header >=20 > + ISH_SPI Spi[PCH_MAX_ISH_SPI_CONTROLLERS]; >=20 > + ISH_UART Uart[PCH_MAX_ISH_UART_CONTROLLERS]; >=20 > + ISH_I2C I2c[PCH_MAX_ISH_I2C_CONTROLLERS]; >=20 > + ISH_GP Gp[PCH_MAX_ISH_GP_PINS]; >=20 > + >=20 > + UINT32 PdtUnlock : 1; ///< ISH PDT Unlock Msg: <= b>0: > False 1: True >=20 > + UINT32 RsvdBits0 : 31; ///< Reserved Bits >=20 > + >=20 > +} ISH_CONFIG; >=20 > + >=20 > +/// >=20 > +/// Premem Policy for Integrated Sensor Hub device. >=20 > +/// >=20 > +typedef struct { >=20 > + CONFIG_BLOCK_HEADER Header; ///< Config Block Header >=20 > + /** >=20 > + ISH Controler 0: Disable; 1: Enable. >=20 > + For Desktop sku, the ISH POR should be disabled. 0:Disable . >=20 > + **/ >=20 > + UINT32 Enable : 1; >=20 > + UINT32 RsvdBits0 : 31; ///< Reserved Bits >=20 > +} ISH_PREMEM_CONFIG; >=20 > + >=20 > +#pragma pack (pop) >=20 > + >=20 > +#endif // _ISH_CONFIG_H_ >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Itss/InterruptCon= fig. > h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Itss/InterruptCon= fig. > h > new file mode 100644 > index 0000000000..7f6fa8675b > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Itss/InterruptCon= fig. > h > @@ -0,0 +1,58 @@ > +/** @file >=20 > + Interrupt policy >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _INTERRUPT_CONFIG_H_ >=20 > +#define _INTERRUPT_CONFIG_H_ >=20 > + >=20 > +#define INTERRUPT_CONFIG_REVISION 1 >=20 > +extern EFI_GUID gInterruptConfigGuid; >=20 > + >=20 > +#pragma pack (push,1) >=20 > + >=20 > +// >=20 > +// --------------------- Interrupts Config -----------------------------= - >=20 > +// >=20 > +typedef enum { >=20 > + PchNoInt, ///< No Interrupt Pin >=20 > + PchIntA, >=20 > + PchIntB, >=20 > + PchIntC, >=20 > + PchIntD >=20 > +} PCH_INT_PIN; >=20 > + >=20 > +/// >=20 > +/// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, > IRQ and interrupt mode for PCH device. >=20 > +/// >=20 > +typedef struct { >=20 > + UINT8 Device; ///< Device number >=20 > + UINT8 Function; ///< Device function >=20 > + UINT8 IntX; ///< Interrupt pin: INTA-INTD (s= ee PCH_INT_PIN) >=20 > + UINT8 Irq; ///< IRQ to be set for device. >=20 > +} PCH_DEVICE_INTERRUPT_CONFIG; >=20 > + >=20 > +#define PCH_MAX_DEVICE_INTERRUPT_CONFIG 128 ///< Number of all > PCH devices >=20 > +#define PCH_MAX_PXRC_CONFIG 8 ///< Number of PXRC > registers in ITSS >=20 > +#define PCH_MAX_ITSS_IPC_REGS 4 ///< Number of IPC reg= isters > in ITSS >=20 > +#define PCH_MAX_ITSS_IRQ_NUM 120 ///< Maximum number of > IRQs >=20 > + >=20 > + >=20 > +/// >=20 > +/// The PCH_INTERRUPT_CONFIG block describes interrupt settings for > PCH. >=20 > +/// >=20 > +typedef struct { >=20 > + CONFIG_BLOCK_HEADER Header; = ///< Config > Block Header >=20 > + UINT8 NumOfDevIntConfig; = ///< Number of > entries in DevIntConfig table >=20 > + UINT8 Rsvd0[3]; = ///< Reserved bytes, align > to multiple 4. >=20 > + PCH_DEVICE_INTERRUPT_CONFIG > DevIntConfig[PCH_MAX_DEVICE_INTERRUPT_CONFIG]; ///< Array which > stores PCH devices interrupts settings >=20 > + UINT8 GpioIrqRoute; = ///< Interrupt routing > for GPIO. Default is 14. >=20 > + UINT8 SciIrqSelect; = ///< Interrupt select for > SCI. Default is 9. >=20 > + UINT8 TcoIrqSelect; = ///< Interrupt select for > TCO. Default is 9. >=20 > + UINT8 TcoIrqEnable; = ///< Enable IRQ > generation for TCO. 0: Disable; 1: Enable. >=20 > +} PCH_INTERRUPT_CONFIG; >=20 > + >=20 > +#pragma pack (pop) >=20 > + >=20 > +#endif // _INTERRUPT_CONFIG_H_ >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Itss/IoApicConfig= .h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Itss/IoApicConfig= .h > new file mode 100644 > index 0000000000..726a27f7a1 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Itss/IoApicConfig= .h > @@ -0,0 +1,60 @@ > +/** @file >=20 > + IoApic policy >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _IOAPIC_CONFIG_H_ >=20 > +#define _IOAPIC_CONFIG_H_ >=20 > + >=20 > +#define IOAPIC_CONFIG_REVISION 1 >=20 > +extern EFI_GUID gIoApicConfigGuid; >=20 > + >=20 > +#pragma pack (push,1) >=20 > + >=20 > +/** >=20 > + The PCH_IOAPIC_CONFIG block describes the expected configuration of > the PCH >=20 > + IO APIC, it's optional and PCH code would ignore it if the BdfValid bi= t is >=20 > + not TRUE. Bus:device:function fields will be programmed to the registe= r >=20 > + P2SB IBDF(P2SB PCI offset R6Ch-6Dh), it's using for the following purp= ose: >=20 > + As the Requester ID when initiating Interrupt Messages to the processo= r. >=20 > + As the Completer ID when responding to the reads targeting the IOxAPI'= s >=20 > + Memory-Mapped I/O registers. >=20 > + This field defaults to Bus 0: Device 31: Function 0 after reset. BIOS = can >=20 > + program this field to provide a unique Bus:Device:Function number for = the >=20 > + internal IOxAPIC. >=20 > + The address resource range of IOAPIC must be reserved in E820 and ACPI > as >=20 > + system resource. >=20 > +**/ >=20 > +typedef struct { >=20 > + CONFIG_BLOCK_HEADER Header; ///< Config Block Header >=20 > + UINT32 IoApicEntry24_119 : 1; ///< 0: Disable; 1: Enable > IOAPIC Entry 24-119 >=20 > + /** >=20 > + Enable 8254 Static Clock Gating during early POST time. 0: Disable, = 1: > Enable >=20 > + Setting 8254CGE is required to support SLP_S0. >=20 > + Enable this if 8254 timer is not used. >=20 > + However, set 8254CGE=3D1 in POST time might fail to boot legacy OS u= sing > 8254 timer. >=20 > + Make sure it is disabled to support legacy OS using 8254 timer. >=20 > + @note: >=20 > + For some OS environment that it needs to set 8254CGE in late state i= t > should >=20 > + set this policy to FALSE and use ItssSet8254ClockGateState (TRUE) i= n > SMM later. >=20 > + This is also required during S3 resume. >=20 > + To avoid SMI requirement in S3 reusme path, it can enable the > Enable8254ClockGatingOnS3 >=20 > + and RC will do 8254 CGE programming in PEI during S3 resume with > BOOT_SAI. >=20 > + **/ >=20 > + UINT32 Enable8254ClockGating : 1; >=20 > + /** >=20 > + Enable 8254 Static Clock Gating on S3 resume path. 0: Disable, 1: > Enable >=20 > + This is only applicable when Enable8254ClockGating is disabled. >=20 > + If Enable8254ClockGating is enabled, RC will do the 8254 CGE > programming on >=20 > + S3 resume path as well. >=20 > + **/ >=20 > + UINT32 Enable8254ClockGatingOnS3 : 1; >=20 > + UINT32 RsvdBits1 : 29; ///< Reserved bits >=20 > + UINT8 IoApicId; ///< This member determines IOAP= IC ID. > Default is 0x02. >=20 > + UINT8 Rsvd0[3]; ///< Reserved bytes >=20 > +} PCH_IOAPIC_CONFIG; >=20 > + >=20 > +#pragma pack (pop) >=20 > + >=20 > +#endif // _IOAPIC_CONFIG_H_ >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Me/MePeiConfig.h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Me/MePeiConfig.h > new file mode 100644 > index 0000000000..82786501f0 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Me/MePeiConfig.h > @@ -0,0 +1,117 @@ > +/** @file >=20 > + ME config block for PEI phase >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _ME_PEI_CONFIG_H_ >=20 > +#define _ME_PEI_CONFIG_H_ >=20 > + >=20 > +#define ME_PEI_PREMEM_CONFIG_REVISION 2 >=20 > +extern EFI_GUID gMePeiPreMemConfigGuid; >=20 > + >=20 > +#ifndef PLATFORM_POR >=20 > +#define PLATFORM_POR 0 >=20 > +#endif >=20 > +#ifndef FORCE_ENABLE >=20 > +#define FORCE_ENABLE 1 >=20 > +#endif >=20 > +#ifndef FORCE_DISABLE >=20 > +#define FORCE_DISABLE 2 >=20 > +#endif >=20 > + >=20 > +#pragma pack (push,1) >=20 > + >=20 > +/** >=20 > + ME Pei Pre-Memory Configuration Structure. >=20 > + >=20 > + Revision 1: >=20 > + - Initial version. >=20 > + Revision 2: >=20 > + - Add SkipCpuReplacementCheck Option. >=20 > + Revision 3: >=20 > + - Deprecate SendDidMsg. >=20 > +**/ >=20 > +typedef struct { >=20 > + CONFIG_BLOCK_HEADER Header; ///< Config Block Header >=20 > + UINT32 HeciTimeouts : 1; ///< 0: Disable; 1: E= nable - > HECI Send/Receive Timeouts. >=20 > + /** >=20 > + (Test) >=20 > + 0: Disabled >=20 > + 1: ME DID init stat 0 - Success >=20 > + 2: ME DID init stat 1 - No Memory in Channels >=20 > + 3: ME DID init stat 2 - Memory Init Error >=20 > + **/ >=20 > + UINT32 DidInitStat : 2; >=20 > + /** >=20 > + (Test) >=20 > + 0: Set to 0 to enable polling for CPU replacement >=20 > + 1: Set to 1 will disable polling for CPU replacement >=20 > + **/ >=20 > + UINT32 DisableCpuReplacedPolling : 1; >=20 > + UINT32 SendDidMsg : 1; ///< (Deprecated)= 0: Disable; > 1: Enable - Enable/Disable to send DID message. >=20 > + /** >=20 > + (Test) >=20 > + 0: ME BIOS will check each messages before sending >=20 > + 1: ME BIOS always sends messages without checking >=20 > + **/ >=20 > + UINT32 DisableMessageCheck : 1; >=20 > + /** >=20 > + (Test) >=20 > + The SkipMbpHob policy determines whether ME BIOS Payload data will > be requested during boot >=20 > + in a MBP message. If set to 1, BIOS will send the MBP message with > SkipMbp flag >=20 > + set causing CSME to respond with MKHI header only and no MBP data >=20 > + 0: ME BIOS will keep MBP and create HOB for MBP data >=20 > + 1: ME BIOS will skip MBP data >=20 > + **/ >=20 > + UINT32 SkipMbpHob : 1; >=20 > + UINT32 HeciCommunication2 : 1; ///< (Test) 0: > Disable; 1: Enable - Enable/Disable HECI2. >=20 > + UINT32 KtDeviceEnable : 1; ///< (Test) 0: Di= sable; 1: > Enable - Enable/Disable Kt Device. >=20 > + UINT32 SkipCpuReplacementCheck : 1; ///< (Test) 0: > Disable; 1: Enable - Enable/Disable to skip CPU replacement check. >=20 > + UINT32 RsvdBits : 22; ///< Reserved for future= use & Config > block alignment >=20 > + UINT32 Heci1BarAddress; ///< HECI1 BAR address. >=20 > + UINT32 Heci2BarAddress; ///< HECI2 BAR address. >=20 > + UINT32 Heci3BarAddress; ///< HECI3 BAR address. >=20 > +} ME_PEI_PREMEM_CONFIG; >=20 > +#pragma pack (pop) >=20 > + >=20 > + >=20 > +#define ME_PEI_CONFIG_REVISION 3 >=20 > +extern EFI_GUID gMePeiConfigGuid; >=20 > + >=20 > +#pragma pack (push,1) >=20 > + >=20 > +/** >=20 > + ME Pei Post-Memory Configuration Structure. >=20 > + >=20 > + Revision 1: >=20 > + - Initial version. >=20 > + Revision 2: >=20 > + - Deprecated Heci3Enabled. >=20 > + Revision 3 >=20 > + - Added EnforceEDebugMode. >=20 > +**/ >=20 > + >=20 > +typedef struct { >=20 > + CONFIG_BLOCK_HEADER Header; ///< Config Block Header >=20 > + >=20 > + UINT32 EndOfPostMessage : 2; ///< 0: Disabled; 1: Sen= d in PEI; > 2: Send in DXE - Send EOP at specific phase. >=20 > + UINT32 Heci3Enabled : 1; ///< @deprecated >=20 > + UINT32 DisableD0I3SettingForHeci : 1; ///< (Test) 0: > Disable; 1: Enable - Enable/Disable D0i3 for HECI. >=20 > + /** >=20 > + Enable/Disable Me Unconfig On Rtc Clear. If enabled, BIOS will send > MeUnconfigOnRtcClearDisable Msg with parameter 0. >=20 > + It will cause ME to unconfig if RTC is cleared. >=20 > + - 0: Disable >=20 > + - 1: Enable >=20 > + - 2: Cmos is clear, status unkonwn >=20 > + - 3: Reserved >=20 > + **/ >=20 > + UINT32 MeUnconfigOnRtcClear : 2; >=20 > + UINT32 MctpBroadcastCycle : 1; ///< (Test) 0= : > Disable; 1: Enable - Program registers for MCTP Cycle. >=20 > + UINT32 EnforceEDebugMode : 1; ///< 0: Disable;= 1: > Enable - Enforces ME to enter Enhanced Debug Mode >=20 > + UINT32 RsvdBits : 24; ///< Reserved for futur= e use & Config > block alignment >=20 > +} ME_PEI_CONFIG; >=20 > + >=20 > +#pragma pack (pop) >=20 > + >=20 > +#endif // _ME_PEI_CONFIG_H_ >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Memory/Ver2/Mem > oryConfig.h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Memory/Ver2/Mem > oryConfig.h > new file mode 100644 > index 0000000000..17c0a10eee > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Memory/Ver2/Mem > oryConfig.h > @@ -0,0 +1,478 @@ > +/** @file >=20 > + Policy definition of Memory Config Block >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _MEMORY_CONFIG_H_ >=20 > +#define _MEMORY_CONFIG_H_ >=20 > + >=20 > + >=20 > +#pragma pack(push, 1) >=20 > + >=20 > +// MEMORY_CONFIG_REVISION 3 adds DDR5 PDA Enumeration training > within MEMORY_CONFIGURATION >=20 > +// MEMORY_CONFIG_REVISION 4 adds LPDDR4 Command Mirroring within > MEMORY_CONFIGURATION >=20 > +// MEMORY_CONFIG_REVISION 5 adds CpuBclkSpread option within > MEMORY_CONFIGURATION >=20 > +// MEMORY_CONFIG_REVISION 6 adds McParity option within > MEMORY_CONFIGURATION >=20 > +// MEMORY_CONFIG_REVISION 7 adds VddqVoltageOverride option within > MEMORY_CONFIGURATION >=20 > +// MEMORY_CONFIG_REVISION 8 adds ExtendedBankHashing option > within MEMORY_CONFIGURATION >=20 > +// MEMORY_CONFIG_REVISION 9 adds IbeccErrorInj option within > MEMORY_CONFIGURATION >=20 > +#define MEMORY_CONFIG_REVISION 9 >=20 > +/// >=20 > +/// MEMORY_CONFIG interface definitions >=20 > +/// >=20 > +#define MRC_MAX_RCOMP_TARGETS 5 >=20 > +/// >=20 > +/// Memory SubSystem Definitions >=20 > +/// >=20 > +#define MEM_CFG_MAX_CONTROLLERS 2 >=20 > +#define MEM_CFG_MAX_CHANNELS 4 >=20 > +#define MEM_CFG_MAX_CHANNEL_SHARE_REGS 2 >=20 > +#define MEM_CFG_MAX_DIMMS 2 >=20 > +#define MEM_CFG_MAX_RANKS_PER_DIMM 2 >=20 > +#define MEM_CFG_NUM_BYTES_MAPPED 2 >=20 > +#define MEM_CFG_MAX_SPD_SIZE 1024 >=20 > +#define MEM_CFG_MAX_SOCKETS > (MEM_CFG_MAX_CONTROLLERS * MEM_CFG_MAX_CHANNELS * > MEM_CFG_MAX_DIMMS) >=20 > +#define MEM_CFG_MAX_ROWS > (MEM_CFG_MAX_RANKS_PER_DIMM * MEM_CFG_MAX_SOCKETS) >=20 > +#ifndef MEM_MAX_SAGV_POINTS >=20 > +#define MEM_MAX_SAGV_POINTS 4 >=20 > +#endif >=20 > +#define MEM_MAX_IBECC_REGIONS 8 >=20 > +/// >=20 > +/// SMRAM Memory Range >=20 > +/// >=20 > +#define PEI_MR_SMRAM_ABSEG_MASK 0x01 >=20 > +#define PEI_MR_SMRAM_HSEG_MASK 0x02 >=20 > + >=20 > +/// >=20 > +/// SA SPD profile selections. >=20 > +/// >=20 > +typedef enum { >=20 > + Default, ///< 0, Default SPD >=20 > + UserDefined, ///< 1, User Defined profile >=20 > + XMPProfile1, ///< 2, XMP Profile 1 >=20 > + XMPProfile2, ///< 3, XMP Profile 2 >=20 > + XMPProfileMax =3D 0xFF ///< Ensures SA_SPD is UINT8 >=20 > +} SA_SPD; >=20 > + >=20 > +/// >=20 > +/// Define the boot modes used by the SPD read function. >=20 > +/// >=20 > +typedef enum { >=20 > + SpdCold, ///< Cold boot >=20 > + SpdWarm, ///< Warm boot >=20 > + SpdS3, ///< S3 resume >=20 > + SpdFast, ///< Fast boot >=20 > + SpdBootModeMax ///< Delimiter >=20 > +} SPD_BOOT_MODE; >=20 > + >=20 > +/** >=20 > + SPD Data Buffer >=20 > +**/ >=20 > +typedef struct { >=20 > + UINT8 > SpdData[MEM_CFG_MAX_CONTROLLERS][MEM_CFG_MAX_CHANNELS][M > EM_CFG_MAX_DIMMS][MEM_CFG_MAX_SPD_SIZE]; ///< SpdData >=20 > +//Next Field Offset 2048 >=20 > +} SPD_DATA_BUFFER; >=20 > + >=20 > +/** >=20 > + DqDqs Mapping >=20 > +**/ >=20 > +typedef struct { >=20 > + UINT8 > DqsMapCpu2Dram[MEM_CFG_MAX_CONTROLLERS][MEM_CFG_MAX_CHA > NNELS][MEM_CFG_NUM_BYTES_MAPPED]; ///< DqsMapCpu2Dram >=20 > + UINT8 > DqMapCpu2Dram[MEM_CFG_MAX_CONTROLLERS][MEM_CFG_MAX_CHA > NNELS][MEM_CFG_NUM_BYTES_MAPPED][8]; ///< DqMapCpu2Dram >=20 > +//Next Field Offset 16 >=20 > +} SA_MEMORY_DQDQS_MAPPING; >=20 > + >=20 > +/** >=20 > + Rcomp Policies >=20 > +**/ >=20 > +typedef struct { >=20 > + UINT16 RcompResistor; ///< Offset 0: Reference R= COMP > resistors on motherboard ~ 100 ohms >=20 > + UINT16 RcompTarget[MRC_MAX_RCOMP_TARGETS]; ///< Offset 1: > RCOMP target values for DqOdt, DqDrv, CmdDrv, CtlDrv, ClkDrv >=20 > +//Next Field Offset 16 >=20 > +} SA_MEMORY_RCOMP; >=20 > + >=20 > +/** >=20 > + SPD Offset Table >=20 > +**/ >=20 > +typedef struct { >=20 > + UINT16 Start; ///< Offset 0 >=20 > + UINT16 End; ///< Offset 2 >=20 > + UINT8 BootMode; ///< Offset 4 >=20 > + UINT8 Reserved3[3]; ///< Offset 5 Reserved for future use >=20 > +} SPD_OFFSET_TABLE; >=20 > + >=20 > +/// >=20 > +/// SA memory address decode. >=20 > +/// >=20 > +typedef struct >=20 > +{ >=20 > + UINT8 Controller; ///< Offset 0 Zero based Controller number >=20 > + UINT8 Channel; ///< Offset 1 Zero based Channel number >=20 > + UINT8 Dimm; ///< Offset 2 Zero based DIMM number >=20 > + UINT8 Rank; ///< Offset 3 Zero based Rank number >=20 > + UINT8 BankGroup; ///< Offset 4 Zero based Bank Group number >=20 > + UINT8 Bank; ///< Offset 5 Zero based Bank number >=20 > + UINT16 Cas; ///< Offset 6 Zero based CAS number >=20 > + UINT32 Ras; ///< Offset 8 Zero based RAS number >=20 > +} SA_ADDRESS_DECODE; >=20 > + >=20 > +typedef UINT8 (EFIAPI * SA_IO_READ_8) (UINTN IoAddres= s); > ///< CPU I/O port 8-bit read. >=20 > +typedef UINT16 (EFIAPI * SA_IO_READ_16) (UINTN IoAddres= s); > ///< CPU I/O port 16-bit read. >=20 > +typedef UINT32 (EFIAPI * SA_IO_READ_32) (UINTN IoAddres= s); > ///< CPU I/O port 32-bit read. >=20 > +typedef UINT8 (EFIAPI * SA_IO_WRITE_8) (UINTN IoAddres= s, > UINT8 Value); > ///< CPU I/O port 8-bit write. >=20 > +typedef UINT16 (EFIAPI * SA_IO_WRITE_16) (UINTN IoAddres= s, > UINT16 Value); > ///< CPU I/O port 16-bit write. >=20 > +typedef UINT32 (EFIAPI * SA_IO_WRITE_32) (UINTN IoAddres= s, > UINT32 Value); > ///< CPU I/O port 32-bit write. >=20 > +typedef UINT8 (EFIAPI * SA_MMIO_READ_8) (UINTN Address)= ; > ///< Memory Mapped I/O port 8-bit read. >=20 > +typedef UINT16 (EFIAPI * SA_MMIO_READ_16) (UINTN Address)= ; > ///< Memory Mapped I/O port 16-bit read. >=20 > +typedef UINT32 (EFIAPI * SA_MMIO_READ_32) (UINTN Address)= ; > ///< Memory Mapped I/O port 32-bit read. >=20 > +typedef UINT64 (EFIAPI * SA_MMIO_READ_64) (UINTN Address)= ; > ///< Memory Mapped I/O port 64-bit read. >=20 > +typedef UINT8 (EFIAPI * SA_MMIO_WRITE_8) (UINTN Address, > UINT8 Value); > ///< Memory Mapped I/O port 8-bit write. >=20 > +typedef UINT16 (EFIAPI * SA_MMIO_WRITE_16) (UINTN Address, > UINT16 Value); > ///< Memory Mapped I/O port 16-bit write. >=20 > +typedef UINT32 (EFIAPI * SA_MMIO_WRITE_32) (UINTN Address, > UINT32 Value); > ///< Memory Mapped I/O port 32-bit write. >=20 > +typedef UINT64 (EFIAPI * SA_MMIO_WRITE_64) (UINTN Address, > UINT64 Value); > ///< Memory Mapped I/O port 64-bit write. >=20 > +typedef UINT8 (EFIAPI * SA_SMBUS_READ_8) (UINTN Address, > RETURN_STATUS *Status); > ///< Smbus 8-bit read. >=20 > +typedef UINT16 (EFIAPI * SA_SMBUS_READ_16) (UINTN Address, > RETURN_STATUS *Status); > ///< Smbus 16-bit read. >=20 > +typedef UINT8 (EFIAPI * SA_SMBUS_WRITE_8) (UINTN Address, > UINT8 Value, RETURN_STATUS *Status); > ///< Smbus 8-bit write. >=20 > +typedef UINT16 (EFIAPI * SA_SMBUS_WRITE_16) (UINTN Address, > UINT16 Value, RETURN_STATUS *Status); > ///< Smbus 16-bit write. >=20 > +typedef UINT32 (EFIAPI * SA_GET_PCI_DEVICE_ADDRESS) (UINT8 Bus, > UINT8 Device, UINT8 Function, UINT8 Offset); > ///< Get PCI device address. >=20 > +typedef UINT32 (EFIAPI * SA_GET_PCIE_DEVICE_ADDRESS) (UINT8 Bus, > UINT8 Device, UINT8 Function, UINT8 Offset); > ///< Get PCI express device address. >=20 > +typedef VOID (EFIAPI * SA_GET_RTC_TIME) (UINT8 *Second, > UINT8 *Minute, UINT8 *Hour, UINT8 *Day, UINT8 *Month, UINT16 *Year); > ///< Get the current time value. >=20 > +typedef UINT64 (EFIAPI * SA_GET_CPU_TIME) (VOID); > ///< The current CPU time in milliseconds. >=20 > +typedef VOID * (EFIAPI * SA_MEMORY_COPY) (VOID *Destinat= ion, > CONST VOID *Source, UINTN NumBytes); > ///< Perform byte copy operation. >=20 > +typedef VOID * (EFIAPI * SA_MEMORY_SET_BYTE) (VOID *Buffer, > UINTN NumBytes, UINT8 Value); > ///< Perform byte initialization operation. >=20 > +typedef VOID * (EFIAPI * SA_MEMORY_SET_WORD) (VOID *Buffer, > UINTN NumWords, UINT16 Value); > ///< Perform word initialization operation. >=20 > +typedef VOID * (EFIAPI * SA_MEMORY_SET_DWORD) (VOID *Buffer, > UINTN NumDwords, UINT32 Value); > ///< Perform dword initialization operation. >=20 > +typedef UINT64 (EFIAPI * SA_LEFT_SHIFT_64) (UINT64 Data, U= INTN > NumBits); > ///< Left shift the 64-bit data value by specified number of bits. >=20 > +typedef UINT64 (EFIAPI * SA_RIGHT_SHIFT_64) (UINT64 Data, U= INTN > NumBits); > ///< Right shift the 64-bit data value by specified number of bits. >=20 > +typedef UINT64 (EFIAPI * SA_MULT_U64_U32) (UINT64 > Multiplicand, UINT32 Multiplier); > ///< Multiply a 64-bit data value by a 32-bit data value. >=20 > +typedef UINT64 (EFIAPI * SA_DIV_U64_U64) (UINT64 Dividen= d, > UINT64 Divisor, UINT64 *Remainder); > ///< Divide a 64-bit data value by a 64-bit data value. >=20 > +typedef BOOLEAN (EFIAPI * SA_GET_SPD_DATA) > (SPD_BOOT_MODE BootMode, UINT8 SpdAddress, UINT8 *Buffer, UINT8 > *Ddr3Table, UINT32 Ddr3TableSize, UINT8 *Ddr4Table, UINT32 > Ddr4TableSize, UINT8 *LpddrTable, UINT32 LpddrTableSize); ///= < Read > the SPD data over the SMBus, at the given SmBus SPD address and copy the > data to the data structure. >=20 > +typedef UINT8 (EFIAPI * SA_GET_MC_ADDRESS_DECODE) (UINT64 > Address, SA_ADDRESS_DECODE *DramAddress); >=20 > +typedef UINT8 (EFIAPI * SA_GET_MC_ADDRESS_ENCODE) > (SA_ADDRESS_DECODE *DramAddress, UINT64 Address); >=20 > +typedef BOOLEAN (EFIAPI * SA_GET_RANDOM_NUMBER) (UINT32 > *Rand); > ///< Get the next random 32-bit number. >=20 > +typedef EFI_STATUS (EFIAPI * SA_CPU_MAILBOX_READ) (UINT32 Type, > UINT32 Command, UINT32 *Value, UINT32 *Status); > ///< Perform a CPU mailbox read. >=20 > +typedef EFI_STATUS (EFIAPI * SA_CPU_MAILBOX_WRITE) (UINT32 Type, > UINT32 Command, UINT32 Value, UINT32 *Status); > ///< Perform a CPU mailbox write. >=20 > +typedef UINT32 (EFIAPI * SA_GET_MEMORY_VDD) (VOID > *GlobalData, UINT32 DefaultVdd); > ///< Get the current memory voltage (VDD). >=20 > +typedef UINT32 (EFIAPI * SA_SET_MEMORY_VDD) (VOID > *GlobalData, UINT32 DefaultVdd, UINT32 Value); > ///< Set the memory voltage (VDD) to the given value. >=20 > +typedef UINT32 (EFIAPI * SA_CHECKPOINT) (VOID *GlobalDa= ta, > UINT32 CheckPoint, VOID *Scratch); > ///< Check point that is called at various points in the MRC. >=20 > +typedef VOID (EFIAPI * SA_DEBUG_HOOK) (VOID *GlobalDa= ta, > UINT16 DisplayDebugNumber); > ///< Typically used to display to the I/O port 80h. >=20 > +typedef UINT8 (EFIAPI * SA_CHANNEL_EXIST) (VOID *Outputs, > UINT8 Channel); > ///< Returns whether Channel is or is not present. >=20 > +typedef INT32 (EFIAPI * SA_PRINTF) (VOID *Debug, U= INT32 > Level, char *Format, ...); > ///< Print to output stream/device. >=20 > +typedef VOID (EFIAPI * SA_DEBUG_PRINT) (VOID *String); > ///< Output a string to the debug stream/device. >=20 > +typedef UINT32 (EFIAPI * SA_CHANGE_MARGIN) (VOID > *GlobalData, UINT8 Param, INT32 Value0, INT32 Value1, UINT8 EnMultiCast, > UINT8 Channel, UINT8 RankIn, UINT8 Byte, UINT8 BitIn, UINT8 > UpdateMrcData, UINT8 SkipWait, UINT32 RegFileParam); ///< Change the > margin. >=20 > +typedef UINT8 (EFIAPI * SA_SIGN_EXTEND) (UINT8 Value, U= INT8 > OldMsb, UINT8 NewMsb); > ///< Sign extends OldMSB to NewMSB Bits (Eg: Bit 6 to Bit 7). >=20 > +typedef VOID (EFIAPI * SA_SHIFT_PI_COMMAND_TRAIN) (VOID > *GlobalData, UINT8 Channel, UINT8 Iteration, UINT8 RankMask, UINT8 > GroupMask, INT32 NewValue, UINT8 UpdateHost); > ///< Move CMD/CTL/CLK/CKE PIs during training. >=20 > +typedef VOID (EFIAPI * SA_UPDATE_VREF) (VOID *GlobalDa= ta, > UINT8 Channel, UINT8 RankMask, UINT16 DeviceMask, UINT8 VrefType, > INT32 Offset, BOOLEAN UpdateMrcData, BOOLEAN PDAmode, BOOLEAN > SkipWait); ///< Update the Vref value = and wait until it is > stable. >=20 > +typedef UINT8 (EFIAPI * SA_GET_RTC_CMOS) (UINT8 Location= ); > ///< Get the current value of the specified RTC CMOS location. >=20 > +typedef UINT64 (EFIAPI * SA_MSR_READ_64) (UINT32 Locatio= n); > ///< Get the current value of the specified MSR location. >=20 > +typedef UINT64 (EFIAPI * SA_MSR_WRITE_64) (UINT32 Locatio= n, > UINT64 Data); > ///< Set the current value of the specified MSR location. >=20 > +typedef VOID (EFIAPI * SA_MRC_RETURN_FROM_SMC) (VOID > *GlobalData, UINT32 MrcStatus); > ///< Hook function after returning from MrcStartMemoryConfiguration() >=20 > +typedef VOID (EFIAPI * SA_MRC_DRAM_RESET) (UINT32 > PciEBaseAddress, UINT32 ResetValue); > ///< Assert or deassert DRAM_RESET# pin; this is used in JEDEC Reset. >=20 > +typedef VOID (EFIAPI * SA_DELAY_NS) (VOID *GlobalDa= ta, > UINT32 DelayNs); > ///< Delay (stall) for the given amount of nanoseconds. >=20 > +typedef VOID (EFIAPI * SA_SET_LOCK_PRMRR) (UINT64 > PrmrrBaseAddress, UINT32 PrmrrSize); >=20 > + >=20 > + >=20 > +/// >=20 > +/// Function calls into the SA. >=20 > +/// >=20 > +typedef struct { >=20 > + SA_IO_READ_8 IoRead8; ///< Offset 0: - C= PU I/O port 8-bit > read. >=20 > + SA_IO_READ_16 IoRead16; ///< Offset 4: - C= PU I/O port 16- > bit read. >=20 > + SA_IO_READ_32 IoRead32; ///< Offset 8: - C= PU I/O port 32- > bit read. >=20 > + SA_IO_WRITE_8 IoWrite8; ///< Offset 12: - C= PU I/O port 8-bit > write. >=20 > + SA_IO_WRITE_16 IoWrite16; ///< Offset 16: - C= PU I/O port 16- > bit write. >=20 > + SA_IO_WRITE_32 IoWrite32; ///< Offset 20: - C= PU I/O port 32- > bit write. >=20 > + SA_MMIO_READ_8 MmioRead8; ///< Offset 24: - M= emory > Mapped I/O port 8-bit read. >=20 > + SA_MMIO_READ_16 MmioRead16; ///< Offset 28: - M= emory > Mapped I/O port 16-bit read. >=20 > + SA_MMIO_READ_32 MmioRead32; ///< Offset 32: - M= emory > Mapped I/O port 32-bit read. >=20 > + SA_MMIO_READ_64 MmioRead64; ///< Offset 36: - M= emory > Mapped I/O port 64-bit read. >=20 > + SA_MMIO_WRITE_8 MmioWrite8; ///< Offset 40: - M= emory > Mapped I/O port 8-bit write. >=20 > + SA_MMIO_WRITE_16 MmioWrite16; ///< Offset 44: - M= emory > Mapped I/O port 16-bit write. >=20 > + SA_MMIO_WRITE_32 MmioWrite32; ///< Offset 48: - M= emory > Mapped I/O port 32-bit write. >=20 > + SA_MMIO_WRITE_64 MmioWrite64; ///< Offset 52: - M= emory > Mapped I/O port 64-bit write. >=20 > + SA_SMBUS_READ_8 SmbusRead8; ///< Offset 56: - S= mbus 8-bit > read. >=20 > + SA_SMBUS_READ_16 SmbusRead16; ///< Offset 60: - S= mbus 16- > bit read. >=20 > + SA_SMBUS_WRITE_8 SmbusWrite8; ///< Offset 64: - S= mbus 8- > bit write. >=20 > + SA_SMBUS_WRITE_16 SmbusWrite16; ///< Offset 68: - S= mbus > 16-bit write. >=20 > + SA_GET_PCI_DEVICE_ADDRESS GetPciDeviceAddress; ///< Offset 72: - > Get PCI device address. >=20 > + SA_GET_PCIE_DEVICE_ADDRESS GetPcieDeviceAddress; ///< Offset 76: - > Get PCI express device address. >=20 > + SA_GET_RTC_TIME GetRtcTime; ///< Offset 80: - G= et the > current time value. >=20 > + SA_GET_CPU_TIME GetCpuTime; ///< Offset 84: - T= he current > CPU time in milliseconds. >=20 > + SA_MEMORY_COPY CopyMem; ///< Offset 88: - P= erform > byte copy operation. >=20 > + SA_MEMORY_SET_BYTE SetMem; ///< Offset 92: - P= erform > byte initialization operation. >=20 > + SA_MEMORY_SET_WORD SetMemWord; ///< Offset 96: - > Perform word initialization operation. >=20 > + SA_MEMORY_SET_DWORD SetMemDword; ///< Offset 100: - > Perform dword initialization operation. >=20 > + SA_LEFT_SHIFT_64 LeftShift64; ///< Offset 104: - L= eft shift the > 64-bit data value by specified number of bits. >=20 > + SA_RIGHT_SHIFT_64 RightShift64; ///< Offset 108: - R= ight shift the > 64-bit data value by specified number of bits. >=20 > + SA_MULT_U64_U32 MultU64x32; ///< Offset 112: - M= ultiply a > 64-bit data value by a 32-bit data value. >=20 > + SA_DIV_U64_U64 DivU64x64; ///< Offset 116: - D= ivide a 64-bit > data value by a 64-bit data value. >=20 > + SA_GET_SPD_DATA GetSpdData; ///< Offset 120: - R= ead the > SPD data over the SMBus, at the given SmBus SPD address and copy the data > to the data structure. >=20 > + SA_GET_RANDOM_NUMBER GetRandomNumber; ///< Offset 124: - > Get the next random 32-bit number. >=20 > + SA_CPU_MAILBOX_READ CpuMailboxRead; ///< Offset 128: - > Perform a CPU mailbox read. >=20 > + SA_CPU_MAILBOX_WRITE CpuMailboxWrite; ///< Offset 132: - > Perform a CPU mailbox write. >=20 > + SA_GET_MEMORY_VDD GetMemoryVdd; ///< Offset 136: - G= et > the current memory voltage (VDD). >=20 > + SA_SET_MEMORY_VDD SetMemoryVdd; ///< Offset 140: - S= et > the memory voltage (VDD) to the given value. >=20 > + SA_CHECKPOINT CheckPoint; ///< Offset 144: - C= heck point > that is called at various points in the MRC. >=20 > + SA_DEBUG_HOOK DebugHook; ///< Offset 148: - T= ypically > used to display to the I/O port 80h. >=20 > + SA_DEBUG_PRINT DebugPrint; ///< Offset 152: - O= utput a > string to the debug stream/device. >=20 > + SA_GET_RTC_CMOS GetRtcCmos; ///< Offset 156: - G= et the > current value of the specified RTC CMOS location. >=20 > + SA_MSR_READ_64 ReadMsr64; ///< Offset 160: - G= et the > current value of the specified MSR location. >=20 > + SA_MSR_WRITE_64 WriteMsr64; ///< Offset 164 - S= et the > current value of the specified MSR location. >=20 > + SA_MRC_RETURN_FROM_SMC MrcReturnFromSmc; ///< Offset 168 - > Hook function after returning from MrcStartMemoryConfiguration() >=20 > + SA_MRC_DRAM_RESET MrcDramReset; ///< Offset 172 - A= ssert > or deassert DRAM_RESET# pin; this is used in JEDEC Reset. >=20 > + SA_DELAY_NS MrcDelayNs; ///< Offset 176 - D= elay (stall) for > the given amount of nanoseconds. >=20 > +} SA_FUNCTION_CALLS; >=20 > + >=20 > +/// >=20 > +/// Function calls into the MRC. >=20 > +/// >=20 > +typedef struct { >=20 > + SA_CHANNEL_EXIST MrcChannelExist; ///< Offset 0: - Re= turns > whether Channel is or is not present. >=20 > + SA_PRINTF MrcPrintf; ///< Offset 4: - Pr= int to output > stream/device. >=20 > + SA_CHANGE_MARGIN MrcChangeMargin; ///< Offset 8: - Ch= ange > the margin. >=20 > + SA_SIGN_EXTEND MrcSignExtend; ///< Offset 12: - Si= gn extends > OldMSB to NewMSB Bits (Eg: Bit 6 to Bit 7). >=20 > + SA_SHIFT_PI_COMMAND_TRAIN ShiftPiCommandTrain; ///< Offset 16: - > Move CMD/CTL/CLK/CKE PIs during training. >=20 > + SA_UPDATE_VREF MrcUpdateVref; ///< Offset 20: - Up= date the > Vref value and wait until it is stable. >=20 > +} SA_MEMORY_FUNCTIONS; >=20 > + >=20 > +/** >=20 > + Memory Configuration >=20 > + The contents of this structure are CRC'd by the MRC for option change > detection. >=20 > + This structure is copied en mass to the MrcInput structure. If you add = fields > here, you must update the MrcInput structure. >=20 > + Revision 1: - Initial version. >=20 > + Revision 2: - Adding ChHashOverride option. >=20 > + Revision 3: - Adding PDA enumeration option. >=20 > + Revision 4: - Adding LPDDR4 Command Mirroring. >=20 > + Revision 5: - Adding CpuBclkSpread option. >=20 > + Revision 6: - Adding McParity option. >=20 > + Revision 7: - Adding VddqVoltageOverride option. >=20 > + Revision 8: - Adding ExtendedBankHashing option. >=20 > + Revision 9: - Adding IbeccErrorInj option >=20 > + **/ >=20 > +typedef struct { >=20 > + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header >=20 > + UINT16 Size; ///< Offset 28 The size of this struct= ure, in bytes. > Must be the first entry in this structure. >=20 > + UINT8 HobBufferSize; ///< Offset 30 Size of HOB buffer for = MRC >=20 > + >=20 > + UINT8 SpdProfileSelected; ///< Offset 31 SPD XMP profile selecti= on - for > XMP supported DIMM: 0=3DDefault DIMM profile, 1=3DCustomized > profile, 2=3DXMP profile 1, 3=3DXMP profile 2. >=20 > + >=20 > + // The following parameters are used only when SpdProfileSelected is > UserDefined (CUSTOM PROFILE) >=20 > + UINT16 tCL; ///< Offset 32 User defined Memory Tim= ing tCL > value, valid when SpdProfileSelected is CUSTOM_PROFILE: > 0=3DAUTO, 31=3DMaximum. >=20 > + UINT16 tRCDtRP; ///< Offset 34 User defined Memory Tim= ing tRCD > value (same as tRP), valid when SpdProfileSelected is CUSTOM_PROFILE: > 0=3DAUTO, 63=3DMaximum >=20 > + UINT16 tRAS; ///< Offset 36 User defined Memory Tim= ing tRAS > value, valid when SpdProfileSelected is CUSTOM_PROFILE: > 0=3DAUTO, 64=3DMaximum. >=20 > + UINT16 tWR; ///< Offset 38 User defined Memory Tim= ing tWR > value, valid when SpdProfileSelected is CUSTOM_PROFILE: > 0=3DAUTO, legal values: 5, 6, 7, 8, 10, 12, 14, 16, 18, 20, 24. >=20 > + UINT16 tRFC; ///< Offset 40 User defined Memory Tim= ing tRFC > value, valid when SpdProfileSelected is CUSTOM_PROFILE: > 0=3DAUTO, 1023=3DMaximum. >=20 > + UINT16 tRRD; ///< Offset 42 User defined Memory Tim= ing tRRD > value, valid when SpdProfileSelected is CUSTOM_PROFILE: > 0=3DAUTO, 15=3DMaximum. >=20 > + UINT16 tWTR; ///< Offset 44 User defined Memory Tim= ing tWTR > value, valid when SpdProfileSelected is CUSTOM_PROFILE: > 0=3DAUTO, 28=3DMaximum. >=20 > + UINT16 tRTP; ///< Offset 46 User defined Memory Tim= ing tRTP > value, valid when SpdProfileSelected is CUSTOM_PROFILE: > 0=3DAUTO, 15=3DMaximum. DDR4 legal values: 5, 6, 7, 8, 9, 10, 12 >=20 > + UINT16 tFAW; ///< Offset 48 User defined Memory Tim= ing tFAW > value, valid when SpdProfileSelected is CUSTOM_PROFILE: > 0=3DAUTO, 63=3DMaximum. >=20 > + UINT16 tCWL; ///< Offset 50 User defined Memory Tim= ing tCWL > value, valid when SpdProfileSelected is CUSTOM_PROFILE: > 0=3DAUTO, 20=3DMaximum. >=20 > + UINT16 tREFI; ///< Offset 52 User defined Memory Tim= ing tREFI > value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=3DAUTO, > 65535=3DMaximum. >=20 > + UINT16 PciIndex; ///< Offset 54 Pci index register addr= ess: > 0xCF8=3DDefault >=20 > + UINT16 PciData; ///< Offset 56 Pci data register addre= ss: > 0xCFC=3DDefault >=20 > + UINT16 VddVoltage; ///< Offset 58 DRAM voltage (Vdd) in m= illivolts: > 0=3DPlatform Default (no override), 1200=3D1.2V, 1350=3D1.35V etc. >=20 > + UINT16 Idd3n; ///< Offset 60 EPG Active standby curr= ent (Idd3N) > in milliamps from DIMM datasheet. >=20 > + UINT16 Idd3p; ///< Offset 62 EPG Active power-down c= urrent > (Idd3P) in milliamps from DIMM datasheet. >=20 > + >=20 > + UINT32 EccSupport:1; ///< Offset 64 Bit 0 - DIMM Ecc Su= pport > option - for Desktop only: 0=3DDisable, 1=3DEnable >=20 > + UINT32 MrcSafeConfig:1; ///< Bit 1 - MRC Safe Mo= de: > 0=3DDisable, 1=3DEnable >=20 > + UINT32 RemapEnable:1; ///< Bit 2 - This option= is used to > control whether to enable/disable memory remap above 4GB: 0=3DDisable, > 1=3DEnable. >=20 > + UINT32 ScramblerSupport:1; ///< Bit 3 - Memory scra= mbler > support: 0=3DDisable, 1=3DEnable >=20 > + UINT32 Vc1ReadMeter:1; ///< Bit 4 - VC1 Read Me= tering > Enable: 0=3DDisable, 1=3DEnable >=20 > + UINT32 ForceSingleSubchannel:1; ///< Bit 5 - TRUE means = use > SubChannel0 only (for LPDDR4): 0=3DDisable, 1=3DEnable >=20 > + UINT32 SimicsFlag:1; ///< Bit 6 - Option to E= nable SIMICS: > 0=3DDisable, 1=3DEnable >=20 > + UINT32 Ddr4DdpSharedClock:1; ///< Bit 7 - Select if C= LK0 is shared > between Rank0 and Rank1 in DDR4 DDP package. 0=3DNot shared, > 1=3DShared >=20 > + UINT32 SharedZqPin:1; ///< Bit 8 - Select if t= he ZQ resistor is > shared between Ranks in DDR4/LPDDR4 DRAM Packages 0=3DNot > Shared, 1=3DShared >=20 > + UINT32 LpDqsOscEn:1; ///< Bit 9 - LPDDR Write= DQ/DQS > Retraining: 0=3DDisable, 1=3DEnable >=20 > + UINT32 RmtPerTask:1; ///< Bit 10 - Rank Margin= Tool Per Task. > 0 =3D Disabled, 1 =3D Enabled >=20 > + UINT32 TrainTrace:1; ///< Bit 11 - Trained sta= te tracing debug. > 0 =3D Disabled, 1 =3D Enabled >=20 > + UINT32 SafeMode:1; ///< Bit 12 - Define if s= afe mode is > enabled for MC/IO >=20 > + UINT32 MsHashEnable:1; ///< Bit 13 - Controller = Hash Enable: > 0=3DDisable, 1=3DEnable >=20 > + UINT32 DisPgCloseIdleTimeout:1; ///< Bit 14 - Disable Pag= e Close > Idle Timeout: 0=3DEnable, 1=3DDisable >=20 > + UINT32 Ibecc:1; ///< Bit 15 - Inband ECC = - for LPDDR4, > LPDDR5 and DDR4 only: 0=3DDisable, 1=3DEnable >=20 > + UINT32 IbeccParity:1; ///< Bit 16 - Inband ECC = Parity Control - > for LPDDR4, LPDDR5 and DDR4 only: 0=3DDisable, 1=3DEnable >=20 > + UINT32 IbeccOperationMode:2; ///< Bits 17:18 - Inband = ECC > Operation Mode: 0=3DFunctional Mode protects requests based on the > address range, 1=3DMakes all requests non protected and ignore range > checks, 2=3DMakes all requests protected and ignore range checks >=20 > + UINT32 ChHashOverride:1; ///< Bit 19 - Select if C= hannel Hash > setting values will be taken from input parameters or automatically taken > from POR values depending on DRAM type detected. >=20 > + UINT32 McParity:1; ///< Bit 20 - MC Parity C= ontrol - Enable > Parity for CMI/MC: 0=3DDisable, 1=3DEnable >=20 > + UINT32 IbeccErrorInj:1; ///< Bit 21 - In-Band ECC= Error Injection: > 1=3DEnable, 0=3DDisable >=20 > + UINT32 RsvdO64B22t31:10; ///< Bits 22:31 reserved >=20 > + /** >=20 > + Disables a DIMM slot in the channel even if a DIMM is present\n >=20 > + Array index represents the channel number (0 =3D channel 0, 1 =3D cha= nnel > 1)\n >=20 > + 0x0 =3D DIMM 0 and DIMM 1 enabled\n >=20 > + 0x1 =3D DIMM 0 disabled, DIMM 1 enabled\n >=20 > + 0x2 =3D DIMM 0 enabled, DIMM 1 disabled\n >=20 > + 0x3 =3D DIMM 0 and DIMM 1 disabled (will disable the whole channel)= \n >=20 > + **/ >=20 > + UINT8 > DisableDimmChannel[MEM_CFG_MAX_CONTROLLERS][MEM_CFG_MAX_C > HANNELS]; ///< Offset 68-75 >=20 > + UINT8 Ratio; ///< Offset 76 DDR Frequency ratio, to= multiply by > 133 or 100 MHz depending on RefClk. 0 =3D Auto >=20 > + UINT8 ProbelessTrace; ///< Offset 77 Probeless Trace: > 0=3DDisabled, 1=3DEnabled >=20 > + /** >=20 > + - Channel Hash Enable.\n >=20 > + NOTE: BIT7 will interleave the channels at a 2 cache-line granularit= y, BIT8 > at 4 and BIT9 at 8\n >=20 > + 0=3DBIT6, 1=3DBIT7, 2=3DBIT8, 3=3DBIT9 >=20 > + **/ >=20 > + UINT8 ChHashInterleaveBit; ///< Offset 78 Option to select interl= eave > Address bit. Valid values are 0 - 3 for BITS 6 - 9 (Valid values for BDW = are 0-7 > for BITS 6 - 13) >=20 > + UINT8 SmramMask; ///< Offset 79 Reserved memory ranges = for > SMRAM >=20 > + UINT32 BClkFrequency; ///< Offset 80 Base reference clock va= lue, in > Hertz: 100000000 =3D 100Hz, 125000000=3D125Hz, 167000000=3D167Hz, > 250000000=3D250Hz >=20 > + >=20 > + /// Training Algorithms 1 Offset 84 >=20 > + UINT32 ECT:1; ///< Bit 0 - Enable/Disable Early Comm= and Training. > Note it is not recommended to change this setting from the default value: > 0=3DDisable, 1=3DEnable. >=20 > + UINT32 SOT:1; ///< Bit 1 - Enable/Disable Sense Amp = Offset > Training. Note it is not recommended to change this setting from the defa= ult > value: 0=3DDisable, 1=3DEnable. >=20 > + UINT32 ERDMPRTC2D:1; ///< Bit 2 - Enable/Disable Early Read= MPR > Timing Centering 2D. Note it is not recommended to change this setting fr= om > the default value: 0=3DDisable, 1=3DEnable. >=20 > + UINT32 RDMPRT:1; ///< Bit 3 - Enable/Disable Read MPR T= raining. > Note it is not recommended to change this setting from the default value: > 0=3DDisable, 1=3DEnable. >=20 > + UINT32 RCVET:1; ///< Bit 4 - Enable/Disable Receive En= able > Training. Note it is not recommended to change this setting from the defa= ult > value: 0=3DDisable, 1=3DEnable. >=20 > + UINT32 JWRL:1; ///< Bit 5 - Enable/Disable JEDEC Writ= e Leveling > Training. Note it is not recommended to change this setting from the defa= ult > value: 0=3DDisable, 1=3DEnable. >=20 > + UINT32 EWRTC2D:1; ///< Bit 6 - Enable/Disable Early Writ= e Time > Centering 2D Training. Note it is not recommended to change this setting > from the default value: 0=3DDisable, 1=3DEnable. >=20 > + UINT32 ERDTC2D:1; ///< Bit 7 - Enable/Disable Early Read= Time > Centering 2D Training. Note it is not recommended to change this setting > from the default value: 0=3DDisable, 1=3DEnable. >=20 > + UINT32 WRTC1D:1; ///< Bit 8 - Enable/Disable 1D Write T= iming > Centering Training. Note it is not recommended to change this setting fro= m > the default value: 0=3DDisable, 1=3DEnable. >=20 > + UINT32 WRVC1D:1; ///< Bit 9 - Enable/Disable 1D Write V= oltage > Centering Training. Note it is not recommended to change this setting fro= m > the default value: 0=3DDisable, 1=3DEnable. >=20 > + UINT32 RDTC1D:1; ///< Bit 10 - Enable/Disable 1D Read T= iming > Centering Training. Note it is not recommended to change this setting fro= m > the default value: 0=3DDisable, 1=3DEnable. >=20 > + UINT32 DIMMODTT:1; ///< Bit 11 - Enable/Disable DIMM ODT > Training. Note it is not recommended to change this setting from the defa= ult > value: 0=3DDisable, 1=3DEnable. >=20 > + UINT32 DIMMRONT:1; ///< Bit 12 - Enable/Disable DIMM RON > training. Note it is not recommended to change this setting from the defa= ult > value: 0=3DDisable, 1=3DEnable. >=20 > + UINT32 WRDSEQT:1; ///< Bit 13 - Enable/Disable Write Dri= ve > Strength / Equalization Training 2D. Note it is not recommended to change > this setting from the default value: 0=3DDisable, 1=3DEnable. >=20 > + UINT32 WRSRT:1; ///< Bit 14 - Enable/Disable Write Sle= w Rate > traning. Note it is not recommended to change this setting from the defau= lt > value: 0=3DDisable, 1=3DEnable. >=20 > + UINT32 RDODTT:1; ///< Bit 15 - Enable/Disable Read ODT = Training. > Note it is not recommended to change this setting from the default value: > 0=3DDisable, 1=3DEnable. >=20 > + UINT32 RDEQT:1; ///< Bit 16 - Enable/Disable Read Equa= lization > Training. Note it is not recommended to change this setting from the defa= ult > value: 0=3DDisable, 1=3DEnable. >=20 > + UINT32 RDAPT:1; ///< Bit 17 - Enable/Disable Read Ampl= ifier Power > Training. Note it is not recommended to change this setting from the defa= ult > value: 0=3DDisable, 1=3DEnable. >=20 > + UINT32 WRTC2D:1; ///< Bit 18 - Enable/Disable 2D Write = Timing > Centering Training. Note it is not recommended to change this setting fro= m > the default value: 0=3DDisable, 1=3DEnable. >=20 > + UINT32 RDTC2D:1; ///< Bit 19 - Enable/Disable 2D Read T= iming > Centering Training. Note it is not recommended to change this setting fro= m > the default value: 0=3DDisable, 1=3DEnable. >=20 > + UINT32 WRVC2D:1; ///< Bit 20 - Enable/Disable 2D Write = Voltage > Centering Training. Note it is not recommended to change this setting fro= m > the default value: 0=3DDisable, 1=3DEnable. >=20 > + UINT32 RDVC2D:1; ///< Bit 21 - Enable/Disable 2D Read V= oltage > Centering Training. Note it is not recommended to change this setting fro= m > the default value: 0=3DDisable, 1=3DEnable. >=20 > + UINT32 CMDVC:1; ///< Bit 22 - Enable/Disable Command V= ref > Centering Training. Note it is not recommended to change this setting fro= m > the default value 0=3DDisable, 1=3DEnable. >=20 > + UINT32 LCT:1; ///< Bit 23 - Enable/Disable Late Comm= and Training. > Note it is not recommended to change this setting from the default value: > 0=3DDisable, 1=3DEnable. >=20 > + UINT32 RTL:1; ///< Bit 24 - Enable/Disable Round Tri= p Latency > function. Note it is not recommended to change this setting from the defa= ult > value: 0=3DDisable, 1=3DEnable. >=20 > + UINT32 TAT:1; ///< Bit 25 - Enable/Disable Turn Arou= nd Time > function. Note it is not recommended to change this setting from the defa= ult > value: 0=3DDisable, 1=3DEnable. >=20 > + UINT32 RMT:1; ///< Bit 26 - Enable/Disable Rank Marg= in Tool > function: 0=3DDisable, 1=3DEnable. >=20 > + UINT32 MEMTST:1; ///< Bit 27 - Enable/Disable Memory Te= st > function: 0=3DDisable, 1=3DEnable. >=20 > + UINT32 ALIASCHK:1; ///< Bit 28 - Enable/Disable DIMM SPD = Alias > Check: 0=3DDisable, 1=3DEnable >=20 > + UINT32 RCVENC1D:1; ///< Bit 29 - Enable/Disable Receive E= nable > Centering Training (LPDDR Only). Note it is not recommended to change thi= s > setting from the default value: 0=3DDisable, 1=3DEnable >=20 > + UINT32 RMC:1; ///< Bit 30 - Enable/Disable Retrain M= argin Check. > Note it is not recommended to change this setting from the default value: > 0=3DDisable, 1=3DEnable >=20 > + UINT32 WRDSUDT:1; ///< Bit 31 - Enable/Disable Write Dri= ve > Strength Up/Dn independently. Note it is not recommended to change this > setting from the default value: 0=3DDisable, 1=3DEnable >=20 > + /// Training Algorithms 2 Offset 88 >=20 > + UINT32 DCC : 1; ///< Bit 0 - Enable/Disable Duty Cycl= e Correction: > 0=3DDisable, 1=3DEnable. >=20 > + UINT32 RDVC1D : 1; ///< Bit 1 - Enable/Disable Read Volt= age > Centering 1D: 0=3DDisable, 1=3DEnable. >=20 > + UINT32 TXTCO : 1; ///< Bit 2 - Enable/Disable Write TCO= Comp > Training: 0=3DDisable, 1=3DEnable. >=20 > + UINT32 CLKTCO : 1; ///< Bit 3 - Enable/Disable Clock TCO= Comp > Training: 0=3DDisable, 1=3DEnable. >=20 > + UINT32 CMDSR : 1; ///< Bit 4 - Enable/Disable CMD Slew = Rate > Training: 0=3DDisable, 1=3DEnable. >=20 > + UINT32 CMDDSEQ : 1; ///< Bit 5 - Enable/Disable CMD Drive= Strength > and Tx Equalization: 0=3DDisable, 1=3DEnable. >=20 > + UINT32 DIMMODTCA : 1; ///< Bit 6 - Enable/Disable Dimm ODT = CA > Training: 0=3DDisable, 1=3DEnable. >=20 > + UINT32 TXTCODQS : 1; ///< Bit 7 - Enable/Disable Write TCO= Dqs > Training: 0=3DDisable, 1=3DEnable. >=20 > + UINT32 CMDDRUD : 1; ///< Bit 8 - Enable/Disable CMD/CTL D= rive > Strength Up/Dn 2D: 0=3DDisable, 1=3DEnable. >=20 > + UINT32 VCCDLLBP : 1; ///< Bit 9 - Enable/Disable VccDLL by= pass to > VccIOG training: 0=3DDisable, 1=3DEnable. >=20 > + UINT32 PVTTDNLP : 1; ///< Bit 10 - Enable/Disable PanicVttD= nLp > Training: 0=3DDisable, 1=3DEnable. >=20 > + UINT32 RDVREFDC : 1; ///< Bit 11 - Enable/Disable Read Vref= Decap > Training: 0=3DDisable, 1=3DEnable. >=20 > + UINT32 VDDQT : 1; ///< Bit 12 - Enable/Disable Vddq Trai= ning: > 0=3DDisable, 1=3DEnable. >=20 > + UINT32 RMTBIT : 1; ///< Bit 13 - Enable/Disable Rank Marg= in Tool Per > Bit: 0=3DDisable, 1=3DEnable. >=20 > + UINT32 PDA : 1; ///< BIT 14 - Enable/Disable PDA Enume= ration > Training. Note it is not recommended to change this setting from the defa= ult > value: 0=3DDisable, 1=3DEnable. >=20 > + UINT32 WRITE0 : 1; ///< BIT 15 - Write0 feature enablemen= t >=20 > + UINT32 ReservedBits2 :16; ///< Bits 16:31 - Reserved >=20 > + >=20 > + UINT32 MrcTimeMeasure:1; ///< Offset 92 Bit 0 - Enables seri= al debug > level to display the MRC execution times only: 0=3DDisable, 1=3DEn= able >=20 > + UINT32 MrcFastBoot:1; ///< Bit 1 - Enables the = MRC fast boot > path for faster cold boot execution: 0=3DDisable, 1=3DEnable >=20 > + UINT32 DqPinsInterleaved:1; ///< Bit 2 - Interleaving= mode of > DQ/DQS pins which depends on board routing: 0=3DDisable, 1=3DEnabl= e >=20 > + UINT32 RankInterleave:1; ///< Bit 3 - Rank Interle= ave Mode: > 0=3DDisable, 1=3DEnable >=20 > + UINT32 EnhancedInterleave:1; ///< Bit 4 - Enhanced Int= erleave > Mode: 0=3DDisable, 1=3DEnable >=20 > + UINT32 WeaklockEn:1; ///< Bit 5 - Weak Lock En= able: > 0=3DDisable, 1=3DEnable >=20 > + UINT32 ChHashEnable:1; ///< Bit 6 - Channel Hash= Enable: > 0=3DDisable, 1=3DEnable >=20 > + UINT32 EnablePwrDn:1; ///< Bit 7 - Enable Power= Down control > for DDR: 0=3DPCODE control, 1=3DBIOS control >=20 > + UINT32 EnablePwrDnLpddr:1; ///< Bit 8 - Enable Power= Down for > LPDDR: 0=3DPCODE control, 1=3DBIOS control >=20 > + UINT32 SrefCfgEna:1; ///< Bit 9 - Enable Self = Refresh: > 0=3DDisable, 1=3DEnable >=20 > + UINT32 ThrtCkeMinDefeatLpddr:1; ///< Bit 10 - Throttler CK= E min > defeature for LPDDR: 0=3DDisable, 1=3DEnable >=20 > + UINT32 ThrtCkeMinDefeat:1; ///< Bit 11 - Throttler CK= E min > defeature: 0=3DDisable, 1=3DEnable >=20 > + UINT32 AutoSelfRefreshSupport:1; ///< Bit 12 - FALSE =3D No= auto self > refresh support, TRUE =3D auto self refresh support >=20 > + UINT32 ExtTemperatureSupport:1; ///< Bit 13 - FALSE =3D No= extended > temperature support, TRUE =3D extended temperature support >=20 > + UINT32 MobilePlatform:1; ///< Bit 14 - Memory contr= oller device > id indicates: TRUE if mobile, FALSE if not. Note: This will be aut= o- > detected and updated. >=20 > + UINT32 Force1Dpc:1; ///< Bit 15 - TRUE means f= orce one DIMM > per channel, FALSE means no limit >=20 > + UINT32 ForceSingleRank:1; ///< Bit 16 - TRUE means u= se Rank0 > only (in each DIMM): 0=3DDisable, 1=3DEnable >=20 > + UINT32 VttTermination:1; ///< Bit 17 - Vtt Terminat= ion for Data > ODT: 0=3DDisable, 1=3DEnable >=20 > + UINT32 VttCompForVsshi:1; ///< Bit 18 - Enable/Disab= le Vtt > Comparator For Vsshi: 0=3DDisable, 1=3DEnable >=20 > + UINT32 ExitOnFailure:1; ///< Bit 19 - MRC option f= or exit on > failure or continue on failure: 0=3DDisable, 1=3DEnable >=20 > + UINT32 NewFeatureEnable1:1; ///< Bit 20 - Generic enab= le knob > for new feature set 1 0: Disable ; 1: Enable >=20 > + UINT32 NewFeatureEnable2:1; ///< Bit 21 - Generic enab= le knob > for new feature set 2 0: Disable ; 1: Enable >=20 > + UINT32 RhPrevention:1; ///< Bit 22 - RH Preventio= n > Enable/Disable: 0=3DDisable, 1=3DEnable >=20 > + UINT32 RhSolution:1; ///< Bit 23 - Type of solu= tion to be used > for RHP - 0/1 =3D HardwareRhp/Refresh2x >=20 > + UINT32 RefreshPanicWm:4; ///< Bit 24-27 - Refresh P= anic > Watermark, Range 1-8, default 8. >=20 > + UINT32 RefreshHpWm:4; ///< Bit 28-31 - Refresh H= igh Profile > Watermark, Range 1-7, default 7. >=20 > + UINT32 VddSettleWaitTime; ///< Offset 96 Amount of time in > microseconds to wait for Vdd to settle on top of 200us required by JEDEC > spec: Default=3D0 >=20 > + UINT16 SrefCfgIdleTmr; ///< Offset 100 Self Refresh idle time= r: > 512=3DMinimal, 65535=3DMaximum >=20 > + UINT16 ChHashMask; ///< Offset 102 Channel Hash Mask: > 0x0001=3DBIT6 set(Minimal), 0x3FFF=3DBIT[19:6] set(Maximum), 0x30CE=3D > BIT[19:18, 13:12 ,9:7] set >=20 > + UINT16 DdrFreqLimit; ///< Offset 104 Memory Frequency setti= ng: > 3=3D1067, 5=3D1333, 7=3D1600, 9=3D1867, 11=3D2133, 13=3D2400, 15=3D266= 7 >=20 > + UINT8 MaxRttWr; ///< Offset 106 Maximum DIMM RTT_WR to= use > in power training: 0=3DODT Off, 1 =3D 120 ohms >=20 > + UINT8 ThrtCkeMinTmr; ///< Offset 107 Throttler CKE min time= r: > 0=3DMinimal, 0xFF=3DMaximum, 0x00=3DDefault >=20 > + UINT8 ThrtCkeMinTmrLpddr; ///< Offset 108 Throttler CKE min time= r for > LPDDR: 0=3DMinimal, 0xFF=3DMaximum, 0x00=3DDefault >=20 > + BOOLEAN PerBankRefresh; ///< Offset 109 Enables and Disables t= he > per bank refresh. This only impacts memory technologies that support PBR= : > LPDDR3, LPDDR4. FALSE=3DDisabled, TRUE=3DEnabled >=20 > + UINT8 SaGv; ///< Offset 110 SA GV: 0=3DDisabled= , > 1=3DPoint1, 2=3DPoint2, 3=3DPoint3, 4=3DPoint4, 5=3DEnabled >=20 > + UINT8 NModeSupport; ///< Offset 111 Memory N Mode Support = - > Enable user to select Auto, 1N or 2N: 0=3DAUTO, 1=3D1N, 2=3D2N. >=20 > + UINT8 RefClk; ///< Offset 112 Selects the DDR base r= eference > clock. 0x01 =3D 100MHz, 0x00 =3D 133MHz >=20 > + UINT8 EnCmdRate; ///< Offset 113 CMD Rate Enable: 0=3DD= isable, > 5=3D2 CMDs, 7=3D3 CMDs, 9=3D4 CMDs, 11=3D5 CMDs, 13=3D6 CMDs, 15= =3D7 > CMDs >=20 > + UINT8 Refresh2X; ///< Offset 114 Refresh 2x: 0=3DDis= able, > 1=3DEnable for WARM or HOT, 2=3DEnable for HOT only >=20 > + UINT8 EpgEnable; ///< Offset 115 Enable Energy Performa= nce Gain. >=20 > + UINT8 UserThresholdEnable; ///< Offset 116 Flag to manually selec= t the > DIMM CLTM Thermal Threshold, 0=3DDisable, 1=3DEnable, 0=3DDefault >=20 > + UINT8 UserBudgetEnable; ///< Offset 117 Flag to manually selec= t the > Budget Registers for CLTM Memory Dimms , 0=3DDisable, 1=3DEnable, > 0=3DDefault >=20 > + UINT8 RetrainOnFastFail; ///< Offset 118 Restart MRC in Cold mo= de if > SW MemTest fails during Fast flow. 0 =3D Disabled, 1 =3D Enabled >=20 > + UINT8 PowerDownMode; ///< Offset 119 CKE Power Down Mode: > 0xFF=3DAUTO, 0=3DNo Power Down, 1=3D APD mode, 6=3DPPD-DLL Off > mode >=20 > + UINT8 PwdwnIdleCounter; ///< Offset 120 CKE Power Down Mode > Idle Counter: 0=3DMinimal, 255=3DMaximum, 0x80=3D0x80 DCLK >=20 > + UINT8 CmdRanksTerminated; ///< Offset 121 LPDDR: Bitmask of rank= s > that have CA bus terminated. 0x01=3DDefault, Rank0 is terminating and > Rank1 is non-terminating >=20 > + UINT16 MsHashMask; ///< Offset 122 Controller Hash Mask: > 0x0001=3DBIT6 set(Minimal), 0x3FFF=3DBIT[19:6] set(Maximum), 0x30CE=3D > BIT[19:18, 13:12 ,9:7] set >=20 > + UINT32 Lp5CccConfig; ///< Offset 124 BitMask where bits [3:= 0] are > controller 0 Channel [3:0] and [7:4] are Controller 1 Channel [3:0]. 0 s= elects > Ascending mapping and 1 selects Descending mapping. >=20 > + UINT8 RMTLoopCount; ///< Offset 128 Indicates the Loop Cou= nt to > be used for Rank Margin Tool Testing: 1=3DMinimal, 32=3DMaximum, 0=3DAUTO= , > 0=3DDefault >=20 > + UINT8 MsHashInterleaveBit; ///< Offset 129 Option to select inter= leave > Address bit. Valid values are 0 - 3 for BITS 6 - 9 >=20 > + UINT8 GearRatio; ///< Offset 130 This input control's t= he current > gear expressed as an integer when SAGV is disabled: 0=3DDefault, 1= , 2. >=20 > + UINT8 Ddr4OneDpc; ///< Offset 131 DDR4 1DPC performance > feature: 0 - Disabled; 1 - Enabled on DIMM0 only, 2 - Enabled on DIMM1 on= ly; > 3 - Enabled on both DIMMs. (bit [0] - DIMM0, bit [1] - DIMM1) >=20 > + UINT32 BclkRfiFreq[MEM_MAX_SAGV_POINTS]; ///< Offset 132 Bclk RFI > Frequency for each SAGV point in Hz units. 98000000Hz =3D 98MHz 0 - No > RFI Tuning. Range is 98Mhz-100Mhz. >=20 > + UINT16 SaGvFreq[MEM_MAX_SAGV_POINTS]; ///< Offset 148 > Frequency per SAGV point. 0 is Auto, otherwise holds the frequency value > expressed as an integer: 0=3DDefault, 1067, 1333, 1600, 1800, 1867= , > etc. >=20 > + /** >=20 > + Offset 156 Gear ratio per SAGV point. 0 is Auto, otherwise holds th= e Gear > ratio expressed as an integer: 0=3DDefault, 1, 2. >=20 > + Only valid combinations of Gear Ratio per point is: >=20 > + | point | set1 | set2 | set3 >=20 > + | 0 | 1 | 2 | 2 >=20 > + | 1 | 1 | 2 | 2 >=20 > + | 2 | 1 | 2 | 2 >=20 > + | 3 | 1 | 2 | 1 >=20 > + **/ >=20 > + UINT8 SaGvGear[MEM_MAX_SAGV_POINTS]; ///< Offse= t 156 >=20 > + UINT8 IbeccProtectedRegionEnable[MEM_MAX_IBECC_REGIONS]; ///< > Offset 160 Enable use of address range for ECC Protection: > 0=3DDefault, 1 >=20 > + UINT16 IbeccProtectedRegionBase[MEM_MAX_IBECC_REGIONS]; ///< > Offset 168 Base address for address range of ECC Protection: > 0=3DDefault, 1 >=20 > + UINT16 IbeccProtectedRegionMask[MEM_MAX_IBECC_REGIONS]; ///< > Offset 184 Mask address for address range of ECC Protection: > 0=3DDefault, 1 >=20 > + UINT32 CmdMirror; ///< Offset 200 BitMask where bits [3:= 0] are > controller 0 Channel [3:0] and [7:4] are Controller 1 Channel [3:0]. 0 = =3D No > Command Mirror and 1 =3D Command Mirror. >=20 > + UINT8 CpuBclkSpread; ///< Offset 204 CPU BCLK Spread Spectu= rm: 0 > =3D Disabled; 1 =3D Enabled >=20 > + UINT8 ExtendedBankHashing; ///< Offset 205 Enable EBH Extended > Bank Hashing: 0=3DDisabled; 1 =3D Enabled. >=20 > + UINT16 VddqVoltageOverride; ///< Offset 206 VccddqVoltage override > in # of 1mV >=20 > + UINT8 MarginLimitCheck; ///< Offse= t 208 Margin limit > check enable: 0=3DDisable, 1=3DL1 only, 2=3DL2 only, 3=3DBoth L1 a= nd L2 >=20 > + UINT8 RsvdO209; ///< Offse= t 209 >=20 > + UINT16 MarginLimitL2; ///< Offse= t 210 Margin limit > check L2 threshold: 100=3DDefault >=20 > +} MEMORY_CONFIGURATION; >=20 > + >=20 > +/// Memory Configuration >=20 > +/// The contents of this structure are not CRC'd by the MRC for option > change detection. >=20 > +/// Revision 1: - Initial version. >=20 > +/// Revision 2: - Added MemTestOnWarmBoot >=20 > +typedef struct { >=20 > + CONFIG_BLOCK_HEADER Header; ///< Offset 0-23 Config = Block > Header >=20 > + SA_FUNCTION_CALLS SaCall; ///< Offset 24 Functio= n calls into > the SA. >=20 > + SA_MEMORY_FUNCTIONS MrcCall; ///< Offset 204 Functio= n calls > into the MRC. >=20 > + SPD_DATA_BUFFER *SpdData; ///< Offset 240 Memory = SPD > data, will be used by the MRC when SPD SmBus address is zero. >=20 > + UINT32 Reserved0; >=20 > + SA_MEMORY_DQDQS_MAPPING *DqDqsMap; ///< Offset 244 > LPDDR DQ bit and DQS byte swizzling between CPU and DRAM. >=20 > + SA_MEMORY_RCOMP *RcompData; ///< Offset 248 DDR RCO= MP > resistors and target values. >=20 > + UINT64 PlatformMemorySize; ///< Offset 252 The min= imum > platform memory size required to pass control into DXE >=20 > + UINT32 CleanMemory:1; ///< Offset 256 Ask MRC= to clear > memory content: FALSE=3DDo not Clear Memory; TRUE=3DClear > Memory >=20 > + UINT32 ReservedBits5:31; >=20 > + /** >=20 > + Sets the serial debug message level\n >=20 > + 0x00 =3D Disabled\n >=20 > + 0x01 =3D Errors only\n >=20 > + 0x02 =3D Errors and Warnings\n >=20 > + 0x03 =3D Errors, Warnings, and Info\n >=20 > + 0x04 =3D Errors, Warnings, Info, and Events\n >=20 > + 0x05 =3D Displays Memory Init Execution Time Summary only\n >=20 > + **/ >=20 > + UINT8 SerialDebugLevel; ///< Offset 260 >=20 > + UINT8 MemTestOnWarmBoot; ///< Offset 261 Run Bas= e > Memory Test On WarmBoot: 0=3DDisabled, 1=3DEnabled >=20 > + UINT8 Reserved11[2]; ///< Offset 262 - 263 R= eserved >=20 > +} MEMORY_CONFIG_NO_CRC; >=20 > +#pragma pack(pop) >=20 > + >=20 > +#endif // _MEMORY_CONFIG_H_ >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Overclocking/Over= cl > ockingConfig.h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Overclocking/Over= cl > ockingConfig.h > new file mode 100644 > index 0000000000..462c02cef1 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Overclocking/Over= cl > ockingConfig.h > @@ -0,0 +1,236 @@ > +/** @file >=20 > + Overclocking Config Block. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _OVERCLOCKING_PREMEM_CONFIG_H_ >=20 > +#define _OVERCLOCKING_PREMEM_CONFIG_H_ >=20 > + >=20 > +#define OVERCLOCKING_CONFIG_REVISION 9 >=20 > + >=20 > +extern EFI_GUID gOverclockingPreMemConfigGuid; >=20 > + >=20 > +#pragma pack (push,1) >=20 > + >=20 > +// >=20 > +// Max number of VF point offset >=20 > +// >=20 > +#ifndef CPU_OC_MAX_VF_POINTS >=20 > +#define CPU_OC_MAX_VF_POINTS 0xF >=20 > +#endif >=20 > + >=20 > +#ifndef CPU_OC_MAX_CORES >=20 > +#define CPU_OC_MAX_CORES 8 >=20 > +#endif >=20 > +/** >=20 > + Overclocking Configuration Structure. >=20 > + >=20 > + Revision 1: >=20 > + - Initial version. >=20 > + Revision 2 >=20 > + - Add PerCoreHtDisable >=20 > + Revision 3 >=20 > + - Add Avx2VoltageScaleFactor and Avx512VoltageScaleFactor >=20 > + Revision 4 >=20 > + - Add CoreVfPointOffsetMode & CoreVfPointOffset & CoreVfPointRatio & > CoreVfPointCount >=20 > + Revision 5 >=20 > + - Change OcLock default to 'Enabled' >=20 > + Revision 6: >=20 > + - Add DisableCoreMask. >=20 > + Revision 7 >=20 > + Add UnlimitedIccMax >=20 > + Revision 8 >=20 > + - Add PerCoreRatioOverride and PerCoreRatio for Per Core PState > overclocking. >=20 > + Revision 9 >=20 > + - Add VccInVoltageOverride. >=20 > +**/ >=20 > +typedef struct { >=20 > + CONFIG_BLOCK_HEADER Header; ///< Config Block Head= er >=20 > + /** >=20 > + Overclocking support. This controls whether OC mailbox transactions ar= e > sent. >=20 > + If disabled, all policies in this config block besides OcSupport and O= cLock > will be ignored. >=20 > + 0: Disable; >=20 > + 1: Enable. >=20 > + @note If PcdOverclockEnable is disabled, this should also be disabled. >=20 > + **/ >=20 > + UINT32 OcSupport : 1; >=20 > + UINT32 OcLock : 1; ///< If enabled, sets = OC lock bit in MSR > 0x194[20], locking the OC mailbox and other OC configuration settings.; 0= : > Disable; 1: Enable (Lock). >=20 > + /** >=20 > + Core voltage mode, specifies which voltage mode the processor will be > operating. >=20 > + 0: Adaptive Mode allows the processor to interpolate a voltage > curve when beyond fused P0 range; >=20 > + 1: Override, sets one voltage for for the entire frequency range, Pn-P= 0. >=20 > + **/ >=20 > + UINT32 CoreVoltageMode : 1; >=20 > + UINT32 CorePllVoltageOffset : 6; ///< Core PLL voltage = offset. > 0: No offset. Range 0-63 in 17.5mv units. >=20 > + UINT32 Avx2RatioOffset : 5; ///< AVX2 Ratio Offset= . 0: No > offset. Range is 0-31. Used to lower the AVX ratio to maximize possib= le > ratio for SSE workload. >=20 > + UINT32 Avx3RatioOffset : 5; ///< AVX3 Ratio Offset= . 0: No > offset. Range is 0-31. Used to lower the AVX3 ratio to maximize possi= ble > ratio for SSE workload. >=20 > + UINT32 BclkAdaptiveVoltage : 1; ///< Bclk Adaptive Vol= tage > enable/disable. 0: Disabled, 1: Enabled. When enabled, the CPU V/F > curves are aware of BCLK frequency when calculated. >=20 > + /** >=20 > + Ring Downbin enable/disable. >=20 > + When enabled, the CPU will force the ring ratio to be lower than the c= ore > ratio. >=20 > + Disabling will allow the ring and core ratios to run at the same frequ= ency. >=20 > + Uses OC Mailbox command 0x19. >=20 > + 0: Disables Ring Downbin feature. 1: Enables Ring downbin > feature. >=20 > + **/ >=20 > + UINT32 RingDownBin : 1; >=20 > + /** >=20 > + Ring voltage mode, specifies which voltage mode the processor will be > operating. >=20 > + 0: Adaptive Mode allows the processor to interpolate a voltage > curve when beyond fused P0 range; >=20 > + 1: Override, sets one voltage for for the entire frequency range, Pn-P= 0. >=20 > + **/ >=20 > + UINT32 RingVoltageMode : 1; >=20 > + UINT32 GtVoltageMode : 1; ///< Specifies whether GT voltage= is > operating in Adaptive or Override mode: 0=3DAdaptive, 1=3DOverride >=20 > + UINT32 RealtimeMemoryTiming : 1; ///< Enable/Disable the message > sent to the CPU to allow realtime memory timing changes after MRC_DONE. > 0=3DDisable, 1=3DEnable >=20 > + UINT32 FivrFaults : 1; ///< Fivr Faults. Enable or Disab= le FIVR Faults. > 0: Disabled, 1: Enabled. >=20 > + UINT32 FivrEfficiency : 1; ///< Fivr Efficiency Management. = 0: > Disabled, 1: Enabled. >=20 > + /** >=20 > + Selects Core Voltage & Frequency Point Offset between Legacy and > Selection modes. >=20 > + Need Reset System after enabling OverClocking Feature to Initialize th= e > default value. >=20 > + 0: In Legacy Mode, setting a global offset for the entire VF curve.= >=20 > + 1: In Selection modes, setting a selected VF point. >=20 > + **/ >=20 > + UINT32 CoreVfPointOffsetMode : 1; >=20 > + UINT32 UnlimitedIccMax : 1; ///< Support Unlimited ICCMAX mor= e > than maximum value 255.75A. 0: Disabled, 1: Enabled. >=20 > + UINT32 PerCoreRatioOverride : 1; ///< Enable or disable = Per Core > PState OC supported by writing OCMB 0x1D to program new favored core > ratio to each Core. 0: Disable, 1: enable >=20 > + UINT32 DynamicMemoryChange : 1; ///< Dynamic Memory Timings > Changes; 0: Disabled; 1: Enabled. >=20 > + UINT32 RsvdBits : 2; ///< Reserved for future use >=20 > + >=20 > + /** >=20 > + Maximum core turbo ratio override allows to increase CPU core frequenc= y > beyond the fused max turbo ratio limit (P0). >=20 > + 0. no override/HW defaults.. Range 0-85. >=20 > + **/ >=20 > + UINT8 CoreMaxOcRatio; >=20 > + UINT8 GtMaxOcRatio; ///< Maximum GT turbo ratio overr= ide: > 0=3DMinimal, 60=3DMaximum, 0=3DAUTO >=20 > + /** >=20 > + Maximum ring ratio override allows to increase CPU ring frequency beyo= nd > the fused max ring ratio limit. >=20 > + 0. no override/HW defaults.. Range 0-85. >=20 > + **/ >=20 > + UINT8 RingMaxOcRatio; >=20 > + UINT8 RsvdByte1; >=20 > + /** >=20 > + The core voltage override which is applied to the entire range of cpu = core > frequencies. >=20 > + Used when CoreVoltageMode =3D Override. >=20 > + 0. no override. Range 0-2000 mV. >=20 > + **/ >=20 > + UINT16 CoreVoltageOverride; >=20 > + /** >=20 > + Adaptive Turbo voltage target used to define the interpolation voltage > point when the cpu is operating in turbo mode range. >=20 > + Used when CoreVoltageMode =3D Adaptive. >=20 > + 0. no override. Range 0-2000mV. >=20 > + **/ >=20 > + UINT16 CoreVoltageAdaptive; >=20 > + /** >=20 > + The core voltage offset applied on top of all other voltage modes. Thi= s > offset is applied over the entire frequency range. >=20 > + This is a 2's complement number in mV units. Default: 0 Range: = - > 1000 to 1000. >=20 > + **/ >=20 > + INT16 CoreVoltageOffset; >=20 > + /** >=20 > + The ring voltage override which is applied to the entire range of cpu = ring > frequencies. >=20 > + Used when RingVoltageMode =3D Override. >=20 > + 0. no override. Range 0-2000 mV. >=20 > + **/ >=20 > + UINT16 RingVoltageOverride; >=20 > + /** >=20 > + Adaptive Turbo voltage target used to define the interpolation voltage > point when the ring is operating in turbo mode range. >=20 > + Used when RingVoltageMode =3D Adaptive. >=20 > + 0. no override. Range 0-2000mV. >=20 > + **/ >=20 > + UINT16 RingVoltageAdaptive; >=20 > + /** >=20 > + The ring voltage offset applied on top of all other voltage modes. Thi= s > offset is applied over the entire frequency range. >=20 > + This is a 2's complement number in mV units. Default: 0 Range: = - > 1000 to 1000. >=20 > + **/ >=20 > + INT16 RingVoltageOffset; >=20 > + >=20 > + INT16 GtVoltageOffset; ///< The voltage offse= t applied to GT > slice. Valid range from -1000mv to 1000mv: 0=3DMinimal, > 1000=3DMaximum >=20 > + UINT16 GtVoltageOverride; ///< The GT voltage ov= erride which > is applied to the entire range of GT frequencies 0=3DDefault >=20 > + UINT16 GtExtraTurboVoltage; ///< The adaptive volt= age applied > during turbo frequencies. Valid range from 0 to 2000mV: 0=3DMinimal, > 2000=3DMaximum >=20 > + INT16 SaVoltageOffset; ///< The voltage offse= t applied to the > SA. Valid range from -1000mv to 1000mv: 0=3DDefault >=20 > + UINT32 GtPllVoltageOffset : 6; ///< GT PLL voltage of= fset. 0: > No offset. Range 0-63 in 17.5mv units. >=20 > + UINT32 RingPllVoltageOffset : 6; ///< Ring PLL voltage = offset. 0: > No offset. Range 0-63 in 17.5mv units. >=20 > + UINT32 SaPllVoltageOffset : 6; ///< System Agent PLL = voltage > offset. 0: No offset. Range 0-63 in 17.5mv units. >=20 > + UINT32 McPllVoltageOffset : 6; ///< Memory Controller= PLL > voltage offset. 0: No offset. Range 0-63 in 17.5mv units. >=20 > + UINT32 RsvdBits1 : 8; >=20 > + /** >=20 > + TjMax Offset. Specified value here is clipped by pCode (125 - TjMax Of= fset) > to support TjMax in the range of 62 to 115 deg Celsius. >=20 > + Default: 0 Hardware Defaults Range 10 to 63. 0 =3D No offset = / > Keep HW default. >=20 > + **/ >=20 > + UINT8 TjMaxOffset; >=20 > + UINT8 RsvdByte2[3]; //< Reserved for dword = alignment >=20 > + /** >=20 > + This service controls Core frequency reduction caused by high package > temperatures for processors that >=20 > + implement the Intel Thermal Velocity Boost (TVB) feature. It is requir= ed to > be disabled for supporting >=20 > + overclocking at frequencies higher than the default max turbo frequenc= y. >=20 > + 0: Disables TVB ratio clipping. 1: Enables TVB ratio clipping. >=20 > + **/ >=20 > + UINT32 TvbRatioClipping : 1; >=20 > + /** >=20 > + This service controls thermal based voltage optimizations for processo= rs > that implement the Intel >=20 > + Thermal Velocity Boost (TVB) feature. >=20 > + 0: Disables TVB voltage optimization. 1: Enables TVB voltage > optimization. >=20 > + **/ >=20 > + UINT32 TvbVoltageOptimization : 1; >=20 > + UINT32 RsvdBits2 : 30; >=20 > + /** >=20 > + Defines the per-core HT disable mask where: 1 - Disable selected logic= al > core HT, 0 - is ignored. >=20 > + Input is in HEX and each bit maps to a logical core. Ex. A value of '1= F' would > disable HT for cores 4,3,2,1 and 0. >=20 > + Default is 0, all cores have HT enabled. Range is 0 - 0x1FF. Yo= u can > only disable up to MAX_CORE_COUNT - 1. >=20 > + **/ >=20 > + UINT16 PerCoreHtDisable; >=20 > + /** >=20 > + Avx2 Voltage Guardband Scale Factor >=20 > + This controls the AVX2 Voltage Guardband Scale factor applied to AVX2 > workloads. >=20 > + Valid range is 0-200 in 1/100 units, where a value of 125 would apply = a 1.25 > scale factor. >=20 > + A value of 0 means no scale factor applied (no change to voltage on AV= X > commands) >=20 > + A value of 100 applies the default voltage guardband values (1.0 facto= r). >=20 > + A value > 100 will increase the voltage guardband on AVX2 workloads. >=20 > + A value < 100 will decrease the voltage guardband on AVX2 workloads. >=20 > + >=20 > + 0. No scale factor applied >=20 > + **/ >=20 > + UINT8 Avx2VoltageScaleFactor; >=20 > + /** >=20 > + Avx512 Voltage Guardband Scale Factor >=20 > + This controls the AVX512 Voltage Guardband Scale factor applied to > AVX512 workloads. >=20 > + Valid range is 0-200 in 1/100 units, where a value of 125 would apply = a 1.25 > scale factor. >=20 > + A value of 0 means no scale factor applied (no change to voltage on AV= X > commands) >=20 > + A value of 100 applies the default voltage guardband values (1.0 facto= r). >=20 > + A value > 100 will increase the voltage guardband on AVX512 workloads. >=20 > + A value < 100 will decrease the voltage guardband on AVX512 workloads. >=20 > + >=20 > + 0. No scale factor applied >=20 > + **/ >=20 > + UINT8 Avx512VoltageScaleFactor; >=20 > + /** >=20 > + Array used to specifies the Core Voltage Offset applied to the each > selected VF Point. >=20 > + This voltage is specified in millivolts. >=20 > + **/ >=20 > + INT16 CoreVfPointOffset[CPU_OC_MAX_VF_POINTS]; >=20 > + UINT8 RsvdByte3[2]; ///< Just to keep native alignment. >=20 > + /** >=20 > + Array for the each selected VF Point to display the Core Ration. >=20 > + **/ >=20 > + UINT8 CoreVfPointRatio[CPU_OC_MAX_VF_POINTS]; >=20 > + /** >=20 > + Number of supported Core Voltage & Frequency Point. >=20 > + **/ >=20 > + UINT8 CoreVfPointCount; >=20 > + /** >=20 > + Core mask is a bitwise indication of which core should be disabled. Bi= t 0 - > core 0, bit 7 - core 7. >=20 > + **/ >=20 > + UINT32 DisableCoreMask; >=20 > + UINT8 PerCoreRatio[CPU_OC_MAX_CORES]; >=20 > + /** >=20 > + The VcccIn voltage override. >=20 > + This will override VccIn output voltage level to the voltage value spe= cified. >=20 > + The voltage level is fixed and will not change except on PKG C-states = or > resets. >=20 > + >=20 > + 0. no override. Range 0-3000 mV. >=20 > + **/ >=20 > + UINT32 VccInVoltageOverride; >=20 > +} OVERCLOCKING_PREMEM_CONFIG; >=20 > + >=20 > +#pragma pack (pop) >=20 > + >=20 > +#endif // _CPU_OVERCLOCKING_CONFIG_H_ >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/P2sb/P2sbConfig.h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/P2sb/P2sbConfig.h > new file mode 100644 > index 0000000000..69271205b1 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/P2sb/P2sbConfig.h > @@ -0,0 +1,34 @@ > +/** @file >=20 > + P2sb policy >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _P2SB_CONFIG_H_ >=20 > +#define _P2SB_CONFIG_H_ >=20 > + >=20 > +#define P2SB_CONFIG_REVISION 1 >=20 > +extern EFI_GUID gP2sbConfigGuid; >=20 > + >=20 > +#pragma pack (push,1) >=20 > + >=20 > +/** >=20 > + This structure contains the policies which are related to P2SB device. >=20 > +**/ >=20 > +typedef struct { >=20 > + CONFIG_BLOCK_HEADER Header; ///< Config Block Head= er >=20 > + /** >=20 > + (Test) >=20 > + The sideband MMIO register access to specific ports will be locked >=20 > + before 3rd party code execution. Currently it disables PSFx access. >=20 > + This policy unlocks the sideband MMIO space for those IPs. >=20 > + 0: Lock sideband access ; 1: Unlock sideband access. >=20 > + NOTE: Do not set this policy "SbAccessUnlock" unless its necessary. >=20 > + **/ >=20 > + UINT32 SbAccessUnlock : 1; >=20 > + UINT32 Rsvdbits : 31; ///< Reserved bits >=20 > +} PCH_P2SB_CONFIG; >=20 > + >=20 > +#pragma pack (pop) >=20 > + >=20 > +#endif // _P2SB_CONFIG_H_ >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/PchDmi/PchDmiConf= i > g.h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/PchDmi/PchDmiConf > ig.h > new file mode 100644 > index 0000000000..b73108bcfd > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/PchDmi/PchDmiConf > ig.h > @@ -0,0 +1,44 @@ > +/** @file >=20 > + DMI policy >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _PCH_DMI_CONFIG_H_ >=20 > +#define _PCH_DMI_CONFIG_H_ >=20 > + >=20 > +#define PCH_DMI_CONFIG_REVISION 2 >=20 > +extern EFI_GUID gPchDmiConfigGuid; >=20 > + >=20 > + >=20 > +#pragma pack (push,1) >=20 > + >=20 > + >=20 > +/** >=20 > + The PCH_DMI_CONFIG block describes the expected configuration of the > PCH for DMI. >=20 > + Revision 1: - Initial version. >=20 > + Revision 2: - Add OpioRecenter >=20 > +**/ >=20 > +typedef struct { >=20 > + CONFIG_BLOCK_HEADER Header; ///< Config Block Header >=20 > + >=20 > + UINT32 PwrOptEnable : 1; ///< 0: Disable; 1: Enabl= e DMI > Power Optimizer on PCH side. >=20 > + UINT32 DmiAspmCtrl : 8; ///< ASPM configuration on the P= CH side > of the DMI/OPI Link. Default is PchPcieAspmAutoConfig >=20 > + UINT32 CwbEnable : 1; ///< 0: Disable; 1: Enable Central > Write Buffer feature configurable and enabled by default >=20 > + UINT32 L1RpCtl : 1; ///< 0: Disable; 1: Enable Allow DMI > enter L1 when all root ports are in L1, L0s or link down. Disabled by def= ault. >=20 > + /** >=20 > + When set to TRUE turns on: >=20 > + - L1 State Controller Power Gating >=20 > + - L1 State PHY Data Lane Power Gating >=20 > + - PHY Common Lane Power Gating >=20 > + - Hardware Autonomous Enable >=20 > + - PMC Request Enable and Sleep Enable >=20 > + **/ >=20 > + UINT32 DmiPowerReduction : 1; >=20 > + UINT32 OpioRecenter : 1; ///< 0: Disable; 1: Enable Opio > Recentering Disable for Pcie latency >=20 > + UINT32 Rsvdbits : 19; ///< Reserved bits >=20 > +} PCH_DMI_CONFIG; >=20 > + >=20 > +#pragma pack (pop) >=20 > + >=20 > +#endif // _PCH_DMI_CONFIG_H_ >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/PcieRp/PchPcieRp/= Pc > hPcieRpConfig.h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/PcieRp/PchPcieRp/= P > chPcieRpConfig.h > new file mode 100644 > index 0000000000..de086473a9 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/PcieRp/PchPcieRp/= P > chPcieRpConfig.h > @@ -0,0 +1,368 @@ > +/** @file >=20 > + PCH Pcie root port policy >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _PCH_PCIERP_CONFIG_H_ >=20 > +#define _PCH_PCIERP_CONFIG_H_ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +#define PCIE_RP_CONFIG_REVISION 1 >=20 > +#define PCIE_RP_PREMEM_CONFIG_REVISION 1 >=20 > +#define PCIE_RP_DXE_CONFIG_REVISION 1 >=20 > + >=20 > +extern EFI_GUID gPchPcieConfigGuid; >=20 > +extern EFI_GUID gPcieRpPreMemConfigGuid; >=20 > + >=20 > +#pragma pack (push,1) >=20 > + >=20 > +#define PCIE_LINK_EQ_COEFFICIENTS_MAX 10 >=20 > +#define PCIE_LINK_EQ_PRESETS_MAX 11 >=20 > + >=20 > +typedef enum { >=20 > + PchPcieOverrideDisabled =3D 0, >=20 > + PchPcieL1L2Override =3D 0x01, >=20 > + PchPcieL1SubstatesOverride =3D 0x02, >=20 > + PchPcieL1L2AndL1SubstatesOverride =3D 0x03, >=20 > + PchPcieLtrOverride =3D 0x04 >=20 > +} PCH_PCIE_OVERRIDE_CONFIG; >=20 > + >=20 > +/** >=20 > + PCIe device table entry entry >=20 > + >=20 > + The PCIe device table is being used to override PCIe device ASPM setti= ngs. >=20 > + To take effect table consisting of such entries must be instelled as P= PI >=20 > + on gPchPcieDeviceTablePpiGuid. >=20 > + Last entry VendorId must be 0. >=20 > +**/ >=20 > +typedef struct { >=20 > + UINT16 VendorId; ///< The vendor Id of Pci Express= card ASPM > setting override, 0xFFFF means any Vendor ID >=20 > + UINT16 DeviceId; ///< The Device Id of Pci Express= card ASPM > setting override, 0xFFFF means any Device ID >=20 > + UINT8 RevId; ///< The Rev Id of Pci Express ca= rd ASPM setting > override, 0xFF means all steppings >=20 > + UINT8 BaseClassCode; ///< The Base Class Code of Pci E= xpress card > ASPM setting override, 0xFF means all base class >=20 > + UINT8 SubClassCode; ///< The Sub Class Code of Pci Ex= press card > ASPM setting override, 0xFF means all sub class >=20 > + UINT8 EndPointAspm; ///< Override device ASPM (see: > PCH_PCIE_ASPM_CONTROL) >=20 > + ///< Bit 1 must be set in Overrid= eConfig for this field to > take effect >=20 > + UINT16 OverrideConfig; ///< The override config bitmap (= see: > PCH_PCIE_OVERRIDE_CONFIG). >=20 > + /** >=20 > + The L1Substates Capability Offset Override. (applicable if bit 2 is = set in > OverrideConfig) >=20 > + This field can be zero if only the L1 Substate value is going to be = override. >=20 > + **/ >=20 > + UINT16 L1SubstatesCapOffset; >=20 > + /** >=20 > + L1 Substate Capability Mask. (applicable if bit 2 is set in Override= Config) >=20 > + Set to zero then the L1 Substate Capability [3:0] is ignored, and on= ly L1s > values are override. >=20 > + Only bit [3:0] are applicable. Other bits are ignored. >=20 > + **/ >=20 > + UINT8 L1SubstatesCapMask; >=20 > + /** >=20 > + L1 Substate Port Common Mode Restore Time Override. (applicable if b= it > 2 is set in OverrideConfig) >=20 > + L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid > value of 0, but not the L1sTpowerOnValue. >=20 > + If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime, > L1sTpowerOnScale, and L1sTpowerOnValue are ignored, >=20 > + and only L1SubstatesCapOffset is override. >=20 > + **/ >=20 > + UINT8 L1sCommonModeRestoreTime; >=20 > + /** >=20 > + L1 Substate Port Tpower_on Scale Override. (applicable if bit 2 is s= et in > OverrideConfig) >=20 > + L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid > value of 0, but not the L1sTpowerOnValue. >=20 > + If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime, > L1sTpowerOnScale, and L1sTpowerOnValue are ignored, >=20 > + and only L1SubstatesCapOffset is override. >=20 > + **/ >=20 > + UINT8 L1sTpowerOnScale; >=20 > + /** >=20 > + L1 Substate Port Tpower_on Value Override. (applicable if bit 2 is s= et in > OverrideConfig) >=20 > + L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid > value of 0, but not the L1sTpowerOnValue. >=20 > + If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime, > L1sTpowerOnScale, and L1sTpowerOnValue are ignored, >=20 > + and only L1SubstatesCapOffset is override. >=20 > + **/ >=20 > + UINT8 L1sTpowerOnValue; >=20 > + >=20 > + /** >=20 > + SnoopLatency bit definition >=20 > + Note: All Reserved bits must be set to 0 >=20 > + >=20 > + BIT[15] - When set to 1b, indicates that the values in bits 9:0 = are valid >=20 > + When clear values in bits 9:0 will be ignored >=20 > + BITS[14:13] - Reserved >=20 > + BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in= these bits >=20 > + 000b - 1 ns >=20 > + 001b - 32 ns >=20 > + 010b - 1024 ns >=20 > + 011b - 32,768 ns >=20 > + 100b - 1,048,576 ns >=20 > + 101b - 33,554,432 ns >=20 > + 110b - Reserved >=20 > + 111b - Reserved >=20 > + BITS[9:0] - Snoop Latency Value. The value in these bits will be m= ultiplied > with >=20 > + the scale in bits 12:10 >=20 > + >=20 > + This field takes effect only if bit 3 is set in OverrideConfig. >=20 > + **/ >=20 > + UINT16 SnoopLatency; >=20 > + /** >=20 > + NonSnoopLatency bit definition >=20 > + Note: All Reserved bits must be set to 0 >=20 > + >=20 > + BIT[15] - When set to 1b, indicates that the values in bits 9:0 = are valid >=20 > + When clear values in bits 9:0 will be ignored >=20 > + BITS[14:13] - Reserved >=20 > + BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in= these bits >=20 > + 000b - 1 ns >=20 > + 001b - 32 ns >=20 > + 010b - 1024 ns >=20 > + 011b - 32,768 ns >=20 > + 100b - 1,048,576 ns >=20 > + 101b - 33,554,432 ns >=20 > + 110b - Reserved >=20 > + 111b - Reserved >=20 > + BITS[9:0] - Non Snoop Latency Value. The value in these bits will = be > multiplied with >=20 > + the scale in bits 12:10 >=20 > + >=20 > + This field takes effect only if bit 3 is set in OverrideConfig. >=20 > + **/ >=20 > + UINT16 NonSnoopLatency; >=20 > + >=20 > + /** >=20 > + Forces LTR override to be permanent >=20 > + The default way LTR override works is: >=20 > + rootport uses LTR override values provided by BIOS until connected > device sends an LTR message, then it will use values from the message >=20 > + This settings allows force override of LTR mechanism. If it's enable= d, then: >=20 > + rootport will use LTR override values provided by BIOS forever; LT= R > messages sent from connected device will be ignored >=20 > + **/ >=20 > + UINT8 ForceLtrOverride; >=20 > + UINT8 Reserved[3]; >=20 > +} PCH_PCIE_DEVICE_OVERRIDE; >=20 > + >=20 > +/// >=20 > +/// The values before AutoConfig match the setting of PCI Express Base > Specification 1.1, please be careful for adding new feature >=20 > +/// >=20 > +typedef enum { >=20 > + PchPcieAspmDisabled, >=20 > + PchPcieAspmL0s, >=20 > + PchPcieAspmL1, >=20 > + PchPcieAspmL0sL1, >=20 > + PchPcieAspmAutoConfig, >=20 > + PchPcieAspmMax >=20 > +} PCH_PCIE_ASPM_CONTROL; >=20 > + >=20 > +/** >=20 > + Refer to PCH EDS for the PCH implementation values corresponding >=20 > + to below PCI-E spec defined ranges >=20 > +**/ >=20 > +typedef enum { >=20 > + PchPcieL1SubstatesDisabled, >=20 > + PchPcieL1SubstatesL1_1, >=20 > + PchPcieL1SubstatesL1_1_2, >=20 > + PchPcieL1SubstatesMax >=20 > +} PCH_PCIE_L1SUBSTATES_CONTROL; >=20 > + >=20 > +enum PCH_PCIE_MAX_PAYLOAD { >=20 > + PchPcieMaxPayload128 =3D 0, >=20 > + PchPcieMaxPayload256, >=20 > + PchPcieMaxPayloadMax >=20 > +}; >=20 > + >=20 > +typedef enum { >=20 > + PcieLinkHardwareEq =3D 0, ///< Hardware is responsible for performing > coefficient/preset search. >=20 > + PcieLinkFixedEq ///< No coefficient/preset search is performe= d. Fixed > values are used. >=20 > +} PCIE_LINK_EQ_METHOD; >=20 > + >=20 > +typedef enum { >=20 > + PcieLinkEqPresetMode =3D 0, ///< Use presets during PCIe link equali= zation >=20 > + PcieLinkEqCoefficientMode ///< Use coefficients during PCIe link > equalization >=20 > +} PCIE_LINK_EQ_MODE; >=20 > + >=20 > +typedef struct { >=20 > + UINT32 PreCursor; ///< Pre-cursor coefficient >=20 > + UINT32 PostCursor; ///< Post-cursor coefficient >=20 > +} PCIE_LINK_EQ_COEFFICIENTS; >=20 > + >=20 > +/** >=20 > + PCIe Link EQ Platform Settings >=20 > +**/ >=20 > +typedef struct { >=20 > + UINT8 PcieLinkEqMethod; ///< Tells = BIOS which link EQ > method should be used for this port. Please refer to > PCIE_LINK_EQ_METHOD for details of supported methods. Default: > PcieLinkHardwareEq >=20 > + UINT8 PcieLinkEqMode; ///< Tells = BIOS which mode > should be used for PCIe link EQ. Please refer to PCIE_LINK_EQ_MODE for > details of supported modes. Default: depends on SoC >=20 > + /** >=20 > + Specifies if BIOS should perform local transmitter override during p= hase 2 > of EQ process. >=20 > + If enabled value in Ph2LocalTransmitterOverridePreset must be valid. >=20 > + 0: Disabled; 1: Enabled >=20 > + **/ >=20 > + UINT8 LocalTransmitterOverrideEnable; >=20 > + /** >=20 > + Tells BIOS how many presets/coefficients should be used during link = EQ. >=20 > + Entries in the Ph3CoefficientsList or Ph3PresetList(depending on cho= sen > mode) need to be valid up to the number specified in this field. >=20 > + **/ >=20 > + UINT8 Ph3NumberOfPresetsOrCoefficients; >=20 > + >=20 > + PCIE_LINK_EQ_COEFFICIENTS > Ph3CoefficientsList[PCIE_LINK_EQ_COEFFICIENTS_MAX]; ///< List of the > PCIe coefficients to be used during equalization process. Only valid if > PcieLinkEqMode is PcieLinkEqCoefficientMode >=20 > + UINT32 Ph3PresetList[PCIE_LINK_EQ_PRESETS_MAX]; = ///< > List of the PCIe preset values to be used during equalization process. On= ly > valid if PcieLinkEqMode is PcieLinkEqPresetMode >=20 > + UINT32 Ph1DownstreamPortTransmitterPreset; ///< S= pecifies > the value of the downstream port transmitter preset to be used during > phase 1 of the equalization process. Will be applied to all lanes >=20 > + UINT32 Ph1UpstreamPortTransmitterPreset; ///< S= pecifies the > value of the upstream port transmitter preset to be used during phase 1 o= f > the equalization process. Will be applied to all lanes >=20 > + /** >=20 > + Specifies the preset that should be used during local transmitter ov= erride > during phase 2 of EQ process. >=20 > + Used only if LocalTransmitterOverrideEnable is TRUE. Will be applied= to all > PCIe lanes of the root port. >=20 > + Valid up to the PCIE_LINK_EQ_PRESET_MAX value. Default: 0<\b> >=20 > + **/ >=20 > + UINT32 Ph2LocalTransmitterOverridePreset; >=20 > +} PCIE_LINK_EQ_PLATFORM_SETTINGS; >=20 > + >=20 > +#define PCH_PCIE_NO_SUCH_CLOCK 0xFF >=20 > + >=20 > +typedef enum { >=20 > + PchClockUsagePchPcie0 =3D 0, >=20 > + PchClockUsagePchPcie1 =3D 1, >=20 > + PchClockUsagePchPcie2 =3D 2, >=20 > + PchClockUsagePchPcie3 =3D 3, >=20 > + PchClockUsagePchPcie4 =3D 4, >=20 > + PchClockUsagePchPcie5 =3D 5, >=20 > + PchClockUsagePchPcie6 =3D 6, >=20 > + PchClockUsagePchPcie7 =3D 7, >=20 > + PchClockUsagePchPcie8 =3D 8, >=20 > + PchClockUsagePchPcie9 =3D 9, >=20 > + PchClockUsagePchPcie10 =3D 10, >=20 > + PchClockUsagePchPcie11 =3D 11, >=20 > + PchClockUsagePchPcie12 =3D 12, >=20 > + PchClockUsagePchPcie13 =3D 13, >=20 > + PchClockUsagePchPcie14 =3D 14, >=20 > + PchClockUsagePchPcie15 =3D 15, >=20 > + PchClockUsagePchPcie16 =3D 16, >=20 > + PchClockUsagePchPcie17 =3D 17, >=20 > + PchClockUsagePchPcie18 =3D 18, >=20 > + PchClockUsagePchPcie19 =3D 19, >=20 > + PchClockUsagePchPcie20 =3D 20, >=20 > + PchClockUsagePchPcie21 =3D 21, >=20 > + PchClockUsagePchPcie22 =3D 22, >=20 > + PchClockUsagePchPcie23 =3D 23, >=20 > + /** >=20 > + Quantity of PCH and CPU PCIe ports, as well as their encoding in thi= s > enum, may change between >=20 > + silicon generations and series. Do not assume that PCH port 0 will b= e > always encoded by 0. >=20 > + Instead, it is recommended to use (PchClockUsagePchPcie0 + > PchPortIndex) style to be forward-compatible >=20 > + **/ >=20 > + PchClockUsageCpuPcie0 =3D 0x40, >=20 > + PchClockUsageCpuPcie1 =3D 0x41, >=20 > + PchClockUsageCpuPcie2 =3D 0x42, >=20 > + PchClockUsageCpuPcie3 =3D 0x43, >=20 > + >=20 > + PchClockUsageLan =3D 0x70, >=20 > + PchClockUsageUnspecified =3D 0x80, ///< In use for a purpose not lis= ted > above >=20 > + PchClockUsageNotUsed =3D 0xFF >=20 > +} PCH_PCIE_CLOCK_USAGE; >=20 > + >=20 > +/** >=20 > + PCH_PCIE_CLOCK describes PCIe source clock generated by PCH. >=20 > +**/ >=20 > +typedef struct { >=20 > + UINT8 Usage; ///< Purpose of given clock (see > PCH_PCIE_CLOCK_USAGE). Default: Unused, 0xFF >=20 > + UINT8 ClkReq; ///< ClkSrc - ClkReq mapping. Default: 1:1 mappi= ng with > Clock numbers >=20 > + UINT8 RsvdBytes[2]; ///< Reserved byte >=20 > +} PCH_PCIE_CLOCK; >=20 > + >=20 > +/** >=20 > + The PCH_PCI_EXPRESS_ROOT_PORT_CONFIG describe the feature and > capability of each PCH PCIe root port. >=20 > +**/ >=20 > +typedef struct { >=20 > + PCIE_ROOT_PORT_COMMON_CONFIG PcieRpCommonConfig; ///an > instance of Pcie Common Config >=20 > + UINT8 ExtSync; ///< Indicate whether the extended synch = is > enabled. 0: Disable; 1: Enable. >=20 > + // >=20 > + // Error handlings >=20 > + // >=20 > + UINT8 SystemErrorEnable; ///< Indicate whether the System Error is > enabled. 0: Disable; 1: Enable. >=20 > + /** >=20 > + The Multiple VC (MVC) supports hardware to avoid HoQ block for laten= cy > sensitive TC. >=20 > + Currently it is only applicable to Root Ports with 2pX4 port configu= ration > with 2 VCs,or >=20 > + DMI port configuration with 3 VCs. For Root Ports 2pX4 configuration= , two > RPs (RP0, >=20 > + RP2) shall support two PCIe VCs (VC0 & VC1) and the other RPs (RP1, = RP3) > shall be >=20 > + disabled. >=20 > + 0: Disable; 1: Enable >=20 > + **/ >=20 > + UINT8 MvcEnabled; >=20 > + /** >=20 > + Virtual Pin Port is industry standard introduced to PCIe Hot Plug su= pport in > systems >=20 > + when GPIO pins expansion is needed. It is server specific feature. >=20 > + 0x00: Default; 0xFF: Disabled >=20 > + **/ >=20 > + UINT8 VppPort; >=20 > + UINT8 VppAddress; ///< PCIe Hot Plug V= PP SMBus > Address. Default is zero. >=20 > + UINT8 RsvdBytes0[3]; ///< Reserved bytes >=20 > +} PCH_PCIE_ROOT_PORT_CONFIG; >=20 > + >=20 > +/** >=20 > + The PCH_PCIE_CONFIG block describes the expected configuration of the > PCH PCI Express controllers >=20 > + Revision 1: >=20 > + - Initial version. >=20 > +**/ >=20 > +typedef struct { >=20 > + CONFIG_BLOCK_HEADER Header; ///< Config Block Head= er >=20 > + /// >=20 > + /// These members describe the configuration of each PCH PCIe root por= t. >=20 > + /// >=20 > + PCIE_COMMON_CONFIG PcieCommonConfig; >=20 > + PCH_PCIE_ROOT_PORT_CONFIG > RootPort[PCH_MAX_PCIE_ROOT_PORTS]; >=20 > + PCIE_LINK_EQ_PLATFORM_SETTINGS PcieLinkEqPlatformSettings; ///< > Global PCIe link EQ settings that BIOS will use during PCIe link EQ for e= very > port. >=20 > + /// >=20 > + /// 0: Use project default equalization settings; 1: Use > equalization settings from PcieLinkEqPlatformSettings >=20 > + /// >=20 > + UINT8 OverrideEqualizationDefaults; >=20 > + /// >=20 > + /// (Test) This member describes whether PCIE root port Port 8x= h > Decode is enabled. 0: Disable; 1: Enable. >=20 > + /// >=20 > + UINT8 EnablePort8xhDecode; >=20 > + /// >=20 > + /// (Test) The Index of PCIe Port that is selected for Port8xh > Decode (0 Based) >=20 > + /// >=20 > + UINT8 PchPciePort8xhDecodePortIndex; >=20 > + UINT8 RsvdBytes0[1]; >=20 > +} PCH_PCIE_CONFIG; >=20 > + >=20 > +/** >=20 > + The PCH_PCIE_RP_PREMEM_CONFIG block describes early configuration > of the PCH PCI Express controllers >=20 > + Revision 1: >=20 > + - Initial version. >=20 > +**/ >=20 > +typedef struct { >=20 > + CONFIG_BLOCK_HEADER Header; ///< Conf= ig Block > Header >=20 > + /** >=20 > + Root Port enabling mask. >=20 > + Bit0 presents RP1, Bit1 presents RP2, and so on. >=20 > + 0: Disable; 1: Enable. >=20 > + **/ >=20 > + UINT32 RpEnabledMask; >=20 > + /// Configuration of PCIe source clocks >=20 > + /// >=20 > + PCH_PCIE_CLOCK PcieClock[PCH_MAX_PCIE_CLOCKS]; >=20 > + >=20 > + /** >=20 > + Per Controller Bifurcation Configuration >=20 > + 0: Disabled; 1: 4x1; 2: 1x2_2x1; 3: 2x2; 4: 1x4; 5: 4x2; 6: 1= x4_2x2; 7: > 2x2_1x4; 8: 2x4; 9: 1x8 (see: PCIE_BIFURCATION_CONFIG) >=20 > + **/ >=20 > + UINT8 Bifurcation[PCH_MAX_PCIE_CONTROLLERS]; >=20 > + UINT8 Rsvd4[(4 - PCH_MAX_PCIE_CONTROLLERS % 4) % 4]; >=20 > +} PCH_PCIE_RP_PREMEM_CONFIG; >=20 > + >=20 > +/** >=20 > + The PCIE_RP_DXE_CONFIG block describes the expected configuration of > the PCH PCI Express controllers in DXE phase >=20 > + >=20 > + Revision 1: >=20 > + - Init version >=20 > +**/ >=20 > +typedef struct { >=20 > + CONFIG_BLOCK_HEADER Header; ///< Config Block= Header >=20 > + >=20 > + /** >=20 > + PCIe device override table >=20 > + The PCIe device table is being used to override PCIe device ASPM > settings. >=20 > + And it's only used in DXE phase. >=20 > + Please refer to PCH_PCIE_DEVICE_OVERRIDE structure for the table. >=20 > + Last entry VendorId must be 0. >=20 > + **/ >=20 > + PCH_PCIE_DEVICE_OVERRIDE *PcieDeviceOverrideTablePtr; >=20 > +} PCIE_RP_DXE_CONFIG; >=20 > + >=20 > +#pragma pack (pop) >=20 > + >=20 > +#endif // _PCH_PCIERP_CONFIG_H_ >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/PcieRp/PcieConfig= .h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/PcieRp/PcieConfig= .h > new file mode 100644 > index 0000000000..f5859f50d9 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/PcieRp/PcieConfig= .h > @@ -0,0 +1,213 @@ > +/** @file >=20 > + PCIe Config Block >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _PCIE_CONFIG_H_ >=20 > +#define _PCIE_CONFIG_H_ >=20 > +#include >=20 > + >=20 > +#define PCIE_CONFIG_REVISION 3 >=20 > +/* >=20 > +Revision 2< / b>: >=20 > +FomsCp - Deprecated >=20 > +Revision 3< / b>: >=20 > +Added PCIE_EQ_PARAM HwEqGen3CoeffList for all > CPU_PCIE_MAX_ROOT_PORTS >=20 > +Added PCIE_EQ_PARAM HwEqGen4CoeffList for all > CPU_PCIE_MAX_ROOT_PORTS >=20 > +Added PCIE_EQ_PARAM HwEqGen5CoeffList for all > CPU_PCIE_MAX_ROOT_PORTS >=20 > +*/ >=20 > + >=20 > +extern EFI_GUID gPcieConfigGuid; >=20 > + >=20 > +#pragma pack (push,1) >=20 > + >=20 > +enum PCIE_COMPLETION_TIMEOUT { >=20 > + PcieCompletionTO_Default, >=20 > + PcieCompletionTO_50_100us, >=20 > + PcieCompletionTO_1_10ms, >=20 > + PcieCompletionTO_16_55ms, >=20 > + PcieCompletionTO_65_210ms, >=20 > + PcieCompletionTO_260_900ms, >=20 > + PcieCompletionTO_1_3P5s, >=20 > + PcieCompletionTO_4_13s, >=20 > + PcieCompletionTO_17_64s, >=20 > + PcieCompletionTO_Disabled >=20 > +}; >=20 > + >=20 > +enum PCIE_SPEED { >=20 > + PcieAuto, >=20 > + PcieGen1, >=20 > + PcieGen2, >=20 > + PcieGen3, >=20 > + PcieGen4 >=20 > +}; >=20 > + >=20 > +/** >=20 > + Represent lane specific PCIe Gen3 equalization parameters. >=20 > +**/ >=20 > +typedef struct { >=20 > + UINT8 Cm; ///< Coefficient C-1 >=20 > + UINT8 Cp; ///< Coefficient C+1 >=20 > + UINT8 Rsvd0[2]; ///< Reserved bytes >=20 > +} PCIE_EQ_PARAM; >=20 > + >=20 > +typedef struct { >=20 > + UINT16 LtrMaxSnoopLatency; ///< (Test) Lat= ency > Tolerance Reporting, Max Snoop Latency. >=20 > + UINT16 LtrMaxNoSnoopLatency; ///< (Test) Lat= ency > Tolerance Reporting, Max Non-Snoop Latency. >=20 > + UINT8 SnoopLatencyOverrideMode; ///< (Test) Lat= ency > Tolerance Reporting, Snoop Latency Override Mode. >=20 > + UINT8 SnoopLatencyOverrideMultiplier; ///< (Test) Lat= ency > Tolerance Reporting, Snoop Latency Override Multiplier. >=20 > + UINT16 SnoopLatencyOverrideValue; ///< (Test) Lat= ency > Tolerance Reporting, Snoop Latency Override Value. >=20 > + UINT8 NonSnoopLatencyOverrideMode; ///< (Test) > Latency Tolerance Reporting, Non-Snoop Latency Override Mode. >=20 > + UINT8 NonSnoopLatencyOverrideMultiplier; ///< (Test) > Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier. >=20 > + UINT16 NonSnoopLatencyOverrideValue; ///< (Test) > Latency Tolerance Reporting, Non-Snoop Latency Override Value. >=20 > + UINT8 LtrConfigLock; ///< 0: Disable= ; 1: Enable. >=20 > + UINT8 ForceLtrOverride; >=20 > + UINT16 RsvdByte1; >=20 > +} PCIE_LTR_CONFIG; >=20 > + >=20 > + >=20 > +/** >=20 > + Specifies the form factor that the slot >=20 > + implements. For custom form factors that >=20 > + do not require any special handling please >=20 > + set PcieFormFactorOther. >=20 > +**/ >=20 > +typedef enum { >=20 > + PcieFormFactorOther =3D 0, >=20 > + PcieFormFactorCem, >=20 > + PcieFormFactorMiniPci, >=20 > + PcieFormFactorM2, >=20 > + PcieFormFactorOcuLink, >=20 > + PcieFormFactorExpressModule, // Also known as Server IO module(SIOM) >=20 > + PcieFormFactorExpressCard, >=20 > + PcieFormFactorU2 // Also known as SF-8639 >=20 > +} PCIE_FORM_FACTOR; >=20 > + >=20 > +//Note: This structure will be expanded to hold all common PCIe policies > between SA and PCH RootPort >=20 > +typedef struct { >=20 > + UINT32 HotPlug : 1; ///< Indicate whether = the root port is hot > plug available. 0: Disable; 1: Enable. >=20 > + UINT32 PmSci : 1; ///< Indicate whether = the root port > power manager SCI is enabled. 0: Disable; 1: Enable. >=20 > + UINT32 TransmitterHalfSwing : 1; ///< Indicate whether = the > Transmitter Half Swing is enabled. 0: Disable; 1: Enable. >=20 > + UINT32 AcsEnabled : 1; ///< Indicate whether = the ACS is > enabled. 0: Disable; 1: Enable. >=20 > + // >=20 > + // Error handlings >=20 > + // >=20 > + UINT32 AdvancedErrorReporting : 1; ///< Indicate whether = the > Advanced Error Reporting is enabled. 0: Disable; 1: Enable. >=20 > + UINT32 UnsupportedRequestReport : 1; ///< Indicate whether = the > Unsupported Request Report is enabled. 0: Disable; 1: Enable. >=20 > + UINT32 FatalErrorReport : 1; ///< Indicate whether = the Fatal Error > Report is enabled. 0: Disable; 1: Enable. >=20 > + UINT32 NoFatalErrorReport : 1; ///< Indicate whether = the No Fatal > Error Report is enabled. 0: Disable; 1: Enable. >=20 > + UINT32 CorrectableErrorReport : 1; ///< Indicate whether = the > Correctable Error Report is enabled. 0: Disable; 1: Enable. >=20 > + UINT32 SystemErrorOnFatalError : 1; ///< Indicate whether = the > System Error on Fatal Error is enabled. 0: Disable; 1: Enable. >=20 > + UINT32 SystemErrorOnNonFatalError : 1; ///< Indicate whether = the > System Error on Non Fatal Error is enabled. 0: Disable; 1: Enable. >=20 > + UINT32 SystemErrorOnCorrectableError : 1; ///< Indicate whether = the > System Error on Correctable Error is enabled. 0: Disable; 1: Enabl= e. >=20 > + /** >=20 > + Max Payload Size supported, Default 128B, see enum > CPU_PCIE_MAX_PAYLOAD >=20 > + Changes Max Payload Size Supported field in Device Capabilities of t= he > root port. >=20 > + **/ >=20 > + UINT32 MaxPayload : 2; >=20 > + UINT32 DpcEnabled : 1; ///< Downstream Port C= ontainment. > 0: Disable; 1: Enable >=20 > + UINT32 RpDpcExtensionsEnabled : 1; ///< RP Extensions for > Downstream Port Containment. 0: Disable; 1: Enable >=20 > + /** >=20 > + Indicates how this root port is connected to endpoint. 0: built-in d= evice; > 1: slot >=20 > + Built-in is incompatible with hotplug-capable ports. >=20 > + **/ >=20 > + UINT32 SlotImplemented : 1; >=20 > + UINT32 PtmEnabled : 1; ///< Enables PTM capab= ility >=20 > + UINT32 SlotPowerLimitScale : 2; ///< (Test) Spe= cifies scale > used for slot power limit value. Leave as 0 to set to default. Default is > zero. >=20 > + UINT32 SlotPowerLimitValue : 12; //< (Test) Spec= ifies > upper limit on power supplies by slot. Leave as 0 to set to default. Defa= ult is > zero. >=20 > + /** >=20 > + Probe CLKREQ# signal before enabling CLKREQ# based power > management. >=20 > + Conforming device shall hold CLKREQ# low until CPM is enabled. This > feature attempts >=20 > + to verify CLKREQ# signal is connected by testing pad state before en= abling > CPM. >=20 > + In particular this helps to avoid issues with open-ended PCIe slots. >=20 > + This is only applicable to non hot-plug ports. >=20 > + 0: Disable; 1: Enable. >=20 > + **/ >=20 > + UINT32 ClkReqDetect : 1; >=20 > + /** >=20 > + Set if the slot supports manually operated retention latch. >=20 > + **/ >=20 > + UINT32 MrlSensorPresent : 1; >=20 > + UINT32 RelaxedOrder : 1; >=20 > + UINT32 NoSnoop : 1; >=20 > + UINT32 RsvdBits0 : 28; ///< Reserved bits. >=20 > + /** >=20 > + PCIe Gen3 Equalization Phase 3 Method (see CPU_PCIE_EQ_METHOD). >=20 > + 0: DEPRECATED, hardware equalization; 1: hardware > equalization; 4: Fixed Coefficients >=20 > + **/ >=20 > + UINT8 Gen3EqPh3Method; >=20 > + UINT8 PhysicalSlotNumber; ///< Indicates the slo= t number for > the root port. Default is the value as root port index. >=20 > + UINT8 CompletionTimeout; ///< The completion ti= meout > configuration of the root port (see: CPU_PCIE_COMPLETION_TIMEOUT). > Default is PchPcieCompletionTO_Default. >=20 > + // >=20 > + // Power Management >=20 > + // >=20 > + UINT8 Aspm; ///< The ASPM configur= ation of the root > port (see: CPU_PCIE_ASPM_CONTROL). Default is > PchPcieAspmAutoConfig. >=20 > + UINT8 L1Substates; ///< The L1 Substates = configuration of > the root port (see: CPU_PCIE_L1SUBSTATES_CONTROL). Default is > PchPcieL1SubstatesL1_1_2. >=20 > + UINT8 LtrEnable; ///< Latency Tolerance= Reporting > Mechanism. 0: Disable; 1: Enable. >=20 > + UINT8 EnableCpm; ///< Enables Clock Pow= er Management; > even if disabled, CLKREQ# signal can still be controlled by L1 PM substat= es > mechanism >=20 > + UINT8 PcieSpeed; ///< Contains speed of= PCIe bus (see: > PCIE_SPEED) >=20 > + /** >=20 > + (Test) >=20 > + Forces LTR override to be permanent >=20 > + The default way LTR override works is: >=20 > + rootport uses LTR override values provided by BIOS until connected dev= ice > sends an LTR message, then it will use values from the message >=20 > + This settings allows force override of LTR mechanism. If it's enabled,= then: >=20 > + rootport will use LTR override values provided by BIOS forever; LTR > messages sent from connected device will be ignored >=20 > + **/ >=20 > + PCIE_LTR_CONFIG PcieRpLtrConfig; ///< (Tes= t) > Latency Tolerance Reporting Policies including LTR limit and Override >=20 > + /** >=20 > + The number of milliseconds reference code will wait for link to exit= Detect > state for enabled ports >=20 > + before assuming there is no device and potentially disabling the por= t. >=20 > + It's assumed that the link will exit detect state before root port > initialization (sufficient time >=20 > + elapsed since PLTRST de-assertion) therefore default timeout is zero= . > However this might be useful >=20 > + if device power-up seqence is controlled by BIOS or a specific devic= e > requires more time to detect. >=20 > + In case of non-common clock enabled the default timout is 15ms. >=20 > + Default: 0 >=20 > + **/ >=20 > + UINT16 DetectTimeoutMs; >=20 > + UINT8 FormFactor; // Please check PCIE_FORM_FACTOR for supported > values >=20 > + UINT8 Reserved; >=20 > +} PCIE_ROOT_PORT_COMMON_CONFIG; >=20 > + >=20 > +/** >=20 > + PCIe Common Config >=20 > + @note This structure will be expanded to hold all common PCIe policies > between SA and PCH >=20 > +**/ >=20 > +typedef struct { >=20 > + /// >=20 > + /// This member describes whether Peer Memory Writes are enabled on > the platform. 0: Disable; 1: Enable. >=20 > + /// >=20 > + UINT32 EnablePeerMemoryWrite : 1; >=20 > + /** >=20 > + RpFunctionSwap allows BIOS to use root port function number swapping > when root port of function 0 is disabled. >=20 > + A PCIE device can have higher functions only when Function0 exists. = To > satisfy this requirement, >=20 > + BIOS will always enable Function0 of a device that contains more tha= n 0 > enabled root ports. >=20 > + - Enabled: One of enabled root ports get assigned to Function0. >=20 > + This offers no guarantee that any particular root port will be ava= ilable at a > specific DevNr:FuncNr location >=20 > + - Disabled: Root port that corresponds to Function0 will be kept vis= ible > even though it might be not used. >=20 > + That way rootport - to - DevNr:FuncNr assignment is constant. This > option will impact ports 1, 9, 17. >=20 > + NOTE: This option will not work if ports 1, 9, 17 are fused or con= figured > for RST PCIe storage or disabled through policy >=20 > + In other words, it only affects ports that would become hidd= en > because they have no device connected. >=20 > + NOTE: Disabling function swap may have adverse impact on power > management. This option should ONLY >=20 > + be used when each one of root ports 1, 9, 17: >=20 > + - is configured as PCIe and has correctly configured ClkReq sign= al, or >=20 > + - does not own any mPhy lanes (they are configured as SATA or US= B) >=20 > + **/ >=20 > + UINT32 RpFunctionSwap : 1; >=20 > + /** >=20 > + Compliance Test Mode shall be enabled when using Compliance Load > Board. >=20 > + 0: Disable, 1: Enable >=20 > + **/ >=20 > + UINT32 ComplianceTestMode : 1; >=20 > + UINT32 RsvdBits0 : 29; ///< Reserved bits >=20 > + /// >=20 > + /// List of coefficients used during equalization (applicable to both > software and hardware EQ) >=20 > + /// Deprecated Policy >=20 > + /// >=20 > + PCIE_EQ_PARAM > HwEqGen3CoeffList[PCIE_HWEQ_COEFFS_MAX]; >=20 > +} PCIE_COMMON_CONFIG; >=20 > + >=20 > + >=20 > +#pragma pack (pop) >=20 > +#endif // _PCIE_CONFIG_H_ >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Pmc/AdrConfig.h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Pmc/AdrConfig.h > new file mode 100644 > index 0000000000..5c7811823d > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Pmc/AdrConfig.h > @@ -0,0 +1,86 @@ > +/** @file >=20 > + ADR policy >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +#ifndef _ADR_CONFIG_H_ >=20 > +#define _ADR_CONFIG_H_ >=20 > + >=20 > +#include >=20 > + >=20 > +#define ADR_CONFIG_REVISION 1 >=20 > +extern EFI_GUID gAdrConfigGuid; >=20 > + >=20 > +#pragma pack (push,1) >=20 > + >=20 > +typedef enum { >=20 > + AdrScale1us, >=20 > + AdrScale10us, >=20 > + AdrScale100us, >=20 > + AdrScale1ms, >=20 > + AdrScale10ms, >=20 > + AdrScale100ms, >=20 > + AdrScale1s, >=20 > + AdrScale10s >=20 > +} ADR_TIMER_SCALE; >=20 > + >=20 > +/** >=20 > + ADR Source Enable >=20 > +**/ >=20 > +typedef union { >=20 > + struct { >=20 > + UINT32 Reserved1 : 1; >=20 > + UINT32 AdrSrcPbo : 1; >=20 > + UINT32 AdrSrcPmcUncErr : 1; >=20 > + UINT32 AdrSrcPchThrm : 1; >=20 > + UINT32 AdrSrcMePbo : 1; >=20 > + UINT32 AdrSrcCpuThrm : 1; >=20 > + UINT32 AdrSrcMegbl : 1; >=20 > + UINT32 AdrSrcLtReset : 1; >=20 > + UINT32 AdrSrcPmcWdt : 1; >=20 > + UINT32 AdrSrcMeWdt : 1; >=20 > + UINT32 AdrSrcPmcFw : 1; >=20 > + UINT32 AdrSrcPchpwrFlr : 1; >=20 > + UINT32 AdrSrcSyspwrFlr : 1; >=20 > + UINT32 Reserved2 : 1; >=20 > + UINT32 AdrSrcMiaUxsErr : 1; >=20 > + UINT32 AdrSrcMiaUxErr : 1; >=20 > + UINT32 AdrSrcCpuThrmWdt : 1; >=20 > + UINT32 AdrSrcMeUncErr : 1; >=20 > + UINT32 AdrSrcAdrGpio : 1; >=20 > + UINT32 AdrSrcOcwdtNoicc : 1; >=20 > + UINT32 AdrSrcOcwdtIcc : 1; >=20 > + UINT32 AdrSrcCseHecUncErr : 1; >=20 > + UINT32 AdrSrcPmcSramUncErr : 1; >=20 > + UINT32 AdrSrcPmcIromParity : 1; >=20 > + UINT32 AdrSrcPmcRfFusaErr : 1; >=20 > + UINT32 Reserved3 : 4; >=20 > + UINT32 AdrSrcPpbrParityErr : 1; >=20 > + UINT32 Reserved4 : 2; >=20 > + } Field; >=20 > + UINT32 Value; >=20 > +} ADR_SOURCE_ENABLE; >=20 > + >=20 > +/** >=20 > + ADR Configuration >=20 > + Revision 1: - Initial version. >=20 > +**/ >=20 > +typedef struct { >=20 > + CONFIG_BLOCK_HEADER Header; ///< Config Block Header >=20 > + UINT32 AdrEn : 2; ///< Determine if Adr is ena= bled - 0: > PLATFORM_POR, 1: FORCE_ENABLE, 2: FORCE_DISABLE >=20 > + UINT32 AdrTimerEn : 2; ///< Determine if Adr timer = options are > enabled - 0: PLATFORM_POR, 1: FORCE_ENABLE, 2: FORCE_DISABLE >=20 > + UINT32 AdrTimer1Val : 2; ///< Determines the Timeout = value used > for the ADR timer 1. A value of zero bypasses the timer >=20 > + UINT32 AdrMultiplier1Val : 8; ///< Specifies the tick freq= uency upon > which the timer 1 will increment. ADR_TIMER_SCALE should be used to > encode values >=20 > + UINT32 AdrTimer2Val : 8; ///< Determines the Timeout = value used > for the ADR timer 2. A value of zero bypasses the timer >=20 > + UINT32 AdrMultiplier2Val : 8; ///< Specifies the tick freq= uency upon > which the timer 2 will increment. ADR_TIMER_SCALE should be used to > encode values >=20 > + UINT32 AdrHostPartitionReset : 2; ///< Determine if Host Parti= tion > Reset is enabled - 0: PLATFORM_POR, 1: FORCE_ENABLE, 2: FORCE_DISABLE >=20 > + UINT32 AdrSrcOverride : 1; ///< Check if default ADR so= urces will be > overriten with custom 0: Not overwritten, 1: Overwritten >=20 > + UINT32 ReservedBits : 31; >=20 > + ADR_SOURCE_ENABLE AdrSrcSel; ///< Determine which ADR > sources are enabled - 0: Enabled, 1: Disabled >=20 > +} ADR_CONFIG; >=20 > + >=20 > +#pragma pack (pop) >=20 > + >=20 > +#endif // _ADR_CONFIG_H_ >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Pmc/PmConfig.h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Pmc/PmConfig.h > new file mode 100644 > index 0000000000..2f8e19b50b > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Pmc/PmConfig.h > @@ -0,0 +1,391 @@ > +/** @file >=20 > + Power Management policy >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _PM_CONFIG_H_ >=20 > +#define _PM_CONFIG_H_ >=20 > + >=20 > +#include >=20 > + >=20 > +#define PM_CONFIG_REVISION 2 >=20 > +extern EFI_GUID gPmConfigGuid; >=20 > + >=20 > +#pragma pack (push,1) >=20 > + >=20 > +/** >=20 > + This structure allows to customize PCH wake up capability from S5 or > DeepSx by WOL, LAN, PCIE wake events. >=20 > +**/ >=20 > +typedef struct { >=20 > + /** >=20 > + Corresponds to the PME_B0_S5_DIS bit in the General PM Configuration > B (GEN_PMCON_B) register. >=20 > + When set to 1, this bit blocks wake events from PME_B0_STS in S5, > regardless of the state of PME_B0_EN. >=20 > + When cleared (default), wake events from PME_B0_STS are allowed in S= 5 > if PME_B0_EN =3D 1. 0: Disable; 1: Enable. >=20 > + **/ >=20 > + UINT32 PmeB0S5Dis : 1; >=20 > + UINT32 WolEnableOverride : 1; ///< Corresponds to the "WOL Ena= ble > Override" bit in the General PM Configuration B (GEN_PMCON_B) register. > 0: Disable; 1: Enable. >=20 > + UINT32 PcieWakeFromDeepSx : 1; ///< Determine if enable PCIe to > wake from deep Sx. 0: Disable; 1: Enable. >=20 > + UINT32 WoWlanEnable : 1; ///< Determine if WLAN wake from= Sx, > corresponds to the "HOST_WLAN_PP_EN" bit in the PWRM_CFG3 register. > 0: Disable; 1: Enable. >=20 > + UINT32 WoWlanDeepSxEnable : 1; ///< Determine if WLAN wake from > DeepSx, corresponds to the "DSX_WLAN_PP_EN" bit in the PWRM_CFG3 > register. 0: Disable; 1: Enable. >=20 > + UINT32 LanWakeFromDeepSx : 1; ///< Determine if enable LAN to > wake from deep Sx. 0: Disable; 1: Enable. >=20 > + UINT32 RsvdBits0 : 26; >=20 > +} PCH_WAKE_CONFIG; >=20 > + >=20 > +typedef enum { >=20 > + PchDeepSxPolDisable, >=20 > + PchDpS5BatteryEn, >=20 > + PchDpS5AlwaysEn, >=20 > + PchDpS4S5BatteryEn, >=20 > + PchDpS4S5AlwaysEn, >=20 > + PchDpS3S4S5BatteryEn, >=20 > + PchDpS3S4S5AlwaysEn >=20 > +} PCH_DEEP_SX_CONFIG; >=20 > + >=20 > +typedef enum { >=20 > + PchSlpS360us =3D 1, >=20 > + PchSlpS31ms, >=20 > + PchSlpS350ms, >=20 > + PchSlpS32s >=20 > +} PCH_SLP_S3_MIN_ASSERT; >=20 > + >=20 > +typedef enum { >=20 > + PchSlpS4PchTime, ///< The time defined in PCH EDS Power Sequencing > and Reset Signal Timings table >=20 > + PchSlpS41s, >=20 > + PchSlpS42s, >=20 > + PchSlpS43s, >=20 > + PchSlpS44s >=20 > +} PCH_SLP_S4_MIN_ASSERT; >=20 > + >=20 > +typedef enum { >=20 > + PchSlpSus0ms =3D 1, >=20 > + PchSlpSus500ms, >=20 > + PchSlpSus1s, >=20 > + PchSlpSus4s, >=20 > +} PCH_SLP_SUS_MIN_ASSERT; >=20 > + >=20 > +typedef enum { >=20 > + PchSlpA0ms =3D 1, >=20 > + PchSlpA4s, >=20 > + PchSlpA98ms, >=20 > + PchSlpA2s, >=20 > +} PCH_SLP_A_MIN_ASSERT; >=20 > + >=20 > +typedef enum { >=20 > + S0ixDisQNoChange, >=20 > + S0ixDisQDciOob, >=20 > + S0ixDisQUsb2Dbc, >=20 > + S0ixDisQMax, >=20 > +} S0IX_DISQ_PROBE_TYPE; >=20 > + >=20 > +/** >=20 > + Low Power Mode Enable config. >=20 > + Used to configure if respective S0i2/3 sub-states are to be supported >=20 > + by the platform. Each bit corresponds to one LPM state - LPMx->BITx. >=20 > + Some sub-states will require external FETs controlled by > EXT_PWR_GATE#/EXT_PWR_GATE2# pins >=20 > + to gate v1p05-PHY or v1p05-IS supplies >=20 > +**/ >=20 > +typedef union { >=20 > + struct { >=20 > + UINT32 S0i2p0En : 1; ///< LPM0 - S0i2.0 Enable >=20 > + UINT32 S0i2p1En : 1; ///< LPM1 - S0i2.1 Enable >=20 > + /** >=20 > + LPM2 - S0i2.2 Enable. >=20 > + Requires EXT_PWR_GATE# controlled FET to gate v1p05 PHY. >=20 > + Refer to V1p05PhyExtFetControlEn. >=20 > + **/ >=20 > + UINT32 S0i2p2En : 1; >=20 > + UINT32 S0i3p0En : 1; ///< LPM3 - S0i3.0 Enable >=20 > + UINT32 S0i3p1En : 1; ///< LPM4 - S0i3.1 Enable >=20 > + UINT32 S0i3p2En : 1; ///< LPM5 - S0i3.2 Enable >=20 > + /** >=20 > + LPM5 - S0i3.3 Enable. >=20 > + Requires EXT_PWR_GATE# controlled FET to gate v1p05 PHY. >=20 > + Refer to V1p05PhyExtFetControlEn. >=20 > + **/ >=20 > + UINT32 S0i3p3En : 1; >=20 > + /** >=20 > + LPM7 - S0i3.4 Enable. >=20 > + Requires EXT_PWR_GATE2# controlled FET to gate v1p05-SRAM/ISCLK. >=20 > + Refer to V1p05IsExtFetControlEn. >=20 > + **/ >=20 > + UINT32 S0i3p4En : 1; >=20 > + UINT32 Reserved : 24; ///< Reserved >=20 > + } Field; >=20 > + UINT32 Val; >=20 > +} PMC_LPM_S0IX_SUB_STATE_EN; >=20 > + >=20 > +/** >=20 > + Description of Global Reset Trigger/Event Mask register >=20 > +**/ >=20 > +typedef union { >=20 > + struct { >=20 > + UINT32 Reserved1 : 1; >=20 > + UINT32 Pbo : 1; >=20 > + UINT32 PmcUncErr : 1; >=20 > + UINT32 PchThrm : 1; >=20 > + UINT32 MePbo : 1; >=20 > + UINT32 CpuThrm : 1; >=20 > + UINT32 Megbl : 1; >=20 > + UINT32 LtReset : 1; >=20 > + UINT32 PmcWdt : 1; >=20 > + UINT32 MeWdt : 1; >=20 > + UINT32 PmcFw : 1; >=20 > + UINT32 PchpwrFlr : 1; >=20 > + UINT32 SyspwrFlr : 1; >=20 > + UINT32 Reserved2 : 1; >=20 > + UINT32 MiaUxsErr : 1; >=20 > + UINT32 MiaUxErr : 1; >=20 > + UINT32 CpuThrmWdt : 1; >=20 > + UINT32 MeUncErr : 1; >=20 > + UINT32 AdrGpio : 1; >=20 > + UINT32 OcwdtNoicc : 1; >=20 > + UINT32 OcwdtIcc : 1; >=20 > + UINT32 CseHecUncErr : 1; >=20 > + UINT32 PmcSramUncErr : 1; >=20 > + UINT32 PmcIromParity : 1; >=20 > + UINT32 PmcRfFusaErr : 1; >=20 > + UINT32 Reserved3 : 4; >=20 > + UINT32 PpbrParityErr : 1; >=20 > + UINT32 Reserved4 : 2; >=20 > + } Field; >=20 > + UINT32 Value; >=20 > +} PMC_GLOBAL_RESET_MASK; >=20 > + >=20 > +/** >=20 > + The PCH_PM_CONFIG block describes expected miscellaneous power > management settings. >=20 > + The PowerResetStatusClear field would clear the Power/Reset status bit= s, > please >=20 > + set the bits if you want PCH Init driver to clear it, if you want to c= heck the >=20 > + status later then clear the bits. >=20 > + >=20 > + Revision 1: >=20 > + - Initial version. >=20 > + Revision 2 >=20 > + - Added C10DynamicThresholdAdjustment >=20 > +**/ >=20 > +typedef struct { >=20 > + CONFIG_BLOCK_HEADER Header; ///< Config = Block Header >=20 > + >=20 > + PCH_WAKE_CONFIG WakeConfig; ///< Specify= Wake Policy >=20 > + UINT32 PchDeepSxPol : 4; ///< Deep Sx= Policy. Refer to > PCH_DEEP_SX_CONFIG for each value. Default is > PchDeepSxPolDisable. >=20 > + UINT32 PchSlpS3MinAssert : 4; ///< SLP_S3 = Minimum > Assertion Width Policy. Refer to PCH_SLP_S3_MIN_ASSERT for each value. > Default is PchSlpS350ms. >=20 > + UINT32 PchSlpS4MinAssert : 4; ///< SLP_S4 = Minimum > Assertion Width Policy. Refer to PCH_SLP_S4_MIN_ASSERT for each value. > Default is PchSlpS44s. >=20 > + UINT32 PchSlpSusMinAssert : 4; ///< SLP_SUS= Minimum > Assertion Width Policy. Refer to PCH_SLP_SUS_MIN_ASSERT for each value. > Default is PchSlpSus4s. >=20 > + UINT32 PchSlpAMinAssert : 4; ///< SLP_A M= inimum > Assertion Width Policy. Refer to PCH_SLP_A_MIN_ASSERT for each value. > Default is PchSlpA2s. >=20 > + UINT32 RsvdBits0 : 12; >=20 > + /** >=20 > + This member describes whether or not the LPC ClockRun feature of PCH > should >=20 > + be enabled. 0: Disable; 1: Enable >=20 > + **/ >=20 > + UINT32 SlpStrchSusUp : 1; ///< 0: D= isable; 1: > Enable SLP_X Stretching After SUS Well Power Up >=20 > + /** >=20 > + Enable/Disable SLP_LAN# Low on DC Power. 0: Disable; 1: > Enable. >=20 > + Configure On DC PHY Power Diable according to policy SlpLanLowDc. >=20 > + When this is enabled, SLP_LAN# will be driven low when ACPRESENT is > low. >=20 > + This indicates that LAN PHY should be powered off on battery mode. >=20 > + This will override the DC_PP_DIS setting by WolEnableOverride. >=20 > + **/ >=20 > + UINT32 SlpLanLowDc : 1; >=20 > + /** >=20 > + PCH power button override period. >=20 > + 000b-4s, 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s >=20 > + Default is 0: 4s >=20 > + **/ >=20 > + UINT32 PwrBtnOverridePeriod : 3; >=20 > + /** >=20 > + (Test) >=20 > + Disable/Enable PCH to CPU enery report feature. 0: Disable; 1= : > Enable. >=20 > + Enery Report is must have feature. Wihtout Energy Report, the > performance report >=20 > + by workloads/benchmarks will be unrealistic because PCH's energy is = not > being accounted >=20 > + in power/performance management algorithm. >=20 > + If for some reason PCH energy report is too high, which forces CPU t= o try > to reduce >=20 > + its power by throttling, then it could try to disable Energy Report = to do > first debug. >=20 > + This might be due to energy scaling factors are not correct or the L= PM > settings are not >=20 > + kicking in. >=20 > + **/ >=20 > + UINT32 DisableEnergyReport : 1; >=20 > + /** >=20 > + When set to Disable, PCH will internal pull down AC_PRESENT in deep = SX > and during G3 exit. >=20 > + When set to Enable, PCH will not pull down AC_PRESENT. >=20 > + This setting is ignored when DeepSx is not supported. >=20 > + Default is 0:Disable >=20 > + **/ >=20 > + UINT32 DisableDsxAcPresentPulldown : 1; >=20 > + /** >=20 > + Power button native mode disable. >=20 > + While FALSE, the PMC's power button logic will act upon the input va= lue > from the GPIO unit, as normal. >=20 > + While TRUE, this will result in the PMC logic constantly seeing the = power > button as de-asserted. >=20 > + Default is FALSE. >=20 > + **/ >=20 > + UINT32 DisableNativePowerButton : 1; >=20 > + UINT32 MeWakeSts : 1; ///< Cl= ear the ME_WAKE_STS > bit in the Power and Reset Status (PRSTS) register. 0: Disable; 1: > Enable. >=20 > + UINT32 WolOvrWkSts : 1; ///< Cl= ear the > WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register. 0: > Disable; 1: Enable. >=20 > + /* >=20 > + Set true to enable TCO timer. >=20 > + When FALSE, it disables PCH ACPI timer, and stops TCO timer. >=20 > + @note: This will have significant power impact when it's enabled. >=20 > + If TCO timer is disabled, uCode ACPI timer emulation must be enabled= , >=20 > + and WDAT table must not be exposed to the OS. >=20 > + 0: Disable, 1: Enable >=20 > + */ >=20 > + UINT32 EnableTcoTimer : 1; >=20 > + /* >=20 > + When VRAlert# feature pin is enabled and its state is '0', >=20 > + the PMC requests throttling to a T3 Tstate to the PCH throttling uni= t. >=20 > + 0: Disable; 1: Enable. >=20 > + */ >=20 > + UINT32 VrAlert : 1; >=20 > + /** >=20 > + Decide if PS_ON is to be enabled. This is available on desktop only. >=20 > + PS_ON is a new C10 state from the CPU on desktop SKUs that enables a >=20 > + lower power target that will be required by the California Energy >=20 > + Commission (CEC). When FALSE, PS_ON is to be disabled.} >=20 > + 0: Disable; 1: Enable. >=20 > + **/ >=20 > + UINT32 PsOnEnable : 1; >=20 > + /** >=20 > + Enable/Disable platform support for CPU_C10_GATE# pin to control > gating >=20 > + of CPU VccIO and VccSTG rails instead of SLP_S0# pin. This policy ne= eds >=20 > + to be set if board design includes support for CPU_C10_GATE# pin. >=20 > + 0: Disable; 1: Enable >=20 > + **/ >=20 > + UINT32 CpuC10GatePinEnable : 1; >=20 > + /** >=20 > + Control whether to enable PMC debug messages to Trace Hub. >=20 > + When Enabled, PMC HW will send debug messages to trace hub; >=20 > + When Disabled, PMC HW will never send debug meesages to trace hub. >=20 > + @note: When enabled, system may not enter S0ix >=20 > + 0: Disable; 1: Enable. >=20 > + **/ >=20 > + UINT32 PmcDbgMsgEn : 1; >=20 > + /** >=20 > + Enable/Disable ModPHY SUS Power Domain Dynamic Gating. >=20 > + EXT_PWR_GATE# signal (if supported on platform) can be used to >=20 > + control external FET for power gating ModPHY >=20 > + @note: This setting is not supported and ignored on PCH-H >=20 > + 0: Disable; 1: Enable. >=20 > + **/ >=20 > + UINT32 ModPhySusPgEnable : 1; >=20 > + /** >=20 > + (Test) >=20 > + This policy option enables USB2 PHY SUS Well Power Gating functional= ity. >=20 > + @note: This setting is not supported and ignored on PCH-H >=20 > + 0: disable USB2 PHY SUS Well Power Gating >=20 > + 1: enable USB2 PHY SUS Well Power Gating >=20 > + **/ >=20 > + UINT32 Usb2PhySusPgEnable : 1; >=20 > + /** >=20 > + Enable Os Idle Mode. >=20 > + 0: Disable; 1: Enable. >=20 > + **/ >=20 > + UINT32 OsIdleEnable : 1; >=20 > + /** >=20 > + Enable control using EXT_PWR_GATE# pin of external FET >=20 > + to power gate v1p05-PHY >=20 > + 0: Disable; 1: Enable. >=20 > + **/ >=20 > + UINT32 V1p05PhyExtFetControlEn : 1; >=20 > + /** >=20 > + Enable control using EXT_PWR_GATE2# pin of external FET >=20 > + to power gate v1p05-IS supply >=20 > + 0: Disable; 1: Enable. >=20 > + **/ >=20 > + UINT32 V1p05IsExtFetControlEn : 1; >=20 > + /** >=20 > + Enable/Disable the Low Power Mode Host S0ix Auto-Demotion >=20 > + feature. This feature enables the PMC to autonomously manage >=20 > + the deepest allowed S0ix substate to combat thrashing between >=20 > + power management states. >=20 > + 0: Disable; 1: Enable. >=20 > + **/ >=20 > + UINT32 S0ixAutoDemotion : 1; >=20 > + /** >=20 > + Enable/Disable Latch Events C10 Exit. When this bit is set to 1, >=20 > + SLP_S0# entry events in SLP_S0_DEBUG_REGx registers are captured >=20 > + on C10 exit (instead of C10 entry which is default) >=20 > + 0: Disable; 1: Enable. >=20 > + **/ >=20 > + UINT32 LatchEventsC10Exit : 1; >=20 > + UINT32 RsvdBits1 : 10; >=20 > + /* >=20 > + Power button debounce configuration >=20 > + Debounce time can be specified in microseconds. Only certain values > according >=20 > + to below formula are supported: >=20 > + DebounceTime =3D (2 ^ PADCFG_DW2.DEBOUNCE)*(glitch filter clock > period). >=20 > + RTC clock with f =3D 32 KHz is used for glitch filter. >=20 > + DebounceTime =3D (2 ^ PADCFG_DW2.DEBOUNCE)*(31.25 us). >=20 > + Supported DebounceTime values are following: >=20 > + DebounceTime =3D 0 -> Debounce feature disabled >=20 > + DebounceTime > 0 && < 250us -> Not supported >=20 > + DebounceTime =3D 250us - 1024000us -> Supported range (DebounceTime > =3D 250us * 2^n) >=20 > + For values not supported by HW, they will be rounded down to closest > supported one >=20 > + Default is 0 >=20 > + */ >=20 > + UINT32 PowerButtonDebounce; >=20 > + /** >=20 > + Reset Power Cycle Duration could be customized in the unit of second= . > Please refer to EDS >=20 > + for all support settings. PCH HW default is 4 seconds, and range is = 1~4 > seconds, where >=20 > + 0 is default, 1 is 1 second, 2 is 2 seconds, ... 4 is 4 secon= ds. >=20 > + And make sure the setting correct, which never less than the followi= ng > register. >=20 > + - GEN_PMCON_B.SLP_S3_MIN_ASST_WDTH >=20 > + - GEN_PMCON_B.SLP_S4_MIN_ASST_WDTH >=20 > + - PWRM_CFG.SLP_A_MIN_ASST_WDTH >=20 > + - PWRM_CFG.SLP_LAN_MIN_ASST_WDTH >=20 > + **/ >=20 > + UINT8 PchPwrCycDur; >=20 > + /** >=20 > + Specifies the Pcie Pll Spread Spectrum Percentage >=20 > + The value of this policy is in 1/10th percent units. >=20 > + Valid spread range is 0-20. A value of 0xFF is reserved for AUTO. >=20 > + A value of 0 is SSC of 0.0%. A value of 20 is SSC of 2.0% >=20 > + The default is 0xFF: AUTO - No BIOS override. >=20 > + **/ >=20 > + UINT8 PciePllSsc; >=20 > + /** >=20 > + Tells BIOS to enable C10 dynamic threshold adjustment mode. >=20 > + BIOS will only attemt to enable it on PCH SKUs which support it. >=20 > + **/ >=20 > + UINT8 C10DynamicThresholdAdjustment; >=20 > + UINT8 Rsvd0[1]; ///< Res= erved bytes >=20 > + /** >=20 > + (Test) >=20 > + Low Power Mode Enable/Disable config. >=20 > + Configure if respective S0i2/3 sub-states are to be supported >=20 > + by the platform. By default all sub-states are enabled but >=20 > + for test purpose respective states can be disabled. >=20 > + Default is 0xFF >=20 > + **/ >=20 > + PMC_LPM_S0IX_SUB_STATE_EN LpmS0ixSubStateEnable; >=20 > + /* >=20 > + Set true to enable Timed GPIO 0 timer. >=20 > + 0: Disable, 1: Enable >=20 > + */ >=20 > + UINT32 EnableTimedGpio0 : 1; >=20 > + /* >=20 > + Set true to enable Timed GPIO 1 timer. >=20 > + 0: Disable, 1: Enable >=20 > + */ >=20 > + UINT32 EnableTimedGpio1 : 1; >=20 > + UINT32 Rsvdbits : 30; >=20 > + >=20 > + /** >=20 > + Set true to enable override of Global Reset Event/Trigger masks. >=20 > + Values from GlobalResetTriggerMask and GlobalResetEventMask will >=20 > + be used as override value. >=20 > + 0: Disable, 1: Enable >=20 > + **/ >=20 > + UINT8 GlobalResetMasksOverride; >=20 > + UINT8 Rsvd1[3]; ///< Reserved bytes >=20 > + /* >=20 > + Mask for enabling Global Reset Trigger prevention >=20 > + */ >=20 > + PMC_GLOBAL_RESET_MASK GlobalResetTriggerMask; >=20 > + /* >=20 > + Mask for enabling Global Reset Event prevention >=20 > + */ >=20 > + PMC_GLOBAL_RESET_MASK GlobalResetEventMask; >=20 > +} PCH_PM_CONFIG; >=20 > + >=20 > +#pragma pack (pop) >=20 > + >=20 > +#endif // _PM_CONFIG_H_ >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Psf/PsfConfig.h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Psf/PsfConfig.h > new file mode 100644 > index 0000000000..033e416b83 > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Psf/PsfConfig= .h > @@ -0,0 +1,32 @@ > +/** @file >=20 > + Primary Sideband Fabric policy. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +#ifndef _PSF_CONFIG_H_ >=20 > +#define _PSF_CONFIG_H_ >=20 > + >=20 > +#define PSF_CONFIG_REVISION 1 >=20 > +extern EFI_GUID gPsfConfigGuid; >=20 > + >=20 > +#pragma pack (push,1) >=20 > + >=20 > +/** >=20 > + The PSF_CONFIG block describes the expected configuration of the > Primary >=20 > + Sideband Fabric. >=20 > +**/ >=20 > +typedef struct { >=20 > + CONFIG_BLOCK_HEADER Header; ///< Config Block Header >=20 > + /** >=20 > + Psf Tcc (Time Coordinated Computing) Enable will decrease psf > transaction latency by disable >=20 > + some psf power management features. 0: Disable; 1: Enable. >=20 > + **/ >=20 > + UINT32 TccEnable : 1; >=20 > + UINT32 RsvdBits0 : 31; ///< Reserved bits >=20 > +} PSF_CONFIG; >=20 > + >=20 > +#pragma pack (pop) >=20 > + >=20 > +#endif // _PSF_CONFIG_H_ >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Rst/RstConfig.h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Rst/RstConfig.h > new file mode 100644 > index 0000000000..469d46a205 > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Rst/RstConfig= .h > @@ -0,0 +1,82 @@ > +/** @file >=20 > + Rst policy >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _RST_CONFIG_H_ >=20 > +#define _RST_CONFIG_H_ >=20 > +#include >=20 > +#include >=20 > + >=20 > +#define RST_CONFIG_REVISION 1 >=20 > +extern EFI_GUID gRstConfigGuid; >=20 > + >=20 > +#pragma pack (push,1) >=20 > + >=20 > +typedef enum { >=20 > + SataOromDelay2sec, >=20 > + SataOromDelay4sec, >=20 > + SataOromDelay6sec, >=20 > + SataOromDelay8sec >=20 > +} SATA_OROM_DELAY; >=20 > + >=20 > +/** >=20 > + This structure describes the details of Intel RST for PCIe Storage rem= apping >=20 > + Note: In order to use this feature, Intel RST Driver is required >=20 > +**/ >=20 > +typedef struct { >=20 > + /** >=20 > + This member describes whether or not the Intel RST for PCIe Storage > remapping should be enabled. 0: Disable; 1: Enable. >=20 > + Note 1: If Sata Controller is disabled, PCIe Storage Remapping shoul= d be > disabled as well >=20 > + Note 2: If PCIe Storage remapping is enabled, the PCH integrated AHC= I > controllers Class Code is configured as RAID >=20 > + **/ >=20 > + UINT32 Enable : 1; >=20 > + /** >=20 > + Intel RST for PCIe Storage remapping - PCIe Port Selection (1-based,= 0 > =3D autodetect) >=20 > + The supported ports for PCIe Storage remapping is different depend o= n > the platform and cycle router >=20 > + **/ >=20 > + UINT32 RstPcieStoragePort : 5; >=20 > + /** >=20 > + PCIe Storage Device Reset Delay in milliseconds (ms), which it guara= ntees > such delay gap is fulfilled >=20 > + before PCIe Storage Device configuration space is accessed after an = reset > caused by the link disable and enable step. >=20 > + Default value is 100ms. >=20 > + **/ >=20 > + UINT32 DeviceResetDelay : 8; >=20 > + UINT32 RsvdBits0 : 18; ///< Reserved bits >=20 > + >=20 > +} RST_HARDWARE_REMAPPED_STORAGE_CONFIG; >=20 > + >=20 > +/** >=20 > + Rapid Storage Technology settings. >=20 > + >=20 > + Revision 1: >=20 > + - Initial version. >=20 > +**/ >=20 > +typedef struct { >=20 > + CONFIG_BLOCK_HEADER Header; ///< Config = Block Header >=20 > + >=20 > + UINT32 Raid0 : 1; ///< 0 : Disable; 1 : En= able RAID0 >=20 > + UINT32 Raid1 : 1; ///< 0 : Disable; 1 : En= able RAID1 >=20 > + UINT32 Raid10 : 1; ///< 0 : Disable; 1 : En= able RAID10 >=20 > + UINT32 Raid5 : 1; ///< 0 : Disable; 1 : En= able RAID5 >=20 > + UINT32 Irrt : 1; ///< 0 : Disable; 1 : En= able Intel Rapid > Recovery Technology >=20 > + UINT32 OromUiBanner : 1; ///< 0 : Disable; 1 : En= able > OROM UI and BANNER >=20 > + UINT32 OromUiDelay : 2; ///< 00b : 2 secs; 01= b : 4 secs; > 10b : 6 secs; 11 : 8 secs (see : SATA_OROM_DELAY) >=20 > + UINT32 HddUnlock : 1; ///< 0 : Disable; 1 : En= able. > Indicates that the HDD password unlock in the OS is enabled >=20 > + UINT32 LedLocate : 1; ///< 0 : Disable; 1 : En= able. > Indicates that the LED/SGPIO hardware is attached and ping to locate feat= ure > is enabled on the OS >=20 > + UINT32 IrrtOnly : 1; ///< 0 : Disable; 1 : En= able. Allow > only IRRT drives to span internal and external ports >=20 > + UINT32 SmartStorage : 1; ///< 0 : Disable; 1 : En= able RST > Smart Storage caching Bit >=20 > + UINT32 LegacyOrom : 1; ///< 0 : Disable; 1 = : Enable RST > Legacy OROM >=20 > + UINT32 OptaneMemory : 1; ///< 0: Disable; 1: Enable= RST > Optane(TM) Memory >=20 > + UINT32 CpuAttachedStorage : 1; ///< 0: Disable; 1: Enable= > CPU Attached Storage >=20 > + UINT32 RsvdBits0 : 17; ///< Reserved Bits >=20 > + /** >=20 > + This member describes the details of implementation of Intel RST for= PCIe > Storage remapping (Intel RST Driver is required) >=20 > + Note: RST for PCIe Sorage remapping is supported only for first SATA > controller if more controllers are available >=20 > + **/ >=20 > + RST_HARDWARE_REMAPPED_STORAGE_CONFIG > HardwareRemappedStorageConfig[PCH_MAX_RST_PCIE_STORAGE_CR]; >=20 > +} RST_CONFIG; >=20 > + >=20 > +#pragma pack (pop) >=20 > +#endif >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Rtc/RtcConfig.h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Rtc/RtcConfig.h > new file mode 100644 > index 0000000000..1f354c10ae > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Rtc/RtcConfig= .h > @@ -0,0 +1,38 @@ > +/** @file >=20 > + RTC policy >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _RTC_CONFIG_H_ >=20 > +#define _RTC_CONFIG_H_ >=20 > + >=20 > +#define RTC_CONFIG_REVISION 1 >=20 > +extern EFI_GUID gRtcConfigGuid; >=20 > + >=20 > +#pragma pack (push,1) >=20 > + >=20 > +/** >=20 > + The RTC_CONFIG block describes the expected configuration of RTC > configuration. >=20 > +**/ >=20 > +typedef struct { >=20 > + CONFIG_BLOCK_HEADER Header; ///< Config Block Header >=20 > + /** >=20 > + When set, prevents RTC TS (BUC.TS) from being changed. >=20 > + This BILD bit has different function compared to LPC/eSPI, SPI. >=20 > + 0: Disabled; 1: Enabled >=20 > + **/ >=20 > + UINT32 BiosInterfaceLock : 1; >=20 > + /** >=20 > + When set, bytes 38h-3Fh in the upper 128bytes bank of RTC RAM are > locked >=20 > + and cannot be accessed. >=20 > + Writes will be droipped and reads will not return any guaranteed dat= a. >=20 > + 0: Disabled; 1: Enabled >=20 > + **/ >=20 > + UINT32 MemoryLock : 1; >=20 > + UINT32 RsvdBits0 : 30; >=20 > +} RTC_CONFIG; >=20 > + >=20 > +#pragma pack (pop) >=20 > + >=20 > +#endif // _RTC_CONFIG_H_ >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Sata/SataConfig.h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Sata/SataConfig.h > new file mode 100644 > index 0000000000..c560fdd3ab > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Sata/SataConfig.h > @@ -0,0 +1,168 @@ > +/** @file >=20 > + Sata policy >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _SATA_CONFIG_H_ >=20 > +#define _SATA_CONFIG_H_ >=20 > + >=20 > +#include >=20 > + >=20 > +#define SATA_CONFIG_REVISION 1 >=20 > +extern EFI_GUID gSataConfigGuid; >=20 > + >=20 > +#pragma pack (push,1) >=20 > + >=20 > +typedef enum { >=20 > + SataModeAhci, >=20 > + SataModeRaid, >=20 > + SataModeMax >=20 > +} SATA_MODE; >=20 > + >=20 > +typedef enum { >=20 > + SataSpeedDefault, >=20 > + SataSpeedGen1, >=20 > + SataSpeedGen2, >=20 > + SataSpeedGen3 >=20 > +} SATA_SPEED; >=20 > + >=20 > +typedef enum { >=20 > + SataRstMsix, >=20 > + SataRstMsi, >=20 > + SataRstLegacy >=20 > +} SATA_RST_INTERRUPT; >=20 > + >=20 > +typedef enum { >=20 > + SataRaidClient, >=20 > + SataRaidAlternate, >=20 > + SataRaidServer >=20 > +} SATA_RAID_DEV_ID; >=20 > + >=20 > +/** >=20 > + This structure configures the features, property, and capability for e= ach > SATA port. >=20 > +**/ >=20 > +typedef struct { >=20 > + /** >=20 > + Enable SATA port. >=20 > + It is highly recommended to disable unused ports for power savings >=20 > + **/ >=20 > + UINT32 Enable : 1; ///< 0: Disable; 1:= Enable >=20 > + UINT32 HotPlug : 1; ///< 0: Disable= ; 1: Enable >=20 > + UINT32 InterlockSw : 1; ///< 0: Disable= ; 1: Enable >=20 > + UINT32 External : 1; ///< 0: Disable= ; 1: Enable >=20 > + UINT32 SpinUp : 1; ///< 0: Disable= ; 1: Enable the > COMRESET initialization Sequence to the device >=20 > + UINT32 SolidStateDrive : 1; ///< 0: HDD; 1:= SSD >=20 > + UINT32 DevSlp : 1; ///< 0: Disable= ; 1: Enable DEVSLP > on the port >=20 > + UINT32 EnableDitoConfig : 1; ///< 0: Disable= ; 1: Enable > DEVSLP Idle Timeout settings (DmVal, DitoVal) >=20 > + UINT32 DmVal : 4; ///< DITO multiplier. = Default is > 15. >=20 > + UINT32 DitoVal : 10; ///< DEVSLP Idle Timeo= ut (DITO), Default > is 625. >=20 > + /** >=20 > + Support zero power ODD 0: Disable, 1: Enable. >=20 > + This is also used to disable ModPHY dynamic power gate. >=20 > + **/ >=20 > + UINT32 ZpOdd : 1; >=20 > + UINT32 DevSlpResetConfig : 4; ///< 0: Hardware defau= lt; 0x01: > GpioResumeReset; 0x03: GpioHostDeepReset; 0x05: > GpioPlatformReset; 0x07: GpioDswReset >=20 > + UINT32 SataPmPtm : 1; ///< Deprecated >=20 > + UINT32 RxPolarity : 1; ///< 0: Disable= ; 1: Enable; Rx > Polarity >=20 > + UINT32 RsvdBits0 : 3; ///< Reserved fields f= or future > expansion w/o protocol change >=20 > +} PCH_SATA_PORT_CONFIG; >=20 > + >=20 > +/** >=20 > + This structure lists PCH supported SATA thermal throttling register se= tting > for customization. >=20 > + The settings is programmed through SATA Index/Data registers. >=20 > + When the SuggestedSetting is enabled, the customized values are ignore= d. >=20 > +**/ >=20 > +typedef struct { >=20 > + UINT32 P0T1M : 2; ///< Port 0 T1 Multipler >=20 > + UINT32 P0T2M : 2; ///< Port 0 T2 Multipler >=20 > + UINT32 P0T3M : 2; ///< Port 0 T3 Multipler >=20 > + UINT32 P0TDisp : 2; ///< Port 0 Tdispatch >=20 > + >=20 > + UINT32 P1T1M : 2; ///< Port 1 T1 Multipler >=20 > + UINT32 P1T2M : 2; ///< Port 1 T2 Multipler >=20 > + UINT32 P1T3M : 2; ///< Port 1 T3 Multipler >=20 > + UINT32 P1TDisp : 2; ///< Port 1 Tdispatch >=20 > + >=20 > + UINT32 P0Tinact : 2; ///< Port 0 Tinactive >=20 > + UINT32 P0TDispFinit : 1; ///< Port 0 Alternate Fast Init = Tdispatch >=20 > + UINT32 P1Tinact : 2; ///< Port 1 Tinactive >=20 > + UINT32 P1TDispFinit : 1; ///< Port 1 Alternate Fast Init = Tdispatch >=20 > + UINT32 SuggestedSetting : 1; ///< 0: Disable; 1: Enable > suggested representative values >=20 > + UINT32 RsvdBits0 : 9; ///< Reserved bits >=20 > +} SATA_THERMAL_THROTTLING; >=20 > + >=20 > +/** >=20 > + The SATA_CONFIG block describes the expected configuration of the > SATA controllers. >=20 > + >=20 > + Revision 1: >=20 > + - Initial version. >=20 > +**/ >=20 > +typedef struct { >=20 > + CONFIG_BLOCK_HEADER Header; ///< Config = Block Header >=20 > + /// >=20 > + /// This member describes whether or not the SATA controllers should b= e > enabled. 0: Disable; 1: Enable. >=20 > + /// >=20 > + UINT8 Enable; >=20 > + UINT8 TestMode; ///< (Test) 0:= Disable; 1: > Allow entrance to the PCH SATA test modes >=20 > + UINT8 SalpSupport; ///< 0: Disable; 1: E= nable > Aggressive Link Power Management >=20 > + UINT8 PwrOptEnable; ///< 0: Disable; 1: E= nable SATA > Power Optimizer on PCH side. >=20 > + /** >=20 > + EsataSpeedLimit >=20 > + When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the e= SATA > port speed. >=20 > + Please be noted, this setting could be cleared by HBA reset, which m= ight > be issued >=20 > + by EFI AHCI driver when POST time, or by SATA inbox driver/RST drive= r > after POST. >=20 > + To support the Speed Limitation when POST, the EFI AHCI driver shoul= d > preserve the >=20 > + setting before and after initialization. For support it after POST, = it's > dependent on >=20 > + driver's behavior. >=20 > + 0: Disable; 1: Enable >=20 > + **/ >=20 > + UINT8 EsataSpeedLimit; >=20 > + UINT8 LedEnable; ///< SATA LED indicates= SATA controller > activity. 0: Disable; 1: Enable SATA LED. >=20 > + /** >=20 > + This option allows to configure SATA controller device ID while in R= AID > mode. >=20 > + Refer to SATA_RAID_DEV_ID enumeration for supported options. >=20 > + Choosing Client will allow RST driver loading, RSTe driver will not = be able to > load >=20 > + Choosing Alternate will not allow RST inbox driver loading in Window= s >=20 > + Choosing Server will allow RSTe driver loading, RST driver will not = load >=20 > + 0: Client; 1: Alternate; 2: Server >=20 > + **/ >=20 > + UINT8 RaidDeviceId; >=20 > + /** >=20 > + Controlls which interrupts will be linked to SATA controller CAP lis= t >=20 > + This option will take effect only if SATA controller is in RAID mode >=20 > + Default: PchSataMsix >=20 > + **/ >=20 > + UINT8 SataRstInterrupt; >=20 > + >=20 > + /** >=20 > + Determines the system will be configured to which SATA mode. >=20 > + Refer to SATA_MODE enumeration for supported options. Default is > SataModeAhci. >=20 > + **/ >=20 > + UINT8 SataMode; >=20 > + /** >=20 > + Indicates the maximum speed the SATA controller can support. >=20 > + Refer to SATA_SPEED enumeration for supported options. >=20 > + 0h: SataSpeedDefault; 1h: 1.5 Gb/s (Gen 1); 2h: 3 Gb/s(Gen 2)= ; > 3h: 6 Gb/s (Gen 1) >=20 > + **/ >=20 > + UINT8 SpeedLimit; >=20 > + UINT8 EnclosureSupport; ///< Enclosure Manag= ement > Support. 0: Disable; 1: Enable >=20 > + /** >=20 > + Controlls whenever Serial GPIO support is enabled for controller >=20 > + 0: Disable; 1: Enable >=20 > + **/ >=20 > + UINT8 SgpioSupport; >=20 > + /** >=20 > + This member configures the features, property, and capability for ea= ch > SATA port. >=20 > + **/ >=20 > + PCH_SATA_PORT_CONFIG PortSettings[PCH_MAX_SATA_PORTS]; >=20 > + /** >=20 > + This field decides the settings of Sata thermal throttling. When the > Suggested Setting >=20 > + is enabled, PCH RC will use the suggested representative values. >=20 > + **/ >=20 > + SATA_THERMAL_THROTTLING ThermalThrottling; >=20 > +} SATA_CONFIG; >=20 > + >=20 > +#pragma pack (pop) >=20 > + >=20 > +#endif // _SATA_CONFIG_H_ >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Scs/ScsConfig.h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Scs/ScsConfig.h > new file mode 100644 > index 0000000000..2ebc901896 > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Scs/ScsConfig= .h > @@ -0,0 +1,139 @@ > +/** @file >=20 > + Scs policy >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _SCS_CONFIG_H_ >=20 > +#define _SCS_CONFIG_H_ >=20 > + >=20 > +#include >=20 > +#include >=20 > + >=20 > +#define SCS_SDCARD_CONFIG_REVISION 1 >=20 > +#define SCS_EMMC_CONFIG_REVISION 1 >=20 > +#define SCS_EMMC_DXE_CONFIG_REVISION 1 >=20 > +#define SCS_SDCARD_MAX_DATA_GPIOS 4 >=20 > +#define SCS_EMMC_MAX_DATA_GPIOS 8 >=20 > +extern EFI_GUID gSdCardConfigGuid; >=20 > +extern EFI_GUID gEmmcConfigGuid; >=20 > +extern EFI_GUID gUfsConfigGuid; >=20 > +extern EFI_GUID gEmmcDxeConfigGuid; >=20 > + >=20 > +#pragma pack (push,1) >=20 > + >=20 > +/** >=20 > + This structre holds the DLL configuration >=20 > + register values that will be programmed by RC >=20 > + if EnableCustomDlls field is set to TRUE. Those >=20 > + policies should be used by platform if default values >=20 > + provided by RC are not sufficient to provide stable operation >=20 > + at all supported spped modes. RC will blindly set the DLL values >=20 > + as provided in this structre. >=20 > + >=20 > + For help with obtaining valid DLL values for your platform please >=20 > + contact enabling support. >=20 > +**/ >=20 > +typedef struct { >=20 > + UINT32 TxCmdDelayControl; // Offset 820h: Tx CMD Delay Control >=20 > + UINT32 TxDataDelayControl1; // Offset 824h: Tx Data Delay Control = 1 >=20 > + UINT32 TxDataDelayControl2; // Offset 828h: Tx Data Delay Control = 2 >=20 > + UINT32 RxCmdDataDelayControl1; // Offset 82Ch: Rx CMD + Data Delay > Control 1 >=20 > + UINT32 RxCmdDataDelayControl2; // Offset 834h: Rx CMD + Data Delay > Control 2 >=20 > + UINT32 RxStrobeDelayControl; // Offset 830h: Rx Strobe Delay Contro= l, > valid only for eMMC >=20 > +} SCS_SD_DLL; >=20 > + >=20 > +/** >=20 > + SD GPIO settings >=20 > +**/ >=20 > +typedef struct { >=20 > + /** >=20 > + GPIO signals pin muxing settings. If signal can be enable only on a = single > pin >=20 > + then this parameter should be set to 0. Refer to > GPIO_*_MUXING_SDCARD_*x_* in GpioPins*.h >=20 > + for supported settings on a given platform >=20 > + **/ >=20 > + UINT32 PinMux; >=20 > + /** >=20 > + GPIO Pads Internal Termination. >=20 > + For more information please see Platform Design Guide. >=20 > + Check GPIO_ELECTRICAL_CONFIG for reference >=20 > + **/ >=20 > + UINT32 PadTermination; >=20 > +} MUX_GPIO_PARAM; >=20 > + >=20 > +typedef struct { >=20 > + MUX_GPIO_PARAM PowerEnable; >=20 > + MUX_GPIO_PARAM Cmd; >=20 > + MUX_GPIO_PARAM Data[SCS_SDCARD_MAX_DATA_GPIOS]; >=20 > + MUX_GPIO_PARAM Cdb; >=20 > + MUX_GPIO_PARAM Clk; >=20 > + MUX_GPIO_PARAM Wp; >=20 > +} SCS_SDCARD_GPIO_CONFIG; >=20 > + >=20 > +typedef struct { >=20 > + MUX_GPIO_PARAM Cmd; >=20 > + MUX_GPIO_PARAM Data[SCS_EMMC_MAX_DATA_GPIOS]; >=20 > + MUX_GPIO_PARAM Rclk; >=20 > + MUX_GPIO_PARAM Clk; >=20 > + MUX_GPIO_PARAM Resetb; >=20 > +} SCS_EMMC_GPIO_CONFIG; >=20 > + >=20 > +typedef struct { >=20 > + CONFIG_BLOCK_HEADER Header; >=20 > + >=20 > + UINT32 Enable : 1; ///< Enable/Disable SdCard 0:= Disabled, 1: > Enabled >=20 > + UINT32 PowerEnableActiveHigh : 1; ///< Determine SD_PWREN# > polarity 0: Active low, 1: Active high >=20 > + UINT32 UseCustomDlls : 1; ///< Use tuned DLL values fro= m policy > 0: Use default DLL, 1: Use values from TunedDllValues field >=20 > + UINT32 Reserved : 29; >=20 > + SCS_SD_DLL CustomDllValues; ///< Structure containing cus= tom DLL > values for SD card >=20 > + SCS_SDCARD_GPIO_CONFIG GpioConfig; >=20 > +} SCS_SDCARD_CONFIG; >=20 > + >=20 > +typedef struct { >=20 > + UINT32 Hs400RxValue : 7; ///< Value of the tuned HS400 Rx value >=20 > + UINT32 Hs400TxValue : 7; ///< Value of the tuned HS400 Tx value >=20 > + UINT32 Reserved : 18; >=20 > +} SCS_EMMC_TUNED_DLL; >=20 > + >=20 > +typedef struct { >=20 > + CONFIG_BLOCK_HEADER Header; >=20 > + >=20 > + UINT32 Enable : 1; ///< Enable/Disable eMMC 0: Disabled= , 1: > Enabled >=20 > + UINT32 Hs400Supported : 1; ///< Enable/Disable eMMC HS400 suppo= rt > 0: Disabled, 1: Enabled >=20 > + UINT32 UseCustomDlls : 1; ///< Use custom DLL values from poli= cy > 0: Use default DLL, 1: Use values from TunedDllValues field >=20 > + UINT32 Reserved : 29; >=20 > + SCS_SD_DLL CustomDllValues; ///< Structure containing custom DLL > values for eMMC ///< Structure containing tuned DLL se= ttings for > eMMC >=20 > + SCS_EMMC_GPIO_CONFIG GpioConfig; >=20 > +} SCS_EMMC_CONFIG; >=20 > + >=20 > +typedef enum { >=20 > + DriverStrength33Ohm =3D 0, >=20 > + DriverStrength40Ohm, >=20 > + DriverStrength50Ohm >=20 > +} SCS_EMMC_DRIVER_STRENGTH; >=20 > + >=20 > +typedef struct { >=20 > + UINT32 TuningSuccessful : 1; ///< Informs software tuning module ab= out > previous software tuning status. >=20 > + UINT32 Hs400RxValue : 7; ///< Value of the tuned HS400 Rx value > returned from software tuning module >=20 > + UINT32 Hs400TxValue : 7; ///< Value of the tuned HS400 Tx value > returned from software tuning module >=20 > + UINT32 Reserved : 17; >=20 > +} SCS_EMMC_SOFTWARE_TUNING_RESULTS; >=20 > + >=20 > +typedef struct { >=20 > + CONFIG_BLOCK_HEADER Header; >=20 > + >=20 > + UINT32 EnableSoftwareHs400Tuning : 1; ///< Enable/= Disable > software eMMC HS400 tuning: 0 - Disable, 1 - Enable >=20 > + UINT32 DriverStrength : 2; ///< I/O dri= ver strength: 0 - 33 > Ohm, 1 - 40 Ohm, 2 - 50 Ohm >=20 > + UINT32 Reserved : 29; >=20 > + EFI_LBA TuningLba; ///< Specifi= es LBA which will be > used during software tuning process. >=20 > + SCS_EMMC_SOFTWARE_TUNING_RESULTS PreviousTuningResults; ///< > Informes software tuning module about previous software tuning results.} > SCS_EMMC_DXE_CONFIG; >=20 > +} SCS_EMMC_DXE_CONFIG; >=20 > + >=20 > +typedef struct { >=20 > + UINT32 Enable : 1; ///< Enable/Disable UFS controller 0: Disabled,= 1: > Enabled >=20 > + UINT32 Reserved : 31; >=20 > +} SCS_UFS_CONTROLLER_CONFIG; >=20 > + >=20 > +#pragma pack (pop) >=20 > + >=20 > +#endif // _SCS_CONFIG_H_ >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/SerialIo/SerialIo= Confi > g.h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/SerialIo/SerialIo= Confi > g.h > new file mode 100644 > index 0000000000..d76937cf59 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/SerialIo/SerialIo= Confi > g.h > @@ -0,0 +1,32 @@ > +/** @file >=20 > + Serial IO policy >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _SERIAL_IO_CONFIG_H_ >=20 > +#define _SERIAL_IO_CONFIG_H_ >=20 > + >=20 > +#define SERIAL_IO_CONFIG_REVISION 1 >=20 > +extern EFI_GUID gSerialIoConfigGuid; >=20 > + >=20 > +#include >=20 > + >=20 > +#pragma pack (push,1) >=20 > + >=20 > +/** >=20 > + The SERIAL_IO_CONFIG block provides the configurations to set the Seri= al > IO controllers >=20 > + >=20 > + Revision 1: >=20 > + - Inital version. >=20 > +**/ >=20 > +typedef struct { >=20 > + CONFIG_BLOCK_HEADER Header; = ///< Config Block > Header >=20 > + SERIAL_IO_SPI_CONFIG > SpiDeviceConfig[PCH_MAX_SERIALIO_SPI_CONTROLLERS]; ///< SPI > Configuration >=20 > + SERIAL_IO_I2C_CONFIG > I2cDeviceConfig[PCH_MAX_SERIALIO_I2C_CONTROLLERS]; ///< I2C > Configuration >=20 > + SERIAL_IO_UART_CONFIG > UartDeviceConfig[PCH_MAX_SERIALIO_UART_CONTROLLERS]; ///< UART > Configuration >=20 > +} SERIAL_IO_CONFIG; >=20 > + >=20 > +#pragma pack (pop) >=20 > + >=20 > +#endif // _SERIAL_IO_CONFIG_H_ >=20 > diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/SiConf= ig.h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/SiConfig.h > new file mode 100644 > index 0000000000..7ee4554b1d > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/SiConfig.h > @@ -0,0 +1,152 @@ > +/** @file >=20 > + Si Config Block >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _SI_CONFIG_H_ >=20 > +#define _SI_CONFIG_H_ >=20 > + >=20 > +#define SI_CONFIG_REVISION 2 >=20 > + >=20 > +extern EFI_GUID gSiConfigGuid; >=20 > + >=20 > + >=20 > +#pragma pack (push,1) >=20 > + >=20 > +/** >=20 > + The Silicon Policy allows the platform code to publish a set of config= uration >=20 > + information that the RC drivers will use to configure the silicon hard= ware. >=20 > + >=20 > + Revision 1: >=20 > + - Initial version. >=20 > + Revision 2: >=20 > + - Added TraceHubMemBase >=20 > +**/ >=20 > +typedef struct { >=20 > + CONFIG_BLOCK_HEADER Header; ///< Offset 0 - 27 Config Block Header >=20 > + // >=20 > + // Platform specific common policies that used by several silicon > components. >=20 > + // >=20 > + UINT8 CsmFlag; ///< CSM status flag. >=20 > + /** >=20 > + This is used to skip the SSID programming in silicon code. >=20 > + When set to TRUE, silicon code will not do any SSID programming and > platform code >=20 > + needs to handle that by itself properly. >=20 > + 0: FALSE, 1: TRUE >=20 > + **/ >=20 > + UINT8 SkipSsidProgramming; >=20 > + UINT8 RsvdBytes0[2]; >=20 > + /** >=20 > + When SkipSsidProgramming is FALSE, silicon code will use this as def= ault > value >=20 > + to program the SVID for all internal devices. >=20 > + 0: use silicon default SVID 0x8086 , Non-zero: use customized > SVID. >=20 > + **/ >=20 > + UINT16 CustomizedSvid; >=20 > + /** >=20 > + When SkipSsidProgramming is FALSE, silicon code will use this as def= ault > value >=20 > + to program the Sid for all internal devices. >=20 > + 0: use silicon default SSID 0x7270 , Non-zero: use customized > SSID. >=20 > + **/ >=20 > + UINT16 CustomizedSsid; >=20 > + /** >=20 > + SsidTablePtr contains the SVID_SID_INIT_ENTRY table. >=20 > + This is valid when SkipSsidProgramming is FALSE; >=20 > + It doesn't need to contain entries for all Intel internal devices. >=20 > + It can only contains the SVID_SID_INIT_ENTRY entries for those Dev# > Func# which needs >=20 > + to be overridden. >=20 > + In the enties, only Dev, Function, SubSystemVendorId, and SubSystemI= d > are required. >=20 > + Default is NULL. >=20 > + >=20 > + E.g. Platform only needs to override BDF 0:31:5 to AAAA:BBBB and BDF > 0:31:3 to CCCC:DDDD, >=20 > + it can be done in platform like this: >=20 > + STATIC SVID_SID_INIT_ENTRY mSsidTablePtr[SI_MAX_DEVICE_COUNT] =3D > {0}; >=20 > + >=20 > + VOID SiPolicyUpdate () { >=20 > + UINT32 EntryCount =3D 0; >=20 > + SiPolicy->SkipSsidProgramming =3D FALSE; >=20 > + SiPolicy->SsidTablePtr =3D mSsidTablePtr; >=20 > + >=20 > + mSsidTablePtr[EntryCount].Address.Bits.Device =3D SpiDeviceNumbe= r (); >=20 > + mSsidTablePtr[EntryCount].Address.Bits.Function =3D SpiFunctionNum= ber > (); >=20 > + mSsidTablePtr[EntryCount].SvidSidValue.SubSystemVendorId =3D > 0xAAAA; >=20 > + mSsidTablePtr[EntryCount].SvidSidValue.SubSystemId =3D 0xBBB= B; >=20 > + EntryCount ++; >=20 > + mSsidTablePtr[EntryCount].Address.Bits.Device =3D HdaDevNumber (= ); >=20 > + mSsidTablePtr[EntryCount].Address.Bits.Function =3D HdaFuncNumber = (); >=20 > + mSsidTablePtr[EntryCount].SvidSidValue.SubSystemVendorId =3D 0xCCC= C; >=20 > + mSsidTablePtr[EntryCount].SvidSidValue.SubSystemId =3D 0xDDD= D; >=20 > + EntryCount ++; >=20 > + ASSERT (EntryCount < SI_MAX_DEVICE_COUNT); >=20 > + SiPolicy->NumberOfSsidTableEntry =3D EntryCount; >=20 > + } >=20 > + **/ >=20 > + UINT32 *SsidTablePtr; >=20 > + /** >=20 > + Number of valid enties in SsidTablePtr. >=20 > + This is valid when SkipSsidProgramming is FALSE; >=20 > + Default is 0. >=20 > + **/ >=20 > + UINT16 NumberOfSsidTableEntry; >=20 > + UINT8 RsvdBytes1[2]; >=20 > + /** >=20 > + If Trace Hub is enabled and trace to memory is desired, Platform cod= e or > BootLoader needs to allocate trace hub memory >=20 > + as reserved, and save allocated memory base to TraceHubMemBase to > ensure Trace Hub memory is configured properly. >=20 > + To get total trace hub memory size please refer to > TraceHubCalculateTotalBufferSize () >=20 > + >=20 > + Noted: If EDKII memory service is used to allocate memory, it will r= equire > double memory size to support size-aligned memory allocation, >=20 > + so Platform code or FSP Wrapper code should ensure enough memory > available for size-aligned TraceHub memory allocation. >=20 > + **/ >=20 > + UINT32 TraceHubMemBase; // Offset 58 >=20 > + /** >=20 > + This is used to skip setting BIOS_DONE MSR during firmware update bo= ot > mode. >=20 > + When set to TRUE and boot mode is BOOT_ON_FLASH_UPDATE, >=20 > + skip setting BIOS_DONE MSR at EndofPei. >=20 > + 0: FALSE, 1: TRUE >=20 > + **/ >=20 > + UINT8 SkipBiosDoneWhenFwUpdate; >=20 > + UINT8 RsvdBytes2[3]; >=20 > +} SI_CONFIG; >=20 > + >=20 > +#pragma pack (pop) >=20 > + >=20 > +#define DEFAULT_SSVID 0x8086 >=20 > +#define DEFAULT_SSDID 0x7270 >=20 > +#define SI_MAX_DEVICE_COUNT 70 >=20 > + >=20 > +/// >=20 > +/// Subsystem Vendor ID / Subsystem ID >=20 > +/// >=20 > +typedef struct { >=20 > + UINT16 SubSystemVendorId; >=20 > + UINT16 SubSystemId; >=20 > +} SVID_SID_VALUE; >=20 > + >=20 > +// >=20 > +// Below is to match PCI_SEGMENT_LIB_ADDRESS () which can directly send > to PciSegmentRead/Write functions. >=20 > +// >=20 > +typedef struct { >=20 > + union { >=20 > + struct { >=20 > + UINT32 Register:12; >=20 > + UINT32 Function:3; >=20 > + UINT32 Device:5; >=20 > + UINT32 Bus:8; >=20 > + UINT32 Reserved1:4; >=20 > + UINT32 Segment:16; >=20 > + UINT32 Reserved2:16; >=20 > + } Bits; >=20 > + UINT64 SegBusDevFuncRegister; >=20 > + } Address; >=20 > + SVID_SID_VALUE SvidSidValue; >=20 > + UINT32 Reserved; >=20 > +} SVID_SID_INIT_ENTRY; >=20 > + >=20 > + >=20 > +typedef struct { >=20 > + UINT32 SkipBus; >=20 > + UINT32 SkipDevice; >=20 > + UINT32 SkipFunction; >=20 > +} SVID_SID_SKIP_TABLE; >=20 > + >=20 > +#endif // _SI_CONFIG_H_ >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/SiPreMemConfig.h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/SiPreMemConfig.h > new file mode 100644 > index 0000000000..4bf014e9ba > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/SiPreMemConfig.h > @@ -0,0 +1,67 @@ > +/** @file >=20 > + Si Config Block PreMem >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _SI_PREMEM_CONFIG_H_ >=20 > +#define _SI_PREMEM_CONFIG_H_ >=20 > + >=20 > +#define SI_PREMEM_CONFIG_REVISION 1 >=20 > + >=20 > +extern EFI_GUID gSiPreMemConfigGuid; >=20 > + >=20 > +typedef enum { >=20 > + ProbeTypeDisabled =3D 0x00, >=20 > + ProbeTypeDciOob =3D 0x02, >=20 > + ProbeTypeUsb3Dbc =3D 0x03, >=20 > + ProbeTypeXdp3 =3D 0x04, >=20 > + ProbeTypeUsb2Dbc =3D 0x05, >=20 > + ProbeType2WireDciOob =3D 0x06, >=20 > + ProbeTypeManual =3D 0x07, >=20 > + ProbeTypeMax >=20 > +} PLATFORM_DEBUG_CONSENT_PROBE_TYPE; >=20 > + >=20 > +#pragma pack (push,1) >=20 > +/** >=20 > + The Silicon PreMem Policy allows the platform code to publish a set of > configuration >=20 > + information that the RC drivers will use to configure the silicon hard= ware. >=20 > + >=20 > + Revision 1: >=20 > + - Initial version. >=20 > +**/ >=20 > +typedef struct { >=20 > + CONFIG_BLOCK_HEADER Header; ///< Offset 0 - 27 Config Block Header >=20 > + /** >=20 > + Platform Debug Consent >=20 > + As a master switch to enable platform debug capability and relevant > settings with specified probe type. >=20 > + Manual: Do not use Platform Debug Consent to override other debug- > relevant policies, but the user must set each debug option manually, aime= d > at advanced users. >=20 > + >=20 > + PDC-dependent policies are listed: >=20 > + DciPreMemConfig->DciEn >=20 > + DciPreMemConfig->DciDbcMode >=20 > + CpuTraceHubConfig->EnableMode >=20 > + CpuTraceHubConfig->CpuTraceHubMemReg0Size >=20 > + CpuTraceHubConfig->CpuTraceHubMemReg1Size >=20 > + PchTraceHubPreMemConfig->EnableMode >=20 > + PchTraceHubPreMemConfig->MemReg0Size >=20 > + PchTraceHubPreMemConfig->MemReg1Size >=20 > + >=20 > + Note: DCI OOB (aka BSSB) uses CCA probe. >=20 > + Refer to definition of PLATFORM_DEBUG_CONSENT_PROBE_TYPE >=20 > + 0:Disabled; 2:DCI OOB; 3:USB3 DbC; 4:XDP3/MIPI60 5:USB2 DbC; > 6:2-wire DCI OOB; 7:Manual >=20 > + **/ >=20 > + UINT32 PlatformDebugConsent : 4; >=20 > + UINT32 RsvdBits : 28; >=20 > + /** >=20 > + This is used to skip override boot mode during firmware update boot > mode. >=20 > + When set to TRUE and boot mode is BOOT_ON_FLASH_UPDATE, >=20 > + skip setting boot mode to BOOT_WITH_FULL_CONFIGURATION in PEI > memory init. >=20 > + 0: FALSE, 1: TRUE >=20 > + **/ >=20 > + UINT8 SkipOverrideBootModeWhenFwUpdate; >=20 > + UINT8 RsvdBytes[3]; >=20 > +} SI_PREMEM_CONFIG; >=20 > + >=20 > +#pragma pack (pop) >=20 > +#endif // _SI_PREMEM_CONFIG_H_ >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Smbus/SmbusConfig > .h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Smbus/SmbusConfig > .h > new file mode 100644 > index 0000000000..36f96a4f32 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Smbus/SmbusConfig > .h > @@ -0,0 +1,50 @@ > +/** @file >=20 > + Smbus policy >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _SMBUS_CONFIG_H_ >=20 > +#define _SMBUS_CONFIG_H_ >=20 > + >=20 > +#define SMBUS_PREMEM_CONFIG_REVISION 1 >=20 > +extern EFI_GUID gSmbusPreMemConfigGuid; >=20 > + >=20 > +#pragma pack (push,1) >=20 > + >=20 > +#define PCH_MAX_SMBUS_RESERVED_ADDRESS 128 >=20 > + >=20 > +/// >=20 > +/// The SMBUS_CONFIG block lists the reserved addresses for non-ARP > capable devices in the platform. >=20 > +/// >=20 > +typedef struct { >=20 > + /** >=20 > + Revision 1: Init version >=20 > + **/ >=20 > + CONFIG_BLOCK_HEADER Header; ///< Config Block Header >=20 > + /** >=20 > + This member describes whether or not the SMBus controller of PCH > should be enabled. >=20 > + 0: Disable; 1: Enable. >=20 > + **/ >=20 > + UINT32 Enable : 1; >=20 > + UINT32 ArpEnable : 1; ///< Enable SMBus ARP support, <= b>0: > Disable; 1: Enable. >=20 > + UINT32 DynamicPowerGating : 1; ///< (Test) Disable > or Enable Smbus dynamic power gating. >=20 > + /// >=20 > + /// (Test) SPD Write Disable, 0: leave SPD Write Disable bit; <= b>1: > set SPD Write Disable bit. >=20 > + /// For security recommendations, SPD write disable bit must be set. >=20 > + /// >=20 > + UINT32 SpdWriteDisable : 1; >=20 > + UINT32 SmbAlertEnable : 1; ///< Enable SMBus Alert pin > (SMBALERT#). 0: Disabled, 1: Enabled. >=20 > + UINT32 RsvdBits0 : 27; ///< Reserved bits >=20 > + UINT16 SmbusIoBase; ///< SMBUS Base Address (IO spac= e). > Default is 0xEFA0. >=20 > + UINT8 Rsvd0; ///< Reserved bytes >=20 > + UINT8 NumRsvdSmbusAddresses; ///< The number of elements in > the RsvdSmbusAddressTable. >=20 > + /** >=20 > + Array of addresses reserved for non-ARP-capable SMBus devices. >=20 > + **/ >=20 > + UINT8 > RsvdSmbusAddressTable[PCH_MAX_SMBUS_RESERVED_ADDRESS]; >=20 > +} PCH_SMBUS_PREMEM_CONFIG; >=20 > + >=20 > +#pragma pack (pop) >=20 > + >=20 > +#endif // _SMBUS_CONFIG_H_ >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Spi/SpiConfig.h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Spi/SpiConfig.h > new file mode 100644 > index 0000000000..f3e52ff453 > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Spi/SpiConfig= .h > @@ -0,0 +1,43 @@ > +/** @file >=20 > + PCH SPI Flash Controller config block >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +#ifndef _SPI_CONFIG_H_ >=20 > +#define _SPI_CONFIG_H_ >=20 > + >=20 > +#define SPI_CONFIG_REVISION 1 >=20 > +extern EFI_GUID gSpiConfigGuid; >=20 > + >=20 > +#pragma pack (push,1) >=20 > + >=20 > +/** >=20 > + Basic configuration for option features of PCH SPI Flash controller >=20 > +**/ >=20 > +typedef struct { >=20 > + CONFIG_BLOCK_HEADER Header; ///< Config Block Header >=20 > + /** >=20 > + Enable extended BIOS Direct Read Region feature >=20 > + Enabling this will make all memory accesses in a decode range to be > translated >=20 > + to BIOS region reads from SPI flash >=20 > + 0: Disabled, 1: Enabled >=20 > + **/ >=20 > + UINT32 ExtendedBiosDecodeRangeEnable : 1; >=20 > + UINT32 RsvdBits0 : 31; ///< Reserved bi= ts >=20 > + /** >=20 > + Base address that will be used for Extended Decode Range. >=20 > + This will be ignored when ExtendedBiosDecodeRangeEnable is set to 0. >=20 > + **/ >=20 > + UINT32 ExtendedBiosDecodeRangeBase; >=20 > + /** >=20 > + Limit address that will be used for Extended Decode Range. >=20 > + This will be ignored when ExtendedBiosDecodeRangeEnable is set to 0. >=20 > + **/ >=20 > + UINT32 ExtendedBiosDecodeRangeLimit; >=20 > +} SPI_CONFIG; >=20 > + >=20 > +#pragma pack (pop) >=20 > + >=20 > +#endif // _SPI_CONFIG_H_ >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Tcss/TcssPeiConfi= g.h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Tcss/TcssPeiConfi= g.h > new file mode 100644 > index 0000000000..53af4ccd45 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Tcss/TcssPeiConfi= g.h > @@ -0,0 +1,145 @@ > +/** @file >=20 > + TCSS PEI policy >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _TCSS_PEI_CONFIG_H_ >=20 > +#define _TCSS_PEI_CONFIG_H_ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +#define TCSS_PEI_CONFIG_REVISION 2 >=20 > +extern EFI_GUID gTcssPeiConfigGuid; >=20 > + >=20 > +#pragma pack (push,1) >=20 > + >=20 > + >=20 > +#define MAX_IOM_AUX_BIAS_COUNT 4 >=20 > + >=20 > +/// >=20 > +/// The IOM_AUX_ORI_PAD_CONFIG describes IOM TypeC port map GPIO > pin. >=20 > +/// Those GPIO setting for DP Aux Orientation Bias Control when the Type= C > port didn't have re-timer. >=20 > +/// IOM needs know Pull-Up and Pull-Down pin for Bias control >=20 > +/// >=20 > +typedef struct { >=20 > + UINT32 GpioPullN; ///< GPIO Pull Up Ping number that is for IOM > indecate the pull up pin from TypeC port. >=20 > + UINT32 GpioPullP; ///< GPIO Pull Down Ping number that is for IOM > indecate the pull down pin from TypeC port. >=20 > +} IOM_AUX_ORI_PAD_CONFIG; >=20 > + >=20 > +/// >=20 > +/// The IOM_EC_INTERFACE_CONFIG block describes interaction between > BIOS and IOM-EC. >=20 > +/// >=20 > + >=20 > +typedef struct { >=20 > + UINT32 VccSt; ///< IOM VCCST request. (Not equal to actual= VCCST > value) >=20 > + UINT32 UsbOverride; ///< IOM to override USB connection. >=20 > + UINT32 D3ColdEnable; ///< Enable/disable D3 Cold support in TCSS >=20 > + UINT32 D3HotEnable; ///< Enable/disable D3 Hot support in TCSS >=20 > +} IOM_INTERFACE_CONFIG; >=20 > + >=20 > +/// >=20 > +/// The PMC_INTERFACE_CONFIG block describes interaction between > BIOS and PMC >=20 > +/// >=20 > +typedef struct { >=20 > + UINT8 PmcPdEnable; ///< PMC PD Solution Enable >=20 > + UINT8 Rsvd[3]; >=20 > +} PMC_INTERFACE_CONFIG; >=20 > + >=20 > +/// >=20 > +/// The SA XDCI INT Pin and IRQ number >=20 > +/// >=20 > +typedef struct { >=20 > + UINT8 IntPing; ///< Int Pin Number >=20 > + UINT8 Irq; ///< Irq Number >=20 > + UINT16 Rsvd; >=20 > +} SA_XDCI_IRQ_INT_CONFIG; >=20 > + >=20 > +/// >=20 > +/// The TCSS_PCIE_PORT_POLICY block describes PCIe settings for TCSS. >=20 > +/// >=20 > +typedef struct { >=20 > + UINT8 AcsEnabled; ///< Indicate whether the = ACS is enabled. > 0: Disable; 1: Enable. >=20 > + UINT8 DpcEnabled; ///< Downstream Port Conta= inment. 0: > Disable; 1: Enable >=20 > + UINT8 RpDpcExtensionsEnabled; ///< RP Extensions for > Downstream Port Containment. 0: Disable; 1: Enable >=20 > + UINT8 LtrEnable; ///< Latency Tolerance Rep= orting > Mechanism. 0: Disable; 1: Enable. >=20 > + UINT8 PtmEnabled; ///< Enables PTM capabilit= y >=20 > + >=20 > + UINT8 Aspm; ///< The ASPM configuratio= n of the root port > (see: PCH_PCIE_ASPM_CONTROL). Default is >=20 > + UINT8 SlotNumber; ///< Indicates the slot nu= mber for the > root port. Default is the value as root port index. >=20 > + UINT8 SlotPowerLimitScale; ///< (Test) Specifi= es scale > used for slot power limit value. Leave as 0 to set to default. Default is > zero. >=20 > + UINT16 SlotPowerLimitValue; ///< (Test) Specifi= es upper > limit on power supplies by slot. Leave as 0 to set to default. Default is > zero. >=20 > + >=20 > + UINT8 AdvancedErrorReporting; ///< Indicate whether the > Advanced Error Reporting is enabled. 0: Disable; 1: Enable. >=20 > + UINT8 UnsupportedRequestReport; ///< Indicate whether the > Unsupported Request Report is enabled. 0: Disable; 1: Enable. >=20 > + UINT8 FatalErrorReport; ///< Indicate whether the = Fatal Error > Report is enabled. 0: Disable; 1: Enable. >=20 > + UINT8 NoFatalErrorReport; ///< Indicate whether the = No Fatal > Error Report is enabled. 0: Disable; 1: Enable. >=20 > + UINT8 CorrectableErrorReport; ///< Indicate whether the > Correctable Error Report is enabled. 0: Disable; 1: Enable. >=20 > + UINT8 SystemErrorOnFatalError; ///< Indicate whether the = System > Error on Fatal Error is enabled. 0: Disable; 1: Enable. >=20 > + UINT8 SystemErrorOnNonFatalError; ///< Indicate whether the > System Error on Non Fatal Error is enabled. 0: Disable; 1: Enable. >=20 > + UINT8 SystemErrorOnCorrectableError; ///< Indicate whether the > System Error on Correctable Error is enabled. 0: Disable; 1: Enabl= e. >=20 > + >=20 > + UINT16 LtrMaxSnoopLatency; ///< Latency Tolerance Rep= orting, > Max Snoop Latency. >=20 > + UINT16 LtrMaxNoSnoopLatency; ///< Latency Tolerance Rep= orting, > Max Non-Snoop Latency. >=20 > + UINT8 SnoopLatencyOverrideMode; ///< Latency Tolerance > Reporting, Snoop Latency Override Mode. >=20 > + UINT8 SnoopLatencyOverrideMultiplier; ///< Latency Tolerance > Reporting, Snoop Latency Override Multiplier. >=20 > + UINT16 SnoopLatencyOverrideValue; ///< Latency Tolerance > Reporting, Snoop Latency Override Value. >=20 > + UINT8 NonSnoopLatencyOverrideMode; ///< Latency Tolerance > Reporting, Non-Snoop Latency Override Mode. >=20 > + UINT8 NonSnoopLatencyOverrideMultiplier; ///< Latency Tolerance > Reporting, Non-Snoop Latency Override Multiplier. >=20 > + UINT16 NonSnoopLatencyOverrideValue; ///< Latency Tolerance > Reporting, Non-Snoop Latency Override Value. >=20 > + UINT8 ForceLtrOverride; ///< 0: Disable; 1:= Enable. >=20 > + UINT8 LtrConfigLock; ///< 0: Disable; 1:= Enable. >=20 > +} TCSS_PCIE_PORT_POLICY; >=20 > + >=20 > +/// >=20 > +/// TCSS_PCIE_PEI_POLICY describes PCIe port settings for TCSS. >=20 > +/// >=20 > +typedef struct { >=20 > + TCSS_PCIE_PORT_POLICY PciePortPolicy[MAX_ITBT_PCIE_PORT]; >=20 > +} TCSS_PCIE_PEI_POLICY; >=20 > + >=20 > +/// >=20 > +/// The TCSS_IOM_PEI_CONFIG block describes IOM Aux/HSL override > settings for TCSS. >=20 > +/// >=20 > +typedef struct { >=20 > + UINT16 AuxOri; ///< Bits defining value for IOM Aux Orientation > Register >=20 > + UINT16 HslOri; ///< Bits defining value for IOM HSL Orientation= Register >=20 > +} TCSS_IOM_ORI_OVERRIDE; >=20 > + >=20 > +/// >=20 > +/// The TCSS_IOM_PEI_CONFIG block describes IOM settings for TCSS. >=20 > +/// >=20 > +typedef struct { >=20 > + IOM_AUX_ORI_PAD_CONFIG > IomAuxPortPad[MAX_IOM_AUX_BIAS_COUNT]; ///< The > IOM_AUX_ORI_BIAS_CTRL port config setting. >=20 > + TCSS_IOM_ORI_OVERRIDE IomOverrides; >=20 > + IOM_INTERFACE_CONFIG IomInterface; ///< = Config > settings are BIOS <-> IOM interface. >=20 > + PMC_INTERFACE_CONFIG PmcInterface; ///< = Config > settings for BIOS <-> PMC interface >=20 > + UINT8 TcStateLimit; ///< = Tcss C-State deep stage >=20 > + UINT8 Usb3ComplModeEnable; >=20 > + UINT8 Reserved[2]; ///< = Reserved bytes for future > use >=20 > +} TCSS_IOM_PEI_CONFIG; >=20 > + >=20 > +/// >=20 > +/// The TCSS_MISC_PEI_CONFIG block describes MISC settings for TCSS. >=20 > +/// >=20 > +typedef struct { >=20 > + SA_XDCI_IRQ_INT_CONFIG SaXdci; ///< System Agent Xdci Int Pin and > Irq setting >=20 > + UINT32 Rsvd; ///< Reserved bytes for future use= , align to > multiple 4 >=20 > +} TCSS_MISC_PEI_CONFIG; >=20 > + >=20 > +/// >=20 > +/// The TCSS_PEI_CONFIG block describes TCSS settings for SA. >=20 > +/// >=20 > +typedef struct { >=20 > + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Head= er >=20 > + TCSS_PCIE_PEI_POLICY PciePolicy; ///< The PCIe Config >=20 > + USB_CONFIG UsbConfig; ///< USB config is shared between = PCH > and SA. >=20 > + TCSS_IOM_PEI_CONFIG IomConfig; ///< The Iom Config >=20 > + TCSS_MISC_PEI_CONFIG MiscConfig; ///< The MISC Config >=20 > +} TCSS_PEI_CONFIG; >=20 > + >=20 > +#pragma pack (pop) >=20 > + >=20 > +#endif /* _TCSS_PEI_CONFIG_H_ */ >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Thc/ThcConfig.h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Thc/ThcConfig.h > new file mode 100644 > index 0000000000..23c3750216 > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Thc/ThcConfig= .h > @@ -0,0 +1,73 @@ > +/** @file >=20 > + Touch Host Controller policy. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +#ifndef _THC_CONFIG_H_ >=20 > +#define _THC_CONFIG_H_ >=20 > + >=20 > +#define THC_CONFIG_REVISION 1 >=20 > +extern EFI_GUID gThcConfigGuid; >=20 > + >=20 > +#pragma pack (push,1) >=20 > + >=20 > +/** >=20 > + Available Port Assignments >=20 > + >=20 > +**/ >=20 > +typedef enum { >=20 > + ThcAssignmentNone, ///< None of the avaialbe controllers assigned >=20 > + ThcAssignmentThc0, ///< Port assigned to THC0 >=20 > + ThcAssignmentThc1 ///< Port assigned to THC1 >=20 > +} THC_PORT_ASSIGNMENT; >=20 > + >=20 > + >=20 > +/** >=20 > + Port Configuration structure required for each Port that THC might use= . >=20 > + >=20 > +**/ >=20 > +typedef struct { >=20 > + UINT32 Assignment; ///< Sets THCx assignment see > THC_PORT_ASSIGNMENT >=20 > + UINT32 InterruptPinMuxing; ///< Each GPIO PORTx/SPIx INTB Pin has > different muxing options refer to GPIO_*_MUXING_THC_SPIx_* >=20 > +} THC_PORT; >=20 > + >=20 > +/** >=20 > + THC_CONFIG block provides the configurations forTouch Host Controllers >=20 > + >=20 > + Assignment field in each THC port controlls the THC behavior. >=20 > + >=20 > + Available scenarios: >=20 > + 1: Single Port 0 used by THC0 >=20 > + - THC0 Enabled >=20 > + - Port0 assigned to THC0 >=20 > + - Port1 unassigned >=20 > + - THC1 will be automatically Disabled. >=20 > + 2: Both ports used by THC0 >=20 > + - THC0 Enabled >=20 > + - Port0 assigned to THC0 >=20 > + - Port1 assigned to THC0 >=20 > + - THC1 will be automatically Disabled. >=20 > + 3: Port 0 used by THC0 and Port 1 used by THC1 >=20 > + - THC0 Enabled >=20 > + - Port0 assigned to THC0 >=20 > + - THC1 Enabled >=20 > + - Port1 assigned to THC1. >=20 > +4: Both Ports unassigned. >=20 > + Both THC Controllers will be disabled in that case. >=20 > + >=20 > + @note >=20 > + Invalid scenario that will cause ASSERT. >=20 > + 1. Same port Number assigned to THC0 or THC1. >=20 > + 2. Two Ports assigned to THC1. >=20 > + >=20 > +**/ >=20 > +typedef struct { >=20 > + CONFIG_BLOCK_HEADER Header; ///< Config Block Header >=20 > + THC_PORT ThcPort[2]; ///< Port Configuration >=20 > +} THC_CONFIG; >=20 > + >=20 > +#pragma pack (pop) >=20 > + >=20 > +#endif // _THC_CONFIG_H_ >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Thermal/ThermalCo= n > fig.h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Thermal/ThermalCo > nfig.h > new file mode 100644 > index 0000000000..a952f74238 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Thermal/ThermalCo > nfig.h > @@ -0,0 +1,153 @@ > +/** @file >=20 > + Thermal policy >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _THERMAL_CONFIG_H_ >=20 > +#define _THERMAL_CONFIG_H_ >=20 > + >=20 > +#define THERMAL_CONFIG_REVISION 1 >=20 > +extern EFI_GUID gThermalConfigGuid; >=20 > + >=20 > +#pragma pack (push,1) >=20 > + >=20 > +/** >=20 > + This structure lists PCH supported throttling register setting for > custimization. >=20 > + When the SuggestedSetting is enabled, the customized values are ignore= d. >=20 > +**/ >=20 > +typedef struct { >=20 > + UINT32 T0Level : 9; ///< Custimized T0Level value. I= f > SuggestedSetting is used, this setting is ignored. >=20 > + UINT32 T1Level : 9; ///< Custimized T1Level value. I= f > SuggestedSetting is used, this setting is ignored. >=20 > + UINT32 T2Level : 9; ///< Custimized T2Level value. I= f > SuggestedSetting is used, this setting is ignored. >=20 > + UINT32 TTEnable : 1; ///< Enable the thermal throttle= function. If > SuggestedSetting is used, this settings is ignored. >=20 > + /** >=20 > + When set to 1 and the programmed GPIO pin is a 1, then PMSync state = 13 > will force at least T2 state. >=20 > + If SuggestedSetting is used, this setting is ignored. >=20 > + **/ >=20 > + UINT32 TTState13Enable : 1; >=20 > + /** >=20 > + When set to 1, this entire register (TL) is locked and remains locke= d until > the next platform reset. >=20 > + If SuggestedSetting is used, this setting is ignored. >=20 > + **/ >=20 > + UINT32 TTLock : 1; >=20 > + UINT32 SuggestedSetting : 1; ///< 0: Disable; 1: Enable > suggested representative values. >=20 > + /** >=20 > + ULT processors support thermal management and cross thermal throttli= ng > between the processor package >=20 > + and LP PCH. The PMSYNC message from PCH to CPU includes specific bit > fields to update the PCH >=20 > + thermal status to the processor which is factored into the processor > throttling. >=20 > + Enable/Disable PCH Cross Throttling; 0: Disabled, 1: Enabled. >=20 > + **/ >=20 > + UINT32 PchCrossThrottling : 1; >=20 > + UINT32 Rsvd0; ///< Reserved bytes >=20 > +} THERMAL_THROTTLE_LEVELS; >=20 > + >=20 > +// >=20 > +// Supported Thermal Sensor Target Width >=20 > +// >=20 > +typedef enum { >=20 > + DmiThermSensWidthX1 =3D 0, >=20 > + DmiThermSensWidthX2 =3D 1, >=20 > + DmiThermSensWidthX4 =3D 2, >=20 > + DmiThermSensWidthX8 =3D 3, >=20 > + DmiThermSensWidthX16 =3D 4 >=20 > +} DMI_THERMAL_SENSOR_TARGET_WIDTH; >=20 > + >=20 > +/** >=20 > + This structure allows to customize DMI HW Autonomous Width Control for > Thermal and Mechanical spec design. >=20 > + When the SuggestedSetting is enabled, the customized values are ignore= d. >=20 > + Look at DMI_THERMAL_SENSOR_TARGET_WIDTH for possible values >=20 > +**/ >=20 > +typedef struct { >=20 > + UINT32 DmiTsawEn : 1; ///< DMI Thermal Sensor Autonomo= us > Width Enable >=20 > + UINT32 SuggestedSetting : 1; ///< 0: Disable; 1: Enable > suggested representative values >=20 > + UINT32 RsvdBits0 : 6; ///< Reserved bits >=20 > + UINT32 TS0TW : 3; ///< Thermal Sensor 0 Target Wid= th > (DmiThermSensWidthx8) >=20 > + UINT32 TS1TW : 3; ///< Thermal Sensor 1 Target Wid= th > (DmiThermSensWidthx4) >=20 > + UINT32 TS2TW : 3; ///< Thermal Sensor 2 Target Wid= th > (DmiThermSensWidthx2) >=20 > + UINT32 TS3TW : 3; ///< Thermal Sensor 3 Target Wid= th > (DmiThermSensWidthx1) >=20 > + UINT32 RsvdBits1 : 12; ///< Reserved bits >=20 > +} DMI_HW_WIDTH_CONTROL; >=20 > + >=20 > +/** >=20 > + This structure configures PCH memory throttling thermal sensor GPIO PI= N > settings >=20 > +**/ >=20 > +typedef struct { >=20 > + /** >=20 > + GPIO PM_SYNC enable, 0:Diabled, 1:Enabled >=20 > + When enabled, RC will overrides the selected GPIO native mode. >=20 > + For GPIO_C, PinSelection 0: CPU_GP_0 (default) or 1: CPU_GP_1 >=20 > + For GPIO_D, PinSelection 0: CPU_GP_3 (default) or 1: CPU_GP_2 >=20 > + For CNL: CPU_GP_0 is GPP_E3, CPU_GP_1 is GPP_E7, CPU_GP_2 is > GPP_B3, CPU_GP_3 is GPP_B4. >=20 > + **/ >=20 > + UINT32 PmsyncEnable : 1; >=20 > + UINT32 C0TransmitEnable : 1; ///< GPIO Transmit enable in C0 = state, > 0:Disabled, 1:Enabled >=20 > + UINT32 PinSelection : 1; ///< GPIO Pin assignment selecti= on, 0: > default, 1: secondary >=20 > + UINT32 RsvdBits0 : 29; >=20 > +} TS_GPIO_PIN_SETTING; >=20 > + >=20 > +enum PCH_PMSYNC_GPIO_X_SELECTION { >=20 > + TsGpioC, >=20 > + TsGpioD, >=20 > + MaxTsGpioPin >=20 > +}; >=20 > + >=20 > +/** >=20 > + This structure supports an external memory thermal sensor (TS-on-DIMM > or TS-on-Board). >=20 > +**/ >=20 > +typedef struct { >=20 > + /** >=20 > + This will enable PCH memory throttling. >=20 > + While this policy is enabled, must also enable EnableExtts in SA poli= cy. >=20 > + 0: Disable; 1: Enable >=20 > + **/ >=20 > + UINT32 Enable : 1; >=20 > + UINT32 RsvdBits0 : 31; >=20 > + /** >=20 > + GPIO_C and GPIO_D selection for memory throttling. >=20 > + It's strongly recommended to choose GPIO_C and GPIO_D for memory > throttling feature, >=20 > + and route EXTTS# accordingly. >=20 > + **/ >=20 > + TS_GPIO_PIN_SETTING TsGpioPinSetting[2]; >=20 > +} PCH_MEMORY_THROTTLING; >=20 > + >=20 > +/** >=20 > + The THERMAL_CONFIG block describes the expected configuration of the > Thermal IP block. >=20 > +**/ >=20 > +typedef struct { >=20 > + CONFIG_BLOCK_HEADER Header; ///< Config Block Header >=20 > + UINT32 PchHotEnable : 1; ///< Enable PCHHOT# pin assertio= n when > temperature is higher than PchHotLevel. 0: Disabled, 1: Enabled. >=20 > + UINT32 RsvdBits0 : 31; >=20 > + /** >=20 > + This field decides the settings of Thermal throttling. When the Sugg= ested > Setting >=20 > + is enabled, PCH RC will use the suggested representative values. >=20 > + **/ >=20 > + THERMAL_THROTTLE_LEVELS TTLevels; >=20 > + /** >=20 > + This field decides the settings of DMI throttling. When the Suggeste= d > Setting >=20 > + is enabled, PCH RC will use the suggested representative values. >=20 > + **/ >=20 > + DMI_HW_WIDTH_CONTROL DmiHaAWC; >=20 > + /** >=20 > + Memory Thermal Management settings >=20 > + **/ >=20 > + PCH_MEMORY_THROTTLING MemoryThrottling; >=20 > + /** >=20 > + The recommendation is the same as Cat Trip point. >=20 > + This field decides the temperature, default is 120. >=20 > + Temperature value used for PCHHOT# pin assertion based on 2s > complement format >=20 > + - 0x001 positive 1'C >=20 > + - 0x000 0'C >=20 > + - 0x1FF negative 1'C >=20 > + - 0x1D8 negative 40'C >=20 > + - and so on >=20 > + **/ >=20 > + UINT16 PchHotLevel; >=20 > + UINT8 Rsvd0[6]; >=20 > + >=20 > + >=20 > +} THERMAL_CONFIG; >=20 > + >=20 > +#pragma pack (pop) >=20 > + >=20 > +#endif // _THERMAL_CONFIG_H_ >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/TraceHub/TraceHub= C > onfig.h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/TraceHub/TraceHub > Config.h > new file mode 100644 > index 0000000000..9c315fb4a4 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/TraceHub/TraceHub > Config.h > @@ -0,0 +1,101 @@ > +/** @file >=20 > + Configurations for CPU and PCH trace hub >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _TRACE_HUB_CONFIG_H_ >=20 > +#define _TRACE_HUB_CONFIG_H_ >=20 > + >=20 > +#include >=20 > + >=20 > +#define CPU_TRACEHUB_PREMEM_CONFIG_REVISION 1 >=20 > +#define PCH_TRACEHUB_PREMEM_CONFIG_REVISION 1 >=20 > + >=20 > +extern EFI_GUID gPchTraceHubPreMemConfigGuid; >=20 > +extern EFI_GUID gCpuTraceHubPreMemConfigGuid; >=20 > + >=20 > +typedef enum { >=20 > + CpuTraceHub, >=20 > + PchTraceHub >=20 > +} TRACE_HUB_DEVICE; >=20 > +/// >=20 > +/// The TRACE_HUB_ENABLE_MODE describes TraceHub mode of > operation >=20 > +/// >=20 > +typedef enum { >=20 > + TraceHubModeDisabled =3D 0, >=20 > + TraceHubModeTargetDebugger =3D 1, >=20 > + TraceHubModeHostDebugger =3D 2, >=20 > + TraceHubModeMax >=20 > +} TRACE_HUB_ENABLE_MODE; >=20 > + >=20 > +/// >=20 > +/// The TRACE_BUFFER_SIZE describes the desired TraceHub buffer size >=20 > +/// >=20 > +typedef enum { >=20 > + TraceBufferNone, >=20 > + TraceBuffer1M, >=20 > + TraceBuffer8M, >=20 > + TraceBuffer64M, >=20 > + TraceBuffer128M, >=20 > + TraceBuffer256M, >=20 > + TraceBuffer512M, >=20 > + TraceBufferMax >=20 > +} TRACE_BUFFER_SIZE; >=20 > + >=20 > +#pragma pack (push,1) >=20 > +/// >=20 > +/// TRACE_HUB_CONFIG block describes TraceHub settings >=20 > +/// >=20 > +typedef struct { >=20 > + /** >=20 > + Trace hub mode. Default is disabled. >=20 > + Target Debugger mode refers to debug tool running on target device its= elf > and it works as a conventional PCI device; >=20 > + Host Debugger mode refers to SUT debugged via probe on host, > configured as ACPI device with PCI configuration sapce hidden. >=20 > + 0 =3D Disable; 1 =3D Target Debugger mode; 2 =3D Host Debugger = mode >=20 > + Refer to TRACE_HUB_ENABLE_MODE >=20 > + **/ >=20 > + UINT8 EnableMode; >=20 > + /** >=20 > + Trace hub memory buffer region size policy. >=20 > + The avaliable memory size options are: 0:0MB (none), 1:1MB, > 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB. >=20 > + Note : Limitation of total buffer size (CPU + PCH) is 512MB. If iTbt i= s > enabled, the total size limits to 256 MB. >=20 > + Refer to TRACE_BUFFER_SIZE >=20 > + **/ >=20 > + UINT8 MemReg0Size; >=20 > + UINT8 MemReg1Size; >=20 > + /** >=20 > + AET Trace. AET base address can be set to FW Base either from CPU trac= e > hub or PCH one. >=20 > + AetEnabled must be exclusive, if AetEnabled =3D 1 for CPU trace hub, m= ust > AetEnabled =3D 0 for PCH one. >=20 > + The default is set to PCH. >=20 > + CPU Trace Hub >=20 > + 0 =3D Disabled; 1 =3D Enabled >=20 > + PCH Trace Hub >=20 > + 0 =3D Disabled; 1 =3D Enabled >=20 > + **/ >=20 > + UINT8 AetEnabled; >=20 > +} TRACE_HUB_CONFIG; >=20 > + >=20 > +/** >=20 > + CPU Trace Hub PreMem Configuration >=20 > + Contains Trace Hub settings for CPU side tracing >=20 > + Revision 1: - Initial version. >=20 > +**/ >=20 > +typedef struct { >=20 > + CONFIG_BLOCK_HEADER Header; ///< Config Block Header >=20 > + TRACE_HUB_CONFIG TraceHub; ///< Trace Hub Config >=20 > +} CPU_TRACE_HUB_PREMEM_CONFIG; >=20 > + >=20 > +/** >=20 > + PCH Trace Hub PreMem Configuration >=20 > + Contains Trace Hub settings for PCH side tracing >=20 > + Revision 1: - Initial version. >=20 > +**/ >=20 > +typedef struct { >=20 > + CONFIG_BLOCK_HEADER Header; ///< Config Block Header >=20 > + TRACE_HUB_CONFIG TraceHub; ///< Trace Hub Config >=20 > +} PCH_TRACE_HUB_PREMEM_CONFIG; >=20 > + >=20 > +#pragma pack (pop) >=20 > + >=20 > +#endif >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Usb/Usb2PhyConfig= . > h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Usb/Usb2PhyConfig= . > h > new file mode 100644 > index 0000000000..99063103c3 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Usb/Usb2PhyConfig= . > h > @@ -0,0 +1,81 @@ > +/** @file >=20 > + USB2 PHY configuration policy >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _USB2_PHY_CONFIG_H_ >=20 > +#define _USB2_PHY_CONFIG_H_ >=20 > + >=20 > +#include >=20 > + >=20 > +#define USB2_PHY_CONFIG_REVISION 1 >=20 > +extern EFI_GUID gUsb2PhyConfigGuid; >=20 > + >=20 > +#pragma pack (push,1) >=20 > + >=20 > +/** >=20 > + This structure configures per USB2 AFE settings. >=20 > + It allows to setup the port electrical parameters. >=20 > +**/ >=20 > +typedef struct { >=20 > +/** Per Port HS Preemphasis Bias (PERPORTPETXISET) >=20 > + 000b - 0mV >=20 > + 001b - 11.25mV >=20 > + 010b - 16.9mV >=20 > + 011b - 28.15mV >=20 > + 100b - 28.15mV >=20 > + 101b - 39.35mV >=20 > + 110b - 45mV >=20 > + 111b - 56.3mV >=20 > +**/ >=20 > + UINT8 Petxiset; >=20 > +/** Per Port HS Transmitter Bias (PERPORTTXISET) >=20 > + 000b - 0mV >=20 > + 001b - 11.25mV >=20 > + 010b - 16.9mV >=20 > + 011b - 28.15mV >=20 > + 100b - 28.15mV >=20 > + 101b - 39.35mV >=20 > + 110b - 45mV >=20 > + 111b - 56.3mV >=20 > +**/ >=20 > + UINT8 Txiset; >=20 > +/** >=20 > + Per Port HS Transmitter Emphasis (IUSBTXEMPHASISEN) >=20 > + 00b - Emphasis OFF >=20 > + 01b - De-emphasis ON >=20 > + 10b - Pre-emphasis ON >=20 > + 11b - Pre-emphasis & De-emphasis ON >=20 > +**/ >=20 > + UINT8 Predeemp; >=20 > +/** >=20 > + Per Port Half Bit Pre-emphasis (PERPORTTXPEHALF) >=20 > + 1b - half-bit pre-emphasis >=20 > + 0b - full-bit pre-emphasis >=20 > +**/ >=20 > + UINT8 Pehalfbit; >=20 > +} USB2_PHY_PARAMETERS; >=20 > + >=20 > +/** >=20 > + This structure holds info on how to tune electrical parameters of USB2 > ports based on board layout >=20 > + >=20 > + Revision 1: >=20 > + - Initial version. >=20 > + >=20 > +**/ >=20 > +typedef struct { >=20 > + CONFIG_BLOCK_HEADER Header; ///< Config Block He= ader >=20 > + /** >=20 > + This structure configures per USB2 port physical settings. >=20 > + It allows to setup the port location and port length, and configures= the > port strength accordingly. >=20 > + Changing this policy values from default ones may require disabling = USB2 > PHY Sus Well Power Gating >=20 > + through Usb2PhySusPgEnable on PCH-LP >=20 > + **/ >=20 > + USB2_PHY_PARAMETERS Port[MAX_USB2_PORTS]; >=20 > +} USB2_PHY_CONFIG; >=20 > + >=20 > +#pragma pack (pop) >=20 > + >=20 > +#endif // _USB2_PHY_CONFIG_H_ >=20 > + >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Usb/Usb3HsioConfi= g. > h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Usb/Usb3HsioConfi= g > .h > new file mode 100644 > index 0000000000..da816b1378 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Usb/Usb3HsioConfi= g > .h > @@ -0,0 +1,138 @@ > +/** @file >=20 > + USB3 Mod PHY configuration policy >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +#ifndef _USB3_HSIO_CONFIG_H_ >=20 > +#define _USB3_HSIO_CONFIG_H_ >=20 > + >=20 > +#include >=20 > + >=20 > +#define USB3_HSIO_CONFIG_REVISION 2 >=20 > +extern EFI_GUID gUsb3HsioConfigGuid; >=20 > + >=20 > +#pragma pack (push,1) >=20 > + >=20 > +/** >=20 > + This structure describes USB3 Port N configuration parameters >=20 > +**/ >=20 > +typedef struct { >=20 > + /** >=20 > + USB 3.0 TX Output Downscale Amplitude Adjustment (orate01margin) >=20 > + HSIO_TX_DWORD8[21:16] >=20 > + Default =3D 00h >=20 > + **/ >=20 > + UINT8 HsioTxDownscaleAmp; >=20 > + /** >=20 > + USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting > (ow2tapgen2deemph3p5) >=20 > + HSIO_TX_DWORD5[21:16] >=20 > + Default =3D 29h (approximately -3.5dB De-Emphasis) >=20 > + **/ >=20 > + UINT8 HsioTxDeEmph; >=20 > + /** >=20 > + Signed Magnatude number added to the CTLE > code.(ctle_adapt_offset_cfg_4_0) >=20 > + HSIO_RX_DWORD25 [20:16] >=20 > + Ex: -1 -- 1_0001. +1: 0_0001 >=20 > + Default =3D 0h >=20 > + **/ >=20 > + UINT8 HsioCtrlAdaptOffsetCfg; >=20 > + /** >=20 > + LFPS filter select for n (filter_sel_n_2_0) >=20 > + HSIO_RX_DWORD51 [29:27] >=20 > + 0h:1.6ns >=20 > + 1h:2.4ns >=20 > + 2h:3.2ns >=20 > + 3h:4.0ns >=20 > + 4h:4.8ns >=20 > + 5h:5.6ns >=20 > + 6h:6.4ns >=20 > + Default =3D 0h >=20 > + **/ >=20 > + UINT8 HsioFilterSelN; >=20 > + /** >=20 > + LFPS filter select for p (filter_sel_p_2_0) >=20 > + HSIO_RX_DWORD51 [26:24] >=20 > + 0h:1.6ns >=20 > + 1h:2.4ns >=20 > + 2h:3.2ns >=20 > + 3h:4.0ns >=20 > + 4h:4.8ns >=20 > + 5h:5.6ns >=20 > + 6h:6.4ns >=20 > + Default =3D 0h >=20 > + **/ >=20 > + UINT8 HsioFilterSelP; >=20 > + /** >=20 > + Controls the input offset (olfpscfgpullupdwnres_sus_usb_2_0) >=20 > + HSIO_RX_DWORD51 [2:0] >=20 > + 000 Prohibited >=20 > + 001 45K >=20 > + 010 Prohibited >=20 > + 011 31K >=20 > + 100 36K >=20 > + 101 36K >=20 > + 110 36K >=20 > + 111 36K >=20 > + Default =3D 3h >=20 > + **/ >=20 > + UINT8 HsioOlfpsCfgPullUpDwnRes; >=20 > + >=20 > + UINT8 HsioTxDeEmphEnable; ///< Enable the write to USB 3.= 0 TX > Output -3.5dB De-Emphasis Adjustment, 0: Disable; 1: Enable. >=20 > + UINT8 HsioTxDownscaleAmpEnable; ///< Enable the write to USB 3.= 0 > TX Output Downscale Amplitude Adjustment, 0: Disable; 1: Enable. >=20 > + UINT8 HsioCtrlAdaptOffsetCfgEnable; ///< Enable the write to Signed > Magnatude number added to the CTLE code, 0: Disable; 1: Enable. >=20 > + UINT8 HsioFilterSelNEnable; ///< Enable the write to LFPS f= ilter select > for n, 0: Disable; 1: Enable. >=20 > + UINT8 HsioFilterSelPEnable; ///< Enable the write to LFPS f= ilter select > for p, 0: Disable; 1: Enable. >=20 > + UINT8 HsioOlfpsCfgPullUpDwnResEnable; ///< Enable the write to > olfpscfgpullupdwnres, 0: Disable; 1: Enable. >=20 > + /** >=20 > + USB 3.0 TX Output - Unique Transition Bit Scale for rate 3 > (rate3UniqTranScale) >=20 > + HSIO_TX_DWORD9[6:0] >=20 > + Default =3D 4Ch >=20 > + **/ >=20 > + UINT8 HsioTxRate3UniqTran; >=20 > + /** >=20 > + USB 3.0 TX Output -Unique Transition Bit Scale for rate 2 > (rate2UniqTranScale) >=20 > + HSIO_TX_DWORD9[14:8] >=20 > + Default =3D 4Ch >=20 > + **/ >=20 > + UINT8 HsioTxRate2UniqTran; >=20 > + /** >=20 > + USB 3.0 TX Output - Unique Transition Bit Scale for rate 1 > (rate1UniqTranScale) >=20 > + HSIO_TX_DWORD9[22:16] >=20 > + Default =3D 4Ch >=20 > + **/ >=20 > + UINT8 HsioTxRate1UniqTran; >=20 > + /** >=20 > + USB 3.0 TX Output - Unique Transition Bit Scale for rate 0 > (rate0UniqTranScale) >=20 > + HSIO_TX_DWORD9[30:24] >=20 > + Default =3D 4Ch >=20 > + **/ >=20 > + UINT8 HsioTxRate0UniqTran; >=20 > + >=20 > + UINT8 HsioTxRate3UniqTranEnable; ///< Enable the write to USB 3.0 TX > Unique Transition Bit Mode for rate 3, 0: Disable; 1: Enable. >=20 > + UINT8 HsioTxRate2UniqTranEnable; ///< Enable the write to USB 3.0 TX > Unique Transition Bit Mode for rate 2, 0: Disable; 1: Enable. >=20 > + UINT8 HsioTxRate1UniqTranEnable; ///< Enable the write to USB 3.0 TX > Unique Transition Bit Mode for rate 1, 0: Disable; 1: Enable. >=20 > + UINT8 HsioTxRate0UniqTranEnable; ///< Enable the write to USB 3.0 TX > Unique Transition Bit Mode for rate 0, 0: Disable; 1: Enable. >=20 > +} HSIO_PARAMETERS; >=20 > + >=20 > +/** >=20 > + Structure for holding USB3 tuning parameters >=20 > + >=20 > + Revision 1: >=20 > + - Initial version. >=20 > + Revision 2: >=20 > + - USB 3.0 TX Output Unique Transition Bit Scale policies added >=20 > +**/ >=20 > +typedef struct { >=20 > + CONFIG_BLOCK_HEADER Header; ///< Config Block He= ader >=20 > + /** >=20 > + These members describe whether the USB3 Port N of PCH is enabled by > platform modules. >=20 > + **/ >=20 > + HSIO_PARAMETERS Port[MAX_USB3_PORTS]; >=20 > +} USB3_HSIO_CONFIG; >=20 > + >=20 > +#pragma pack (pop) >=20 > + >=20 > +#endif // _USB3_HSIO_CONFIG_H_ >=20 > + >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Usb/UsbConfig.h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Usb/UsbConfig.h > new file mode 100644 > index 0000000000..a1c7f0bb04 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Usb/UsbConfig.h > @@ -0,0 +1,149 @@ > +/** @file >=20 > + Common USB policy shared between PCH and CPU >=20 > + Contains general features settings for xHCI and xDCI >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _USB_CONFIG_H_ >=20 > +#define _USB_CONFIG_H_ >=20 > + >=20 > +#define USB_CONFIG_REVISION 2 >=20 > +extern EFI_GUID gUsbConfigGuid; >=20 > + >=20 > +#define MAX_USB2_PORTS 16 >=20 > +#define MAX_USB3_PORTS 10 >=20 > + >=20 > +#pragma pack (push,1) >=20 > + >=20 > +typedef UINT8 USB_OVERCURRENT_PIN; >=20 > +#define USB_OC_SKIP 0xFF >=20 > +#define USB_OC_MAX_PINS 16 ///< Total OC pins number (both > physical and virtual) >=20 > + >=20 > +/** >=20 > + This structure configures per USB2.0 port settings like enabling and > overcurrent protection >=20 > +**/ >=20 > +typedef struct { >=20 > + /** >=20 > + These members describe the specific over current pin number of USB 2= .0 > Port N. >=20 > + It is SW's responsibility to ensure that a given port's bit map is s= et only for >=20 > + one OC pin Description. USB2 and USB3 on the same combo Port must > use the same OC pin. >=20 > + **/ >=20 > + UINT32 OverCurrentPin : 8; >=20 > + UINT32 Enable : 1; ///< 0: Disable; 1: En= able. >=20 > + UINT32 PortResetMessageEnable : 1; ///< 0: Disable USB2 Port= Reset > Message; 1: Enable USB2 Port Reset Message >=20 > + UINT32 RsvdBits0 : 22; ///< Reserved bits >=20 > +} USB2_PORT_CONFIG; >=20 > + >=20 > +/** >=20 > + This structure configures per USB3.x port settings like enabling and > overcurrent protection >=20 > +**/ >=20 > +typedef struct { >=20 > + /** >=20 > + These members describe the specific over current pin number of USB 3= .x > Port N. >=20 > + It is SW's responsibility to ensure that a given port's bit map is s= et only for >=20 > + one OC pin Description. USB2 and USB3 on the same combo Port must > use the same OC pin. >=20 > + **/ >=20 > + UINT32 OverCurrentPin : 8; >=20 > + UINT32 Enable : 1; ///< 0: Disable; 1: Enab= le. >=20 > + UINT32 RsvdBits0 : 23; ///< Reserved bits >=20 > +} USB3_PORT_CONFIG; >=20 > + >=20 > +/** >=20 > + The XDCI_CONFIG block describes the configurations >=20 > + of the xDCI Usb Device controller. >=20 > +**/ >=20 > +typedef struct { >=20 > + /** >=20 > + This member describes whether or not the xDCI controller should be > enabled. >=20 > + 0: Disable; 1: Enable. >=20 > + **/ >=20 > + UINT32 Enable : 1; >=20 > + UINT32 RsvdBits0 : 31; ///< Reserved bits >=20 > +} XDCI_CONFIG; >=20 > + >=20 > + >=20 > +/** >=20 > + This member describes the expected configuration of the USB controller= , >=20 > + Platform modules may need to refer Setup options, schematic, BIOS > specification to update this field. >=20 > + The Usb20OverCurrentPins and Usb30OverCurrentPins field must be > updated by referring the schematic. >=20 > + >=20 > + Revision 1: - Initial version. >=20 > + Revision 2: - Add USB3LinkSpeed >=20 > +**/ >=20 > +typedef struct { >=20 > + CONFIG_BLOCK_HEADER Header; ///< Config Block He= ader >=20 > + /** >=20 > + This policy option when set will make BIOS program Port Disable Over= ride > register during PEI phase. >=20 > + When disabled BIOS will not program the PDO during PEI phase and lea= ve > PDO register unlocked for later programming. >=20 > + If this is disabled, platform code MUST set it before booting into O= S. >=20 > + 1: Enable >=20 > + 0: Disable >=20 > + **/ >=20 > + UINT32 PdoProgramming : 1; >=20 > + /** >=20 > + This option allows for control whether USB should program the > Overcurrent Pins mapping into xHCI. >=20 > + Disabling this feature will disable overcurrent detection functional= ity. >=20 > + Overcurrent Pin mapping data is contained in respective port structu= res > (i.e. USB30_PORT_CONFIG) in OverCurrentPin field. >=20 > + By default this Overcurrent functionality should be enabled and disa= bled > only for OBS debug usage. >=20 > + 1: Will program USB OC pin mapping in respective xHCI controller > registers >=20 > + 0: Will clear OC pin mapping allow for OBS usage of OC pins >=20 > + **/ >=20 > + UINT32 OverCurrentEnable : 1; >=20 > + /** >=20 > + (Test) >=20 > + If this policy option is enabled then BIOS will program OCCFDONE bit= in > xHCI meaning that OC mapping data will be >=20 > + consumed by xHCI and OC mapping registers will be locked. OverCurren= t > mapping data is taken from respective port data >=20 > + structure from OverCurrentPin field. >=20 > + If EnableOverCurrent policy is enabled this also should be enabled, > otherwise xHCI won't consume OC mapping data. >=20 > + 1: Program OCCFDONE bit and make xHCI consume OverCurrent > mapping data >=20 > + 0: Do not program OCCFDONE bit making it possible to use OBS debug o= n > OC pins. >=20 > + **/ >=20 > + UINT32 XhciOcLock : 1; >=20 > + /** >=20 > + Enabling this feature will allow for overriding LTR values for xHCI > controller. >=20 > + Values used for programming will be taken from this config block and > BIOS will disregard recommended ones. >=20 > + 0: disable - do not override recommended LTR values >=20 > + 1: enable - override recommended LTR values >=20 > + **/ >=20 > + UINT32 LtrOverrideEnable : 1; >=20 > + /** >=20 > + This setting enable LBPM GEN1 speed >=20 > + 0: GEN2; >=20 > + 1: GEN1; >=20 > + **/ >=20 > + UINT32 USB3LinkSpeed : 1; >=20 > + UINT32 RsvdBits0 : 27; ///< Re= served bits >=20 > + /** >=20 > + High Idle Time Control override value >=20 > + This setting is used only if LtrOverrideEnable is enabled >=20 > + **/ >=20 > + UINT32 LtrHighIdleTimeOverride; >=20 > + /** >=20 > + Medium Idle Time Control override value >=20 > + This setting is used only if LtrOverrideEnable is enabled >=20 > + **/ >=20 > + UINT32 LtrMediumIdleTimeOverride; >=20 > + /** >=20 > + Low Idle Time Control override value >=20 > + This setting is used only if LtrOverrideEnable is enabled >=20 > + **/ >=20 > + UINT32 LtrLowIdleTimeOverride; >=20 > + /** >=20 > + These members describe whether the USB2 Port N of PCH is enabled by > platform modules. >=20 > + **/ >=20 > + USB2_PORT_CONFIG PortUsb20[MAX_USB2_PORTS]; >=20 > + /** >=20 > + These members describe whether the USB3 Port N of PCH is enabled by > platform modules. >=20 > + **/ >=20 > + USB3_PORT_CONFIG PortUsb30[MAX_USB3_PORTS]; >=20 > + /** >=20 > + This member describes whether or not the xDCI controller should be > enabled. >=20 > + **/ >=20 > + XDCI_CONFIG XdciConfig; >=20 > + >=20 > +} USB_CONFIG; >=20 > + >=20 > +#pragma pack (pop) >=20 > + >=20 > +#endif // _USB_CONFIG_H_ >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/VoltageRegulator/= Cp > uPowerMgmtVrConfig.h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/VoltageRegulator/= Cp > uPowerMgmtVrConfig.h > new file mode 100644 > index 0000000000..8b01ecd262 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/VoltageRegulator/= Cp > uPowerMgmtVrConfig.h > @@ -0,0 +1,114 @@ > +/** @file >=20 > + CPU Power Management VR Config Block. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _CPU_POWER_MGMT_VR_CONFIG_H_ >=20 > +#define _CPU_POWER_MGMT_VR_CONFIG_H_ >=20 > + >=20 > +#define CPU_POWER_MGMT_VR_CONFIG_REVISION 7 >=20 > + >=20 > +extern EFI_GUID gCpuPowerMgmtVrConfigGuid; >=20 > + >=20 > +#pragma pack (push,1) >=20 > + >=20 > +/// >=20 > +/// Defines the maximum number of VR domains supported. >=20 > +/// @warning: Changing this define would cause DWORD alignment issues > in policy structures. >=20 > +/// >=20 > +#define MAX_NUM_VRS 5 >=20 > + >=20 > +/** >=20 > + CPU Power Management VR Configuration Structure. >=20 > + >=20 > + Revision 1: >=20 > + - Initial version. >=20 > + Revision 2: >=20 > + - Updated Acoustic Noise Mitigation. >=20 > + Revision 3: >=20 > + - Deprecate PsysOffset and added PsysOffset1 for Psys Offset Correctio= n >=20 > + Revision 4: >=20 > + - Deprecate TdcTimeWindow and added TdcTimeWindow1 for TDC Time >=20 > + Added Irms support. >=20 > + Revision 5: >=20 > + - Add RfiMitigation. >=20 > + Revision 6: >=20 > + - Added an option to Enable/Disable FIVR Spread Spectrum >=20 > + Revision 7: >=20 > + - Add Dynamic Periodicity Alteration (DPA) tuning feature >=20 > +**/ >=20 > +typedef struct { >=20 > + CONFIG_BLOCK_HEADER Header; ///< Config Block Head= er >=20 > + UINT32 AcousticNoiseMitigation : 1; ///< Enable or Disable= Acoustic > Noise Mitigation feature. 0: Disabled; 1: Enabled >=20 > + /** >=20 > + VR specific mailbox commands. >=20 > + 00b - no VR specific command sent. >=20 > + 01b - A VR mailbox command specifically for the MPS IMPV8 VR will be > sent. >=20 > + 10b - VR specific command sent for PS4 exit issue. >=20 > + 11b - Reserved. >=20 > + **/ >=20 > + UINT32 SendVrMbxCmd : 2; >=20 > + UINT32 EnableMinVoltageOverride : 1; ///< Enable or disable > Minimum Voltage override for minimum voltage runtime and minimum > voltage C8. 0: Disabled 1: Enabled. >=20 > + UINT32 RfiMitigation : 1; ///< Enable or Disable= RFI Mitigation. > 0: Disable - DCM is the IO_N default; 1: Enable - Enable IO_N > DCM/CCM switching as RFI mitigation. >=20 > + UINT32 RsvdBits : 27; ///< Reserved for futu= re use. >=20 > + UINT8 PsysSlope; ///< PCODE MMIO Mailbo= x: Platform > Psys slope correction. 0: Auto Specified in 1/100 increment values= . > Range is 0-200. 125 =3D 1.25. >=20 > + UINT8 PsysOffset; ///< PCODE MMIO Mailbo= x: Platform > Psys offset correction. 0: Auto Units 1/4, Range 0-255. Value of 1= 00 =3D > 100/4 =3D 25 offset. Deprecated >=20 > + UINT8 FivrSpreadSpectrum; ///< Set the Spread Sp= ectrum > Range. 1.5%, Range: 0.5%, 1%, 1.5%, 2%, 3%, 4%, 5%, 6%. Each > Range is translated to internally encoded values. 0.5% =3D 0, 1% =3D 3, 1= .5% =3D 8, > 2% =3D 18, 3% =3D 28, 4% =3D 34, 5% =3D 39, 6% =3D 44. >=20 > + UINT8 RsvdBytes0; >=20 > + /** >=20 > + PCODE MMIO Mailbox: Set the desired RFI frequency, in increments of > 100KHz. >=20 > + 0: Auto >=20 > + Range varies based on XTAL clock: >=20 > + - 0-1918 (Up to 191.8HMz) for 24MHz clock. >=20 > + - 0-1535 (Up to 153.5MHz) for 19MHz clock. >=20 > + **/ >=20 > + UINT16 FivrRfiFrequency; >=20 > + UINT8 RsvdBytes1[2]; >=20 > + /** @name VR Settings >=20 > + The VR related settings are sorted in an array where each index maps t= o > the VR domain as defined below: >=20 > + - 0 =3D System Agent VR >=20 > + - 1 =3D IA Core VR >=20 > + - 2 =3D Ring Vr >=20 > + - 3 =3D GT VR >=20 > + - 4 =3D FIVR VR >=20 > + >=20 > + The VR settings for a given domain must be populated in the appropriat= e > index. >=20 > + **/ >=20 > + ///@{ >=20 > + UINT16 TdcCurrentLimit[MAX_NUM_VRS]; ///< PCODE MMIO > Mailbox: Thermal Design Current current limit. Specified in 1/8A units. R= ange > is 0-4095. 1000 =3D 125A. 0: 0 Amps >=20 > + UINT16 AcLoadline[MAX_NUM_VRS]; ///< PCODE MMIO Mailbo= x: > AcLoadline in 1/100 mOhms (ie. 1250 =3D 12.50 mOhm); Range is 0-6249. > Intel Recommended Defaults vary by domain and SKU. >=20 > + UINT16 DcLoadline[MAX_NUM_VRS]; ///< PCODE MMIO Mailbo= x: > DcLoadline in 1/100 mOhms (ie. 1250 =3D 12.50 mOhm); Range is 0- > 6249.Intel Recommended Defaults vary by domain and SKU. >=20 > + UINT16 Psi1Threshold[MAX_NUM_VRS]; ///< PCODE MMIO > Mailbox: Power State 1 current cuttof in 1/4 Amp increments. Range is 0- > 128A. >=20 > + UINT16 Psi2Threshold[MAX_NUM_VRS]; ///< PCODE MMIO > Mailbox: Power State 2 current cuttof in 1/4 Amp increments. Range is 0- > 128A. >=20 > + UINT16 Psi3Threshold[MAX_NUM_VRS]; ///< PCODE MMIO > Mailbox: Power State 3 current cuttof in 1/4 Amp increments. Range is 0- > 128A. >=20 > + INT16 ImonOffset[MAX_NUM_VRS]; ///< PCODE MMIO Mailbo= x: > Imon offset correction. Value is a 2's complement signed integer. Units > 1/1000, Range 0-63999. For an offset =3D 12.580, use 12580. 0: Auto >=20 > + UINT16 IccMax[MAX_NUM_VRS]; ///< PCODE MMIO Mailbo= x: > VR Icc Max limit. 0-255A in 1/4 A units. 400 =3D 100A. Default: 0 - Au= to, no > override >=20 > + UINT16 VrVoltageLimit[MAX_NUM_VRS]; ///< PCODE MMIO > Mailbox: VR Voltage Limit. Range is 0-7999mV. >=20 > + UINT16 ImonSlope[MAX_NUM_VRS]; ///< PCODE MMIO Mailbo= x: > Imon slope correction. Specified in 1/100 increment values. Range is 0-20= 0. > 125 =3D 1.25. 0: Auto >=20 > + UINT8 Psi3Enable[MAX_NUM_VRS]; ///< PCODE MMIO Mailbo= x: > Power State 3 enable/disable; 0: Disable; 1: Enable. >=20 > + UINT8 Psi4Enable[MAX_NUM_VRS]; ///< PCODE MMIO Mailbo= x: > Power State 4 enable/disable; 0: Disable; 1: Enable. >=20 > + UINT8 VrConfigEnable[MAX_NUM_VRS]; ///< Enable/Disable BI= OS > configuration of VR; 0: Disable; 1: Enable. >=20 > + UINT8 TdcEnable[MAX_NUM_VRS]; ///< PCODE MMIO Mailbo= x: > Thermal Design Current enable/disable; 0: Disable; 1: Enable >=20 > + UINT8 TdcTimeWindow[MAX_NUM_VRS]; ///< @deprecated. > PCODE MMIO Mailbox: Thermal Design Current time window. Defined in milli > seconds. 1ms default >=20 > + UINT8 TdcLock[MAX_NUM_VRS]; ///< PCODE MMIO Mailbo= x: > Thermal Design Current Lock; 0: Disable; 1: Enable. >=20 > + UINT8 FastPkgCRampDisable[MAX_NUM_VRS]; ///< Disable Fast Slew > Rate for Deep Package C States for VR IA,GT,SA,VLCC,FIVR domain based on > Acoustic Noise Mitigation feature enabled. 0: False; 1: True >=20 > + UINT8 SlowSlewRate[MAX_NUM_VRS]; ///< Slew Rate > configuration for Deep Package C States for VR VR IA,GT,SA,VLCC,FIVR > domain based on Acoustic Noise Mitigation feature enabled. 0: > Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16 >=20 > + ///@} >=20 > + UINT16 MinVoltageRuntime; ///< PCODE MMIO Mailbo= x: > Minimum voltage for runtime. Valid if EnableMinVoltageOverride =3D 1 .Ran= ge > 0 to 1999mV. 0: 0mV >=20 > + UINT16 MinVoltageC8; ///< PCODE MMIO Mailbo= x: Minimum > voltage for C8. Valid if EnableMinVoltageOverride =3D 1. Range 0 to 1999m= V. > 0: 0mV >=20 > + UINT16 PsysOffset1; ///< PCODE MMIO Mailbo= x: Platform > Psys offset correction. 0: Auto Units 1/1000, Range 0-63999. For a= n > offset of 25.348, enter 25348. >=20 > + UINT8 RsvdBytes2[2]; >=20 > + UINT32 TdcTimeWindow1[MAX_NUM_VRS]; ///< PCODE MMIO > Mailbox: Thermal Design Current time window. Defined in milli seconds. > 1ms default >=20 > + UINT8 Irms[MAX_NUM_VRS]; ///< PCODE MMIO Mailbo= x: > Current root mean square. 0: Disable; 1: Enable. >=20 > + UINT8 FivrSpectrumEnable; ///< Enable or Disable= FIVR Spread > Spectrum 0: Disable; 1: Enable. >=20 > + UINT8 Rsvd1[2]; >=20 > + UINT8 PreWake; ///< PCODE MMIO Mailbo= x: Acoustic > Noise Mitigation Range. This can be programmed only if > AcousticNoiseMitigation is enabled.Default Value =3D 0 micro ticks > Defines the max pre-wake randomization time in micro ticks. Range is 0-25= 5. >=20 > + UINT8 RampUp; ///< PCODE MMIO Mailbo= x: Acoustic > Noise Mitigation Range. This can be programmed only if > AcousticNoiseMitigation is enabled.Default Value =3D 0 micro ticks > Defines the max ramp up randomization time in micro ticks. Range is 0-255= . >=20 > + UINT8 RampDown; ///< PCODE MMIO Mailbo= x: Acoustic > Noise Mitigation Range. This can be programmed only if > AcousticNoiseMitigation is enabled.Default Value =3D 0 micro ticks > Defines the max ramp down randomization time in micro ticks. Range is 0- > 255. >=20 > + UINT8 Rsvd2[1]; >=20 > +} CPU_POWER_MGMT_VR_CONFIG; >=20 > + >=20 > +#pragma pack (pop) >=20 > + >=20 > +#endif // _CPU_POWER_MGMT_VR_CONFIG_H_ >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Vtd/VtdConfig.h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Vtd/VtdConfig.h > new file mode 100644 > index 0000000000..74ca983a5d > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Vtd/VtdConfig= .h > @@ -0,0 +1,64 @@ > +/** @file >=20 > + VT-d policy definitions. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _VTD_CONFIG_H_ >=20 > +#define _VTD_CONFIG_H_ >=20 > + >=20 > +#include >=20 > +#pragma pack(push, 1) >=20 > + >=20 > +#define VTD_CONFIG_REVISION 1 >=20 > +#define VTD_DXE_CONFIG_REVISION 2 >=20 > + >=20 > +/** >=20 > + The data elements should be initialized by a Platform Module. >=20 > + The data structure is for VT-d driver initialization\n >=20 > + Revision 1: >=20 > + - Initial version. >=20 > +**/ >=20 > +typedef struct { >=20 > + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Con= fig Block > Header >=20 > + /** >=20 > + Offset 28: >=20 > + VT-D Support can be verified by reading CAP ID register as expalined= in > BIOS Spec. >=20 > + This policy is for debug purpose only. >=20 > + If VT-D is not supported, all other policies in this config block wi= ll be > ignored. >=20 > + 0 =3D To use Vt-d; >=20 > + 1 =3D Avoids programming Vtd bars, Vtd overrides and DMAR table. >=20 > + **/ >=20 > + UINT8 VtdDisable; >=20 > + UINT8 X2ApicOptOut; ///< Offset 29 :This field is used t= o enable the > X2APIC_OPT_OUT bit in the DMAR table. 1=3DEnable/Set and > 0=3DDisable/Clear >=20 > + UINT8 DmaControlGuarantee; ///< Offset 30 :This field is used t= o > enable the DMA_CONTROL_GUARANTEE bit in the DMAR table. > 1=3DEnable/Set and 0=3DDisable/Clear >=20 > + UINT8 VtdIgdEnable; ///< Offset 31 :This field is used t= o enable the > VtdIgdEnable Policy. 1=3DEnable/Set and 0=3DDisable/Clear >=20 > + UINT8 VtdIpuEnable; ///< Offset 32 :This field is used t= o enable the > VtdIpuEnable Policy. 1=3DEnable/Set and 0=3DDisable/Clear >=20 > + UINT8 VtdIopEnable; ///< Offset 33 :This field is used t= o enable the > VtdIopEnable Policy. 1=3DEnable/Set and 0=3DDisable/Clear >=20 > + UINT8 VtdItbtEnable; ///< Offset 34 :This field is used t= o enable the > VtdItbtEnable Policy. 1=3DEnable/Set and 0=3DDisable/Clear >=20 > + UINT8 PreBootDmaMask; ///< Offset 35 :Convey > PcdVTdPolicyPropertyMask value from EDK2 IntelSiliconPkg >=20 > + /** >=20 > + Offset 36: >=20 > + This field is used to describe the base addresses for VT-d function:= \n >=20 > + VTD BAR for Gfx if IGfx is supported : BaseAddress[0]=3D0xFED9000= 0,\n >=20 > + VTD BAR for IPU if IPU is supporrted : BaseAddress[1]=3D0xFED92000,\= n >=20 > + VTD BAR for other DMA Agents (except Igfx and IPU) : > BaseAddress[2]=3D0xFED91000,\n >=20 > + VTD BAR for iTBT if iTBT is supported : BaseAddress[3]=3D0xFED84000, > BaseAddress[4]=3D0xFED85000, > BaseAddress[5]=3D0xFED86000,BaseAddress[6]=3D0xFED87000 >=20 > + **/ >=20 > + UINT32 BaseAddress[VTD_ENGINE_NUMBER]; >=20 > + UINT32 DmaBufferSize; ///< Offset 64 :Protect Memory Region > (PMR) DMA buffer size >=20 > + >=20 > + >=20 > +} VTD_CONFIG; >=20 > + >=20 > +/** >=20 > + The data structure is for VT-d driver initialization in DXE\n >=20 > + Revision 1: >=20 > + - Initial version. >=20 > +**/ >=20 > +typedef struct { >=20 > + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Conf= ig Block > Header >=20 > +} VTD_DXE_CONFIG; >=20 > +#pragma pack(pop) >=20 > + >=20 > +#endif // _VTD_CONFIG_H_ >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Wdt/WatchDogConfi > g.h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Wdt/WatchDogConfi > g.h > new file mode 100644 > index 0000000000..8766762580 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Wdt/WatchDogConfi > g.h > @@ -0,0 +1,31 @@ > +/** @file >=20 > + WatchDog policy >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _WATCH_DOG_CONFIG_H_ >=20 > +#define _WATCH_DOG_CONFIG_H_ >=20 > + >=20 > +#define WATCH_DOG_PREMEM_CONFIG_REVISION 1 >=20 > +extern EFI_GUID gWatchDogPreMemConfigGuid; >=20 > + >=20 > +#pragma pack (push,1) >=20 > + >=20 > +/** >=20 > + This policy clears status bits and disable watchdog, then lock the >=20 > + WDT registers. >=20 > + while WDT is designed to be disabled and locked by Policy, >=20 > + bios should not enable WDT by WDT PPI. In such case, bios shows the >=20 > + warning message but not disable and lock WDT register to make sure >=20 > + WDT event trigger correctly. >=20 > +**/ >=20 > +typedef struct { >=20 > + CONFIG_BLOCK_HEADER Header; ///< Config Block Header >=20 > + UINT32 DisableAndLock : 1; ///< (Test) Set 1 to clea= r WDT > status, then disable and lock WDT registers. 0: Disable; 1: Enable= . >=20 > + UINT32 RsvdBits : 31; >=20 > +} PCH_WDT_PREMEM_CONFIG; >=20 > + >=20 > +#pragma pack (pop) >=20 > + >=20 > +#endif // _WATCH_DOG_CONFIG_H_ >=20 > diff --git a/Silicon/Intel/TigerlakeSiliconPkg/SiPkg.dec > b/Silicon/Intel/TigerlakeSiliconPkg/SiPkg.dec > new file mode 100644 > index 0000000000..0982758b77 > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/SiPkg.dec > @@ -0,0 +1,1208 @@ > +## @file >=20 > +# Component description file for the Silicon Reference Code. >=20 > +# >=20 > +# Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > +# SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +# >=20 > +## >=20 > + >=20 > + >=20 > +[Defines] >=20 > +DEC_SPECIFICATION =3D 0x00010017 >=20 > +PACKAGE_NAME =3D SiPkg >=20 > +PACKAGE_VERSION =3D 0.1 >=20 > +PACKAGE_GUID =3D F245E276-44A0-46b3-AEB5-9898BBCF008D >=20 > + >=20 > +[Includes.Common.Private] >=20 > + >=20 > +# >=20 > +# TigerLake Fru >=20 > +# >=20 > +Fru/TglCpu/IncludePrivate >=20 > +Fru/TglPch/IncludePrivate >=20 > + >=20 > +## >=20 > +# IpBlock IncludePrivate >=20 > +# >=20 > +IpBlock/Psf/IncludePrivate >=20 > +IpBlock/Pmc/IncludePrivate >=20 > +IpBlock/Smbus/IncludePrivate >=20 > +IpBlock/Graphics/IncludePrivate >=20 > +IpBlock/CpuPcieRp/IncludePrivate >=20 > +IpBlock/Hda/IncludePrivate >=20 > +IpBlock/PchDmi/IncludePrivate >=20 > +IpBlock/P2sb/IncludePrivate >=20 > +IpBlock/Spi/IncludePrivate >=20 > +IpBlock/Gpio/IncludePrivate >=20 > +IpBlock/Cnvi/IncludePrivate >=20 > +IpBlock/Gbe/IncludePrivate >=20 > +IpBlock/PcieRp/IncludePrivate >=20 > +IpBlock/Vtd/IncludePrivate >=20 > +IpBlock/HostBridge/IncludePrivate >=20 > +IpBlock/SerialIo/IncludePrivate >=20 > + >=20 > +SystemAgent/IncludePrivate >=20 > + >=20 > +Pch/IncludePrivate >=20 > + >=20 > +[Includes] >=20 > +# >=20 > +# TigerLake >=20 > +# >=20 > +Fru/TglCpu/Include >=20 > +Fru/TglPch/Include >=20 > + >=20 > +# CPU PCIe >=20 > +IpBlock/CpuPcieRp/Include >=20 > + >=20 > +IpBlock/Gpio/Include >=20 > + >=20 > + >=20 > +## >=20 > +# >=20 > +# This section is for IP ConfigBlock versions control >=20 > +# >=20 > +# - Memory >=20 > +Include/ConfigBlock/Memory/Ver2 >=20 > +# >=20 > +# - Graphics >=20 > +Include/ConfigBlock/Graphics/Gen12 >=20 > +# >=20 > +# - CPU PCIe >=20 > +Include/ConfigBlock/CpuPcieRp/Gen4 >=20 > +Include/ConfigBlock/CpuDmi >=20 > + >=20 > +# - Hybrid Graphics >=20 > +Include/ConfigBlock/HybridGraphics >=20 > + >=20 > +Include >=20 > +# >=20 > +# SystemAgent >=20 > +# >=20 > +SystemAgent/Include >=20 > +SystemAgent/AcpiTables >=20 > +SystemAgent/AcpiTables/SaSsdt >=20 > +Include/ConfigBlock/Vtd >=20 > +Include/ConfigBlock/PcieRp >=20 > +Include/ConfigBlock/Gna >=20 > +Include/ConfigBlock/CpuPcieRp/Gen4 >=20 > +Include/ConfigBlock/CpuPcieRp/Gen3 >=20 > +Include/ConfigBlock/CpuDmi >=20 > +Include/ConfigBlock/HybridGraphics >=20 > +Include/ConfigBlock/HostBridge >=20 > +# >=20 > +# Cpu >=20 > +# >=20 > +Cpu/Include >=20 > +Include/ConfigBlock/Overclocking >=20 > +Include/ConfigBlock/VoltageRegulator >=20 > + >=20 > +# >=20 > +# Pch >=20 > +# >=20 > +Pch/Include >=20 > +Include/ConfigBlock/Thermal >=20 > +Include/ConfigBlock/P2sb >=20 > +Include/ConfigBlock/Ish >=20 > +Include/ConfigBlock/Usb >=20 > +Include/ConfigBlock/Espi >=20 > +Include/ConfigBlock/Fivr >=20 > +Include/ConfigBlock/Rtc >=20 > +Include/ConfigBlock/Smbus >=20 > +Include/ConfigBlock/Pmc >=20 > +Include/ConfigBlock/Itss >=20 > +Include/ConfigBlock/Scs >=20 > +Include/ConfigBlock/Hda >=20 > +Include/ConfigBlock/Sata >=20 > +Include/ConfigBlock/Rst >=20 > +Include/ConfigBlock/Ieh >=20 > +Include/ConfigBlock/Me >=20 > +Include/ConfigBlock/PchDmi >=20 > +Include/ConfigBlock/Gpio >=20 > +Include/ConfigBlock/Dci >=20 > +Include/ConfigBlock/Cnvi >=20 > +Include/ConfigBlock/Gbe >=20 > +Include/ConfigBlock/TraceHub >=20 > +Include/ConfigBlock/Thc >=20 > +Include/ConfigBlock/Wdt >=20 > +Include/ConfigBlock/PcieRp/PchPcieRp >=20 > +Include/ConfigBlock/PcieRp >=20 > +Include/ConfigBlock/Psf >=20 > +Include/ConfigBlock/SerialIo >=20 > +Include/ConfigBlock/HybridStorage >=20 > +Include/ConfigBlock/Spi >=20 > + >=20 > + >=20 > +# >=20 > +# - Tcss >=20 > +Include/ConfigBlock/Tcss >=20 > +[Guids.common.Private] >=20 > +# >=20 > +# PCH >=20 > +# >=20 > +gPchDeviceTableHobGuid =3D { 0xb3e123d0, 0x7a1e, 0x4db4, { 0xaf, 0= x66, > 0xbe, 0xd4, 0x1e, 0x9c, 0x66, 0x38 }} >=20 > +gWdtHobGuid =3D { 0x65675786, 0xacca, 0x4b11, { 0x8a, 0= xb7, 0xf8, > 0x43, 0xaa, 0x2a, 0x8b, 0xea }} >=20 > +gPchConfigHobGuid =3D { 0x524ed3ca, 0xb250, 0x49f5, { 0x94, 0= xd9, > 0xa2, 0xba, 0xff, 0xc7, 0x0e, 0x14 }} >=20 > +gGpioLibUnlockHobGuid =3D { 0xA7892E49, 0x0F9F, 0x4166, { 0xB8, 0= xD6, > 0x8A, 0x9B, 0xD9, 0x8B, 0x17, 0x38 }} >=20 > +gSiScheduleResetHobGuid =3D { 0xEA0597FF, 0x8858, 0x41CA, { 0xBB, 0= xC1, > 0xFE, 0x18, 0xFC, 0xD2, 0x8E, 0x22 }} >=20 > +gCnviConfigHobGuid =3D { 0xa8d6e4d9, 0x94b7, 0x4fc9, { 0x94, 0= x3f, 0x7a, > 0x9c, 0xb2, 0x31, 0x57, 0xce }} >=20 > + >=20 > +# >=20 > +# CPU >=20 > +# >=20 > +gPeiAcpiCpuDataGuid =3D { 0x7682bbef, 0xb0b6, 0x4939, { 0xae, 0= x66, > 0x1b, 0x3d, 0xf2, 0xf6, 0xaa, 0xf3 }} >=20 > +gCpuStatusCodeDataTypeExceptionHandlerGuid =3D { 0x3BC2BD12, 0xAD2E, > 0x11D5, { 0x87, 0xDD, 0x00, 0x06, 0x29, 0x45, 0xC3, 0xB9 }} >=20 > + >=20 > +# >=20 > +# SA >=20 > +# >=20 > +gSchemaListGuid =3D { 0x3047C2AC, 0x5E8E, 0x4C55, { 0xA1, 0= xCB, 0xEA, > 0xAD, 0x0A, 0x88, 0x86, 0x1B }} >=20 > +gEqPhase3SchemaGuid =3D { 0x145AC084, 0x340E, 0x4777, { 0xBC, 0= x75, > 0xF8, 0x50, 0x5F, 0xFD, 0x50, 0x9D }} >=20 > +gScoreSchemaGuid =3D { 0x8233A1BB, 0x58D5, 0x4F66, { 0xA1, 0= x3F, > 0x8A, 0xA3, 0xED, 0x6A, 0xF5, 0xA0 }} >=20 > +gPortMarginGuid =3D { 0xD7154D12, 0x03B2, 0x4054, { 0x8C, 0= xD2, 0x9F, > 0x4B, 0x20, 0x90, 0xBE, 0xF7 }} >=20 > +gJitterTolerenceGuid =3D { 0xB52A2E04, 0x45FF, 0x484E, { 0xB5, 0= xFE, > 0xEE, 0x47, 0x8F, 0x5F, 0x6C, 0x9B }} >=20 > +gLaneMarginGuid =3D { 0x7AC0996D, 0xA601, 0x4210, { 0x94, 0= x4E, 0x93, > 0x4E, 0x51, 0x7B, 0x6C, 0x57 }} >=20 > +gVocMarginGuid =3D { 0x3578349A, 0x9E98, 0x4F70, { 0x91, 0= xCB, 0xE2, > 0x5B, 0x98, 0x99, 0xBC, 0x16 }} >=20 > + >=20 > +[Guids] >=20 > +gSmbiosProcessorInfoHobGuid =3D {0xe6d73d92, 0xff56, 0x4146, {0x= af, > 0xac, 0x1c, 0x18, 0x81, 0x7d, 0x68, 0x71}} >=20 > +gSmbiosCacheInfoHobGuid =3D {0xd805b74e, 0x1460, 0x4755, {0x= bb, > 0x36, 0x1e, 0x8c, 0x8a, 0xd6, 0x78, 0xd7}} >=20 > + >=20 > +## >=20 > +## IntelFrameworkPkg >=20 > +## >=20 > +# MsegSmramPei.inf >=20 > +gEfiSmmPeiSmramMemoryReserveGuid =3D {0x6dadf1d1, 0xd4cc, 0x4910, > {0xbb, 0x6e, 0x82, 0xb1, 0xfd, 0x80, 0xff, 0x3d}} >=20 > +## >=20 > +## MdeModulePkg >=20 > +## >=20 > +gEfiMemoryTypeInformationGuid =3D {0x4c19049f, 0x4137, 0x4dd3, {0x9c, > 0x10, 0x8b, 0x97, 0xa8, 0x3f, 0xfd, 0xfa}} >=20 > +gEfiCapsuleVendorGuid =3D {0x711c703f, 0xc285, 0x4b10, {0xa3, 0xb0, 0x= 36, > 0xec, 0xbd, 0x3c, 0x8b, 0xe2}} >=20 > +gEfiConsoleOutDeviceGuid =3D { 0xd3b36f2c, 0xd551, 0x11d4, { 0x9a, 0x46, > 0x0, 0x90, 0x27, 0x3f, 0xc1, 0x4d}} >=20 > +## >=20 > +## Common >=20 > +## >=20 > +## Include/ConfigBlock/SiConfig.h >=20 > +gSiConfigGuid =3D {0x4ed6d282, 0x22f3, 0x4fe1, {0xa6, 0x61, 0x6, 0x1a, 0= x97, > 0x38, 0x59, 0xd8}} >=20 > +## >=20 > +gSiPreMemConfigGuid =3D {0xb94c004c, 0xa0ab, 0x40f0, {0x9b, 0x61, 0x0b, > 0x25, 0x88, 0xbe, 0xfd, 0xc6}} >=20 > +## >=20 > +## >=20 > +gPciePreMemConfigGuid =3D {0xd0f9c2a9, 0x7332, 0x4733, {0x8d, 0xb1, 0x98= , > 0x79, 0x27, 0x60, 0xda, 0xe6}} >=20 > +## >=20 > +gSiPkgTokenSpaceGuid =3D {0x977c97c1, 0x47e1, 0x4b6b, {0x96, 0x69, 0x4= 3, > 0x66, 0x99, 0xcb, 0xe4, 0x5b}} >=20 > +## Include/SiConfigHob.h >=20 > +gSiConfigHobGuid =3D {0xb3903068, 0x7482, 0x4424, {0xba, 0x4b, 0x40, 0x5= f, > 0x8f, 0xd7, 0x65, 0x4e}} >=20 > +gBootMediaHobGuid =3D {0x8c7340ea, 0xde8b, 0x4e06, {0xa4, 0x78, 0xec, > 0x8b, 0x62, 0xd7, 0xa, 0x8b}} >=20 > +gEfiPramConfGuid =3D { 0xecb54cd9, 0xe5ae, 0x4fdc, { 0xa9, 0x71, 0xe8, 0= x77, > 0x75, 0x60, 0x68, 0xf7}} >=20 > +## >=20 > +## >=20 > +## IPU's GUIDs >=20 > +## >=20 > +gIpuDataHobGuid =3D {0x61dd66, 0x212b, 0x4dae, {0x9b, 0xc0, 0x30, 0xe0, > 0x2e, 0x3f, 0x40, 0xfd}} >=20 > +gIpuConfigHobGuid =3D {0x446268e5, 0x8c30, 0x4e0a, {0x9b, 0x28, 0xa3, 0= xe7, > 0xf0, 0x4, 0x31, 0xd0}} >=20 > + >=20 > +## Include/FspErrorInfo.h >=20 > +gFspErrorInfoHobGuid =3D {0x611e6a88, 0xadb7, 0x4301, {0x93, 0xff, 0xe4, > 0x73, 0x04, 0xb4, 0x3d, 0xa6}} >=20 > +gStatusCodeDataTypeFspErrorGuid =3D {0x611e6a88, 0xadb7, 0x4301, {0x93, > 0xff, 0xe4, 0x73, 0x04, 0xb4, 0x3d, 0xa6}} >=20 > + >=20 > +## >=20 > +## >=20 > +## SystemAgent >=20 > +## >=20 > +gSaOverclockingPreMemConfigGuid =3D { 0x09ecc29d, 0xdbbe, 0x49fb, { > 0xa6, 0x49, 0x4b, 0xf6, 0x40, 0xe2, 0xeb, 0xd6}} >=20 > +gSaAcpiTableStorageGuid =3D {0x3c0ed5e2, 0x91ea, 0x4b94, { 0x82, 0xd, > 0x9d, 0xaf, 0x9a, 0x3b, 0xb4, 0xa2}} >=20 > +gSaDataHobGuid =3D {0xe07d0bda, 0xbf90, 0x46a9, { 0xb0, 0x0e, 0xb2, 0x= c4, > 0x4a, 0x0e, 0xd6, 0xd0}} >=20 > +gPsmiDataHobGuid =3D {0xa9652bd, 0x6acd, 0x47e5, { 0x80, 0x3a, 0x9, 0x= 53, > 0x7b, 0xd2, 0xa8, 0x48 }} >=20 > +gSaConfigHobGuid =3D {0x762fa2e6, 0xea3b, 0x41c8, { 0x8c, 0x52, 0x63, 0= x76, > 0x6d, 0x70, 0x39, 0xe0}} >=20 > +gCpuPcieHobGuid =3D {0x440ab2e5, 0xa3ea, 0x466f, { 0x84, 0x96, 0xdf, 0x= b1, > 0x3b, 0x75, 0x29, 0x95}} >=20 > +gSaPegHobGuid =3D {0x5807c388, 0xfa06, 0x4683, { 0xab, 0xd3, 0x1b, 0x= 31, > 0xbb, 0x81, 0x2d, 0x23}} >=20 > +gHgAcpiTableStorageGuid =3D {0x8de8964f, 0x2939, 0x4b49, { 0xa3, 0x48, > 0xf6, 0xb2, 0xb2, 0xde, 0x4a, 0x42}} >=20 > +gSaSsdtAcpiTableStorageGuid =3D {0xca89914d, 0x2317, 0x452e, { 0xb2, 0= x45, > 0x36, 0xc6, 0xfb, 0x77, 0xa9, 0xc6}} >=20 > +gSegSsdtAcpiTableStorageGuid =3D {0x10c3800d, 0xe225, 0x480e, { 0x85, > 0xda, 0xbe, 0xed, 0xdb, 0x88, 0xe1, 0xc6}} >=20 > +gHgAcpiTablePchStorageGuid =3D {0xe3164526, 0x690a, 0x4e0d, { 0xb0, 0x= 28, > 0xae, 0xa1, 0x6f, 0xe2, 0xbc, 0xf3}} >=20 > +gSaMiscPeiPreMemConfigGuid =3D {0x4a525577, 0x3469, 0x4f11, { 0x99, 0x= cf, > 0xfb, 0xcd, 0x5e, 0xf1, 0x84, 0xe4}} >=20 > +gSaMiscPeiConfigGuid =3D {0x1def8e6, 0xe998, 0x4e27, { 0x89, 0x98, 0x9= c, > 0xfa, 0xb2, 0x92, 0xbc, 0x50}} >=20 > +gCpuPciePeiPreMemConfigGuid =3D { 0x81baf3c9, 0xf295, 0x4572, { 0x8b, > 0x21, 0x79, 0x3f, 0xa3, 0x1b, 0xa5, 0xdb}} >=20 > +gCpuDmiPreMemConfigGuid =3D { 0x30d12ad5, 0xa3c6, 0x49c7, { 0xa2, 0xfd= , > 0x35, 0x5c, 0xcb, 0x61, 0xcb, 0xcf}} >=20 > +gVmdPeiConfigGuid =3D { 0x79b52c74, 0xb9ba, 0x4f36, {0xa2, 0x40, 0xf2, 0= x41, > 0x0d, 0x20, 0x84, 0x8a}} >=20 > +gVmdInfoHobGuid =3D { 0xccd0306e, 0x7fa1, 0x4df5, {0x99, 0x99= , 0xc1, > 0xf8, 0x9a, 0x1d, 0x1b, 0xa9}} >=20 > +gEfiVmdFeatureVariableGuid =3D { 0x61a14fe8, 0x4dab, 0x4a19, {0xb1, 0xe3= , > 0x97, 0xfb, 0x23, 0xd0, 0x92, 0x12}} >=20 > +gPramPreMemConfigGuid =3D { 0xcf0b9b31, 0xa1a6, 0x46d9, { 0x8d, 0x14, > 0xe3, 0xac, 0x69, 0x0f, 0x52, 0x3a}} >=20 > +gHybridGraphicsConfigGuid =3D { 0xc7956998, 0xc065, 0x46c4, { 0x8e, 0x= 2f, > 0x58, 0x2b, 0x67, 0xeb, 0xbe, 0x2f}} >=20 > +gHybridGraphicsInfoHobGuid =3D { 0x46cbed07, 0x717a, 0x4a75, { 0x85, 0x= b3, > 0xf4, 0xb6, 0xc4, 0xe2, 0x3a, 0x75}} >=20 > +gMemoryConfigGuid =3D { 0x26cf084c, 0xc9db, 0x41bb, { 0x92, 0xc6, 0xd1= , > 0x97, 0xb8, 0xa1, 0xe4, 0xbf}} >=20 > +gMemoryConfigNoCrcGuid =3D { 0xc56c73d0, 0x1cdb, 0x4c0c, { 0xa9, 0x57, > 0xea, 0x62, 0xa9, 0xe6, 0xf5, 0x0c}} >=20 > +gGnaConfigGuid =3D { 0x53e0ef18, 0xb8a8, 0x4795, { 0xa6, 0x6d, 0xe4, 0= x77, > 0x2c, 0xc3, 0xae, 0x82}} >=20 > +gVtdDxeConfigGuid =3D {0xcbbf1996, 0x4a4c, 0x4dd9, {0xab, 0xbe, 0x83, > 0x89, 0x73, 0xd, 0x48, 0xb0}} >=20 > +gPcieDxeConfigGuid =3D {0x1ed2d6f1, 0xa9d2, 0x476e, {0x8e, 0x74, 0xad, > 0xd9, 0x5b, 0x5, 0x10, 0x82}} >=20 > +gMemoryDxeConfigGuid =3D {0xa5c7dda8, 0x686b, 0x404f, {0x86, 0x40, 0xf= 8, > 0x2, 0xd, 0x84, 0x4c, 0x94}} >=20 > +gFspReservedMemoryResourceHobTsegGuid =3D { 0xd038747c, 0xd00c, > 0x4980, { 0xb3, 0x19, 0x49, 0x01, 0x99, 0xa4, 0x7d, 0x55}} >=20 > +gCpuPcieRpPrememConfigGuid =3D { 0x41aef892, 0xc800, 0x4ac0, {0xa9, 0x30= , > 0x84, 0xac, 0x47, 0xca, 0xca, 0x7e}} >=20 > +gCpuPcieRpConfigGuid =3D { 0x9749a5fb, 0x9130, 0x44f0, {0x8f, 0x61, 0xdb= , > 0xff, 0x8e, 0xf2, 0xca, 0xc7}} >=20 > +## Include/Guid/AcpiS3Context.h >=20 > +gEfiAcpiVariableGuid =3D {0xaf9ffd67, 0xec10, 0x488a, {0x9d, 0xfc, 0x6= c, 0xbf, > 0x5e, 0xe2, 0x2c, 0x2e}} >=20 > +## IntelFsp2Pkg/IntelFsp2Pkg.dec gSiMemoryS3DataGuid is the same as > gFspNonVolatileStorageHobGuid >=20 > +gSiMemoryS3DataGuid =3D { 0x721acf02, 0x4d77, 0x4c2a, { 0xb3, 0xdc= , > 0x27, 0x0b, 0x7b, 0xa9, 0xe4, 0xb0 } } >=20 > +gSiMemoryInfoDataGuid =3D { 0x9b2071d4, 0xb054, 0x4e0c, { 0x8d, 0x09= , > 0x11, 0xcf, 0x8b, 0x9f, 0x03, 0x23 } } >=20 > +gSiMemoryPlatformDataGuid =3D { 0x6210d62f, 0x418d, 0x4999, { 0xa2, 0x45= , > 0x22, 0x10, 0x0a, 0x5d, 0xea, 0x44 } } >=20 > +## Include/MrcRmtData.h >=20 > +gEfiMemorySchemaGuid =3D { 0xCE3F6794, 0x4883, 0x492C, { 0x8D, 0xBA, > 0x2F, 0xC0, 0x98, 0x44, 0x77, 0x10}} >=20 > +gMrcSchemaListHobGuid =3D { 0x3047C2AC, 0x5E8E, 0x4C55, { 0xA1, 0xCB, > 0xEA, 0xAD, 0x0A, 0x88, 0x86, 0x1B}} >=20 > +gRmtResultMetadataGuid =3D { 0x02CB1552, 0xD659, 0x4232, { 0xB5, 0x1F, > 0xCA, 0xB1, 0xE1, 0x1F, 0xCA, 0x87}} >=20 > +gRmtResultColumnsGuid =3D { 0x0E60A1EB, 0x331F, 0x42A1, { 0x9D, 0xE7, > 0x45, 0x3E, 0x84, 0x76, 0x11, 0x54}} >=20 > +gMargin2DResultMetadataGuid =3D { 0x48265582, 0x8E49, 0x4AC7, { 0xAA, > 0x06, 0xE1, 0xB9, 0xA7, 0x4C, 0x97, 0x16}} >=20 > +gMargin2DResultColumnsGuid =3D { 0x91A449EC, 0x8A4A, 0x4736, { 0xAD, > 0x71, 0xA3, 0xF6, 0xF6, 0xD7, 0x52, 0xD9}} >=20 > +gSaFspErrorTypePeiGopInit =3D { 0x8106a5cc, 0x30ba, 0x41cf, { 0xa1, 0x78= , > 0x63, 0x38, 0x91, 0x11, 0xae, 0xb2}} >=20 > +gSaFspErrorTypePeiGopGetMode =3D { 0x348cc7fe, 0x1e9a, 0x4c7a, { 0x86, > 0x28, 0xae, 0x48, 0x5b, 0x42, 0x10, 0xf0}} >=20 > +gSaFspErrorTypeCallerId =3D { 0x98230916, 0xe632, 0x49ff, { 0x81, 0x81, = 0x55, > 0xce, 0xe5, 0x10, 0x36, 0x89}} >=20 > +gMrcFspErrorTypeCallerId =3D { 0x5a47c211, 0x642f, 0x4f92, { 0x9c, 0xb3,= 0x7f, > 0xeb, 0x93, 0xda, 0xdd, 0xba}} >=20 > +gMrcFspErrorTypeMemoryInit =3D { 0x5de1c071, 0x2c9c, 0x4a53, { 0x80, 0x2= 1, > 0x4e, 0x80, 0xd2, 0x5d, 0x44, 0xa8}} >=20 > +gSaPciePeiConfigGuid =3D { 0xdaa929a9, 0x5ec9, 0x486a, { 0xb0, 0xf7, 0x8= 2, > 0x3a, 0x55, 0xc7, 0xb5, 0xb3}} >=20 > +gSaPciePeiPreMemConfigGuid =3D { 0xfc5e01a3, 0x69f6, 0x4e35, { 0x9f, 0xc= f, > 0x6, 0x68, 0x7b, 0xab, 0x31, 0xd7}} >=20 > + >=20 > + >=20 > +# >=20 > +# Host Bridge >=20 > +# >=20 > +gHostBridgePeiPreMemConfigGuid =3D {0xbdef6805, 0x2080, 0x44ad, { 0x93= , > 0x2e, 0x00, 0x04, 0xf5, 0x2c, 0xb7, 0xa1}} >=20 > +gHostBridgePeiConfigGuid =3D {0x3b6d998e, 0x8b6e, 0x4f53, { 0xbe, 0x41= , > 0x7, 0x41, 0x95, 0x53, 0x8a, 0xaf}} >=20 > +gHostBridgeDataHobGuid =3D {0x3b682d57, 0xd402, 0x40a6, { 0xb1, 0x34, > 0xa0, 0xc4, 0xf6, 0x31, 0x1d, 0x9}} >=20 > + >=20 > +# >=20 > +# Graphics >=20 > +# >=20 > +gGraphicsPeiPreMemConfigGuid =3D {0x0319c56b, 0xc43a, 0x42f1, { 0x80, > 0xbe, 0xca, 0x5b, 0xd1, 0xd5, 0xc9, 0x28}} >=20 > +gGraphicsPeiConfigGuid =3D {0x04249ac0, 0x0088, 0x439f, { 0xa7, 0x4e, = 0xa7, > 0x04, 0x2a, 0x06, 0x2f, 0x5d}} >=20 > +gGraphicsDxeConfigGuid =3D {0x34d93161, 0xf78e, 0x4915, {0xad, 0xc4, 0= xdb, > 0x67, 0x16, 0x42, 0x39, 0x24}} >=20 > +gGraphicsAcpiTableStorageGuid =3D {0xce9caa0e, 0x8248, 0x442c, { 0x9e, > 0x57, 0x50, 0xf2, 0x12, 0xe2, 0xba, 0xed}} >=20 > +## IpBlock/Graphics/IncludePrivate/GraphicsDataHob.h >=20 > +gGraphicsDataHobGuid =3D { 0x48e6e20a, 0x9110, 0x4332, { 0x8c, 0x9f, 0x5= f, > 0x7c, 0xae, 0x76, 0xfc, 0xf3}} >=20 > + >=20 > +# >=20 > +# IPU >=20 > +# >=20 > +gIpuPreMemConfigGuid =3D { 0x830a222b, 0x3ff5, 0x432e, { 0x9d, 0xd5, > 0x4e, 0xe3, 0xfc, 0xa2, 0xaa, 0xa2}} >=20 > +gIpuAcpiTableStorageGuid =3D {0x9b25dba6, 0x45b3, 0x4190, { 0x99, 0x8d= , > 0xaf, 0x31, 0xdc, 0x21, 0x78, 0x21}} >=20 > + >=20 > +## Include/SsaCommonConfig.h >=20 > +gSsaPostcodeHookGuid =3D {0xADF0A27B, 0x61A6, 0x4F18, {0x9E, 0xAC, 0x46, > 0x87, 0xE7, 0x9E, 0x6F, 0xBB}} >=20 > +gSsaBiosVariablesGuid =3D {0x43eeffe8, 0xa978, 0x41dc, {0x9d, 0xb6, 0x54= , > 0xc4, 0x27, 0xf2, 0x7e, 0x2a}} >=20 > +gSsaBiosResultsGuid =3D {0x8f4e928, 0xf5f, 0x46d4, {0x84, 0x10, 0x47, 0x= 9f, > 0xda, 0x27, 0x9d, 0xb6}} >=20 > +gHobUsageDataGuid =3D {0xc764a821, 0xec41, 0x450d, { 0x9c, 0x99, 0x27, > 0x20, 0xfc, 0x7c, 0xe1, 0xf6 }} >=20 > +## >=20 > +## TBT >=20 > +## >=20 > +gPeiITbtConfigGuid =3D {0xd7e7e1e6, 0xcbec, 0x4f5f, {0xae, 0= xd3, 0xfd, > 0xc0, 0xa8, 0xb0, 0x7e, 0x25}} >=20 > +gDxeITbtConfigGuid =3D {0x196bf9e3, 0x20d7, 0x4b7b, {0x89, 0= xf9, 0x31, > 0xc2, 0x72, 0x08, 0xc9, 0xb9}} >=20 > +gITbtInfoHobGuid =3D {0x74a81eaa, 0x033c, 0x4783, {0xbe, 0= x2b, 0x84, > 0x85, 0x74, 0xa6, 0x97, 0xb7}} >=20 > + >=20 > +## >=20 > +## TCSS >=20 > +## >=20 > +gTcssHobGuid =3D { 0x455702ce, 0x4adb, 0x45d9, { 0x8b, 0x27, 0xf7, 0xb0= , > 0xd9, 0x79, 0x8a, 0xe0}} >=20 > +gTcssSsdtAcpiTableStorageGuid =3D { 0xbd53572c, 0x6486, 0x45e2, { 0x90= , > 0xe, 0xb9, 0x8a, 0xc1, 0xa8, 0x25, 0x45}} >=20 > +gTcssPeiConfigGuid =3D { 0xfb631590, 0x79c9, 0x4f0d, { 0xa9, 0x96, 0xee= , > 0xe2, 0x98, 0x66, 0xfa, 0xfd}} >=20 > +gTcssPeiPreMemConfigGuid =3D { 0x514ed829, 0xb2bb, 0x46be, { 0xa9, 0x78, > 0x6d, 0xc, 0x91, 0xc1, 0xeb, 0xe4}} >=20 > +gTcssSsidHobGuid =3D { 0x8903d47a, 0x8f82, 0x4063, { 0xa8, 0x40, 0x31, = 0x68, > 0x9c, 0x9e, 0x78, 0x20}} >=20 > +## >=20 > +## Telemetry >=20 > +## >=20 > +gTelemetryPeiConfigGuid =3D { 0x8ebf9fee, 0x7496, 0x42b4, { 0xa6,= 0xf6, > 0xcf, 0x2b, 0x33, 0x99, 0x30, 0xd6}} >=20 > +gTelemetryPeiPreMemConfigGuid =3D { 0x422de269, 0xb2ef, 0x4829, { 0x93, > 0x36, 0x0b, 0xe4, 0x98, 0xb5, 0x53, 0xb2}} >=20 > + >=20 > +## >=20 > +## VTD >=20 > +## >=20 > +gVtdDataHobGuid =3D {0x1d60dce8, 0x503a, 0x44a8, { 0xb3, 0x2d, 0x56, 0x= b3, > 0x88, 0xf3, 0x4c, 0x55}} >=20 > +gVtdConfigGuid =3D {0x03e5cf63, 0xbebb, 0x4041, { 0xb7, 0xe7, 0xbf, 0x= 54, > 0x61, 0x20, 0xf1, 0xc5}} >=20 > + >=20 > +# >=20 > +# TRACEHUB >=20 > +# >=20 > +gCpuTraceHubPreMemConfigGuid =3D { 0xf2e17477, 0x93f3, 0x430d, { 0x9e, > 0x08, 0x3c, 0xcc, 0x6e, 0x2f, 0x6c, 0x4b}} >=20 > +gTraceHubDataHobGuid =3D { 0xf1187e54, 0x995f, 0x49d9, { 0xac, = 0xee, > 0xc5, 0x34, 0xf4, 0x5a, 0x18, 0xc7}} >=20 > + >=20 > +## >=20 > +## Cpu >=20 > +## >=20 > +gSmramCpuDataHeaderGuid =3D {0x5848fd2d, 0xd6af, 0x474b, {0x82, 0x75, > 0x95, 0xdd, 0xe7, 0x0a, 0xe8, 0x23}} >=20 > +gCpuAcpiTableStorageGuid =3D {0xc38fb0e2, 0x0c43, 0x49c9, {0xb5, 0x44, > 0x9b, 0x17, 0xaa, 0x4d, 0xcb, 0xa3}} >=20 > +gTxtInfoHobGuid =3D {0x2986883f, 0x88e0, 0x48d0, {0x4b, 0x82, 0x20, 0x= c2, > 0x69, 0x48, 0xdd, 0xac}} >=20 > +gHtBistHobGuid =3D {0xbe644001, 0xe7d4, 0x48b1, {0xb0, 0x96, 0x8b, 0xa= 0, > 0x47, 0xbc, 0x7a, 0xe7}} >=20 > +gProcessorProducerGuid =3D {0x1bf06aea, 0x5bec, 0x4a8d, {0x95, 0x76, 0= x74, > 0x9b, 0x09, 0x56, 0x2d, 0x30}} >=20 > +gCpuInitDataHobGuid =3D {0x266e31cc, 0x13c5, 0x4807, {0xb9, 0xdc, 0x39= , > 0xa6, 0xba, 0x88, 0xff, 0x1a}} >=20 > +gBiosGuardHobGuid =3D {0x66f0c42d, 0x0d0e, 0x4c23, {0x93, 0xc0, 0x2d, > 0x52, 0x95, 0xdc, 0x5e, 0x21}} >=20 > +gCpuSecurityPreMemConfigGuid =3D {0xfd5c346, 0x8260, 0x4067, {0x94, 0x69= , > 0xcf, 0x91, 0x68, 0xa3, 0x42, 0x90}} >=20 > +gCpuConfigLibPreMemConfigGuid =3D {0xfc1c0ec2, 0xc6b4, 0x4f05, {0xbb, > 0x85, 0xc8, 0x0, 0x8d, 0x5b, 0x4a, 0xb7}} >=20 > +gCpuTxtPreMemConfigGuid =3D {0x20b4db03, 0xd160, 0x4f83, {0xa4, 0x1, > 0x9a, 0x8a, 0xa8, 0x88, 0x68, 0x14}} >=20 > +gCpuTestConfigGuid =3D {0xd4dba957, 0xd9c, 0x4af2, {0x9d, 0x40, 0x35, 0x= a8, > 0x44, 0xe4, 0x93, 0xad}} >=20 > +gBiosGuardConfigGuid =3D {0x762f9ddb, 0x1c89, 0x4612, {0x84, 0x6b, 0xee, > 0xdc, 0x8f, 0x62, 0x25, 0x45}} >=20 > +gCpuConfigGuid =3D {0x48c3aac9, 0xd66c, 0x42e4, {0x9b, 0x1d, 0x39, 0x4, = 0x5f, > 0x46, 0x53, 0x41}} >=20 > +gCpuPidTestConfigGuid =3D {0x2511095f, 0xd49e, 0x4537, {0xa6, 0x60, 0x88= , > 0x71, 0x31, 0xd1, 0x53, 0xda}} >=20 > +gCpuPowerMgmtBasicConfigGuid =3D {0xa021e31d, 0x7c14, 0x47da, {0xb5, > 0xec, 0xca, 0xbb, 0x4d, 0x76, 0xed, 0xc8}} >=20 > +gCpuPowerMgmtCustomConfigGuid =3D {0x562fa1c8, 0x55ee, 0x4e2f, {0x91, > 0xca, 0x8d, 0x84, 0x50, 0x3, 0x2f, 0xe}} >=20 > +gCpuPowerMgmtPsysConfigGuid =3D {0x4e7f850, 0x19b5, 0x47ba, {0x9d, > 0x28, 0xb1, 0xe7, 0x5e, 0x1f, 0x48, 0x53}} >=20 > +gCpuPowerMgmtTestConfigGuid =3D {0x5161ed3d, 0x90bf, 0x436f, {0xb8, > 0x33, 0xd7, 0x17, 0x89, 0xb3, 0x48, 0xc1}} >=20 > +gCpuPowerMgmtVrConfigGuid =3D {0x254766c9, 0x929d, 0x4eac, {0x9e, 0xec, > 0xdf, 0xa2, 0x2, 0x44, 0xb5, 0xea}} >=20 > +gTxtPrivateBaseHobGuid =3D {0x651EBDB4, 0x4E1D, 0x422A, {0x82, 0xFB, 0x1= E, > 0xDA, 0x66, 0x71, 0x6C, 0x0B}} >=20 > +gTxtAcmInfoTableGuid =3D {0x7FC03AAA, 0x46A7, 0x18DB, {0x2E, 0xAC, 0x69, > 0x8F, 0x8D, 0x41, 0x7F, 0x5A}} >=20 > +gOverclockingPreMemConfigGuid =3D {0xad151bbc, 0xd5a0, 0x481e, {0x9d, > 0x19, 0xf6, 0x7b, 0x79, 0xe9, 0x8f, 0x68}} >=20 > +gCpuDataHobGuid =3D {0x1eec629f, 0xf3cf, 0x4b02, { 0xa9, 0xa5, 0x27, 0xa= 2, > 0x33, 0x20, 0xbe, 0x5d}} >=20 > + >=20 > +## >=20 > +## Me >=20 > +## >=20 > +gMePlatformReadyToBootGuid =3D {0x03fdf171, 0x1d67, 0x4ace, {0xa9, 0x0= 4, > 0x3e, 0x36, 0xd3, 0x38, 0xfa, 0x74}} >=20 > +gMeSsdtAcpiTableStorageGuid =3D {0x9a8f82d5, 0x39b1, 0x48da, {0x92, 0x= dc, > 0xa2, 0x2d, 0xa8, 0x83, 0x4d, 0xf6}} >=20 > +gMeDataHobGuid =3D {0x1e94f097, 0x5acd, 0x4089, {0xb2, 0xe3, 0xb9, 0xa= 5, > 0xc8, 0x79, 0xa7, 0x0c}} >=20 > +gMeEDebugHobGuid =3D {0x5f672ec1, 0xa8f6, 0x47d3, {0x9c, 0xd0, 0x92, > 0xe9, 0xe9, 0xe0, 0xb3, 0x84}} >=20 > +gPciImrHobGuid =3D {0x49b1eac3, 0x0cd6, 0x451e, {0x96, 0x30, 0x92, 0x4= b, > 0xc2, 0x69, 0x35, 0x86}} >=20 > +gTpm2AcpiTableStorageGuid =3D {0x7d279373, 0xeecc, 0x4d4f, {0xae, 0x2f= , > 0xce, 0xc4, 0xb7, 0x06, 0xb0, 0x6a}} >=20 > +gMeBiosPayloadHobGuid =3D {0x992c52c8, 0xbc01, 0x4ecd, {0x20, 0xbf, 0x= f9, > 0x57, 0x16, 0x0e, 0x9e, 0xf7}} >=20 > +gEfiTouchPanelGuid =3D {0x91b1d27b, 0xe126, 0x48d1, {0x82, 0x34, 0xd2, > 0x8b, 0x81, 0xc8, 0x83, 0x62}} >=20 > +gMeFwHobGuid =3D {0x52885e62, 0x4c4d, 0x9546, {0x2d, 0xba, 0x2a, 0x84, > 0x89, 0xee, 0xa8, 0xa3 }} >=20 > +gMePeiPreMemConfigGuid =3D {0x67ed113b, 0xd4ab, 0x43f5, {0x9c, 0x3c, > 0x35, 0x44, 0x15, 0xaa, 0x47, 0x5c}} >=20 > +gMePeiConfigGuid =3D {0x9bad5628, 0x657b, 0x48e3, {0xb1, 0x11, 0xc3, 0= xb9, > 0xeb, 0xea, 0xee, 0x17}} >=20 > +gMeDxeConfigGuid =3D {0xad08bacc, 0x4906, 0x4d9b, {0xbe, 0xd1, 0x81, > 0xa5, 0x2c, 0x13, 0xdb, 0xf8}} >=20 > +gIvmProtocolGuid =3D {0x3C4852D6, 0xD47B, 0x4F46, {0xB0, 0x5E, 0xB5, 0x= ED, > 0xC1, 0xAA, 0x44, 0x0E}} >=20 > +gSdmProtocolGuid =3D {0xDBA4D603, 0xD7ED, 0x4931, {0x88, 0x23, 0x17, > 0xAD, 0x58, 0x57, 0x05, 0xD5}} >=20 > +gRtmProtocolGuid =3D {0x5565A099, 0x7FE2, 0x45C1, {0xA2, 0x2B, 0xD7, 0x= E9, > 0xDF, 0xEA, 0x9A, 0x2E}} >=20 > +gSvmProtocolGuid =3D {0xF47ACC04, 0xD94B, 0x49CA, {0x87, 0xA6, 0x7F, > 0x7D, 0xC0, 0x3F, 0xBA, 0xF3}} >=20 > +gMeEopDoneHobGuid =3D {0x247323af, 0xc8f1, 0x4b8c, {0x90, 0x87, 0xaa, > 0x4b, 0xa7, 0xb7, 0x6d, 0x6a}} >=20 > +gMePreMemPolicyHobGuid =3D {0xe6de74a5, 0x21b, 0x4f78, {0xa3, 0xcd, > 0x34, 0xd6, 0x7e, 0xe4, 0x82, 0xbf}} >=20 > +gMePolicyHobGuid =3D {0x0341cf17, 0xbc8f, 0x4a20, {0xac, 0x28, 0x6c, 0x= 3c, > 0x32, 0x4c, 0xd4, 0x17}} >=20 > +gMeFspErrorTypeEop =3D {0x948585c4, 0x76a4, 0x45bb, {0xbe, 0x6c, 0x39, > 0x61, 0xc3, 0xab, 0xde, 0x15}} >=20 > +gMeFspErrorTypeCallerId =3D {0x1f4dc7e9, 0x26ca, 0x4336, { 0x8c, 0xe3, 0= x39, > 0x31, 0x3, 0xb5, 0xf3, 0xd7}} >=20 > +gMeConfigSpaceGuid =3D {0xcb405fd3, 0x4404, 0x4ccd, {0x85, 0x18, 0x0d, > 0x03, 0x07, 0x48, 0xd0, 0xa6}} >=20 > +gMeDidSentHobGuid =3D {0x4c3d3af1, 0x1720, 0x4c3f, {0xab, 0x7c, 0x36, 0x= 50, > 0xbb, 0x5b, 0x85, 0x7e}} >=20 > +gMeDisabledEventHobGuid =3D {0x1500b6a7, 0xb82f, 0x456b, {0xba, 0x2b, > 0x4, 0x72, 0x41, 0x6, 0xf, 0x7}} >=20 > +gMeSavedPmconHobGuid =3D {0xb8baee93, 0xea15, 0x4ddc, {0x90, 0xb8, > 0x44, 0x12, 0xd2, 0xea, 0xcf, 0x4f}} >=20 > + >=20 > +## >=20 > +## Amt >=20 > +## >=20 > +gAmtForcePushPetPolicyGuid =3D {0xacc8e1e4, 0x9f9f, 0x4e40, {0xa5, 0x7= e, > 0xf9, 0x9e, 0x52, 0xf3, 0x4c, 0xa5}} >=20 > +gAmtForcePushPetVariableGuid =3D {0xd7ac94af, 0xa498, 0x45ec, {0xbf, > 0xa2, 0xa5, 0x6e, 0x95, 0x34, 0x61, 0x8b}} >=20 > +gMeBiosExtensionSetupGuid =3D {0xaf013532, 0xc828, 0x4fbd, {0x20, 0xae= , > 0xfe, 0xe6, 0xaf, 0xbe, 0xdd, 0x4e}} >=20 > +gAmtPetQueueHobGuid =3D {0xca0801d3, 0xafb1, 0x4dec, {0x9b, 0x65, 0x93= , > 0x65, 0xec, 0xc7, 0x93, 0x6b}} >=20 > +gAmtForcePushPetHobGuid =3D {0x4efa0db6, 0x26dc, 0x4bb1, {0xa7, 0x6f, > 0x14, 0xbc, 0x63, 0x0c, 0x7b, 0x3c}} >=20 > +gAmtPeiConfigGuid =3D {0x7254546a, 0xace3, 0x4a32, {0x9a, 0xc2, 0xf0, = 0xcc, > 0x28, 0x4e, 0x1e, 0x4d}} >=20 > +gAmtDxeConfigGuid =3D {0x3f12ab6b, 0xb04d, 0x4824, {0xbf, 0xb6, 0x3e, > 0xe7, 0x5d, 0x02, 0x0b, 0x84}} >=20 > +gAmtPolicyHobGuid =3D {0x703eb2cd, 0x5ca8, 0x4233, {0x9d, 0xa3, 0x0d, 0x= 2d, > 0x57, 0xe6, 0x73, 0x34}} >=20 > +gAmtMebxDataGuid =3D { 0x912e1538, 0x371d, 0x4ea6, { 0xa8, 0x41, 0xd7, > 0x6a, 0x8, 0x93, 0x3a, 0x70}} >=20 > + >=20 > +## >=20 > +## PCH >=20 > +## >=20 > +gEfiSmbusArpMapGuid =3D {0x707be83e, 0x0bf6, 0x40a5, {0xbe, 0x64, 0x34= , > 0xc0, 0x3a, 0xa0, 0xb8, 0xe2}} >=20 > +gIrmtAcpiTableStorageGuid =3D {0x6684d675, 0xee06, 0x49b2, {0x87, 0x6f= , > 0x79, 0xc5, 0x8f, 0xdd, 0xa5, 0xb7}} >=20 > +gPchGlobalResetGuid =3D { 0x9db31b4c, 0xf5ef, 0x48bb, { 0x94, 0x2b, 0x= 18, > 0x1f, 0x7e, 0x3a, 0x3e, 0x40 }} >=20 > +gI2c0MasterGuid =3D {0xa121a5db, 0xb0cb, 0x46ec, {0xa0, 0xcb, 0x27, 0x= f8, > 0xda, 0x72, 0xd4, 0x0e}} >=20 > +gI2c1MasterGuid =3D {0x55e3d0f9, 0xc954, 0x422d, {0x9c, 0x4c, 0xcc, 0x= 46, > 0x12, 0x7c, 0x5b, 0xa8}} >=20 > +gI2c2MasterGuid =3D {0x9289aa40, 0xdf32, 0x474e, {0xb0, 0x3a, 0xc7, 0x= 7f, > 0x76, 0xd3, 0x45, 0x21}} >=20 > +gI2c3MasterGuid =3D {0xd8b2c17f, 0x4117, 0x4166, {0x90, 0x17, 0x01, 0x= 68, > 0xb4, 0x81, 0xac, 0x18}} >=20 > +gI2c4MasterGuid =3D {0x513d943d, 0x15d9, 0x4bd0, {0xb1, 0x41, 0x14, 0x= 50, > 0x2b, 0xbf, 0xa9, 0xf2}} >=20 > +gI2c5MasterGuid =3D {0x50df382a, 0xb6bf, 0x4435, {0xae, 0xe6, 0x21, 0x= f4, > 0x85, 0x7c, 0xa8, 0xb4}} >=20 > +gChipsetInitHobGuid =3D {0xc1392859, 0x1f75, 0x446e, {0xb3, 0xf5, 0x83= , > 0x35, 0xfc, 0xc8, 0xd1, 0xc4}} >=20 > + >=20 > +gPchGeneralPreMemConfigGuid =3D {0xC65F62FA, 0x52B9, 0x4837, {0x86, > 0xEB, 0x1A, 0xFB, 0xD4, 0xAD, 0xBB, 0x3E}} >=20 > +gDciPreMemConfigGuid =3D {0xAB4AF366, 0x2250, 0x40C3, {0x92, 0xDB, > 0x36, 0x61, 0xC6, 0x71, 0x3C, 0x5A}} >=20 > +gWatchDogPreMemConfigGuid =3D {0xFBCE08CC, 0x60F2, 0x4BDF, {0xB7, > 0x88, 0x09, 0xBB, 0x81, 0x65, 0x52, 0x2B}} >=20 > +gPchTraceHubPreMemConfigGuid =3D {0x8456c11, 0xdb85, 0x4914, {0x8d, > 0x1a, 0xe5, 0xac, 0x64, 0x37, 0xe8, 0x96}} >=20 > +gPcieRpPreMemConfigGuid =3D {0x8377AB38, 0xF8B0, 0x476A, { 0x9C, 0xA1, > 0x68, 0xEA, 0x78, 0x57, 0xD8, 0x2A}} >=20 > +gSmbusPreMemConfigGuid =3D {0x77A6E62C, 0x716B, 0x4386, {0x9E, 0x9C, > 0x23, 0xA0, 0x2E, 0x13, 0x7B, 0x3A}} >=20 > +gLpcPreMemConfigGuid =3D {0xA6E6032F, 0x1E58, 0x407E, {0x9A, 0xB8, 0xC= 6, > 0x30, 0xC6, 0xC4, 0x11, 0x8E}} >=20 > +gHsioPciePreMemConfigGuid =3D {0xE8FB0C12, 0x0DA1, 0x4A20, {0xB3, 0x36= , > 0xFB, 0x75, 0x93, 0x8C, 0xE0, 0x14}} >=20 > +gHsioSataPreMemConfigGuid =3D {0x732260D0, 0xA5C1, 0x4119, {0xAA, > 0x0C, 0x93, 0xDC, 0xAC, 0x67, 0x0A, 0x31}} >=20 > + >=20 > +gPchGeneralConfigGuid =3D {0x6ED94C8C, 0x25F7, 0x4686, {0xB2, 0x46, 0x= CA, > 0x4D, 0xE2, 0x95, 0x4B, 0x5D}} >=20 > +gPchPcieConfigGuid =3D {0x0A53B507, 0x988B, 0x475C, {0xBF, 0x76, 0x33, > 0xDE, 0x10, 0x6D, 0x94, 0x84}} >=20 > +gPchPcieRpDxeConfigGuid =3D {0x475530EA, 0xBD72, 0x416F, {0x98, > 0x9F,0x48, 0x70, 0x5F, 0x14, 0x4E, 0xD9}} >=20 > +gSataConfigGuid =3D {0xF5F87B4F, 0xCC3C, 0x408D, {0x89, 0xE3, 0x61, 0x= C5, > 0x9C, 0x54, 0x07, 0xC4}} >=20 > +gRstConfigGuid =3D {0x43B6F112, 0x3851, 0x4DDC, {0x81, 0xB9, 0xE4, 0x5A, > 0x2B, 0xE, 0xB3, 0x25}} >=20 > +gIoApicConfigGuid =3D {0x2873D0F1, 0x00F6, 0x40AB, {0xAC, 0x36, 0x9A, > 0x68, 0xBA, 0x87, 0x3E, 0x6C}} >=20 > +gPchDmiConfigGuid =3D {0xB3A61210, 0x1CD3, 0x4797, {0x8E, 0xE6, 0xD3, > 0x42, 0x9C, 0x4F, 0x17, 0xBD}} >=20 > +gFlashProtectionConfigGuid =3D {0xD0F71512, 0x9E32, 0x4CC9, {0xA5, 0xA= 3, > 0xAD, 0x67, 0x9A, 0x06, 0x67, 0xB8}} >=20 > +gHdAudioPreMemConfigGuid =3D {0xD38F1E2B, 0x21B3, 0x43D1, {0x9F, 0xA8, > 0xA5, 0xE1, 0x78, 0x73, 0x1E, 0x88}} >=20 > +gHdAudioConfigGuid =3D {0x7EB3CE7E, 0x82E0, 0x4CD7, {0xBD, 0xE5, 0xB2, > 0xBF, 0x4E, 0x91, 0xC3, 0x4C}} >=20 > +gHdAudioDxeConfigGuid =3D {0x22EFC2DE, 0x66EB, 0x412D, {0x97, 0x17, > 0xE7, 0x7A, 0xA1, 0x4E, 0x87, 0x76}} >=20 > +gInterruptConfigGuid =3D {0x09A2B815, 0xBE29, 0x45EF, {0xBF, 0xBF, 0x5= 8, > 0xEA, 0xAC, 0x5E, 0x29, 0x78}} >=20 > +gIshPreMemConfigGuid =3D {0x7C24E649, 0xC1F0, 0x4CF9, {0x87, 0x96, 0xE= 7, > 0xA0, 0xEE, 0x34, 0x43, 0xF8}} >=20 > +gIshConfigGuid =3D {0x433AE2AA, 0xC5A6, 0x46ED, {0x94, 0x19, 0x1E, 0x5= D, > 0xB8, 0x1C, 0x57, 0x40}} >=20 > +gGbeConfigGuid =3D {0x4B2DE99E, 0x7517, 0x4D04, {0x8C, 0x02, 0xF1, 0x1= A, > 0x59, 0x2B, 0x14, 0x2F}} >=20 > +gTsnConfigGuid =3D {0x9E9A93CB, 0x0F4E, 0x4E56, {0x90, 0x2D, 0x6C, 0x7= 6, > 0xDE, 0x90, 0xF7, 0x71}} >=20 > +gLockDownConfigGuid =3D {0x8A838E0A, 0xA639, 0x46F0, {0xA9, 0xCE, 0x70= , > 0xC4, 0x85, 0xFB, 0xA8, 0x0D}} >=20 > +gP2sbConfigGuid =3D {0x2474DCB8, 0x4BB4, 0x49DA, {0x87, 0x83, 0x7C, 0x= D3, > 0xD3, 0x85, 0xFF, 0x07}} >=20 > +gPmConfigGuid =3D {0x93826157, 0xDC85, 0x4E34, {0xAE, 0xD9, 0x6E, 0xA1= , > 0x0D, 0xF9, 0xE3, 0xA7}} >=20 > +gScsConfigGuid =3D {0xF4DE6D52, 0xB5C9, 0x48C0, {0xA0, 0x4A, 0x68, 0x5= 4, > 0x20, 0x94, 0x05, 0xD0}} >=20 > +gScsInfoHobGuid =3D {0x94C5E85B, 0xAA6D, 0x481D, {0x8B, 0xBD, 0x54, 0xAA= , > 0xE2, 0x99, 0x78, 0xB2}} >=20 > +gSdCardConfigGuid =3D {0xD6A3038E, 0x50AE, 0x44B0, {0x93, 0xE2, 0xF7, 0x= 93, > 0xF5, 0x90, 0x50, 0x27}} >=20 > +gEmmcConfigGuid =3D {0xE0C6FB5D, 0x5696, 0x47F3, {0x84, 0xE8, 0xCC, 0x6C= , > 0x68, 0xA4, 0xB2, 0x1D}} >=20 > +gUfsConfigGuid =3D {0x3AF25C55, 0x76B4, 0x4367, {0x85, 0xEF, 0x9D, 0x51, > 0x2F, 0x2F, 0x8F, 0xA7}} >=20 > +gEmmcDxeConfigGuid =3D {0x59440AA6, 0xEB45, 0x4E36, {0xBC, 0x90, 0xBE, > 0xF9, 0x0C, 0xB0, 0xC8, 0x18}} >=20 > +gSerialIoConfigGuid =3D {0x6CC06EBF, 0x0D34, 0x4340, {0xBC, 0x16, 0xDA= , > 0x09, 0xE5, 0x78, 0x3A, 0xDB}} >=20 > +gSerialIrqConfigGuid =3D {0x251701E7, 0xE266, 0x4623, {0x99, 0x68, 0x7= 3, > 0x8C, 0xD2, 0x23, 0x10, 0x96}} >=20 > +gSpiConfigGuid =3D {0x150360EF, 0x99BE, 0x4E43, {0x94, 0xBB, 0xBD, 0x4= 0, > 0x26, 0xCA, 0x34, 0x57}} >=20 > +gEspiConfigGuid =3D {0x60FBF3B8, 0x96D4, 0x4187, {0x84, 0x9E, 0xAA, 0x= F7, > 0x5C, 0x4B, 0xE1, 0xE3}} >=20 > +gThermalConfigGuid =3D {0x4416506D, 0x1197, 0x4722, {0xA5, 0xB4, 0x46, > 0x11, 0xF9, 0x23, 0x9E, 0xAE}} >=20 > +gUsbConfigGuid =3D {0xB2DA9CCD, 0x6A8C, 0x4BB6, {0xB3, 0xE6, 0xCD, 0xF= B, > 0xB7, 0x66, 0x8B, 0xDE}} >=20 > +gUsb2PhyConfigGuid =3D {0x576C1134, 0x2E0C, 0xCB7D, {0xCD, 0x3F, 0xAC, > 0x68, 0x2D, 0xAE, 0xD3, 0xF2}} >=20 > +gUsb3HsioConfigGuid =3D {0xF8AFC238, 0xF176, 0x12CE, {0xBE, 0xF4, 0x69= , > 0xF9, 0xB1, 0xAC, 0x40, 0xD5}} >=20 > +gPchPcieStorageDetectHobGuid =3D {0xC682F3F4, 0x2F46, 0x495E, {0x98, > 0xAA, 0x43, 0x14, 0x4B, 0xA5, 0xA4, 0x85}} >=20 > +gCnviConfigGuid =3D {0xE53EBEF7, 0x103D, 0x4A70, {0x9B, 0x6A, 0x73, 0xEE= , > 0x5F, 0x4C, 0x8D, 0xF5}} >=20 > +gHsioConfigGuid =3D {0xE53EBEE7, 0x103D, 0x4A71, {0x9B, 0x6A, 0x74, 0xEE= , > 0x5F, 0x4C, 0x8D, 0xF5}} >=20 > +gPchRstHobGuid =3D {0x4ECA680C, 0x660D, 0x48F8, {0xAA, 0xD8, 0x94, 0xD6= , > 0x56, 0x10, 0xF9, 0x86}} >=20 > +gPchInfoHobGuid =3D {0x99FD5E18, 0xE262, 0x4E6A, {0x82, 0x66, 0x77, 0x= D0, > 0x36, 0x5F, 0xD6, 0x3E}} >=20 > +gGpioDxeConfigGuid =3D {0x06985984, 0xAFA3, 0x429C, {0x80, 0xCD, 0x69, > 0x43, 0xF3, 0x38, 0x31, 0x4D}} >=20 > +gFivrConfigGuid =3D {0x68EE8BD4, 0x05F2, 0x4656, {0xAE, 0xE4, 0xAD, 0x= 10, > 0xC7, 0x22, 0xC3, 0x4F}} >=20 > +gThcConfigGuid =3D {0x1B318AD1, 0xAA0D, 0x4764, {0x99, 0xFD, 0xBB, 0x2= B, > 0xF4, 0x7F, 0x7E, 0xD6}} >=20 > +gIehConfigGuid =3D {0x42C4D7F3, 0x981D, 0x4475, {0xA2, 0xAE, 0xAD, 0xC= D, > 0xD5, 0xCE, 0x87, 0x1E}} >=20 > +gRtcConfigGuid =3D {0x0E9259B8, 0x3DDE, 0x40C7, {0xAA, 0x5F, 0x94, 0x8= 2, > 0x9A, 0x86, 0x8F, 0xAF}} >=20 > +gCnviConfigGuid =3D {0xa660970e, 0x511b, 0x46bb, {0xa7, 0xb8, 0xec, 0xd= d, > 0xf5, 0xe2, 0x2d, 0x73}} >=20 > +gGpioCheckConflictHobGuid =3D {0x5603f872, 0xefac, 0x40ae, {0xb9, 0x7e, > 0x13, 0xb2, 0xf8, 0x07, 0x80, 0x21}} >=20 > +gPsfConfigGuid =3D {0x49B12CF6, 0x0A56, 0x4B9F, {0xA8, 0x4C, 0xF5, 0x7= D, > 0x21, 0x23, 0x8C, 0x77}} >=20 > +gHybridStorageConfigGuid =3D {0x265CE069, 0xD8CF, 0x48BE, {0xAE, 0x12, > 0x02, 0x4C, 0x25, 0x12, 0xFA, 0xF8}} >=20 > +gHybridStorageHobGuid =3D {0xFF91F620, 0x069E, 0x4191, {0x83, 0x73, 0x11= , > 0x60, 0x9F, 0x24, 0x90, 0xEB}} >=20 > +gAdrConfigGuid =3D {0x5B36A07C, 0x3BBF, 0x4D53, {0x8A, 0x2D, 0xE1, 0xCF, > 0x97, 0x39, 0x0C, 0x65}} >=20 > +gSpiConfigGuid =3D {0xD61A6A07, 0xAD25, 0xBFC2, {0x8C, 0x60, 0xD0, 0xD1, > 0xF4, 0x13, 0x14, 0xBC}} >=20 > + >=20 > +## >=20 > +## Fusa >=20 > +## >=20 > +gFusaConfigGuid =3D {0xF9225896, 0xA9C8, 0x4543, {0xBA, 0x9E, 0x53, 0x3= 2, > 0xD7, 0xBF, 0x8C, 0x2B}} >=20 > +gSiFusaInfoGuid =3D {0xcc7876ba, 0xee7b, 0x4bd4, {0x99, 0x4b, 0x7e, 0xc9= , > 0x74, 0xc9, 0xd8, 0x43}} >=20 > + >=20 > +## >=20 > +## SecurityPkg >=20 > +## >=20 > +## GUID used to "Tcg2PhysicalPresence" variable and > "Tcg2PhysicalPresenceFlags" variable for TPM2 request and response. >=20 > +# Include/Guid/Tcg2PhysicalPresenceData.h >=20 > +gEfiTcg2PhysicalPresenceGuid =3D { 0xaeb9c5c1, 0x94f1, 0x4d02, = { 0xbf, > 0xd9, 0x46, 0x2, 0xdb, 0x2d, 0x3c, 0x54 }} >=20 > +gEfiTrEEPhysicalPresenceGuid =3D {0xf24643c2, 0xc622, 0x494e, = {0x8a, > 0x0d, 0x46, 0x32, 0x57, 0x9c, 0x2d, 0x5b}} >=20 > +gTcoWdtHobGuid =3D { 0x3e405418, 0x0d8c, 0x4f1a, = { 0xb0, 0x55, > 0xbe, 0xf9, 0x08, 0x41, 0x46, 0x8d }} >=20 > + >=20 > +## >=20 > +## UEFI Variable Support (Direct SPI and UFS) >=20 > +## >=20 > +gCseVariableStoragePpiInstanceGuid =3D { 0x9513730d, 0x06ce, 0x4= cf6, { > 0x9d, 0x95, 0xb0, 0x76, 0x31, 0xbc, 0xd5, 0xa9}} >=20 > +gFvbVariableStoragePpiInstanceGuid =3D { 0x5067b88a, 0xaa37, 0x4= 14d, { > 0xa3, 0xca, 0xc8, 0x37, 0xfc, 0xec, 0xd6, 0xf3}} >=20 > +gCseVariableStorageProtocolInstanceGuid =3D { 0x5d5ede0b, 0x5d93, > 0x4aae, { 0xa8, 0xec, 0x08, 0x41, 0xd0, 0x53, 0x85, 0xc4}} >=20 > +gFvbVariableStorageProtocolInstanceGuid =3D { 0xe98252e8, 0xf209, 0x4= ef5, > { 0xab, 0x7e, 0x12, 0x69, 0x45, 0x14, 0x47, 0xbe}} >=20 > +gPeiVariableCacheHobGuid =3D { 0x35212b29, 0x128a, 0x4= 754, { 0xb9, > 0x96, 0x62, 0x45, 0xcc, 0xa8, 0xa0, 0x66}} >=20 > +gCseVariableStorageSecurePreMemoryDataGuid =3D { 0xa1749e1e, 0x8ce1, > 0x4310, { 0xbd, 0x3f, 0x64, 0xc9, 0x01, 0xc6, 0x13, 0xc2}} >=20 > +gCseVariableStorageGeneralDataAreaGuid =3D { 0x6d7a6128, 0x685b, > 0x4f75, { 0x87, 0x87, 0xba, 0x93, 0x08, 0x60, 0x75, 0x0c}} >=20 > +gCseVariableStorageFileSystemGuid =3D { 0xdb798aca, 0x3533, 0x4= 1c7, { > 0x9a, 0x98, 0x00, 0x31, 0x1b, 0x66, 0x0a, 0x15}} >=20 > +gBugCheckVariableGuid =3D { 0xba57e015, 0x65b3, 0x4= c3c, { 0xb2, > 0x74, 0x65, 0x91, 0x92, 0xf6, 0x99, 0xe3}} >=20 > + >=20 > +## >=20 > +## PreMem Performance >=20 > +## >=20 > +gPerfPchPrePolicyGuid =3D {0x3112356F, 0xCC77, 0x4E82, {0x86, 0xD5, = 0x3E, > 0x25, 0xEE, 0x81, 0x92, 0xA4}} >=20 > +gPerfSiValidateGuid =3D {0x681F96E6, 0xF9CF, 0x464D, {0x97, 0x9A, = 0xB1, > 0x11, 0x33, 0xDE, 0x37, 0xA9}} >=20 > +gPerfPchValidateGuid =3D {0xD0FF37D6, 0xA569, 0x4058, {0xB3, 0xDA, = 0x29, > 0x0B, 0x38, 0xC5, 0x32, 0x25}} >=20 > +gPerfAmtValidateGuid =3D {0x9E949422, 0x4A7A, 0x4E41, {0xB0, 0xAB, > 0x3C, 0x0D, 0x88, 0x0A, 0x00, 0xFF}} >=20 > +gPerfCpuValidateGuid =3D {0xB760CFCC, 0xDEEF, 0x4C7E, {0x99, 0x5B, = 0xED, > 0xFE, 0xF2, 0x23, 0xB2, 0x09}} >=20 > +gPerfMeValidateGuid =3D {0x8CF7A498, 0x588D, 0x4D39, {0xBD, 0xAC, > 0x51, 0x0C, 0x31, 0xAF, 0x45, 0xD0}} >=20 > +gPerfSaValidateGuid =3D {0xA73B382B, 0x62D4, 0x4A19, {0xBB, 0xF9, = 0x09, > 0x3E, 0xC5, 0xA5, 0x93, 0x11}} >=20 > +gPerfHeciPreMemGuid =3D {0xD815D922, 0x4994, 0x40B3, {0x97, 0xCC, > 0x07, 0xF3, 0x7D, 0x42, 0xE7, 0x97}} >=20 > +gPerfPchPreMemGuid =3D {0xBB73E2B1, 0xB9FD, 0x4A80, {0xB8, 0x1A, > 0x52, 0x39, 0xE9, 0x4D, 0x06, 0x2E}} >=20 > +gPerfCpuPreMemGuid =3D {0xAC5FCBC6, 0x084D, 0x445D, {0xB3, 0xF3, > 0xCA, 0x16, 0xDE, 0xE9, 0xBB, 0x47}} >=20 > +gPerfMePreMemGuid =3D {0x6051338E, 0x0FFA, 0x40F7, {0xAF, 0xEF, > 0xAB, 0x86, 0x7A, 0x38, 0xCC, 0xF3}} >=20 > +gPerfAmtPreMemGuid =3D {0xDB732D50, 0x9BB8, 0x489A, {0xA1, 0xD1, > 0xDD, 0xD2, 0x16, 0x1D, 0x72, 0xB8}} >=20 > +gPerfAmtPostMemGuid =3D {0x0329D610, 0x4269, 0xD28F, {0x61, 0xBF, > 0xB9, 0xA2, 0xD9, 0xFA, 0x96, 0x93}} >=20 > +gPerfSaPreMemGuid =3D {0x76F18BDA, 0x2195, 0x4FB6, {0x9A, 0x94, > 0x0E, 0x0B, 0xAC, 0xDE, 0xEC, 0xAB}} >=20 > +gPerfEvlGuid =3D {0x8221518B, 0xAC19, 0x4E32, {0xAB, 0x5F, = 0x00, 0x47, > 0x0A, 0x50, 0x69, 0x40}} >=20 > +gPerfMemGuid =3D {0x2B57B316, 0x5CF7, 0x4847, {0xB0, 0x76, = 0x6B, > 0x5D, 0x23, 0xC3, 0xAA, 0x3E}} >=20 > + >=20 > +## >=20 > +## PostMem Performance >=20 > +## >=20 > +gPerfPchPostMemGuid =3D {0x70B67A99, 0x5556, 0x4315, {0xB3, 0x05, > 0xD5, 0xDC, 0x4A, 0x35, 0x63, 0x70}} >=20 > +gPerfSaPostMemGuid =3D {0x9FF0CE92, 0x883F, 0x43DC, {0x8A, 0x07, > 0xE0, 0xCB, 0x6D, 0x56, 0x7D, 0xE0}} >=20 > +gPerfS3CpuInitPostMemGuid =3D {0x976262C2, 0xD202, 0x4D12, {0x82, 0xAD, > 0xF4, 0xA9, 0x8F, 0x9B, 0x96, 0x01}} >=20 > +gPerfSaSecLockPostMemGuid =3D {0x272AC110, 0x0B60, 0x4D07, {0xA5, 0x58, > 0x6D, 0x73, 0xE2, 0x43, 0x85, 0x95}} >=20 > +gPerfCpuStrapPostMemGuid =3D {0x8EF4372B, 0x68F0, 0x4957, {0xBC, 0x4D, > 0x7E, 0x5C, 0xFE, 0xDA, 0xB6, 0x3E}} >=20 > +gPerfMpPostMemGuid =3D {0xA59BAC5B, 0xC6A4, 0x4AEB, {0x84, 0x32, > 0x7A, 0x8B, 0x6B, 0x68, 0x5F, 0x37}} >=20 > +gPerfCpuPostMemGuid =3D {0xE2FE5ED3, 0x1417, 0x451A, {0x95, 0xC9, > 0xD0, 0xB2, 0xB9, 0x7B, 0xE0, 0x54}} >=20 > +gPerfSaResetPostMemGuid =3D {0xBE152BEE, 0xFD19, 0x4274, {0xA8, 0xBA, > 0xFB, 0x31, 0x42, 0xB5, 0xB5, 0xC3}} >=20 > +gPerfCpuPowerMgmtGuid =3D {0x9ED307D6, 0x4AEB, 0x44A9, {0x9B, 0x11, > 0xD8, 0x21, 0x84, 0x9A, 0xCB, 0xF7}} >=20 > +gPerfMePostMemGuid =3D {0x2CC8626D, 0x3387, 0x4817, {0xAB, 0xF6, > 0x86, 0x9A, 0xF5, 0xF0, 0x51, 0xAA}} >=20 > +gPerfHdaPostMemGuid =3D {0xB31883B7, 0x5A05, 0x4040, {0x40, 0x80, > 0x66, 0x8D, 0x29, 0x13, 0xD7, 0x84}} >=20 > + >=20 > +## >=20 > +## Dp-In Guid >=20 > +## >=20 > +## Include/DpInDataHob.h >=20 > +gDpInHobGuid =3D {0x3e110a83, 0xb94b, 0x4648, {0xa2, 0x26, 0x50, 0x9b, > 0xd5, 0x55, 0xe3, 0x6b}} >=20 > +## Include/ConfigBlock/Tcss/DpInPreMemConfig.h >=20 > +gDpInPreMemConfigGuid =3D {0x80c14ba, 0xcc84, 0x4746, {0xbf, 0x6b, 0xd1, > 0xf1, 0x8e, 0xaa, 0xe8, 0x35}} >=20 > + >=20 > +[Protocols.common.Private] >=20 > +## >=20 > +## SA >=20 > +## >=20 > +gSaIotrapSmiProtocolGuid =3D { 0x1861e089, 0xcaa3, 0x473e, { 0x84, 0x= 32, > 0xdc, 0x1f, 0x94, 0xc6, 0xc1, 0xa6 }} >=20 > +gCpuPcieIoTrapProtocolGuid =3D { 0xda904080, 0x33ab, 0x48ca, { 0x97, 0x= 5b, > 0x5f, 0x2f, 0x23, 0x8a, 0x41, 0xb4 }} >=20 > + >=20 > +gPchPcieIoTrapProtocolGuid =3D { 0xd66a1cf, 0x79ad, 0x494b, { 0x97= , 0x8b, > 0xb2, 0x59, 0x81, 0x68, 0x93, 0x34 }} >=20 > + >=20 > +[Protocols] >=20 > +## >=20 > +## MdeModulePkg >=20 > +## >=20 > +gEfiSmmVariableProtocolGuid =3D {0xed32d533, 0x99e6, 0x4209, {0x9c, 0x= c0, > 0x2d, 0x72, 0xcd, 0xd9, 0x98, 0xa7}} >=20 > +gEdkiiPlatformSpecificResetFilterProtocolGuid =3D { 0x695d7835, 0x8d47, > 0x4c11, { 0xab, 0x22, 0xfa, 0x8a, 0xcc, 0xe7, 0xae, 0x7a } } >=20 > +gEdkiiPlatformSpecificResetHandlerProtocolGuid =3D { 0x2df6ba0b, 0x7092, > 0x440d, { 0xbd, 0x4, 0xfb, 0x9, 0x1e, 0xc3, 0xf3, 0xc1 } } >=20 > + >=20 > +## >=20 > +## SystemAgent >=20 > +## >=20 > +gBdatAccessGuid =3D {0x9477482c, 0x8717, 0x4725, {0x98,= 0x28, 0x7b, > 0xd8, 0xc9, 0xa3, 0x75, 0x6a}} >=20 > +gIgdOpRegionProtocolGuid =3D {0x9e67aecf, 0x4fbb, 0x4c84, {0x99,= 0xa5, > 0x10, 0x73, 0x40, 0x7, 0x6d, 0xb4}} >=20 > +gMemInfoProtocolGuid =3D {0xd4d2f201, 0x50e8, 0x4d45, {0x8e,= 0x5, > 0xfd, 0x49, 0xa8, 0x2a, 0x15, 0x69}} >=20 > +gSaPolicyProtocolGuid =3D {0xc6aa1f27, 0x5597, 0x4802, {0x9f,= 0x63, > 0xd6, 0x28, 0x36, 0x59, 0x86, 0x35}} >=20 > +gSaNvsAreaProtocolGuid =3D {0x149a10a5, 0x9d06, 0x4c6b, {0xbe,= 0x44, > 0x08, 0x92, 0xce, 0x20, 0x61, 0xac}} >=20 > +gGopPolicyProtocolGuid =3D {0xec2e931b, 0x3281, 0x48a5, {0x81,= 0x07, > 0xdf, 0x8a, 0x8b, 0xed, 0x3c, 0x5d}} >=20 > +gGen12PolicyProtocolGuid =3D {0x40f60ea0, 0x6c96, 0x4ed3, {0x96,= 0xe5, > 0xba, 0x6f, 0x6d, 0x66, 0x28, 0x9f}} >=20 > +gGen9PolicyProtocolGuid =3D {0xeaaed1ba, 0xf15c, 0x4112, {0xb5,= 0x82, > 0x90, 0x63, 0xac, 0xa0, 0x7f, 0x06}} >=20 > +gGopComponentName2ProtocolGuid =3D {0x651b7ebd, 0xce13, 0x41d0, > {0x82, 0xe5, 0xa0, 0x63, 0xab, 0xbe, 0x9b, 0xb6}} >=20 > +gGopOverrideProtocolGuid =3D {0x4a89a16e, 0x67b8, 0x4429, {0x8c,= 0x47, > 0x43, 0x67, 0x90, 0xf2, 0xf2, 0x69}} >=20 > +gMemoryAddressEncodeDecodeProtocolGuid =3D {0x603df7ca, 0x1ba8, > 0x4c12, {0xa9, 0x8a, 0x49, 0x6d, 0xfe, 0x77, 0xeb, 0xdf}} >=20 > + >=20 > +## >=20 > +## TBT >=20 > +## >=20 > +gITbtPolicyProtocolGuid =3D {0xb0563c42, 0x28ea, 0x40e6, {0x99, 0= x84, > 0xd5, 0xbf, 0xf8, 0xb0, 0x40, 0x56}} >=20 > +gITbtNvsAreaProtocolGuid =3D {0xdabf85bd, 0xfbdc, 0x4ed2, {0xb1, 0= x0d, > 0xc9, 0x08, 0xd0, 0x8c, 0xee, 0xe8}} >=20 > +gDisableITbtBmeProtocolGuid =3D {0x89a9adc3, 0x9b7c, 0x4b53, {0x82= , > 0xbf, 0x78, 0x72, 0x6b, 0x91, 0x4f, 0x9f}} >=20 > + >=20 > +## >=20 > +## Cpu >=20 > +## >=20 > +gCpuInfoProtocolGuid =3D {0xe223cf65, 0xf6ce, 0x4122, {0xb3, 0xaf, 0x4= b, > 0xd1, 0x8a, 0xff, 0x40, 0xa1}} >=20 > +gSmmBiosGuardProtocolGuid =3D {0x17565311, 0x4b71, 0x4340, {0x88, 0xaa= , > 0xdc, 0x9f, 0x44, 0x22, 0xe5, 0x3a}} >=20 > +gCpuNvsAreaProtocolGuid =3D {0xb9cf3f43, 0xbe3e, 0x4e45, {0xa0, 0xbe, > 0x1a, 0x4, 0x89, 0xdf, 0x1a, 0xc9}} >=20 > +gDxeCpuPolicyProtocolGuid =3D {0x8282b977, 0x22f9, 0x4134, {0x99, 0x43= , > 0x7b, 0xcc, 0x5f, 0x40, 0x33, 0x52}} >=20 > +gBiosGuardNvsAreaProtocolGuid =3D {0x5df588da, 0x991e, 0x4a7f, {0x80, > 0x51, 0x70, 0xc7, 0x12, 0xb7, 0xba, 0xb0}} >=20 > +gSmmResourceConfigProtocolGuid =3D {0xA37FC2D2, 0x822D, 0x4A63, {0x9C, > 0x42, 0xBE, 0xB1, 0xD6, 0xEE, 0x85, 0x39}} >=20 > + >=20 > +## >=20 > +## Me >=20 > +## >=20 > +gActiveManagementProtocolGuid =3D {0xd25dc167, 0xeb6a, 0x432d, {0x65= , > 0x91, 0xbf, 0x80, 0x29, 0xb0, 0x05, 0xbb}} >=20 > +gAlertStandardFormatProtocolGuid =3D {0x45de9920, 0xcd54, 0x446a, {0xa0= , > 0x3c, 0x22, 0xe6, 0xfb, 0xb4, 0x51, 0xe4}} >=20 > +gHeciProtocolGuid =3D {0x3c7bc880, 0x41f8, 0x4869, {0xae= , 0xfc, 0x87, > 0x0a, 0x3e, 0xd2, 0x82, 0x99}} >=20 > +gHeciFlowProtocolGuid =3D {0x1498d127, 0x123c, 0x4e52, {0x84= , 0x00, > 0xcc, 0x3c, 0x9f, 0x79, 0xc4, 0x0e}} >=20 > +gMebxProtocolGuid =3D {0x01ab1829, 0xcecd, 0x4cfa, {0xa1= , 0x8c, > 0xea, 0x75, 0xd6, 0x6f, 0x3e, 0x74}} >=20 > +gDxeMePolicyGuid =3D {0xa0b5dc52, 0x4f34, 0x3990, {0xd4= , 0x91, > 0x10, 0x8b, 0xe8, 0xba, 0x75, 0x42}} >=20 > +gMeInfoProtocolGuid =3D {0x7523c8e4, 0x4fbe, 0x9661, {0x29= , 0x96, > 0x14, 0x97, 0xff, 0x36, 0x2f, 0x3b}} >=20 > +gPlatformMeHookProtocolGuid =3D {0xbc52476e, 0xf67e, 0x4301, {0xb2= , > 0x62, 0x36, 0x9c, 0x48, 0x78, 0xaa, 0xc2}} >=20 > +gMeNvsAreaProtocolGuid =3D {0x3bffecfd, 0xd75f, 0x4975, {0xb8= , 0x88, > 0x39, 0x02, 0xbd, 0x69, 0x00, 0x2b}} >=20 > +gJhiProtocolGuid =3D {0xccba3051, 0xa574, 0x4f9d, {0x96= , 0xf4, 0xec, > 0x0d, 0x4a, 0x87, 0xbc, 0x5a}} >=20 > +gIntegratedTouchHidProtocolGuid =3D {0x3d0479c1, 0x6b19, 0x4191, {0xb8= , > 0x09, 0x60, 0x08, 0xdd, 0x07, 0x97, 0x55}} >=20 > +gIntegratedTouchProtocolGuid =3D {0x2b12e46f, 0x3c24, 0x47ff, {0x8b= , > 0x89, 0xc0, 0x60, 0x2c, 0x1c, 0x61, 0x42}} >=20 > +gMeEopDoneProtocolGuid =3D {0x8d9b3387, 0x73db, 0x456f, {0x88= , > 0x9d, 0x6f, 0xfe, 0x90, 0x82, 0x64, 0x09}} >=20 > +gMeSendEopInFspProtocolGuid =3D {0xcecdba92, 0x76c6, 0x4063, {0xaa= , > 0x6b, 0x19, 0xfc, 0x60, 0x5c, 0x70, 0xff}} >=20 > + >=20 > +gHeciAccessProtocolGuid =3D {0x3a5aab32, 0xd5a7, 0x4ce8, {0x88,= 0xe2, > 0xed, 0x8f, 0x7b, 0x43, 0x23, 0x9d}} >=20 > +gHeciTransportProtocolGuid =3D {0x9fc932b9, 0x8851, 0x43f7, {0x8a,= 0x58, > 0xa8, 0xd9, 0x04, 0x01, 0xcd, 0x78}} >=20 > +gHeciControlProtocolGuid =3D {0xd86381d8, 0xff7e, 0x462e, {0x9b,= 0x55, > 0x02, 0x0a, 0x64, 0x1b, 0xe3, 0x4f}} >=20 > +gHeciAccessSmmProtocolGuid =3D {0x5da6182c, 0xf679, 0x49eb, {0x96, > 0xf5, 0xe6, 0x24, 0x9b, 0x54, 0x0b, 0x96}} >=20 > +gHeciTransportSmmProtocolGuid =3D {0xf5f7b292, 0xbb38, 0x4e59, {0xa1, > 0x6e, 0x0f, 0x27, 0x15, 0xd4, 0xb7, 0xf4}} >=20 > +gHeciControlSmmProtocolGuid =3D {0x7e1e508d, 0x7def, 0x4d69, {0xa9, > 0xb3, 0xa5, 0x23, 0xe8, 0x48, 0xc6, 0x98}} >=20 > + >=20 > +## >=20 > +## Amt >=20 > +## >=20 > +gAmtSaveMebxProtocolGuid =3D {0x86682c04, 0xea42, 0x49e5, {0x96= , > 0x81, 0xe3, 0x32, 0xaa, 0xb0, 0x9e, 0xd7}} >=20 > +gDxeAmtPolicyGuid =3D {0x6725e645, 0x4a7f, 0x9969, {0x82= , 0xec, > 0xd1, 0x87, 0x21, 0xde, 0x5a, 0x57}} >=20 > +gAmtReadyToBootProtocolGuid =3D {0xcc9d5c0b, 0x9010, 0x45f1, {0x99= , > 0x3c, 0x83, 0x27, 0x67, 0xf1, 0x67, 0x77}} >=20 > +gMeSmbiosTablesUpdateProtocolGuid =3D {0x5054ee06, 0x4ce0, 0x4acc, > {0x9a, 0x80, 0xdf, 0x73, 0xbf, 0xa5, 0x38, 0xdd}} >=20 > +gOneClickRecoveryProtocolGuid =3D {0x93598eac, 0xc62b, 0x4dbb, {0x96= , > 0x76, 0xe0, 0x5e, 0x8c, 0xc3, 0x84, 0x44}} >=20 > + >=20 > +## >=20 > +## PCH >=20 > +## >=20 > +gThcProtocolGuid =3D {0x00860921, 0x7B9B, 0x4EA8, {0xAD, 0x23, 0x3C, 0x= CA, > 0x33, 0x9E, 0x7D, 0xFE}} >=20 > +gPchSpiProtocolGuid =3D {0xc7d289, 0x1347, 0x4de0, {0xbf, 0x42, 0xe, 0= x26, > 0x9d, 0xe, 0xf3, 0x4a}} >=20 > +gWdtProtocolGuid =3D {0xb42b8d12, 0x2acb, 0x499a, {0xa9, 0x20, 0xdd, 0= x5b, > 0xe6, 0xcf, 0x09, 0xb1}} >=20 > +gPchSerialIoUartDebugInfoProtocolGuid =3D {0x2fd2b1bd, 0x0387, 0x4ec6, > {0x94, 0x1f, 0xf1, 0x4b, 0x7f, 0x1c, 0x94, 0xb6}} >=20 > +gEfiSmmSmbusProtocolGuid =3D {0x72e40094, 0x2ee1, 0x497a, {0x8f, 0x33, > 0x4c, 0x93, 0x4a, 0x9e, 0x9c, 0x0c}} >=20 > +gPchSmmSpiProtocolGuid =3D {0x56521f06, 0xa62, 0x4822, {0x99, 0x63, 0x= df, > 0x1, 0x9d, 0x72, 0xc7, 0xe1}} >=20 > +gPchSmmIoTrapControlGuid =3D {0x514d2afd, 0x2096, 0x4283, {0x9d, 0xa6, > 0x70, 0x0c, 0xd2, 0x7d, 0xc7, 0xa5}} >=20 > +gPchTcoSmiDispatchProtocolGuid =3D {0x9e71d609, 0x6d24, 0x47fd, {0xb5, > 0x72, 0x61, 0x40, 0xf8, 0xd9, 0xc2, 0xa4}} >=20 > +gPchPcieSmiDispatchProtocolGuid =3D {0x3e7d2b56, 0x3f47, 0x42aa, {0x8f= , > 0x6b, 0x22, 0xf5, 0x19, 0x81, 0x8d, 0xab}} >=20 > +gPchAcpiSmiDispatchProtocolGuid =3D {0xd52bb262, 0xf022, 0x49ec, {0x86= , > 0xd2, 0x7a, 0x29, 0x3a, 0x7a, 0x05, 0x4b}} >=20 > +gPchSmiDispatchProtocolGuid =3D {0xE6A81BBF, 0x873D, 0x47FD, {0xB6, > 0xBE, 0x61, 0xB3, 0xE5, 0x72, 0x09, 0x93}} >=20 > +gPchNvsAreaProtocolGuid =3D {0x2e058b2b, 0xedc1, 0x4431, {0x87, 0xd9, > 0xc6, 0xc4, 0xea, 0x10, 0x2b, 0xe3}} >=20 > +gPchEspiSmiDispatchProtocolGuid =3D {0xB3C14FF3, 0xBAE8, 0x456C, {0x86= , > 0x31, 0x27, 0xFE, 0x0C, 0xEB, 0x34, 0x0C}} >=20 > +gPchSmmPeriodicTimerControlGuid =3D {0x6906E93B, 0x603B, 0x4A0F, {0x86= , > 0x92, 0x83, 0x20, 0x04, 0xAA, 0xF2, 0xDB}} >=20 > +gIoTrapExDispatchProtocolGuid =3D {0x5B48E913, 0x707B, 0x4F9D, {0xAF, > 0x2E, 0xEE, 0x03, 0x5B, 0xCE, 0x39, 0x5D}} >=20 > +gPchPolicyProtocolGuid =3D {0x543d5c93, 0x6a28, 0x4513, {0x85= , 0x9a, > 0x82, 0xa7, 0xb9, 0x12, 0xcb, 0xbe}} >=20 > +gScsEmmcSoftwareTuningProtocolGuid =3D {0x972215b2, 0x9616, 0x4de4, > {0xa9, 0x75, 0xb0, 0x74, 0x3e, 0xe1, 0x78, 0x54}} >=20 > + >=20 > +## >=20 > +## Hsti >=20 > +## >=20 > +## HstiSiliconDxe Driver Entry Point >=20 > +gHstiProtocolGuid =3D { 0x1b05de41, 0xc93b, 0x4bb4, { 0xad, 0x47, 0x2a, = 0x78, > 0xac, 0xf, 0xc9, 0xe4 }} >=20 > +## Handler to gather and publish HSTI results on ReadyToBootEvent >=20 > +gHstiPublishCompleteProtocolGuid =3D {0x0f500be6, 0xece4, 0x4ed8, { 0x9= 0, > 0x81, 0x9a, 0xa9, 0xa5, 0x23, 0xfb, 0x7b}} >=20 > +gEfiAdapterInformationProtocolGuid =3D { 0xE5DD1403, 0xD622, 0xC24E, > {0x84, 0x88, 0xC7, 0x1B, 0x17, 0xF5, 0xE8, 0x02 }} >=20 > + >=20 > +## >=20 > +## Silicon Policy >=20 > +## >=20 > +## Include/Protocol/SiPolicyProtocol.h >=20 > +gDxeSiPolicyProtocolGuid =3D { 0xeca27516, 0x306c, 0x4e28, { 0x8c, 0x94, > 0x4e, 0x52, 0x10, 0x96, 0x69, 0x5e }} >=20 > + >=20 > +## >=20 > +## DGR >=20 > +## >=20 > +gEfiSpaLogOutputProtocolGuid =3D { 0x1d10d46b, 0x0306, 0x454a, { 0x90, > 0x8c, 0x93, 0x65, 0xb3, 0x8a, 0x90, 0x26 }} >=20 > + >=20 > +[Ppis.common.Private] >=20 > +gPchHsioChipsetInitSusTblDataPpiGuid =3D { 0x97ed4e5d, 0x01a5, 0x4a3c, { > 0xb7, 0xe9, 0x1a, 0x4e, 0xa3, 0xdd, 0x23, 0xce }} >=20 > +gHybridStorageCfgPpiGuid =3D {0x8557e481, 0xc00e, 0x4929, {0xb4, 0x53, > 0xf6, 0xc2, 0x53, 0x79, 0xb0, 0x13}} >=20 > + >=20 > +[Ppis] >=20 > +## >=20 > +## MdeModulePkg >=20 > +## >=20 > +gPeiCapsulePpiGuid =3D {0x3acf33ee, 0xd892, 0x40f4, {0xa2, 0xfc, 0x38,= 0x54, > 0xd2, 0xe1, 0x32, 0x3d}} >=20 > +gPeiSmmControlPpiGuid =3D {0x61c68702, 0x4d7e, 0x4f43, {0x8d, 0xef, 0x= a7, > 0x43, 0x05, 0xce, 0x74, 0xc5}} >=20 > +gEdkiiPlatformSpecificResetFilterPpiGuid =3D { 0x8c9f4de3, 0x7b90, 0x47e= f, { > 0x93, 0x8, 0x28, 0x7c, 0xec, 0xd6, 0x6d, 0xe8 } } >=20 > +gEdkiiPlatformSpecificResetNotificationPpiGuid =3D { 0xe09f355d, 0xdae8, > 0x4910, { 0xb1, 0x4a, 0x92, 0x78, 0xf, 0xdc, 0xf7, 0xcb } } >=20 > +gEdkiiPlatformSpecificResetHandlerPpiGuid =3D { 0x75cf14ae, 0x3441, 0x49= dc, > { 0xaa, 0x10, 0xbb, 0x35, 0xa7, 0xba, 0x8b, 0xab } } >=20 > + >=20 > +## >=20 > +## SecurityPkg >=20 > +## >=20 > +gPeiTpmInitializedPpiGuid =3D {0xe9db0d58, 0xd48d, 0x47f6, {0x9c, 0x6e= , > 0x6f, 0x40, 0xe8, 0x6c, 0x7b, 0x41}} >=20 > +gPeiTpmInitializationDonePpiGuid =3D {0xa030d115, 0x54dd, 0x447b, { 0x90= , > 0x64, 0xf2, 0x6, 0x88, 0x3d, 0x7c, 0xcc}} >=20 > +## >=20 > +## Common >=20 > +## >=20 > +## Include/Ppi/SiPolicy.h >=20 > +gSiPolicyPpiGuid =3D {0xaebffa01, 0x7edc, 0x49ff, {0x8d, 0x88, 0xcb, 0= x84, > 0x8c, 0x5e, 0x86, 0x70}} >=20 > +## Include/Ppi/SiPolicy.h >=20 > +gSiPreMemPolicyPpiGuid =3D {0xc133fe57, 0x17c7, 0x4b09, {0x8b, 0x3c, 0x9= 7, > 0xc1, 0x89, 0xd0, 0xab, 0x8d}} >=20 > +gFspApiModePpiGuid =3D {0xa1eeab87, 0xc859, 0x479d, {0x89, 0xb5= , > 0x14, 0x61, 0xf4, 0x06, 0x1a, 0x3e}} >=20 > +## Silicon Initialization PPI is used to export End of Silicon init. >=20 > +gEndOfSiInitPpiGuid =3D {0xE2E3D5D1, 0x8356, 0x4F96, {0x9C, 0x9E= , 0x2E, > 0xC3, 0x48, 0x1D, 0xEA, 0x88}} >=20 > +gEfiEndOfPeiSignal2PpiGuid =3D {0x22918381, 0xd018, 0x4d7c, {0x9d, 0x62= , > 0xf5, 0xa5, 0x70, 0x1c, 0x66, 0x80}} >=20 > +gFspTempRamExitPpiGuid =3D {0xbc1cfbdb, 0x7e50, 0x42be, {0xb4, 0x87= , > 0x22, 0xe0, 0xa9, 0x0c, 0xb0, 0x52}} >=20 > +gFspmArchConfigPpiGuid =3D {0x824d5a3a, 0xaf92, 0x4c0c, {0x9f, 0x19= , > 0x19, 0x52, 0x6d, 0xca, 0x4a, 0xbb}} >=20 > +gSiPreMemDefaultPolicyInitPpiGuid =3D {0xfec36242, 0xf8d8, 0x4b43, {0x8= 7, > 0x94, 0x4f, 0x1f, 0x9f, 0x63, 0x8d, 0xdc}} >=20 > +gSiPreMemPolicyReadyPpiGuid =3D {0x85270bef, 0x6984, 0x4375, {0xa6, 0xea= , > 0xb5, 0xaa, 0x90, 0x6e, 0xdd, 0x4a}} >=20 > +gSiDefaultPolicyInitPpiGuid =3D {0xf69abf86, 0x4048, 0x44ef, { 0xa8, 0xe= f, > 0x6c, 0x7f, 0x20, 0x4a, 0xc8, 0xda}} >=20 > +gSiPolicyReadyPpiGuid =3D {0xd570de8c, 0xb9c4, 0x4ffa, {0xad, 0xee= , 0xa5, > 0x82, 0x7c, 0xe3, 0x17, 0x79}} >=20 > + >=20 > +## >=20 > +## UEFI Variable Support (Override Until BP1.5) >=20 > +## >=20 > +gEdkiiVariableStoragePpiGuid =3D { 0x90d915c5, 0xe4c1, 0x4da8, {0xa7, = 0x6f, > 0x9, 0xe5, 0x78, 0x91, 0x65, 0x48}} >=20 > +gEdkiiVariableStorageSelectorPpiGuid =3D { 0x782546d1, 0x03ab, 0x41e4, > {0xa0, 0x1d, 0x7a, 0x9b, 0x22, 0xba, 0x2e, 0x1e}} >=20 > +gReadOnlyVariablePreMemoryDescriptorPpiGuid =3D { 0xbe136fc9, 0xc277, > 0x4dd1, {0xbe, 0x42, 0xce, 0xf0, 0x9f, 0xf4, 0x3f, 0x55}} >=20 > +gEfiReadyToInstallEndOfPei2PpiGuid =3D {0xeef72924, 0x2db2, 0x4569, { 0x= 86, > 0x3f, 0xd4, 0x86, 0xae, 0x7a, 0xe4, 0x12}} >=20 > + >=20 > +## >=20 > +## SystemAgent >=20 > +## >=20 > +gSsaBiosCallBacksPpiGuid =3D {0x99b56126, 0xe16c, 0x4d9b, {0xbb, 0x71, > 0xaa, 0x35, 0x46, 0x1a, 0x70, 0x2f}} >=20 > +gSsaBiosServicesPpiGuid =3D {0x55750d10, 0x6d3d, 0x4bf5, {0x89, 0xd8, > 0xe3, 0x5e, 0xf0, 0xb0, 0x90, 0xf4}} >=20 > +gEnablePeiGraphicsPpiGuid =3D {0x8e3bb474, 0x545, 0x4902, {0x86, 0xb0, > 0x6c, 0xb5, 0xe2, 0x64, 0xb4, 0xa5}} >=20 > +gPeiGraphicsFramebufferReadyPpiGuid =3D {0x590ad868, 0xb0b1, 0x4d20, > {0x91, 0xff, 0xc2, 0xa9, 0xd6, 0x88, 0x81, 0x94}} >=20 > +gMrcMemoryInitDonePpiGuid =3D {0x0ff07255, 0x67c2, 0x456d, {0x9a, 0x95, > 0xc9, 0x16, 0x2c, 0x23, 0x86, 0x8d}} >=20 > +## X Compatibility support PPI >=20 > +gCompatibleMemoryInitPpiGuid =3D {0xca311f82, 0xf490, 0x4b12, {0x9e, 0xe= 1, > 0x2b, 0x66, 0xa3, 0x6c, 0x3e, 0xa}} >=20 > +gVmdInitDonePpiGuid =3D {0x42a187c8, 0xca0a, 0x4750, {0x82, 0xf= d, 0xc9, > 0xa0, 0xd5, 0x9, 0xfe, 0xd1}} >=20 > + >=20 > +## >=20 > +## TwoLm >=20 > +## >=20 > +gMrcMemoryInitDonePpiGuid =3D { 0x598907f5, 0xd5fc, 0x435c, { 0x8a, 0x7= f, > 0x53, 0xc5, 0xa4, 0xb5, 0x31, 0xc4}} >=20 > + >=20 > +## >=20 > +## Nvdimm Cache Info >=20 > +## >=20 > +gNvdimmCachePpiGuid =3D { 0x1bbc5601, 0xe571, 0x4ae0, { 0xbc, 0x38, 0xb= 8, > 0x65, 0x0d, 0x50, 0x6f, 0x5b}} >=20 > + >=20 > +## >=20 > +## Cpu >=20 > +## >=20 > +gPeiCachePpiGuid =3D {0x09be4bc2, 0x790e, 0x4dea, {0x8b, 0xdc, 0x38, 0= x05, > 0x16, 0x98, 0x39, 0x44}} >=20 > +gPeiTxtMemoryUnlockedPpiGuid =3D {0x38cdd10b, 0x767d, 0x4f6e, {0xa7, > 0x44, 0x67, 0xee, 0x1d, 0xfe, 0x2f, 0xa5}} >=20 > +gPeiTxtReadyToRunMemoryInitPpiGuid =3D {0x9ecafd30, 0x29e2, 0x42f6, > {0xba, 0xf3, 0x8b, 0x7d, 0xb8, 0xfe, 0x1f, 0x22}} >=20 > +gPeiReadyToInstallMpPpiGuid =3D { 0x1a266768, 0xfd43, 0x4e18, { 0xa8, 0x= 8a, > 0x35, 0xc7, 0x94, 0xc3, 0x91, 0x0e }} >=20 > +## >=20 > +## Me >=20 > +## >=20 > +gHeciPpiGuid =3D {0xd14319e2, 0x407a, 0x9580, {0x8d, 0xe5, 0x51, 0xa8,= 0xff, > 0xc6, 0xd7, 0xd7}} >=20 > +gMbpSensitivePpiGuid =3D {0xed7c9ce9, 0x5912, 0x4807, {0xec, 0x90, 0x2= 2, > 0x18, 0xbc, 0x7b, 0xfc, 0x6c}} >=20 > +gHeci3IntegratedTouchControllerGuid =3D {0x3e8d0870, 0x271a, 0x4208, > {0x8e, 0xb5, 0x9a, 0xcb, 0x94, 0x02, 0xae, 0x04}} >=20 > +gSiNvmOwnershipAcquiredPpiGuid =3D {0xe5db3d8c, 0xefa4, 0x4308, {0x9a, > 0xab, 0x6b, 0x97, 0x81, 0x09, 0x98, 0xa0}} >=20 > +gHeciAccessPpiGuid =3D {0x3a5aab32, 0xd5a7, 0x4ce8, {0x88, 0xe2, 0xed, 0= x8f, > 0x7b, 0x43, 0x23, 0x9d}} >=20 > +gHeciTransportPpiGuid =3D {0x9fc932b9, 0x8851, 0x43f7, {0x8a, 0x58, 0xa8= , > 0xd9, 0x04, 0x01, 0xcd, 0x78}} >=20 > +gHeciControlPpiGuid =3D {0xd86381d8, 0xff7e, 0x462e, {0x9b, 0x55, 0x02, > 0x0a, 0x64, 0x1b, 0xe3, 0x4f}} >=20 > +gMeBeforeDidSentPpiGuid =3D {0xd497b143, 0xf3ef, 0x4192, {0xa8, 0xc5, > 0x5e, 0xf6, 0xcd, 0x6e, 0x4c, 0x87}} >=20 > + >=20 > +## >=20 > +## PCH >=20 > +## >=20 > +gWdtPpiGuid =3D {0xf38d1338, 0xaf7a, 0x4fb6, {0x91, 0xdb, 0x1a, 0x9c, = 0x21, > 0x83, 0x57, 0x0d}} >=20 > +gPchSpiPpiGuid =3D {0xdade7ce3, 0x6971, 0x4b75, {0x82, 0x5e, 0xe, 0xe0= , > 0xeb, 0x17, 0x72, 0x2d}} >=20 > +gPeiSmbusPolicyPpiGuid =3D {0x63b6e435, 0x32bc, 0x49c6, {0x81, 0xbd, 0= xb7, > 0xa1, 0xa0, 0xfe, 0x1a, 0x6c}} >=20 > + >=20 > +## >=20 > +## TCSS >=20 > +## >=20 > +gTcssPeiInitDonePpiGuid =3D {0x5ad291b8, 0xace4, 0x416a, {0xb7, 0x50, 0x= 7, > 0x63, 0x59, 0xfc, 0xc1, 0x5b}} >=20 > + >=20 > +[LibraryClasses] >=20 > +## @libraryclass >=20 > +## Common >=20 > +## >=20 > +MmPciLib|Include/Library/MmPciLib.h >=20 > + >=20 > +## @libraryclass >=20 > +## SampleCode >=20 > +## >=20 > +## CPU >=20 > +## >=20 > +CpuPolicyLib|Cpu/Include/Library/CpuPolicyLib.h >=20 > + >=20 > +## @libraryclass >=20 > +## Me >=20 > +## >=20 > + >=20 > +MeChipsetLib|Me/Include/Library/MeChipsetLib.h >=20 > + >=20 > +PeiMePolicyLib|Me/Include/Library/PeiMePolicyLib.h >=20 > +PttHciLib|Me/Include/Library/PttHciLib.h >=20 > +PttHeciLib|Me/Include/Library/PttHeciLib.h >=20 > +## @libraryclass >=20 > +## Pch >=20 > +## >=20 > +GpioLib|Include/Library/GpioLib.h >=20 > +GpioLib|Include/Library/GpioNativeLib.h >=20 > +PchCycleDecodingLib|Pch/Include/Library/PchCycleDecodingLib.h >=20 > +EspiLib|Include/Library/PchEspiLib.h >=20 > +GbeLib|Include/Library/GbeLib.h >=20 > +GbeMdiLib|IpBlock/Gbe/IncludePrivate/Library/GbeMdiLib.h >=20 > +PchHsioLib|Pch/IncludePrivate/PchHsio.h >=20 > +PchInfoLib|Pch/Include/Library/PchInfoLib.h >=20 > +PchP2sbLib|Pch/Include/Library/PchP2sbLib.h >=20 > +PchPcieRpLib|Pch/Include/Library/PchPcieRpLib.h >=20 > +PchPcrLib|Pch/Include/Library/PchPcrLib.h >=20 > +PchPolicyLib|Pch/Include/Library/PchPolicyLib.h >=20 > +PchSbiAccessLib|Pch/IncludePrivate/Library/PchSbiAccessLib.h >=20 > +SerialIoAccessLib|Include/Library/SerialIoAccessLib.h >=20 > +DxePchPolicyLib|Pch/Include/Library/DxePchPolicyLib.h >=20 > + >=20 > +## @libraryclass >=20 > +## Sa >=20 > +## >=20 > +DxeSaPolicyLib|SystemAgent/Include/Library/DxeSaPolicyLib.h >=20 > +SaPlatformLib|SystemAgent/Include/Library/SaPlatformLib.h >=20 > +Include/Library/VoltageRegulatorCommands.h >=20 > + >=20 > +[PcdsFixedAtBuild] >=20 > +## From MdeModulePkg.dec >=20 > +## Progress Code for S3 Suspend start. >=20 > +## PROGRESS_CODE_S3_SUSPEND_START =3D > (EFI_SOFTWARE_SMM_DRIVER | (EFI_OEM_SPECIFIC | 0x00000000)) =3D > 0x03078000 >=20 > +gSiPkgTokenSpaceGuid.PcdProgressCodeS3SuspendStart|0x03078000|UIN > T32|0x30001032 >=20 > +## Progress Code for S3 Suspend end. >=20 > +## PROGRESS_CODE_S3_SUSPEND_END =3D (EFI_SOFTWARE_SMM_DRIVER > | (EFI_OEM_SPECIFIC | 0x00000001)) =3D 0x03078001 >=20 > +gSiPkgTokenSpaceGuid.PcdProgressCodeS3SuspendEnd|0x03078001|UINT > 32|0x30001033 >=20 > +## >=20 > +## PcdNemCodeCacheBase is usally the same as PEI FV Base address, >=20 > +## FLASH_BASE+FLASH_REGION_FV_RECOVERY_OFFSET from > PlatformPkg.fdf. >=20 > +## >=20 > +## Restriction: >=20 > +## 1) PcdNemCodeCacheBase - (PcdTemporaryRamBase + > PcdTemporaryRamSize) >=3D 4K >=20 > +## 2) PcdTemporaryRamBase >=3D 4G - 64M >=20 > +## >=20 > +gSiPkgTokenSpaceGuid.PcdNemCodeCacheBase|0xFFF80000|UINT32|0x20 > 000009 >=20 > +## >=20 > +## NemCodeCacheSize is usally the same as PEI FV Size, >=20 > +## FLASH_REGION_FV_RECOVERY_SIZE from PlatformPkg.fdf. >=20 > +## >=20 > +## Restriction: >=20 > +## 1) PcdNemTotalCacheSize =3D NemCodeCacheSize + > PcdTemporaryRamSize >=20 > +## <=3D Maximun CPU NEM total size (Code + Data) >=20 > +## =3D LLC size - 0.5M >=20 > +## 2) PcdTemporaryRamSize <=3D Maximum CPU NEM data size >=20 > +## =3D MLC size >=20 > +## NOTE: The size restriction may be changed in next generation processo= r. >=20 > +## Please refer to Processor BWG for detail. >=20 > +## >=20 > +gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress|0xFF800000|UINT32|0x1 > 0000001 >=20 > +gSiPkgTokenSpaceGuid.PcdBiosSize|0x00800000|UINT32|0x10000002 >=20 > +gSiPkgTokenSpaceGuid.PcdTemporaryRamBase|0xfef00000|UINT32|0x000 > 10028 >=20 > +gSiPkgTokenSpaceGuid.PcdTemporaryRamSize|0x2000|UINT32|0x0001002 > 9 >=20 > +gSiPkgTokenSpaceGuid.PcdTopMemoryCacheSize|0x0|UINT32|0x0001002 > A >=20 > +gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase|0xFFE60000|UINT32|0x > 30000004 >=20 > +gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize|0x000A0000|UINT32|0x3 > 0000005 >=20 > +gSiPkgTokenSpaceGuid.PcdFlashMicrocodeOffset|0x00000060|UINT32|0x3 > 0000013 >=20 > +gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset|0x00660000|UINT32|0 > x30000006 >=20 > +## >=20 > +## The CPU Trace Hub's BARs base and size >=20 > +## >=20 > +gSiPkgTokenSpaceGuid.PcdCpuTraceHubMtbBarBase|0xfad00000|UINT32| > 0x30000007 >=20 > +gSiPkgTokenSpaceGuid.PcdCpuTraceHubMtbBarSize|0x100000|UINT32|0x > 30000008 >=20 > +gSiPkgTokenSpaceGuid.PcdCpuTraceHubSwBarBase|0xfc000000|UINT32|0 > x30000009 >=20 > +gSiPkgTokenSpaceGuid.PcdCpuTraceHubSwBarSize|0x800000|UINT32|0x30 > 00000A >=20 > +gSiPkgTokenSpaceGuid.PcdCpuTraceHubRtitBarBase|0xfacfc000|UINT32|0 > x3000000B >=20 > +gSiPkgTokenSpaceGuid.PcdCpuTraceHubRtitBarSize|0x4000|UINT32|0x300 > 0000C >=20 > +gSiPkgTokenSpaceGuid.PcdCpuTraceHubFwBarBase|0xfae00000|UINT32|0 > x3000000D >=20 > +gSiPkgTokenSpaceGuid.PcdCpuTraceHubFwBarSize|0x200000|UINT32|0x30 > 00000E >=20 > + >=20 > +gSiPkgTokenSpaceGuid.PcdFspWrapperEnable > |FALSE|BOOLEAN|0x3000000F >=20 > +gSiPkgTokenSpaceGuid.PcdFspBinaryEnable|FALSE|BOOLEAN|0x30000010 >=20 > +gSiPkgTokenSpaceGuid.PcdEmbeddedEnable|0x0|UINT8|0x30000012 >=20 > + >=20 > +## >=20 > +## PcdEfiGcdAllocateType is using for EFI_GCD_ALLOCATE_TYPE selection >=20 > +## value of the struct >=20 > +## 0x00 EfiGcdAllocateAnySearchBottomUp >=20 > +## 0x01 EfiGcdAllocateMaxAddressSearchBottomUp >=20 > +## 0x03 EfiGcdAllocateAnySearchTopDown >=20 > +## 0x04 EfiGcdAllocateMaxAddressSearchTopDown >=20 > +## >=20 > +## below value should not using in this situation >=20 > +## 0x05 EfiGcdMaxAllocateType : design for max value of struct >=20 > +## 0x02 EfiGcdAllocateAddress : design for speccification address alloc= ate >=20 > +## >=20 > +gSiPkgTokenSpaceGuid.PcdEfiGcdAllocateType|0x01|UINT8|0x40000000 >=20 > + >=20 > +## >=20 > +## Handshake register value driven to DMA controller PCIE venodr specif= ic > configuration register from FW >=20 > +## (LC/CM to host) >=20 > +## >=20 > +gSiPkgTokenSpaceGuid.PcdITbtToPcieRegister|0xEC|UINT8|0x40000003 >=20 > +## >=20 > +## Handshake register value driven from DMA controller PCIE venodr > specific configuration register to FW >=20 > +## (HOST to LC/CM) >=20 > +## >=20 > +gSiPkgTokenSpaceGuid.PcdPcieToITbtRegister|0xF0|UINT8|0x40000004 >=20 > + >=20 > +gSiPkgTokenSpaceGuid.PcdAbove4GBMmioBase|0x0000004000000000|UIN > T64|0x40000005 >=20 > +gSiPkgTokenSpaceGuid.PcdAbove4GBMmioSize|0x0000004000000000|UIN > T64|0x40000006 >=20 > + >=20 > +gSiPkgTokenSpaceGuid.PcdSmmEntryPointBinFile|{ 0x52, 0xce, 0xc8, 0xe0, > 0x51, 0x2b, 0xc2, 0x4c, 0xb3, 0xc7, 0xd2, 0x11, 0xa6, 0x25, 0xc1, 0xba > }|VOID*|0x40000007 >=20 > +gSiPkgTokenSpaceGuid.PcdSpsBinFile|{ 0xEE, 0xE3, 0x34, 0x71, 0xA6, 0x7F, > 0x89, 0x44, 0x87, 0xA7, 0xAE, 0x38, 0x98, 0x4E, 0xAE, 0xD8 > }|VOID*|0x40000008 >=20 > +gSiPkgTokenSpaceGuid.PcdSpsSmmEntryPointBinFile|{ 0x5B, 0x63, 0x7D, > 0x7C, 0x9C, 0x8B, 0x3C, 0x46, 0x9F, 0x7F, 0x91, 0xF6, 0x09, 0x06, 0x84, 0= x8F > }|VOID*|0x40000009 >=20 > +gSiPkgTokenSpaceGuid.PcdSpaBinFile|{ 0xE1, 0x19, 0xB7, 0x7B, 0x2A, 0x53, > 0x40, 0x7B, 0xA3, 0x4C, 0xC4, 0xF9, 0xE2, 0x6C, 0x27, 0x74 > }|VOID*|0x4000000A >=20 > +gSiPkgTokenSpaceGuid.PcdSpaSmmEntryPointBinFile|{ 0xD7, 0xAD, 0xB2, > 0x9F, 0x4D, 0x53, 0x4B, 0xA6, 0x8D, 0x55, 0x5D, 0x28, 0x91, 0x60, 0x10, 0= x19 > }|VOID*|0x4000000B >=20 > + >=20 > +## >=20 > +## - DpIn Silicon Feature >=20 > +## >=20 > +# Note: PcdDpInEnable is Default Disable. Override it based on Platform= / > CPU >=20 > +gSiPkgTokenSpaceGuid.PcdDpInEnable|FALSE|BOOLEAN|0x4000000C >=20 > +# Note: For PcdMaxDpInExtPortSupported, we can have Maximum value > of 0x08. >=20 > +# Please Don't exceed beyond that. As it will cause boundary overflow= . >=20 > +# Currently hadrware wise maximum Dp-In External Port supported is 4. >=20 > +# And it will never exceed the value of 0x08. That's why we don't sup= port >=20 > +# PcdMaxDpInExtPortSupported value more than 0x08 >=20 > +gSiPkgTokenSpaceGuid.PcdMaxDpInExtPortSupported|0x4|UINT8|0x4000 > 000D >=20 > + >=20 > +gSiPkgTokenSpaceGuid.VtdEngine1BaseAddeess|0xFED90000|UINT32|0x5 > 0000001 >=20 > +gSiPkgTokenSpaceGuid.VtdEngine2BaseAddeess|0xFED92000|UINT32|0x5 > 0000002 >=20 > +gSiPkgTokenSpaceGuid.VtdEngine3BaseAddeess|0xFED91000|UINT32|0x5 > 0000003 >=20 > +gSiPkgTokenSpaceGuid.VtdEngine4BaseAddeess|0xFED84000|UINT32|0x5 > 0000004 >=20 > +gSiPkgTokenSpaceGuid.VtdEngine5BaseAddeess|0xFED85000|UINT32|0x5 > 0000005 >=20 > +gSiPkgTokenSpaceGuid.VtdEngine6BaseAddeess|0xFED86000|UINT32|0x5 > 0000006 >=20 > +gSiPkgTokenSpaceGuid.VtdEngine7BaseAddeess|0xFED87000|UINT32|0x5 > 0000007 >=20 > +## >=20 > +## Those PCDs are used to control build process. >=20 > +## >=20 > +gSiPkgTokenSpaceGuid.PcdTraceHubEnable > |FALSE|BOOLEAN|0xF0000001 >=20 > +gSiPkgTokenSpaceGuid.PcdSmmVariableEnable > |FALSE|BOOLEAN|0xF0000002 >=20 > +gSiPkgTokenSpaceGuid.PcdAtaEnable > |FALSE|BOOLEAN|0xF0000004 >=20 > +gSiPkgTokenSpaceGuid.PcdAcpiEnable |TRUE > |BOOLEAN|0xF0000009 >=20 > +gSiPkgTokenSpaceGuid.PcdSourceDebugEnable > |FALSE|BOOLEAN|0xF000000B >=20 > +gSiPkgTokenSpaceGuid.PcdPpmEnable |TRUE > |BOOLEAN|0xF000000C >=20 > +gSiPkgTokenSpaceGuid.PcdIntegratedTouchEnable > |FALSE|BOOLEAN|0xF000000F >=20 > +gSiPkgTokenSpaceGuid.PcdPttEnable > |FALSE|BOOLEAN|0xF0000011 >=20 > +gSiPkgTokenSpaceGuid.PcdJhiEnable > |FALSE|BOOLEAN|0xF0000012 >=20 > +gSiPkgTokenSpaceGuid.PcdSoftwareGuardEnable > |FALSE|BOOLEAN|0xF0000013 >=20 > +gSiPkgTokenSpaceGuid.PcdSmbiosEnable |TRUE > |BOOLEAN|0xF0000014 >=20 > +gSiPkgTokenSpaceGuid.PcdS3Enable |TRUE > |BOOLEAN|0xF0000015 >=20 > +gSiPkgTokenSpaceGuid.PcdOverclockEnable > |FALSE|BOOLEAN|0xF0000016 >=20 > +gSiPkgTokenSpaceGuid.PcdCpuPowerOnConfigEnable > |FALSE|BOOLEAN|0xF0000017 >=20 > +gSiPkgTokenSpaceGuid.PcdSsaFlagEnable > |FALSE|BOOLEAN|0xF0000018 >=20 > +gSiPkgTokenSpaceGuid.PcdEvLoaderEnable > |FALSE|BOOLEAN|0xF0000019 >=20 > +gSiPkgTokenSpaceGuid.PcdIgdEnable |TRUE > |BOOLEAN|0xF000001A >=20 > +gSiPkgTokenSpaceGuid.PcdPegEnable |TRUE > |BOOLEAN|0xF000001B >=20 > +gSiPkgTokenSpaceGuid.PcdSaDmiEnable |TRUE > |BOOLEAN|0xF000001C >=20 > +gSiPkgTokenSpaceGuid.PcdGnaEnable |FALSE > |BOOLEAN|0xF000001E >=20 > +gSiPkgTokenSpaceGuid.PcdVtdEnable |TRUE > |BOOLEAN|0xF0000020 >=20 > +gSiPkgTokenSpaceGuid.PcdBiosGuardEnable > |FALSE|BOOLEAN|0xF0000021 >=20 > +gSiPkgTokenSpaceGuid.PcdSimicsEnable > |FALSE|BOOLEAN|0xF0000022 >=20 > +gSiPkgTokenSpaceGuid.PcdBdatEnable > |FALSE|BOOLEAN|0xF0000023 >=20 > +gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable |TRUE > |BOOLEAN|0xF0000024 >=20 > +gSiPkgTokenSpaceGuid.PcdPeiDisplayEnable |TRUE > |BOOLEAN|0xF0000025 >=20 > +gSiPkgTokenSpaceGuid.PcdOcWdtEnable > |FALSE|BOOLEAN|0xF0000029 >=20 > +gSiPkgTokenSpaceGuid.PcdMinTreeEnable > |FALSE|BOOLEAN|0xF000002A # To separate modules used in mininal > source tree and advanced features >=20 > +gSiPkgTokenSpaceGuid.PcdBootGuardEnable > |FALSE|BOOLEAN|0xF0000030 >=20 > +gSiPkgTokenSpaceGuid.PcdSerialIoUartEnable > |FALSE|BOOLEAN|0xF0000033 >=20 > +gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable > |FALSE|BOOLEAN|0xF0000037 >=20 > +gSiPkgTokenSpaceGuid.PcdBfxEnable > |FALSE|BOOLEAN|0xF000003A >=20 > +gSiPkgTokenSpaceGuid.PcdThcEnable > |FALSE|BOOLEAN|0xF000003B >=20 > + >=20 > +gSiPkgTokenSpaceGuid.PcdPpamEnable > |FALSE|BOOLEAN|0xF000003F >=20 > +gSiPkgTokenSpaceGuid.PcdPsmiEnable > |FALSE|BOOLEAN|0xF0000042 >=20 > +gSiPkgTokenSpaceGuid.PcdCpuPcieEnable |TRUE > |BOOLEAN|0xF0000043 >=20 > +gSiPkgTokenSpaceGuid.PcdHybridStorageSupport > |FALSE|BOOLEAN|0xF0000044 >=20 > +gSiPkgTokenSpaceGuid.PcdMrcTraceMessageSupported |TRUE > |BOOLEAN|0xF0000045 >=20 > +gSiPkgTokenSpaceGuid.PcdTmeLibSupported > |FALSE|BOOLEAN|0xF0000046 >=20 > +gSiPkgTokenSpaceGuid.PcdAdlLpSupport > |FALSE|BOOLEAN|0xF0000047 >=20 > +gSiPkgTokenSpaceGuid.PcdSpsStateSaveEnable > |FALSE|BOOLEAN|0xF0000048 >=20 > +gSiPkgTokenSpaceGuid.PcdSpaEnable > |FALSE|BOOLEAN|0xF0000049 >=20 > + >=20 > +## PCD for TraceHub >=20 > +[PcdsDynamic, PcdsPatchableInModule] >=20 > +## From MdeModulePkg.dec >=20 > +## Default OEM ID for ACPI table creation, its length must be 0x6 bytes = to > follow ACPI specification. >=20 > +gSiPkgTokenSpaceGuid.PcdAcpiDefaultOemId|"INTEL "|VOID*|0x30001034 >=20 > +## Default OEM Table ID for ACPI table creation, it is "EDK2 ". >=20 > +gSiPkgTokenSpaceGuid.PcdAcpiDefaultOemTableId|0x20202020324B4445| > UINT64|0x30001035 >=20 > +## Default OEM Revision for ACPI table creation. >=20 > +gSiPkgTokenSpaceGuid.PcdAcpiDefaultOemRevision|0x00000002|UINT32| > 0x30001036 >=20 > +## Default Creator ID for ACPI table creation. >=20 > +gSiPkgTokenSpaceGuid.PcdAcpiDefaultCreatorId|0x20202020|UINT32|0x30 > 001037 >=20 > +## Default Creator Revision for ACPI table creation. >=20 > +gSiPkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision|0x01000013|UINT3 > 2|0x30001038 >=20 > +## ME HECI interface configuration >=20 > +gMeConfigSpaceGuid.PcdHeciDumpsEnabled|TRUE|BOOLEAN|0x50000001 >=20 > +gMeConfigSpaceGuid.PcdHeciTimeoutsEnabled|TRUE|BOOLEAN|0x500000 > 02 >=20 > + >=20 > + >=20 > +[PcdsFixedAtBuild, PcdsPatchableInModule] >=20 > +## This value is used to set the base address of PCH devices >=20 > +gSiPkgTokenSpaceGuid.PcdSmbusBaseAddress|0x0000EFA0|UINT16|0x000 > 10031 >=20 > +gSiPkgTokenSpaceGuid.PcdTcoBaseAddress|0x0400|UINT16|0x00010033 >=20 > +gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress|0x1800|UINT16|0x00010035 >=20 > + >=20 > + >=20 > +## Stack size in the temporary RAM. >=20 > +## 0 means half of TemporaryRamSize. >=20 > +gSiPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0|UINT32|0x00010 > 036 >=20 > +## >=20 > +## PcdFviSmbiosType determines the SMBIOS OEM type (0x80 to 0xFF) > defined in SMBIOS, >=20 > +## values 0-0x7F will be treated as disable FVI reporting. >=20 > +## FVI structure uses it as SMBIOS OEM type to provide version > information. >=20 > +## >=20 > +gSiPkgTokenSpaceGuid.PcdFviSmbiosType|0xDD|UINT8|0x00010037 >=20 > +gSiPkgTokenSpaceGuid.PcdSaPciPrint|FALSE|BOOLEAN|0x00010039 >=20 > +## >=20 > +## SMBIOS defaults >=20 > +## >=20 > +gSiPkgTokenSpaceGuid.PcdSmbiosDefaultSocketDesignation|"U3E1"|VOID > *|0x0001003a >=20 > +gSiPkgTokenSpaceGuid.PcdSmbiosDefaultSerialNumber|"To Be Filled By > O.E.M."|VOID*|0x0001003b >=20 > +gSiPkgTokenSpaceGuid.PcdSmbiosDefaultAssetTag|"To Be Filled By > O.E.M."|VOID*|0x0001003c >=20 > +gSiPkgTokenSpaceGuid.PcdSmbiosDefaultPartNumber|"To Be Filled By > O.E.M."|VOID*|0x0001003d >=20 > + >=20 > +## >=20 > +## Allocate 56 KB [0x2000..0xFFFF] of I/O space for Pci Devices >=20 > +## If PcdPciReservedMemLimit =3D0 Pci Reserved default MMIO Limit is > 0xE0000000 else use PcdPciReservedMemLimit . >=20 > +## >=20 > +gSiPkgTokenSpaceGuid.PcdPciReservedIobase |0x2000 > |UINT16|0x00010041 >=20 > +gSiPkgTokenSpaceGuid.PcdPciReservedIoLimit |0xFFFF > |UINT16|0x00010042 >=20 > +gSiPkgTokenSpaceGuid.PcdPciReservedMemLimit |0x0000 > |UINT32|0x00010043 >=20 > +gSiPkgTokenSpaceGuid.PcdPciDmaAbove4G |FALSE > |BOOLEAN|0x00010044 >=20 > +gSiPkgTokenSpaceGuid.PcdPciNoExtendedConfigSpace|FALSE > |BOOLEAN|0x00010045 >=20 > + >=20 > +## >=20 > +## Default 8MB TSEG for Release build BIOS when IED disabled (Also a > default) >=20 > +## >=20 > +gSiPkgTokenSpaceGuid.PcdTsegSize|0x00800000|UINT32|0x00010046 >=20 > +## >=20 > +## gSiPkgTokenSpaceGuid.PcdFwStsSmbiosType determines the SMBIOS > OEM type (0x80 to 0xFF) defined >=20 > +## in SMBIOS, values 0-0x7F will be treated as disable FWSTS SMBIOS > reporting. >=20 > +## FWSTS structure uses it as SMBIOS OEM type to provide FWSTS > information. >=20 > +## >=20 > +gSiPkgTokenSpaceGuid.PcdFwStsSmbiosType|0xDB|UINT8|0x00010047 >=20 > + >=20 > +## >=20 > +## Maximum Address the AP Wakeup Buffer can start. >=20 > +## >=20 > +gSiPkgTokenSpaceGuid.PcdCpuApWakeupBufferMaxAddr|0x58000|UINT3 > 2|0x00010048 >=20 > + >=20 > +## >=20 > +## Silicon Reference Code versions >=20 > +## >=20 > +##Revision:Weekly build number >=20 > +gSiPkgTokenSpaceGuid.PcdSiliconInitVersionRevision|0x33|UINT8|0x00010 > 051 >=20 > + >=20 > +##Build[7:4]:Daily build number. >=20 > +##Build[3:0]:Patch build number. >=20 > + >=20 > +## >=20 > +## Temp MEM IO resource >=20 > +## >=20 > +gSiPkgTokenSpaceGuid.PcdSiliconInitTempPciBusMin |2 |UINT8 > |0x00010053 >=20 > +gSiPkgTokenSpaceGuid.PcdSiliconInitTempPciBusMax |10 |UINT8 > |0x00010054 >=20 > +gSiPkgTokenSpaceGuid.PcdSiliconInitTempMemBaseAddr > |0xFE600000|UINT32|0x00010055 >=20 > +gSiPkgTokenSpaceGuid.PcdSiliconInitTempMemSize > |0x00200000|UINT32|0x00010056 >=20 > + >=20 > +## >=20 > +## This PCD specifies the base address of the HPET timer. >=20 > +## The acceptable values are 0xFED00000, 0xFED01000, 0xFED02000, and > 0xFED03000 >=20 > +## >=20 > +gSiPkgTokenSpaceGuid.PcdSiHpetBaseAddress > |0xFED00000|UINT32|0x00010057 >=20 > +## >=20 > +## This PCD specifies the base address of the IO APIC. >=20 > +## The acceptable values are 0xFECxx000. >=20 > +## >=20 > +gSiPkgTokenSpaceGuid.PcdSiIoApicBaseAddress > |0xFEC00000|UINT32|0x00010058 >=20 > + >=20 > + >=20 > +## >=20 > +## VTD Base Addresses >=20 > +## >=20 > + >=20 > +## Null-terminated string of the Version of Physical Presence interface > supported by platform. >=20 > +# @Prompt Version of Physical Presence interface supported by platform. >=20 > +gSiPkgTokenSpaceGuid.PcdTcgPhysicalPresenceInterfaceVer|"1.3"|VOID*| > 0x00000008 >=20 > + >=20 > +## This PCD specifies Master of TraceHub device >=20 > +gSiPkgTokenSpaceGuid.PcdTraceHubDebugLibMaster|0x0|UINT32|0x0001 > 1000 >=20 > +## This PCD specifies Channel of TraceHub device >=20 > +gSiPkgTokenSpaceGuid.PcdTraceHubDebugLibChannel|0x0|UINT32|0x0001 > 1001 >=20 > + >=20 > + >=20 > +[PcdsPatchableInModule, PcdsFixedAtBuild] >=20 > +## This value is used to set the base address of MCH >=20 > +gSiPkgTokenSpaceGuid.PcdMchBaseAddress|0xFEDC0000|UINT64|0x00010 > 030 >=20 > +## 128KB window >=20 > +gSiPkgTokenSpaceGuid.PcdMchMmioSize|0x20000|UINT32|0x50000000 >=20 > +gSiPkgTokenSpaceGuid.PcdSiliconInitVersionMajor > |0x0A|UINT8|0x00010049 >=20 > +gSiPkgTokenSpaceGuid.PcdSiliconInitVersionValue > |0x0000000800260020|UINT64|0x00010077 >=20 > + >=20 > +##Minor:the program that supported by same core generation. >=20 > +gSiPkgTokenSpaceGuid.PcdSiliconInitVersionMinor > |0x00|UINT8|0x00010050 >=20 > + >=20 > +gSiPkgTokenSpaceGuid.PcdSiliconInitVersionBuild > |0x10|UINT8|0x00010052 >=20 > +gSiPkgTokenSpaceGuid.PcdRegBarBaseAddress|0xFB000000|UINT32|0x000 > 10059 >=20 > +[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx] >=20 > +## >=20 > +## SerialIo Uart Configuration >=20 > +## >=20 > +gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugEnable |0 |UINT8 > |0x00210001 # 0:Disable, 1:Enable and Initialize, 2:Enable without Initia= lizing >=20 > +gSiPkgTokenSpaceGuid.PcdSerialIoUartNumber |2 |UINT8 > |0x00210002 >=20 > +gSiPkgTokenSpaceGuid.PcdSerialIoUartMode |2 |UINT8 > |0x00210003 # 0:Disabled, 1:Enabled, 2:Hidden, 3:COM, 4:SkipInit >=20 > +gSiPkgTokenSpaceGuid.PcdSerialIoUartBaudRate |115200 > |UINT32|0x00210004 # 0:Default, Max:6000000 >=20 > +gSiPkgTokenSpaceGuid.PcdSerialIoUartParity |1 |UINT8 > |0x00210008 # 0:DefaultParity, 1:NoParity, 2:EvenParity, 3:OddParity >=20 > +gSiPkgTokenSpaceGuid.PcdSerialIoUartDataBits |8 |UINT8 > |0x00210009 # 0:Default, 5,6,7,8 >=20 > +gSiPkgTokenSpaceGuid.PcdSerialIoUartStopBits |1 |UINT8 > |0x0021000A # 0:DefaultStopBits, 1:OneStopBit, 2:OneFiveStopBits, > 3:TwoStopBits >=20 > +gSiPkgTokenSpaceGuid.PcdSerialIoUartAutoFlow |0 |UINT8 > |0x0021000B # 0:No HW flow control, Only RX/TX Enabled; 1:HW Flow Control > On, Rts/Cts lines enabled; >=20 > +gSiPkgTokenSpaceGuid.PcdSerialIoUartRxPinMux |0x0 > |UINT32|0x0021000C # Pin muxing config for UART Rx pin >=20 > +gSiPkgTokenSpaceGuid.PcdSerialIoUartTxPinMux |0x0 > |UINT32|0x00210010 # Pin muxing config for UART Tx pin >=20 > +gSiPkgTokenSpaceGuid.PcdSerialIoUartRtsPinMux |0x0 > |UINT32|0x00210014 # Pin muxing config for UART Rts pin >=20 > +gSiPkgTokenSpaceGuid.PcdSerialIoUartCtsPinMux |0x0 > |UINT32|0x00210018 # Pin muxing config for UART Cts pin >=20 > +gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugMmioBase |0xFE036000 > |UINT32|0x0021001C # PcdSerialIoUartMode =3D Enabled, need to assign > MMIO Resource in SEC/PEI Phase >=20 > + >=20 > +gSiPkgTokenSpaceGuid.PcdLpcUartDebugEnable |0x1 |UINT8 > |0x00210026 # 0:Disable, 1:Enable >=20 > +gSiPkgTokenSpaceGuid.PcdDebugInterfaceFlags |0x12 |UINT8 > |0x00210027 # BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5- > TraceHub, BIT2 - Not used. >=20 > +gSiPkgTokenSpaceGuid.PcdSerialDebugLevel |0x3 |UINT8 > |0x00210028 # {0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Erro= r > Warnings and Info, 4:Load Error Warnings and Info, 5:Load Error Warnings > Info and Verbose >=20 > +gSiPkgTokenSpaceGuid.PcdIsaSerialUartBase |0x0 |UINT8 > |0x00210029 # 0:0x3F8, 1:0x2F8 >=20 > + >=20 > +## UART Lib TimeOut >=20 > +gSiPkgTokenSpaceGuid.PcdSerialIoUartTimeOut |1000000 |UINT32 > |0x00210020 # Write TimeOut in Micro Seconds - 0 =3D disabbled, default 1 > second, >=20 > +gSiPkgTokenSpaceGuid.PcdSerialIoUartLibSkipMmioCheck |FALSE > |BOOLEAN|0x00210024 # If TRUE MMIO sanity checks are skipped >=20 > + >=20 > +## UART Dxe Driver IgnoreBaudRateSet >=20 > +## TRUE - Blocks changing BaudRate, so that driver will not override UAR= T's > initial configuration. >=20 > +## Required to support redirection on higher BaudRates. >=20 > +## FALSE - Allows for UART settings to be changed through the Serial Io > Protocol >=20 > +## >=20 > +gSiPkgTokenSpaceGuid.PcdSerialIoUartDriverIgnoreBaudRateSet|FALSE|B > OOLEAN|0x00210025 >=20 > + >=20 > +## >=20 > +## SerialIo 2nd Uart Configuration >=20 > +## >=20 > +gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartEnable |0 |UINT8 > |0x0021002A # 0:Disable, 1:Enable and Initialize, 2:Enable without Initia= lizing >=20 > +gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartNumber |2 |UINT8 > |0x0021002B >=20 > +gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartMode |2 |UINT8 > |0x0021002C # 0:Disabled, 1:Enabled, 2:Hidden, 3:COM, 4:SkipInit >=20 > +gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartBaudRate |115200 > |UINT32|0x0021002D # 0:Default, Max:6000000 >=20 > +gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartParity |1 |UINT8 > |0x00210031 # 0:DefaultParity, 1:NoParity, 2:EvenParity, 3:OddParity >=20 > +gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartDataBits |8 |UINT8 > |0x00210032 # 0:Default, 5,6,7,8 >=20 > +gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartStopBits |1 |UINT8 > |0x00210033 # 0:DefaultStopBits, 1:OneStopBit, 2:OneFiveStopBits, > 3:TwoStopBits >=20 > +gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartAutoFlow |0 |UINT8 > |0x00210034 # 0:No HW flow control, Only RX/TX Enabled; 1:HW Flow Control > On, Rts/Cts lines enabled; >=20 > +gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartRxPinMux |0x0 > |UINT32|0x00210035 # Pin muxing config for UART Rx pin >=20 > +gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartTxPinMux |0x0 > |UINT32|0x00210039 # Pin muxing config for UART Tx pin >=20 > +gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartRtsPinMux |0x0 > |UINT32|0x0021003D # Pin muxing config for UART Rts pin >=20 > +gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartCtsPinMux |0x0 > |UINT32|0x00210041 # Pin muxing config for UART Cts pin >=20 > +gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartMmioBase |0xFE034000 > |UINT32|0x00210045 # PcdSerialIoUartMode =3D Enabled, need to assign > MMIO Resource in SEC/PEI Phase >=20 > + >=20 > +## >=20 > +## PCI Express MMIO region length >=20 > +## Valid settings: 0x20000000/512MB, 0x10000000/256MB, > 0x8000000/128MB, 0x4000000/64MB >=20 > +## >=20 > +gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000|UINT32|0 > x00200001 >=20 > +## >=20 > +## Typically this should be the same with > gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress. >=20 > +## This PCD is added for supporting different PCD type in different phas= es. >=20 > +## >=20 > +gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress > |0xC0000000|UINT64|0x00200002 >=20 > +## >=20 > +## PCI Express MMIO temporary region length in SEC phase. >=20 > +## Valid settings: 0x20000000/512MB, 0x10000000/256MB, > 0x8000000/128MB, 0x4000000/64MB >=20 > +## >=20 > +gSiPkgTokenSpaceGuid.PcdTemporaryPciExpressRegionLength|0x10000000 > |UINT32|0x00200005 >=20 > + >=20 > +## Specifies the SMRR2 base address.

>=20 > +# @Prompt SMRR2 base address. >=20 > +# @Expression 0x80000001 | > (gSiPkgTokenSpaceGuid.PcdCpuSmmSmrr2Base & 0xfff) =3D=3D 0 >=20 > +gSiPkgTokenSpaceGuid.PcdCpuSmmSmrr2Base|0|UINT32|0x20000002 >=20 > + >=20 > +## Specifies the SMRR2 range size.

>=20 > +# @Prompt SMRR2 range size. >=20 > +# @Expression 0x80000001 | > (gSiPkgTokenSpaceGuid.PcdCpuSmmSmrr2Size & 0xfff) =3D=3D 0 >=20 > +gSiPkgTokenSpaceGuid.PcdCpuSmmSmrr2Size|0|UINT32|0x20000003 >=20 > + >=20 > +## Specifies the SMRR2 range cache type. >=20 > +# If SMRR2 is used to map a flash/ROM based handler, it would be > configured as WP.

>=20 > +# 5: WP(Write Protect).
>=20 > +# 6: WB(Write Back).
>=20 > +# @Prompt SMRR2 range cache type. >=20 > +gSiPkgTokenSpaceGuid.PcdCpuSmmSmrr2CacheType|5|UINT8|0x20000004 >=20 > + >=20 > +## Indidates if SMM PROT MODE feature is supported.

>=20 > +# TRUE - SMM PROT MODE feature is supported.
>=20 > +# FALSE - SMM PROT MODE feature is not supported.
>=20 > +# @Prompt SMM PROT MODE feature. >=20 > +gSiPkgTokenSpaceGuid.PcdCpuSmmProtectedModeEnable|FALSE|BOOLEA > N|0x20000008 >=20 > + >=20 > +## Specifies the a size of memory region to reserve in SMM for testing o= nly. >=20 > +# One can look in BIOS serial log for PCD to get region base address. >=20 > +# Note: A different region may be allocated in release build than debug > build. >=20 > +# @Prompt SMM test region size.\r >=20 > +gSiPkgTokenSpaceGuid.PcdSmmTestRsvMemorySize|0x0|UINT32|0x20000 > 00E >=20 > + >=20 > +[PcdsDynamic] >=20 > + >=20 > +## Indidates if SMM Code Access Check feature is supported.

>=20 > +# TRUE - SMM Code Access Check feature is supported.
>=20 > +# FALSE - SMM Code Access Check feature is not supported.
>=20 > +# @Prompt SMM Code Access Check feature. >=20 > +gSiPkgTokenSpaceGuid.PcdCpuSmmCodeAccessCheckEnable|TRUE|BOOLE > AN|0x001000D >=20 > + >=20 > +## Causes all UEFI variables to be treated as volatile and hence never > written to non-volatile >=20 > +## storage. >=20 > +## This is useful in cases such as a simulation environment that does no= t > emulate a non-volatile >=20 > +## storage device or in recovery scenarios where system errors prevent > non-volatile storage from being accessed >=20 > +gSiPkgTokenSpaceGuid.PcdNvVariableEmulationMode|FALSE|BOOLEAN|0 > x0010000E >=20 > + >=20 > +## Enables or disables storage of UEFI variables using the CSE Variable > Storage drivers >=20 > +## If disabled at runtime, it must be set before the CSE Variable Stor= age > driver loads. >=20 > +gSiPkgTokenSpaceGuid.PcdEnableCseVariableStorage|FALSE|BOOLEAN|0x > 0010000F >=20 > + >=20 > +## Enables or disables storage of UEFI variables using the FVB Variable > Storage drivers >=20 > +## If disabled at runtime, it must be set before the FVB Variable Stora= ge > driver loads. >=20 > +gSiPkgTokenSpaceGuid.PcdEnableFvbVariableStorage|TRUE|BOOLEAN|0x0 > 0100010 >=20 > + >=20 > -- > 2.24.0.windows.2