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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Nate DeSimone > -----Original Message----- > From: Luo, Heng > Sent: Sunday, January 31, 2021 5:37 PM > To: devel@edk2.groups.io > Cc: Chaganty, Rangasai V ; Desimone, > Nathaniel L > Subject: [PATCH 21/40] TigerlakeSiliconPkg/IpBlock: Add P2sb component >=20 > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3171 >=20 > Adds the following files: > * IpBlock/P2sb/IncludePrivate > * IpBlock/P2sb/Library > * IpBlock/P2sb/LibraryPrivate >=20 > Cc: Sai Chaganty > Cc: Nate DeSimone > Signed-off-by: Heng Luo > --- >=20 > Silicon/Intel/TigerlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Library/Pch= Sbi > AccessLib.h | 112 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Register/P2= sb > Regs.h | 65 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/IpBlock/P2sb/Library/PeiDxeSmmCpuRegba > rAccessLib/CpuRegbarAccessLib.c | 494 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/IpBlock/P2sb/Library/PeiDxeSmmCpuRegba > rAccessLib/PeiDxeSmmCpuRegbarAccessLib.inf | 35 > +++++++++++++++++++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/IpBlock/P2sb/Library/PeiDxeSmmPchPcrLib= / > PchPcrLib.c | 313 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/IpBlock/P2sb/Library/PeiDxeSmmPchPcrLib= / > PeiDxeSmmPchPcrLib.inf | 35 > +++++++++++++++++++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmPc= h > SbiAccessLib/PchSbiAccessLib.c | 253 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmPc= h > SbiAccessLib/PeiDxeSmmPchSbiAccessLib.inf | 36 > ++++++++++++++++++++++++++++++++++++ > 8 files changed, 1343 insertions(+) >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Library/P= chS > biAccessLib.h > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Library/P= chS > biAccessLib.h > new file mode 100644 > index 0000000000..3fab933bbd > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Library/P= chS > biAccessLib.h > @@ -0,0 +1,112 @@ > +/** @file >=20 > + Header file for PchSbiAccessLib. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _PCH_SBI_ACCESS_LIB_H_ >=20 > +#define _PCH_SBI_ACCESS_LIB_H_ >=20 > + >=20 > +#include >=20 > + >=20 > +/** >=20 > + PCH SBI opcode definitions >=20 > +**/ >=20 > +typedef enum { >=20 > + MemoryRead =3D 0x0, >=20 > + MemoryWrite =3D 0x1, >=20 > + PciConfigRead =3D 0x4, >=20 > + PciConfigWrite =3D 0x5, >=20 > + PrivateControlRead =3D 0x6, >=20 > + PrivateControlWrite =3D 0x7, >=20 > + GpioLockUnlock =3D 0x13 >=20 > +} PCH_SBI_OPCODE; >=20 > + >=20 > +/** >=20 > + PCH SBI response status definitions >=20 > +**/ >=20 > +typedef enum { >=20 > + SBI_SUCCESSFUL =3D 0, >=20 > + SBI_UNSUCCESSFUL =3D 1, >=20 > + SBI_POWERDOWN =3D 2, >=20 > + SBI_MIXED =3D 3, >=20 > + SBI_INVALID_RESPONSE >=20 > +} PCH_SBI_RESPONSE; >=20 > + >=20 > +/** >=20 > + Execute PCH SBI message >=20 > + Take care of that there is no lock protection when using SBI programmi= ng > in both POST time and SMI. >=20 > + It will clash with POST time SBI programming when SMI happen. >=20 > + Programmer MUST do the save and restore opration while using the > PchSbiExecution inside SMI >=20 > + to prevent from racing condition. >=20 > + This function will reveal P2SB and hide P2SB if it's originally hidden= . If more > than one SBI access >=20 > + needed, it's better to unhide the P2SB before calling and hide it back= after > done. >=20 > + >=20 > + When the return value is "EFI_SUCCESS", the "Response" do not need to > be checked as it would have been >=20 > + SBI_SUCCESS. If the return value is "EFI_DEVICE_ERROR", then this woul= d > provide additional information >=20 > + when needed. >=20 > + >=20 > + @param[in] Pid Port ID of the SBI message >=20 > + @param[in] Offset Offset of the SBI message >=20 > + @param[in] Opcode Opcode >=20 > + @param[in] Posted Posted message >=20 > + @param[in, out] Data32 Read/Write data >=20 > + @param[out] Response Response >=20 > + >=20 > + @retval EFI_SUCCESS Successfully completed. >=20 > + @retval EFI_DEVICE_ERROR Transaction fail >=20 > + @retval EFI_INVALID_PARAMETER Invalid parameter >=20 > + @retval EFI_TIMEOUT Timeout while waiting for respon= se >=20 > +**/ >=20 > +EFI_STATUS >=20 > +PchSbiExecution ( >=20 > + IN PCH_SBI_PID Pid, >=20 > + IN UINT64 Offset, >=20 > + IN PCH_SBI_OPCODE Opcode, >=20 > + IN BOOLEAN Posted, >=20 > + IN OUT UINT32 *Data32, >=20 > + OUT UINT8 *Response >=20 > + ); >=20 > + >=20 > +/** >=20 > + Full function for executing PCH SBI message >=20 > + Take care of that there is no lock protection when using SBI programmi= ng > in both POST time and SMI. >=20 > + It will clash with POST time SBI programming when SMI happen. >=20 > + Programmer MUST do the save and restore opration while using the > PchSbiExecution inside SMI >=20 > + to prevent from racing condition. >=20 > + This function will reveal P2SB and hide P2SB if it's originally hidden= . If more > than one SBI access >=20 > + needed, it's better to unhide the P2SB before calling and hide it back= after > done. >=20 > + >=20 > + When the return value is "EFI_SUCCESS", the "Response" do not need to > be checked as it would have been >=20 > + SBI_SUCCESS. If the return value is "EFI_DEVICE_ERROR", then this woul= d > provide additional information >=20 > + when needed. >=20 > + >=20 > + @param[in] Pid Port ID of the SBI message >=20 > + @param[in] Offset Offset of the SBI message >=20 > + @param[in] Opcode Opcode >=20 > + @param[in] Posted Posted message >=20 > + @param[in] Fbe First byte enable >=20 > + @param[in] Bar Bar >=20 > + @param[in] Fid Function ID >=20 > + @param[in, out] Data32 Read/Write data >=20 > + @param[out] Response Response >=20 > + >=20 > + @retval EFI_SUCCESS Successfully completed. >=20 > + @retval EFI_DEVICE_ERROR Transaction fail >=20 > + @retval EFI_INVALID_PARAMETER Invalid parameter >=20 > + @retval EFI_TIMEOUT Timeout while waiting for respon= se >=20 > +**/ >=20 > +EFI_STATUS >=20 > +PchSbiExecutionEx ( >=20 > + IN PCH_SBI_PID Pid, >=20 > + IN UINT64 Offset, >=20 > + IN PCH_SBI_OPCODE Opcode, >=20 > + IN BOOLEAN Posted, >=20 > + IN UINT16 Fbe, >=20 > + IN UINT16 Bar, >=20 > + IN UINT16 Fid, >=20 > + IN OUT UINT32 *Data32, >=20 > + OUT UINT8 *Response >=20 > + ); >=20 > + >=20 > +#endif // _PCH_SBI_ACCESS_LIB_H_ >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Register/= P2s > bRegs.h > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Register/= P2s > bRegs.h > new file mode 100644 > index 0000000000..44c71af719 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Register/= P2s > bRegs.h > @@ -0,0 +1,65 @@ > +/** @file >=20 > + Register names for PCH P2SB device >=20 > + >=20 > + Conventions: >=20 > + >=20 > + - Register definition format: >=20 > + > Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterS > pace_RegisterName >=20 > + - Prefix: >=20 > + Definitions beginning with "R_" are registers >=20 > + Definitions beginning with "B_" are bits within registers >=20 > + Definitions beginning with "V_" are meaningful values within the bit= s >=20 > + Definitions beginning with "S_" are register size >=20 > + Definitions beginning with "N_" are the bit position >=20 > + - [GenerationName]: >=20 > + Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc= .). >=20 > + Register name without GenerationName applies to all generations. >=20 > + - [ComponentName]: >=20 > + This field indicates the component name that the register belongs to= (e.g. > PCH, SA etc.) >=20 > + Register name without ComponentName applies to all components. >=20 > + Register that is specific to -LP denoted by "_PCH_LP_" in component > name. >=20 > + - SubsystemName: >=20 > + This field indicates the subsystem name of the component that the > register belongs to >=20 > + (e.g. PCIE, USB, SATA, GPIO, PMC etc.). >=20 > + - RegisterSpace: >=20 > + MEM - MMIO space register of subsystem. >=20 > + IO - IO space register of subsystem. >=20 > + PCR - Private configuration register of subsystem. >=20 > + CFG - PCI configuration space register of subsystem. >=20 > + - RegisterName: >=20 > + Full register name. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _P2SB_REGS_H_ >=20 > +#define _P2SB_REGS_H_ >=20 > + >=20 > +// >=20 > +// PCI to P2SB Bridge Registers >=20 > +// >=20 > + >=20 > +#define R_IO_APIC_MEM_INDEX_OFFSET 0x00 >=20 > +#define R_IO_APIC_MEM_DATA_OFFSET 0x10 >=20 > +#define V_P2SB_CFG_IBDF_BUS 0 >=20 > +#define V_P2SB_CFG_IBDF_DEV 30 >=20 > +#define V_P2SB_CFG_IBDF_FUNC 7 >=20 > +#define V_P2SB_CFG_HBDF_BUS 0 >=20 > +#define V_P2SB_CFG_HBDF_DEV 30 >=20 > +#define V_P2SB_CFG_HBDF_FUNC 6 >=20 > + >=20 > +// >=20 > +// Definition for SBI >=20 > +// >=20 > +#define R_P2SB_CFG_SBIADDR 0xD0 >=20 > +#define R_P2SB_CFG_SBIDATA 0xD4 >=20 > +#define R_P2SB_CFG_SBISTAT 0xD8 >=20 > +#define B_P2SB_CFG_SBISTAT_OPCODE 0xFF00 >=20 > +#define B_P2SB_CFG_SBISTAT_POSTED BIT7 >=20 > +#define B_P2SB_CFG_SBISTAT_RESPONSE 0x0006 >=20 > +#define N_P2SB_CFG_SBISTAT_RESPONSE 1 >=20 > +#define B_P2SB_CFG_SBISTAT_INITRDY BIT0 >=20 > +#define R_P2SB_CFG_SBIRID 0xDA >=20 > +#define R_P2SB_CFG_SBIEXTADDR 0xDC >=20 > + >=20 > +#endif >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/P2sb/Library/PeiDxeSmmCpuReg > barAccessLib/CpuRegbarAccessLib.c > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/P2sb/Library/PeiDxeSmmCpuReg > barAccessLib/CpuRegbarAccessLib.c > new file mode 100644 > index 0000000000..9d8851ac37 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/P2sb/Library/PeiDxeSmmCpuReg > barAccessLib/CpuRegbarAccessLib.c > @@ -0,0 +1,494 @@ > +/** @file >=20 > + CPU REGBAR ACCESS library. >=20 > + All function in this library is available for PEI, DXE, and SMM, >=20 > + But do not support UEFI RUNTIME environment call. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +/** >=20 > + Definition for REGBAR address >=20 > + The REGBAR address is used for the CPU IP's SB register access >=20 > +**/ >=20 > +#define CPU_REGBAR_ADDRESS(Pid, Offset) > (PcdGet32(PcdRegBarBaseAddress) | ((UINT8)(Pid) << 16) | > (UINT16)(Offset)) >=20 > + >=20 > +/** >=20 > + Read REGBAR register. >=20 > + It returns REGBAR register and size in 8bytes. >=20 > + The Offset should not exceed 0xFFFF and must be aligned with size. >=20 > + >=20 > + @param[in] CpuSbDevicePid CPU SB Device Port ID >=20 > + @param[in] Offset Register offset of this Port ID >=20 > + >=20 > + @retval UINT64 REGBAR register value. >=20 > +**/ >=20 > +UINT64 >=20 > +CpuRegbarRead64 ( >=20 > + IN CPU_SB_DEVICE_PID CpuSbDevicePid, >=20 > + IN UINT16 Offset >=20 > + ) >=20 > +{ >=20 > + UINT8 Pid; >=20 > + >=20 > + Pid =3D CpuSbDevicePid; >=20 > + if (Pid !=3D INVALID_PID) >=20 > + return ((UINT64) MmioRead32 (CPU_REGBAR_ADDRESS (Pid, Offset)) + > LShiftU64 ((UINT64) MmioRead32 (CPU_REGBAR_ADDRESS (Pid, Offset+4)), > 32)); >=20 > + else >=20 > + return INVALID_DATA_64; >=20 > +} >=20 > + >=20 > + >=20 > +/** >=20 > + Read REGBAR register. >=20 > + It returns REGBAR register and size in 4bytes. >=20 > + The Offset should not exceed 0xFFFF and must be aligned with size. >=20 > + >=20 > + @param[in] CpuSbDevicePid CPU SB Device Port ID >=20 > + @param[in] Offset Register offset of this Port ID >=20 > + >=20 > + @retval UINT32 REGBAR register value. >=20 > +**/ >=20 > +UINT32 >=20 > +CpuRegbarRead32 ( >=20 > + IN CPU_SB_DEVICE_PID CpuSbDevicePid, >=20 > + IN UINT16 Offset >=20 > + ) >=20 > +{ >=20 > + UINT8 Pid; >=20 > + >=20 > + Pid =3D CpuSbDevicePid; >=20 > + if (Pid !=3D INVALID_PID) >=20 > + return MmioRead32 (CPU_REGBAR_ADDRESS (Pid, Offset)); >=20 > + else >=20 > + return INVALID_DATA_32; >=20 > +} >=20 > + >=20 > +/** >=20 > + Read REGBAR register. >=20 > + It returns REGBAR register and size in 2bytes. >=20 > + The Offset should not exceed 0xFFFF and must be aligned with size. >=20 > + >=20 > + @param[in] CpuSbDevicePid CPU SB Device Port ID >=20 > + @param[in] Offset Register offset of this Port ID >=20 > + >=20 > + @retval UINT16 REGBAR register value. >=20 > +**/ >=20 > +UINT16 >=20 > +CpuRegbarRead16 ( >=20 > + IN CPU_SB_DEVICE_PID CpuSbDevicePid, >=20 > + IN UINT16 Offset >=20 > + ) >=20 > +{ >=20 > + UINT16 DwOffset; >=20 > + UINT32 Data32; >=20 > + UINT16 Data16; >=20 > + >=20 > + Data16 =3D 0; >=20 > + Data32 =3D 0; >=20 > + DwOffset =3D 0; >=20 > + >=20 > + if (CpuSbDevicePid =3D=3D INVALID_PID) { >=20 > + return INVALID_DATA_16; >=20 > + } >=20 > + switch (Offset & 0x0003) { >=20 > + case 0: >=20 > + DwOffset =3D Offset; >=20 > + break; >=20 > + case 2: >=20 > + DwOffset =3D Offset - 0x2; >=20 > + break; >=20 > + } >=20 > + Data32 =3D MmioRead32 (CPU_REGBAR_ADDRESS (CpuSbDevicePid, > DwOffset)); >=20 > + switch (Offset & 0x0003) { >=20 > + case 0: >=20 > + Data16 =3D (UINT16) Data32; >=20 > + break; >=20 > + case 2: >=20 > + Data16 =3D (UINT16) (Data32 >> 16); >=20 > + break; >=20 > + } >=20 > + return Data16; >=20 > +} >=20 > + >=20 > +/** >=20 > + Read REGBAR register. >=20 > + It returns REGBAR register and size in 1bytes. >=20 > + The Offset should not exceed 0xFFFF and must be aligned with size. >=20 > + >=20 > + @param[in] CpuSbDevicePid CPU SB Device Port ID >=20 > + @param[in] Offset Register offset of this Port ID >=20 > + >=20 > + @retval UINT8 REGBAR regsiter value >=20 > +**/ >=20 > +UINT8 >=20 > +CpuRegbarRead8 ( >=20 > + IN CPU_SB_DEVICE_PID CpuSbDevicePid, >=20 > + IN UINT16 Offset >=20 > + ) >=20 > +{ >=20 > + UINT16 DwOffset; >=20 > + UINT32 Data32; >=20 > + UINT8 Data8; >=20 > + >=20 > + DwOffset =3D 0; >=20 > + Data32 =3D 0; >=20 > + Data8 =3D 0; >=20 > + >=20 > + if (CpuSbDevicePid =3D=3D INVALID_PID) >=20 > + return INVALID_DATA_8; >=20 > + switch (Offset & 0x0003) { >=20 > + case 0: >=20 > + DwOffset =3D Offset; >=20 > + break; >=20 > + case 1: >=20 > + DwOffset =3D Offset - 0x1; >=20 > + break; >=20 > + case 2: >=20 > + DwOffset =3D Offset - 0x2; >=20 > + break; >=20 > + case 3: >=20 > + DwOffset =3D Offset - 0x3; >=20 > + break; >=20 > + } >=20 > + Data32 =3D MmioRead32 (CPU_REGBAR_ADDRESS (CpuSbDevicePid, > DwOffset)); >=20 > + switch (Offset & 0x0003) { >=20 > + case 0: >=20 > + Data8 =3D (UINT8) Data32; >=20 > + break; >=20 > + case 1: >=20 > + Data8 =3D (UINT8) (Data32 >> 8); >=20 > + break; >=20 > + case 2: >=20 > + Data8 =3D (UINT8) (Data32 >> 16); >=20 > + break; >=20 > + case 3: >=20 > + Data8 =3D (UINT8) (Data32 >> 24); >=20 > + break; >=20 > + } >=20 > + return Data8; >=20 > +} >=20 > + >=20 > + >=20 > +/** >=20 > + Write REGBAR register. >=20 > + It programs REGBAR register and size in 8bytes. >=20 > + The Offset should not exceed 0xFFFF and must be aligned with size. >=20 > + >=20 > + @param[in] CpuSbDevicePid CPU SB Device Port ID >=20 > + @param[in] Offset Register offset of Port ID. >=20 > + @param[in] Data Input Data. Must be the same size as Size > parameter. >=20 > + >=20 > + @retval UINT64 Value written to register >=20 > +**/ >=20 > +UINT64 >=20 > +CpuRegbarWrite64 ( >=20 > + IN CPU_SB_DEVICE_PID CpuSbDevicePid, >=20 > + IN UINT16 Offset, >=20 > + IN UINT64 Data >=20 > + ) >=20 > +{ >=20 > + UINT8 Pid; >=20 > + >=20 > + Pid =3D CpuSbDevicePid; >=20 > + if (Pid !=3D INVALID_PID) { >=20 > + MmioWrite32 (CPU_REGBAR_ADDRESS (Pid, Offset) + 4, (UINT32) > RShiftU64 (Data, 32)); >=20 > + MmioWrite32 (CPU_REGBAR_ADDRESS (Pid, Offset), (UINT32) Data); >=20 > + return Data; >=20 > + } >=20 > + else >=20 > + return INVALID_DATA_64; >=20 > +} >=20 > + >=20 > + >=20 > +/** >=20 > + Write REGBAR register. >=20 > + It programs REGBAR register and size in 4bytes. >=20 > + The Offset should not exceed 0xFFFF and must be aligned with size. >=20 > + >=20 > + @param[in] CpuSbDevicePid CPU SB Device Port ID >=20 > + @param[in] Offset Register offset of Port ID. >=20 > + @param[in] Data Input Data. Must be the same size as Size > parameter. >=20 > + >=20 > + @retval UINT32 Value written to register >=20 > +**/ >=20 > +UINT32 >=20 > +CpuRegbarWrite32 ( >=20 > + IN CPU_SB_DEVICE_PID CpuSbDevicePid, >=20 > + IN UINT16 Offset, >=20 > + IN UINT32 Data >=20 > + ) >=20 > +{ >=20 > + UINT8 Pid; >=20 > + >=20 > + Pid =3D CpuSbDevicePid; >=20 > + if (Pid !=3D INVALID_PID) >=20 > + return MmioWrite32 (CPU_REGBAR_ADDRESS (Pid, Offset), Data); >=20 > + else >=20 > + return INVALID_DATA_32; >=20 > +} >=20 > + >=20 > +/** >=20 > + Write REGBAR register. >=20 > + It programs REGBAR register and size in 2bytes. >=20 > + The Offset should not exceed 0xFFFF and must be aligned with size. >=20 > + >=20 > + @param[in] CpuSbDevicePid CPU SB Device Port ID >=20 > + @param[in] Offset Register offset of Port ID. >=20 > + @param[in] Data Input Data. Must be the same size as Size > parameter. >=20 > + >=20 > + @retval UINT16 Value written to register >=20 > +**/ >=20 > +UINT16 >=20 > +CpuRegbarWrite16 ( >=20 > + IN CPU_SB_DEVICE_PID CpuSbDevicePid, >=20 > + IN UINT16 Offset, >=20 > + IN UINT16 Data >=20 > + ) >=20 > +{ >=20 > + UINT8 Pid; >=20 > + >=20 > + Pid =3D CpuSbDevicePid; >=20 > + if (Pid !=3D INVALID_PID) >=20 > + return MmioWrite16 (CPU_REGBAR_ADDRESS (Pid, Offset), Data); >=20 > + else >=20 > + return INVALID_DATA_16; >=20 > +} >=20 > + >=20 > +/** >=20 > + Write REGBAR register. >=20 > + It programs REGBAR register and size in 1bytes. >=20 > + The Offset should not exceed 0xFFFF and must be aligned with size. >=20 > + >=20 > + @param[in] CpuSbDevicePid CPU SB Device Port ID >=20 > + @param[in] Offset Register offset of Port ID. >=20 > + @param[in] Data Input Data. Must be the same size as Size > parameter. >=20 > + >=20 > + @retval UINT8 Value written to register >=20 > +**/ >=20 > +UINT8 >=20 > +CpuRegbarWrite8 ( >=20 > + IN CPU_SB_DEVICE_PID CpuSbDevicePid, >=20 > + IN UINT16 Offset, >=20 > + IN UINT8 Data >=20 > + ) >=20 > +{ >=20 > + UINT8 Pid; >=20 > + >=20 > + Pid =3D CpuSbDevicePid; >=20 > + if (Pid !=3D INVALID_PID) >=20 > + return MmioWrite8 (CPU_REGBAR_ADDRESS (Pid, Offset), Data); >=20 > + else >=20 > + return INVALID_DATA_8; >=20 > +} >=20 > + >=20 > +/** >=20 > + Write REGBAR register. >=20 > + It programs REGBAR register and size in 4bytes. >=20 > + The Offset should not exceed 0xFFFF and must be aligned with size. >=20 > + >=20 > + @param[in] CpuSbDevicePid CPU SB Device Port ID >=20 > + @param[in] Offset Register offset of Port ID. >=20 > + @param[in] OrData OR Data. Must be the same size as Size > parameter. >=20 > + >=20 > + @retval UINT32 Value written to register >=20 > + >=20 > +**/ >=20 > +UINT32 >=20 > +CpuRegbarOr32 ( >=20 > + IN CPU_SB_DEVICE_PID CpuSbDevicePid, >=20 > + IN UINT16 Offset, >=20 > + IN UINT32 OrData >=20 > + ) >=20 > +{ >=20 > + return CpuRegbarWrite32 (CpuSbDevicePid, Offset, > CpuRegbarRead32(CpuSbDevicePid, Offset) | OrData); >=20 > +} >=20 > + >=20 > +/** >=20 > + Write REGBAR register. >=20 > + It programs REGBAR register and size in 2bytes. >=20 > + The Offset should not exceed 0xFFFF and must be aligned with size. >=20 > + >=20 > + @param[in] CpuSbDevicePid CPU SB Device Port ID >=20 > + @param[in] Offset Register offset of Port ID. >=20 > + @param[in] OrData OR Data. Must be the same size as Size > parameter. >=20 > + >=20 > + @retval UINT16 Value written to register >=20 > + >=20 > +**/ >=20 > +UINT16 >=20 > +CpuRegbarOr16 ( >=20 > + IN CPU_SB_DEVICE_PID CpuSbDevicePid, >=20 > + IN UINT16 Offset, >=20 > + IN UINT16 OrData >=20 > + ) >=20 > +{ >=20 > + return CpuRegbarWrite16 (CpuSbDevicePid, Offset, > CpuRegbarRead16(CpuSbDevicePid, Offset) | OrData); >=20 > +} >=20 > + >=20 > +/** >=20 > + Write REGBAR register. >=20 > + It programs REGBAR register and size in 1bytes. >=20 > + The Offset should not exceed 0xFFFF and must be aligned with size. >=20 > + >=20 > + @param[in] CpuSbDevicePid CPU SB Device Port ID >=20 > + @param[in] Offset Register offset of Port ID. >=20 > + @param[in] OrData OR Data. Must be the same size as Size > parameter. >=20 > + >=20 > + @retval UINT8 Value written to register >=20 > + >=20 > +**/ >=20 > +UINT8 >=20 > +CpuRegbarOr8( >=20 > + IN CPU_SB_DEVICE_PID CpuSbDevicePid, >=20 > + IN UINT16 Offset, >=20 > + IN UINT8 OrData >=20 > + ) >=20 > +{ >=20 > + return CpuRegbarWrite8 (CpuSbDevicePid, Offset, > CpuRegbarRead8(CpuSbDevicePid, Offset) | OrData); >=20 > +} >=20 > + >=20 > +/** >=20 > + Performs a bitwise AND of a 32-bit data. >=20 > + It programs REGBAR register and size in 4bytes. >=20 > + The Offset should not exceed 0xFFFF and must be aligned with size. >=20 > + >=20 > + @param[in] CpuSbDevice CPU SB Device >=20 > + @param[in] Offset Register offset of Port ID. >=20 > + @param[in] AndData And Data. Must be the same size as Size > parameter. >=20 > + >=20 > + @retval UINT32 Value written to register >=20 > + >=20 > +**/ >=20 > +UINT32 >=20 > +CpuRegbarAnd32 ( >=20 > + IN CPU_SB_DEVICE_PID CpuSbDevicePid, >=20 > + IN UINT16 Offset, >=20 > + IN UINT32 AndData >=20 > + ) >=20 > +{ >=20 > + return CpuRegbarWrite32 (CpuSbDevicePid, Offset, CpuRegbarRead32 > (CpuSbDevicePid, Offset) & AndData); >=20 > +} >=20 > + >=20 > +/** >=20 > + Performs a bitwise AND of a 16-bit data. >=20 > + It programs REGBAR register and size in 2bytes. >=20 > + The Offset should not exceed 0xFFFF and must be aligned with size. >=20 > + >=20 > + @param[in] CpuSbDevice CPU SB Device >=20 > + @param[in] Offset Register offset of Port ID. >=20 > + @param[in] AndData And Data. Must be the same size as Size > parameter. >=20 > + >=20 > + @retval UINT16 Value written to register >=20 > + >=20 > +**/ >=20 > +UINT16 >=20 > +CpuRegbarAnd16 ( >=20 > + IN CPU_SB_DEVICE_PID CpuSbDevicePid, >=20 > + IN UINT16 Offset, >=20 > + IN UINT16 AndData >=20 > + ) >=20 > +{ >=20 > + return CpuRegbarWrite16 (CpuSbDevicePid, Offset, CpuRegbarRead16 > (CpuSbDevicePid, Offset) & AndData); >=20 > +} >=20 > + >=20 > +/** >=20 > +Performs a bitwise AND of a 8-bit data. >=20 > +It programs REGBAR register and size in 1byte. >=20 > +The Offset should not exceed 0xFFFF and must be aligned with size. >=20 > + >=20 > +@param[in] CpuSbDevice CPU SB Device >=20 > +@param[in] Offset Register offset of Port ID. >=20 > +@param[in] AndData And Data. Must be the same size as Size > parameter. >=20 > + >=20 > +@retval UINT8 Value written to register >=20 > + >=20 > +**/ >=20 > +UINT8 >=20 > +CpuRegbarAnd8 ( >=20 > + IN CPU_SB_DEVICE_PID CpuSbDevicePid, >=20 > + IN UINT16 Offset, >=20 > + IN UINT8 AndData >=20 > + ) >=20 > +{ >=20 > + return CpuRegbarWrite8 (CpuSbDevicePid, Offset, CpuRegbarRead8 > (CpuSbDevicePid, Offset) & AndData); >=20 > +} >=20 > + >=20 > +/** >=20 > + Write REGBAR register. >=20 > + It programs REGBAR register and size in 4bytes. >=20 > + The Offset should not exceed 0xFFFF and must be aligned with size. >=20 > + >=20 > + @param[in] CpuSbDevicePid CPU SB Device Port ID >=20 > + @param[in] Offset Register offset of Port ID. >=20 > + @param[in] AndData AND Data. Must be the same size as Size > parameter. >=20 > + @param[in] OrData OR Data. Must be the same size as Size > parameter. >=20 > + >=20 > + @retval UINT32 Value written to register >=20 > + >=20 > +**/ >=20 > +UINT32 >=20 > +CpuRegbarAndThenOr32 ( >=20 > + IN CPU_SB_DEVICE_PID CpuSbDevicePid, >=20 > + IN UINT16 Offset, >=20 > + IN UINT32 AndData, >=20 > + IN UINT32 OrData >=20 > + ) >=20 > +{ >=20 > + return CpuRegbarWrite32 (CpuSbDevicePid, Offset, (CpuRegbarRead32 > (CpuSbDevicePid, Offset) & AndData) | OrData); >=20 > +} >=20 > + >=20 > +/** >=20 > + Write REGBAR register. >=20 > + It programs REGBAR register and size in 2bytes. >=20 > + The Offset should not exceed 0xFFFF and must be aligned with size. >=20 > + >=20 > + @param[in] CpuSbDevicePid CPU SB Device Port ID >=20 > + @param[in] Offset Register offset of Port ID. >=20 > + @param[in] AndData AND Data. Must be the same size as Size > parameter. >=20 > + @param[in] OrData OR Data. Must be the same size as Size > parameter. >=20 > + >=20 > + @retval UINT16 Value written to register >=20 > + >=20 > +**/ >=20 > +UINT16 >=20 > +CpuRegbarAndThenOr16 ( >=20 > + IN CPU_SB_DEVICE_PID CpuSbDevicePid, >=20 > + IN UINT16 Offset, >=20 > + IN UINT16 AndData, >=20 > + IN UINT16 OrData >=20 > + ) >=20 > +{ >=20 > + return CpuRegbarWrite16 (CpuSbDevicePid, Offset, (CpuRegbarRead16 > (CpuSbDevicePid, Offset) & AndData) | OrData); >=20 > +} >=20 > + >=20 > +/** >=20 > + Write REGBAR register. >=20 > + It programs REGBAR register and size in 1bytes. >=20 > + The Offset should not exceed 0xFFFF and must be aligned with size. >=20 > + >=20 > + @param[in] CpuSbDevicePid CPU SB Device Port ID >=20 > + @param[in] Offset Register offset of Port ID. >=20 > + @param[in] AndData AND Data. Must be the same size as Size > parameter. >=20 > + @param[in] OrData OR Data. Must be the same size as Size > parameter. >=20 > + >=20 > + @retval UINT8 Value written to register >=20 > + >=20 > +**/ >=20 > +UINT8 >=20 > +CpuRegbarAndThenOr8 ( >=20 > + IN CPU_SB_DEVICE_PID CpuSbDevicePid, >=20 > + IN UINT16 Offset, >=20 > + IN UINT8 AndData, >=20 > + IN UINT8 OrData >=20 > + ) >=20 > +{ >=20 > + return CpuRegbarWrite8 (CpuSbDevicePid, Offset, (CpuRegbarRead8 > (CpuSbDevicePid, Offset) & AndData) | OrData); >=20 > +} >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/P2sb/Library/PeiDxeSmmCpuReg > barAccessLib/PeiDxeSmmCpuRegbarAccessLib.inf > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/P2sb/Library/PeiDxeSmmCpuReg > barAccessLib/PeiDxeSmmCpuRegbarAccessLib.inf > new file mode 100644 > index 0000000000..596543f34f > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/P2sb/Library/PeiDxeSmmCpuReg > barAccessLib/PeiDxeSmmCpuRegbarAccessLib.inf > @@ -0,0 +1,35 @@ > +## @file >=20 > +# CPU REGBAR ACCESS Library. >=20 > +# >=20 > +# All function in this library is available for PEI, DXE, and SMM, >=20 > +# But do not support UEFI RUNTIME environment call. >=20 > +# >=20 > +# Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > +# SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +# >=20 > +## >=20 > + >=20 > + >=20 > +[Defines] >=20 > +INF_VERSION =3D 0x00010017 >=20 > +BASE_NAME =3D PeiDxeSmmCpuRegbarAccessLib >=20 > +FILE_GUID =3D CA92B911-528D-4FBB-9A5A-7BC22AA1A6D0 >=20 > +VERSION_STRING =3D 1.0 >=20 > +MODULE_TYPE =3D BASE >=20 > +LIBRARY_CLASS =3D CpuRegbarAccessLib >=20 > + >=20 > + >=20 > +[LibraryClasses] >=20 > +BaseLib >=20 > +IoLib >=20 > +DebugLib >=20 > + >=20 > +[Packages] >=20 > +MdePkg/MdePkg.dec >=20 > +TigerlakeSiliconPkg/SiPkg.dec >=20 > + >=20 > +[Pcd] >=20 > +gSiPkgTokenSpaceGuid.PcdRegBarBaseAddress >=20 > + >=20 > +[Sources] >=20 > +CpuRegbarAccessLib.c >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/P2sb/Library/PeiDxeSmmPchPcrL= i > b/PchPcrLib.c > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/P2sb/Library/PeiDxeSmmPchPcrL= i > b/PchPcrLib.c > new file mode 100644 > index 0000000000..c4f3740c86 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/P2sb/Library/PeiDxeSmmPchPcrL= i > b/PchPcrLib.c > @@ -0,0 +1,313 @@ > +/** @file >=20 > + PCH PCR library. >=20 > + All function in this library is available for PEI, DXE, and SMM, >=20 > + But do not support UEFI RUNTIME environment call. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +#ifndef MDEPKG_NDEBUG >=20 > +/** >=20 > + Checks if the offset is valid for a given memory access width. Offset = must > align to width size. >=20 > + >=20 > + @param[in] Offset Offset of a register >=20 > + @param[in] Size Size of memory access in bytes >=20 > + >=20 > + @retval FALSE Offset is not valid for a given memory access >=20 > + @retval TRUE Offset is valid >=20 > +**/ >=20 > +STATIC >=20 > +BOOLEAN >=20 > +PchIsPcrOffsetValid ( >=20 > + IN UINT32 Offset, >=20 > + IN UINTN Size >=20 > + ) >=20 > +{ >=20 > + if (!IsP2sb20bPcrSupported ()) { >=20 > + if (((Offset & (Size - 1)) !=3D 0) || (Offset > 0xFFFF)) { >=20 > + DEBUG ((DEBUG_ERROR, "PCR offset error. Invalid Offset: %x Size: %= x", > Offset, Size)); >=20 > + return FALSE; >=20 > + } else { >=20 > + return TRUE; >=20 > + } >=20 > + } else { >=20 > + if (((Offset & (Size - 1)) !=3D 0) || (Offset > 0xFFFFF)) { >=20 > + DEBUG ((DEBUG_ERROR, "PCR offset error. Invalid Offset: %x Size: %= x", > Offset, Size)); >=20 > + return FALSE; >=20 > + } else { >=20 > + return TRUE; >=20 > + } >=20 > + } >=20 > +} >=20 > +#endif >=20 > + >=20 > +/** >=20 > + Read PCR register. >=20 > + It returns PCR register and size in 4bytes. >=20 > + The Offset should not exceed 0xFFFF and must be aligned with size. >=20 > + >=20 > + @param[in] Pid Port ID >=20 > + @param[in] Offset Register offset of this Port ID >=20 > + >=20 > + @retval UINT32 PCR register value. >=20 > +**/ >=20 > +UINT32 >=20 > +PchPcrRead32 ( >=20 > + IN PCH_SBI_PID Pid, >=20 > + IN UINT32 Offset >=20 > + ) >=20 > +{ >=20 > +#ifndef MDEPKG_NDEBUG >=20 > + ASSERT (PchIsPcrOffsetValid (Offset, 4)); >=20 > +#endif >=20 > + return MmioRead32 (PCH_PCR_ADDRESS (Pid, Offset)); >=20 > +} >=20 > + >=20 > +/** >=20 > + Read PCR register. >=20 > + It returns PCR register and size in 2bytes. >=20 > + The Offset should not exceed 0xFFFF and must be aligned with size. >=20 > + >=20 > + @param[in] Pid Port ID >=20 > + @param[in] Offset Register offset of this Port ID >=20 > + >=20 > + @retval UINT16 PCR register value. >=20 > +**/ >=20 > +UINT16 >=20 > +PchPcrRead16 ( >=20 > + IN PCH_SBI_PID Pid, >=20 > + IN UINT32 Offset >=20 > + ) >=20 > +{ >=20 > +#ifndef MDEPKG_NDEBUG >=20 > + ASSERT (PchIsPcrOffsetValid (Offset, 2)); >=20 > +#endif >=20 > + return MmioRead16 (PCH_PCR_ADDRESS (Pid, Offset)); >=20 > +} >=20 > + >=20 > +/** >=20 > + Read PCR register. >=20 > + It returns PCR register and size in 1bytes. >=20 > + The Offset should not exceed 0xFFFF and must be aligned with size. >=20 > + >=20 > + @param[in] Pid Port ID >=20 > + @param[in] Offset Register offset of this Port ID >=20 > + >=20 > + @retval UINT8 PCR register value >=20 > +**/ >=20 > +UINT8 >=20 > +PchPcrRead8 ( >=20 > + IN PCH_SBI_PID Pid, >=20 > + IN UINT32 Offset >=20 > + ) >=20 > +{ >=20 > + return MmioRead8 (PCH_PCR_ADDRESS (Pid, Offset)); >=20 > +} >=20 > + >=20 > +/** >=20 > + Write PCR register. >=20 > + It programs PCR register and size in 4bytes. >=20 > + The Offset should not exceed 0xFFFF and must be aligned with size. >=20 > + >=20 > + @param[in] Pid Port ID >=20 > + @param[in] Offset Register offset of Port ID. >=20 > + @param[in] Data Input Data. Must be the same size as Size paramet= er. >=20 > + >=20 > + @retval UINT32 Value written to register >=20 > +**/ >=20 > +UINT32 >=20 > +PchPcrWrite32 ( >=20 > + IN PCH_SBI_PID Pid, >=20 > + IN UINT32 Offset, >=20 > + IN UINT32 Data >=20 > + ) >=20 > +{ >=20 > +#ifndef MDEPKG_NDEBUG >=20 > + ASSERT (PchIsPcrOffsetValid (Offset, 4)); >=20 > +#endif >=20 > + MmioWrite32 (PCH_PCR_ADDRESS (Pid, Offset), Data); >=20 > + >=20 > + return Data; >=20 > + >=20 > +} >=20 > + >=20 > +/** >=20 > + Write PCR register. >=20 > + It programs PCR register and size in 2bytes. >=20 > + The Offset should not exceed 0xFFFF and must be aligned with size. >=20 > + >=20 > + @param[in] Pid Port ID >=20 > + @param[in] Offset Register offset of Port ID. >=20 > + @param[in] Data Input Data. Must be the same size as Size paramet= er. >=20 > + >=20 > + @retval UINT16 Value written to register >=20 > +**/ >=20 > +UINT16 >=20 > +PchPcrWrite16 ( >=20 > + IN PCH_SBI_PID Pid, >=20 > + IN UINT32 Offset, >=20 > + IN UINT16 Data >=20 > + ) >=20 > +{ >=20 > +#ifndef MDEPKG_NDEBUG >=20 > + ASSERT (PchIsPcrOffsetValid (Offset, 2)); >=20 > +#endif >=20 > + MmioWrite16 (PCH_PCR_ADDRESS (Pid, Offset), Data); >=20 > + >=20 > + return Data; >=20 > +} >=20 > + >=20 > +/** >=20 > + Write PCR register. >=20 > + It programs PCR register and size in 1bytes. >=20 > + The Offset should not exceed 0xFFFF and must be aligned with size. >=20 > + >=20 > + @param[in] Pid Port ID >=20 > + @param[in] Offset Register offset of Port ID. >=20 > + @param[in] Data Input Data. Must be the same size as Size paramet= er. >=20 > + >=20 > + @retval UINT8 Value written to register >=20 > +**/ >=20 > +UINT8 >=20 > +PchPcrWrite8 ( >=20 > + IN PCH_SBI_PID Pid, >=20 > + IN UINT32 Offset, >=20 > + IN UINT8 Data >=20 > + ) >=20 > +{ >=20 > + >=20 > + MmioWrite8 (PCH_PCR_ADDRESS (Pid, Offset), Data); >=20 > + >=20 > + return Data; >=20 > +} >=20 > + >=20 > +/** >=20 > + Write PCR register. >=20 > + It programs PCR register and size in 4bytes. >=20 > + The Offset should not exceed 0xFFFF and must be aligned with size. >=20 > + >=20 > + @param[in] Pid Port ID >=20 > + @param[in] Offset Register offset of Port ID. >=20 > + @param[in] AndData AND Data. Must be the same size as Size parameter= . >=20 > + @param[in] OrData OR Data. Must be the same size as Size parameter. >=20 > + >=20 > + @retval UINT32 Value written to register >=20 > + >=20 > +**/ >=20 > +UINT32 >=20 > +PchPcrAndThenOr32 ( >=20 > + IN PCH_SBI_PID Pid, >=20 > + IN UINT32 Offset, >=20 > + IN UINT32 AndData, >=20 > + IN UINT32 OrData >=20 > + ) >=20 > +{ >=20 > + return PchPcrWrite32 (Pid, Offset, (PchPcrRead32 (Pid, Offset) & AndDa= ta) > | OrData); >=20 > +} >=20 > + >=20 > +/** >=20 > + Write PCR register and read back. >=20 > + The read back ensures the PCR cycle is completed before next operation= . >=20 > + It programs PCR register and size in 4bytes. >=20 > + The Offset should not exceed 0xFFFF and must be aligned with size. >=20 > + >=20 > + @param[in] Pid Port ID >=20 > + @param[in] Offset Register offset of Port ID. >=20 > + @param[in] AndData AND Data. Must be the same size as Size parameter= . >=20 > + @param[in] OrData OR Data. Must be the same size as Size parameter. >=20 > + >=20 > + @retval UINT32 Value read back from the register >=20 > +**/ >=20 > +UINT32 >=20 > +PchPcrAndThenOr32WithReadback ( >=20 > + IN PCH_SBI_PID Pid, >=20 > + IN UINT32 Offset, >=20 > + IN UINT32 AndData, >=20 > + IN UINT32 OrData >=20 > + ) >=20 > +{ >=20 > + PchPcrWrite32 (Pid, Offset, (PchPcrRead32 (Pid, Offset) & AndData) | > OrData); >=20 > + return PchPcrRead32 (Pid, Offset); >=20 > +} >=20 > + >=20 > +/** >=20 > + Write PCR register. >=20 > + It programs PCR register and size in 2bytes. >=20 > + The Offset should not exceed 0xFFFF and must be aligned with size. >=20 > + >=20 > + @param[in] Pid Port ID >=20 > + @param[in] Offset Register offset of Port ID. >=20 > + @param[in] AndData AND Data. Must be the same size as Size parameter= . >=20 > + @param[in] OrData OR Data. Must be the same size as Size parameter. >=20 > + >=20 > + @retval UINT16 Value written to register >=20 > + >=20 > +**/ >=20 > +UINT16 >=20 > +PchPcrAndThenOr16 ( >=20 > + IN PCH_SBI_PID Pid, >=20 > + IN UINT32 Offset, >=20 > + IN UINT16 AndData, >=20 > + IN UINT16 OrData >=20 > + ) >=20 > +{ >=20 > + return PchPcrWrite16 (Pid, Offset, (PchPcrRead16 (Pid, Offset) & AndDa= ta) > | OrData); >=20 > +} >=20 > + >=20 > +/** >=20 > + Write PCR register. >=20 > + It programs PCR register and size in 1bytes. >=20 > + The Offset should not exceed 0xFFFF and must be aligned with size. >=20 > + >=20 > + @param[in] Pid Port ID >=20 > + @param[in] Offset Register offset of Port ID. >=20 > + @param[in] AndData AND Data. Must be the same size as Size parameter= . >=20 > + @param[in] OrData OR Data. Must be the same size as Size parameter. >=20 > + >=20 > + @retval UINT8 Value written to register >=20 > + >=20 > +**/ >=20 > +UINT8 >=20 > +PchPcrAndThenOr8 ( >=20 > + IN PCH_SBI_PID Pid, >=20 > + IN UINT32 Offset, >=20 > + IN UINT8 AndData, >=20 > + IN UINT8 OrData >=20 > + ) >=20 > +{ >=20 > + return PchPcrWrite8 (Pid, Offset, (PchPcrRead8 (Pid, Offset) & AndData= ) | > OrData); >=20 > +} >=20 > + >=20 > +/** >=20 > + Get PCH IP PID number >=20 > + >=20 > + @param[in] IpEnum PCH IP in PCH_IP_PID_ENUM >=20 > + >=20 > + @retval 0 PID of this IP is not supported >=20 > + !0 PID of the IP. >=20 > +**/ >=20 > +PCH_SBI_PID >=20 > +PchPcrGetPid ( >=20 > + PCH_IP_PID_ENUM IpEnum >=20 > + ) >=20 > +{ >=20 > + switch (IpEnum) { >=20 > + case PchIpDmi: >=20 > + return PID_DMI; >=20 > + case PchIpIclk: >=20 > + return PID_ICLK; >=20 > + default: >=20 > + ASSERT (FALSE); >=20 > + return PCH_INVALID_PID; >=20 > + } >=20 > +} >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/P2sb/Library/PeiDxeSmmPchPcrL= i > b/PeiDxeSmmPchPcrLib.inf > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/P2sb/Library/PeiDxeSmmPchPcrL= i > b/PeiDxeSmmPchPcrLib.inf > new file mode 100644 > index 0000000000..2efeba374f > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/P2sb/Library/PeiDxeSmmPchPcrL= i > b/PeiDxeSmmPchPcrLib.inf > @@ -0,0 +1,35 @@ > +## @file >=20 > +# PCH PCR Library. >=20 > +# >=20 > +# All function in this library is available for PEI, DXE, and SMM, >=20 > +# But do not support UEFI RUNTIME environment call. >=20 > +# >=20 > +# Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > +# SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +# >=20 > +## >=20 > + >=20 > + >=20 > +[Defines] >=20 > +INF_VERSION =3D 0x00010017 >=20 > +BASE_NAME =3D PeiDxeSmmPchPcrLib >=20 > +FILE_GUID =3D 117C8D19-445B-46BF-B624-109F63709375 >=20 > +VERSION_STRING =3D 1.0 >=20 > +MODULE_TYPE =3D BASE >=20 > +LIBRARY_CLASS =3D PchPcrLib >=20 > + >=20 > + >=20 > +[LibraryClasses] >=20 > +BaseLib >=20 > +IoLib >=20 > +DebugLib >=20 > +PchInfoLib >=20 > + >=20 > + >=20 > +[Packages] >=20 > +MdePkg/MdePkg.dec >=20 > +TigerlakeSiliconPkg/SiPkg.dec >=20 > + >=20 > + >=20 > +[Sources] >=20 > +PchPcrLib.c >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmm= P > chSbiAccessLib/PchSbiAccessLib.c > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmm= P > chSbiAccessLib/PchSbiAccessLib.c > new file mode 100644 > index 0000000000..8017dee3aa > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmm= P > chSbiAccessLib/PchSbiAccessLib.c > @@ -0,0 +1,253 @@ > +/** @file >=20 > + PCH SBI access library. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +/** >=20 > + Execute PCH SBI message >=20 > + Take care of that there is no lock protection when using SBI programmi= ng > in both POST time and SMI. >=20 > + It will clash with POST time SBI programming when SMI happen. >=20 > + Programmer MUST do the save and restore opration while using the > PchSbiExecution inside SMI >=20 > + to prevent from racing condition. >=20 > + This function will reveal P2SB and hide P2SB if it's originally hidden= . If more > than one SBI access >=20 > + needed, it's better to unhide the P2SB before calling and hide it back= after > done. >=20 > + >=20 > + When the return value is "EFI_SUCCESS", the "Response" do not need to > be checked as it would have been >=20 > + SBI_SUCCESS. If the return value is "EFI_DEVICE_ERROR", then this woul= d > provide additional information >=20 > + when needed. >=20 > + >=20 > + @param[in] Pid Port ID of the SBI message >=20 > + @param[in] Offset Offset of the SBI message >=20 > + @param[in] Opcode Opcode >=20 > + @param[in] Posted Posted message >=20 > + @param[in, out] Data32 Read/Write data >=20 > + @param[out] Response Response >=20 > + >=20 > + @retval EFI_SUCCESS Successfully completed. >=20 > + @retval EFI_DEVICE_ERROR Transaction fail >=20 > + @retval EFI_INVALID_PARAMETER Invalid parameter >=20 > + @retval EFI_TIMEOUT Timeout while waiting for respon= se >=20 > +**/ >=20 > +EFI_STATUS >=20 > +PchSbiExecution ( >=20 > + IN PCH_SBI_PID Pid, >=20 > + IN UINT64 Offset, >=20 > + IN PCH_SBI_OPCODE Opcode, >=20 > + IN BOOLEAN Posted, >=20 > + IN OUT UINT32 *Data32, >=20 > + OUT UINT8 *Response >=20 > + ) >=20 > +{ >=20 > + return PchSbiExecutionEx ( Pid, >=20 > + Offset, >=20 > + Opcode, >=20 > + Posted, >=20 > + 0x000F, >=20 > + 0x0000, >=20 > + 0x0000, >=20 > + Data32, >=20 > + Response >=20 > + ); >=20 > +} >=20 > + >=20 > +/** >=20 > + Full function for executing PCH SBI message >=20 > + Take care of that there is no lock protection when using SBI programmi= ng > in both POST time and SMI. >=20 > + It will clash with POST time SBI programming when SMI happen. >=20 > + Programmer MUST do the save and restore opration while using the > PchSbiExecution inside SMI >=20 > + to prevent from racing condition. >=20 > + This function will reveal P2SB and hide P2SB if it's originally hidden= . If more > than one SBI access >=20 > + needed, it's better to unhide the P2SB before calling and hide it back= after > done. >=20 > + >=20 > + When the return value is "EFI_SUCCESS", the "Response" do not need to > be checked as it would have been >=20 > + SBI_SUCCESS. If the return value is "EFI_DEVICE_ERROR", then this woul= d > provide additional information >=20 > + when needed. >=20 > + >=20 > + @param[in] Pid Port ID of the SBI message >=20 > + @param[in] Offset Offset of the SBI message >=20 > + @param[in] Opcode Opcode >=20 > + @param[in] Posted Posted message >=20 > + @param[in] Fbe First byte enable >=20 > + @param[in] Bar Bar >=20 > + @param[in] Fid Function ID >=20 > + @param[in, out] Data32 Read/Write data >=20 > + @param[out] Response Response >=20 > + >=20 > + @retval EFI_SUCCESS Successfully completed. >=20 > + @retval EFI_DEVICE_ERROR Transaction fail >=20 > + @retval EFI_INVALID_PARAMETER Invalid parameter >=20 > + @retval EFI_TIMEOUT Timeout while waiting for respon= se >=20 > +**/ >=20 > +EFI_STATUS >=20 > +PchSbiExecutionEx ( >=20 > + IN PCH_SBI_PID Pid, >=20 > + IN UINT64 Offset, >=20 > + IN PCH_SBI_OPCODE Opcode, >=20 > + IN BOOLEAN Posted, >=20 > + IN UINT16 Fbe, >=20 > + IN UINT16 Bar, >=20 > + IN UINT16 Fid, >=20 > + IN OUT UINT32 *Data32, >=20 > + OUT UINT8 *Response >=20 > + ) >=20 > +{ >=20 > + UINT64 P2sbBase; >=20 > + UINTN Timeout; >=20 > + UINT16 SbiStat; >=20 > + >=20 > + // >=20 > + // Check opcode valid >=20 > + // >=20 > + switch (Opcode) { >=20 > + case MemoryRead: >=20 > + case MemoryWrite: >=20 > + case PciConfigRead: >=20 > + case PciConfigWrite: >=20 > + case PrivateControlRead: >=20 > + case PrivateControlWrite: >=20 > + case GpioLockUnlock: >=20 > + break; >=20 > + default: >=20 > + return EFI_INVALID_PARAMETER; >=20 > + break; >=20 > + } >=20 > + >=20 > + P2sbBase =3D P2sbPciCfgBase (); >=20 > + if (PciSegmentRead16 (P2sbBase + PCI_VENDOR_ID_OFFSET) =3D=3D 0xFFFF) = { >=20 > + ASSERT (FALSE); >=20 > + return EFI_DEVICE_ERROR; >=20 > + } >=20 > + /// >=20 > + /// BWG Section 2.2.1 >=20 > + /// 1. Poll P2SB PCI offset D8h[0] =3D 0b >=20 > + /// Make sure the previous opeartion is completed. >=20 > + /// >=20 > + Timeout =3D 0xFFFFFFF; >=20 > + while (Timeout > 0) { >=20 > + SbiStat =3D PciSegmentRead16 (P2sbBase + R_P2SB_CFG_SBISTAT); >=20 > + if ((SbiStat & B_P2SB_CFG_SBISTAT_INITRDY) =3D=3D 0) { >=20 > + break; >=20 > + } >=20 > + Timeout--; >=20 > + } >=20 > + if (Timeout =3D=3D 0) { >=20 > + return EFI_TIMEOUT; >=20 > + } >=20 > + // >=20 > + // Initial Response status >=20 > + // >=20 > + *Response =3D SBI_INVALID_RESPONSE; >=20 > + SbiStat =3D 0; >=20 > + /// >=20 > + /// 2. Write P2SB PCI offset D0h[31:0] with Address and Destination Po= rt ID >=20 > + /// >=20 > + PciSegmentWrite32 (P2sbBase + R_P2SB_CFG_SBIADDR, (UINT32) ((Pid << > 24) | (UINT16) Offset)); >=20 > + /// >=20 > + /// 3. Write P2SB PCI offset DCh[31:0] with extended address, which is > expected to be 0 in CNL PCH. >=20 > + /// >=20 > + PciSegmentWrite32 (P2sbBase + R_P2SB_CFG_SBIEXTADDR, (UINT32) > RShiftU64 (Offset, 16)); >=20 > + /// >=20 > + /// 5. Set P2SB PCI offset D8h[15:8] =3D 00000110b for read >=20 > + /// Set P2SB PCI offset D8h[15:8] =3D 00000111b for write >=20 > + // >=20 > + // Set SBISTAT[15:8] to the opcode passed in >=20 > + // Set SBISTAT[7] to the posted passed in >=20 > + // >=20 > + PciSegmentAndThenOr16 ( >=20 > + (P2sbBase + R_P2SB_CFG_SBISTAT), >=20 > + (UINT16) ~(B_P2SB_CFG_SBISTAT_OPCODE | > B_P2SB_CFG_SBISTAT_POSTED), >=20 > + (UINT16) ((Opcode << 8) | (Posted << 7)) >=20 > + ); >=20 > + /// >=20 > + /// 6. Write P2SB PCI offset DAh[15:0] =3D F000h >=20 > + /// >=20 > + // >=20 > + // Set RID[15:0] =3D Fbe << 12 | Bar << 8 | Fid >=20 > + // >=20 > + PciSegmentWrite16 ( >=20 > + (P2sbBase + R_P2SB_CFG_SBIRID), >=20 > + (((Fbe & 0x000F) << 12) | ((Bar & 0x0007) << 8) | (Fid & 0x00FF)) >=20 > + ); >=20 > + >=20 > + switch (Opcode) { >=20 > + case MemoryWrite: >=20 > + case PciConfigWrite: >=20 > + case PrivateControlWrite: >=20 > + case GpioLockUnlock: >=20 > + /// >=20 > + /// 4. Write P2SB PCI offset D4h[31:0] with the intended data acco= rdingly >=20 > + /// >=20 > + PciSegmentWrite32 ((P2sbBase + R_P2SB_CFG_SBIDATA), *Data32); >=20 > + break; >=20 > + default: >=20 > + /// >=20 > + /// 4. Write P2SB PCI offset D4h[31:0] with dummy data such as 0, >=20 > + /// because all D0-DFh register range must be touched in CNL PCH >=20 > + /// for a successful SBI transaction. >=20 > + /// >=20 > + PciSegmentWrite32 ((P2sbBase + R_P2SB_CFG_SBIDATA), 0); >=20 > + break; >=20 > + } >=20 > + /// >=20 > + /// 7. Set P2SB PCI offset D8h[0] =3D 1b, Poll P2SB PCI offset D8h[0] = =3D 0b >=20 > + /// >=20 > + // >=20 > + // Set SBISTAT[0] =3D 1b, trigger the SBI operation >=20 > + // >=20 > + PciSegmentOr16 (P2sbBase + R_P2SB_CFG_SBISTAT, (UINT16) > B_P2SB_CFG_SBISTAT_INITRDY); >=20 > + // >=20 > + // Poll SBISTAT[0] =3D 0b, Polling for Busy bit >=20 > + // >=20 > + Timeout =3D 0xFFFFFFF; >=20 > + while (Timeout > 0) { >=20 > + SbiStat =3D PciSegmentRead16 (P2sbBase + R_P2SB_CFG_SBISTAT); >=20 > + if ((SbiStat & B_P2SB_CFG_SBISTAT_INITRDY) =3D=3D 0) { >=20 > + break; >=20 > + } >=20 > + Timeout--; >=20 > + } >=20 > + if (Timeout =3D=3D 0) { >=20 > + // >=20 > + // If timeout, it's fatal error. >=20 > + // >=20 > + return EFI_TIMEOUT; >=20 > + } else { >=20 > + /// >=20 > + /// 8. Check if P2SB PCI offset D8h[2:1] =3D 00b for successful tran= saction >=20 > + /// >=20 > + *Response =3D (UINT8) ((SbiStat & B_P2SB_CFG_SBISTAT_RESPONSE) >> > N_P2SB_CFG_SBISTAT_RESPONSE); >=20 > + if (*Response =3D=3D SBI_SUCCESSFUL) { >=20 > + switch (Opcode) { >=20 > + case MemoryRead: >=20 > + case PciConfigRead: >=20 > + case PrivateControlRead: >=20 > + /// >=20 > + /// 9. Read P2SB PCI offset D4h[31:0] for SBI data >=20 > + /// >=20 > + *Data32 =3D PciSegmentRead32 (P2sbBase + R_P2SB_CFG_SBIDATA); >=20 > + break; >=20 > + default: >=20 > + break; >=20 > + } >=20 > + return EFI_SUCCESS; >=20 > + } else if (*Response =3D=3D SBI_POWERDOWN) { >=20 > + return EFI_NO_RESPONSE; >=20 > + } else { >=20 > + return EFI_DEVICE_ERROR; >=20 > + } >=20 > + } >=20 > +} >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmm= P > chSbiAccessLib/PeiDxeSmmPchSbiAccessLib.inf > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmm= P > chSbiAccessLib/PeiDxeSmmPchSbiAccessLib.inf > new file mode 100644 > index 0000000000..4199a0a6c7 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmm= P > chSbiAccessLib/PeiDxeSmmPchSbiAccessLib.inf > @@ -0,0 +1,36 @@ > +## @file >=20 > +# PCH SBI access library. >=20 > +# >=20 > +# All function in this library is available for PEI, DXE, and SMM, >=20 > +# But do not support UEFI RUNTIME environment call. >=20 > +# >=20 > +# Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > +# SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +# >=20 > +## >=20 > + >=20 > + >=20 > +[Defines] >=20 > +INF_VERSION =3D 0x00010017 >=20 > +BASE_NAME =3D PeiDxeSmmPchSbiAccessLib >=20 > +FILE_GUID =3D 96ECB0FB-A975-4DC8-B88A-D90C3378CE87 >=20 > +VERSION_STRING =3D 1.0 >=20 > +MODULE_TYPE =3D BASE >=20 > +LIBRARY_CLASS =3D PchSbiAccessLib >=20 > + >=20 > + >=20 > +[LibraryClasses] >=20 > +BaseLib >=20 > +IoLib >=20 > +DebugLib >=20 > +PciSegmentLib >=20 > +PchPciBdfLib >=20 > + >=20 > + >=20 > +[Packages] >=20 > +MdePkg/MdePkg.dec >=20 > +TigerlakeSiliconPkg/SiPkg.dec >=20 > + >=20 > + >=20 > +[Sources] >=20 > +PchSbiAccessLib.c >=20 > -- > 2.24.0.windows.2