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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Nate DeSimone > -----Original Message----- > From: Luo, Heng > Sent: Sunday, January 31, 2021 5:37 PM > To: devel@edk2.groups.io > Cc: Chaganty, Rangasai V ; Desimone, > Nathaniel L > Subject: [PATCH 16/40] TigerlakeSiliconPkg/IpBlock: Add Gbe component >=20 > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3171 >=20 > Adds the following files: > * IpBlock/Gbe/IncludePrivate > * IpBlock/Gbe/Library > * IpBlock/Gbe/LibraryPrivate >=20 > Cc: Sai Chaganty > Cc: Nate DeSimone > Signed-off-by: Heng Luo > --- >=20 > Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Gbe/IncludePrivate/Library/GbeM= d > iLib.h | 324 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Gbe/IncludePrivate/Register/Gbe= R > egs.h | 68 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Gbe/Library/PeiDxeSmmGbeLib/Gb > eLib.c | 121 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Gbe/Library/PeiDxeSmmGbeLib/Pei > DxeSmmGbeLib.inf | 43 > +++++++++++++++++++++++++++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Gbe/LibraryPrivate/PeiDxeSmmGb > eMdiLib/GbeMdiLib.c | 388 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Gbe/LibraryPrivate/PeiDxeSmmGb > eMdiLib/PeiDxeSmmGbeMdiLib.inf | 34 > ++++++++++++++++++++++++++++++++++ > 6 files changed, 978 insertions(+) >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Gbe/IncludePrivate/Library/Gb= e > MdiLib.h > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Gbe/IncludePrivate/Library/Gb= e > MdiLib.h > new file mode 100644 > index 0000000000..b8274ed3dc > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Gbe/IncludePrivate/Library/Gb= e > MdiLib.h > @@ -0,0 +1,324 @@ > +/** @file >=20 > + Header file for GbeMdiLib. >=20 > + >=20 > + Conventions: >=20 > + >=20 > + - Prefixes: >=20 > + Definitions beginning with "R_" are registers >=20 > + Definitions beginning with "B_" are bits within registers >=20 > + Definitions beginning with "V_" are meaningful values within the bit= s >=20 > + Definitions beginning with "S_" are register sizes >=20 > + Definitions beginning with "N_" are the bit position >=20 > + - In general, PCH registers are denoted by "_PCH_" in register names >=20 > + - Registers / bits that are different between PCH generations are deno= ted > by >=20 > + "_PCH_[generation_name]_" in register/bit names. >=20 > + - Registers / bits that are specific to PCH-H denoted by "_H_" in regi= ster/bit > names. >=20 > + Registers / bits that are specific to PCH-LP denoted by "_LP_" in > register/bit names. >=20 > + e.g., "_PCH_LP_" >=20 > + Registers / bits names without or _LP_ apply for LP. >=20 > + - Registers / bits that are different between SKUs are denoted by > "_[SKU_name]" >=20 > + at the end of the register/bit names >=20 > + - Registers / bits of new devices introduced in a PCH generation will = be just > named >=20 > + as "_PCH_" without [generation_name] inserted. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _GBE_MDI_LIB_H_ >=20 > +#define _GBE_MDI_LIB_H_ >=20 > + >=20 > +// >=20 > +// Maximum loop time for GbE status check >=20 > +// 4000 * 50 =3D 200 mSec in total >=20 > +// >=20 > +#define GBE_MAX_LOOP_TIME 4000 >=20 > +#define GBE_ACQUIRE_MDIO_DELAY 50 >=20 > +#define GBE_MDI_SET_PAGE_DELAY 4000 // 4 mSec delay after setting > page >=20 > + >=20 > +// >=20 > +// LAN PHY MDI settings >=20 > +// >=20 > +// MDI Control Register Bits >=20 > +// 31:30 Reserved >=20 > +// This field is reserved and returns 0. >=20 > +// 29 Interrupt Enable. >=20 > +// When this bit is set to 1 by software, it causes the device to = assert >=20 > +// an interrupt indicating the end of an MDI cycle. >=20 > +// 28 Ready. >=20 > +// Set to 1 by the device at the end of MDI transaction (i.e., ind= icates a > Read or >=20 > +// Write has been completed. It should be reset to 0 by software a= t the > same time the >=20 > +// command is written. >=20 > +// 27:26 Opcode >=20 > +// For an MDI write, the opcode equals 01b, and for MDI read, 10b.= 00b > and >=20 > +// 11b are reserved and should not be used. >=20 > +// 25:21 PHYAdd >=20 > +// PHY Address >=20 > +// 20:16 RegAdd >=20 > +// PHY Register Address >=20 > +// 15:0 Data >=20 > + >=20 > +#define B_PHY_MDI_READY BIT28 >=20 > +#define B_PHY_MDI_READ BIT27 >=20 > +#define B_PHY_MDI_WRITE BIT26 >=20 > +// >=20 > +// PHY SPECIFIC registers >=20 > +// >=20 > +#define B_PHY_MDI_PHY_ADDRESS_02 BIT22 >=20 > +// >=20 > +// PHY GENERAL registers >=20 > +// Registers 0 to 15 are defined by the specification >=20 > +// Registers 16 to 31 are left available to the vendor >=20 > +// >=20 > +#define B_PHY_MDI_PHY_ADDRESS_01 BIT21 >=20 > +#define B_PHY_MDI_PHY_ADDRESS_MASK (BIT25 | BIT24 | BIT23 | BIT22 > | BIT21) >=20 > +// >=20 > +// PHY Identifier Register 2 >=20 > +// Bits [15:10] - PHY ID Number - The PHY identifier composed of bits= 3 > through 18 >=20 > +// of the Organizationally Unique Iden= tifier (OUI) >=20 > +// Bits [9:4] - Device Model Number >=20 > +// Bits [3:0] - Device Revision Number >=20 > +// >=20 > +#define R_PHY_MDI_GENEREAL_REGISTER_03_PHY_IDENTIFIER_2 > 0x00030000 >=20 > + >=20 > +#define MDI_REG_SHIFT(x) (x << 16) >=20 > +#define B_PHY_MDI_PHY_REGISTER_MASK (BIT20 | BIT19 | B= IT18 > | BIT17 | BIT16) >=20 > +#define R_PHY_MDI_PHY_REG_SET_ADDRESS 0x00110000 // Used > after new page setting >=20 > +#define R_PHY_MDI_PHY_REG_DATA_READ_WRITE 0x00120000 >=20 > +#define R_PHY_MDI_PHY_REG_SET_PAGE 0x001F0000 >=20 > + >=20 > +// >=20 > +// LAN PHY MDI registers and bits >=20 > +// >=20 > + >=20 > +// >=20 > +// Page 769 Port Control Registers >=20 > +// 6020h (769 * 32) >=20 > +// >=20 > +#define PHY_MDI_PAGE_769_PORT_CONTROL_REGISTERS 769 >=20 > +// >=20 > +// Custom Mode Control PHY Address 01, Page 769, Register 16 >=20 > +// >=20 > +#define R_PHY_MDI_PAGE_769_REGISETER_16_CMC 0x0010 >=20 > +// >=20 > +// Custom Mode Control >=20 > +// Page 769, Register 16, BIT 10 >=20 > +// 0 - normal MDIO frequency access >=20 > +// 1 - reduced MDIO frequency access (slow mdio) >=20 > +// required for read during cable disconnect >=20 > +// >=20 > +#define > B_PHY_MDI_PAGE_769_REGISETER_16_CMC_MDIO_FREQ_ACCESS > BIT10 >=20 > +// >=20 > +// Port General Configuration PHY Address 01, Page 769, Register 17 >=20 > +// >=20 > +#define R_PHY_MDI_PAGE_769_REGISETER_17_PGC 0x0011 >=20 > +// >=20 > +// Page 769, Register 17, BIT 4 >=20 > +// Enables host wake up >=20 > +// >=20 > +#define B_PHY_MDI_PAGE_769_REGISETER_17_PGC_HOST_WAKE_UP > BIT4 >=20 > +// >=20 > +// Page 769, Register 17, BIT 2 >=20 > +// Globally enable the MAC power down feature while the >=20 > +// GbE supports WoL. When set to 1b, >=20 > +// pages 800 and 801 are enabled for >=20 > +// configuration and Host_WU_Active is not blocked for writes. >=20 > +// >=20 > +#define B_PHY_MDI_PAGE_769_REGISETER_17_PGC_MACPD_ENABLE > BIT2 >=20 > + >=20 > +// >=20 > +// Page 800 Wake Up Registers >=20 > +// 6400h (800 * 32) >=20 > +// >=20 > +#define PHY_MDI_PAGE_800_WAKE_UP_REGISTERS 800 >=20 > +// >=20 > +// Wake Up Control - WUC PHY Address 01, Page 800, Register 1 >=20 > +// 1h (Register 1) >=20 > +// >=20 > +#define R_PHY_MDI_PAGE_800_REGISETER_1_WUC 0x0001 >=20 > +// >=20 > +// Wake Up Control - (WUC) >=20 > +// Page 800, Register 1, BIT 0 >=20 > +// Advance Power Management Enable (APME) >=20 > +// If set to 1b, APM wake up is enabled. >=20 > +// >=20 > +#define B_PHY_MDI_PAGE_800_REGISETER_1_WUC_APME BIT0 >=20 > +// >=20 > +// Receive Address Low - RAL PHY Address 01, Page 800, Register 16 >=20 > +// 10h (Register 16) >=20 > +// >=20 > +#define R_PHY_MDI_PAGE_800_REGISETER_16_RAL0 0x0010 >=20 > +// >=20 > +// Receive Address Low - RAL PHY Address 01, Page 800, Register 17 >=20 > +// 11h (Register 17) >=20 > +// >=20 > +#define R_PHY_MDI_PAGE_800_REGISETER_17_RAL1 0x0011 >=20 > +// >=20 > +// Receive Address High - RAH PHY Address 01, Page 800, Register 18 >=20 > +// 12h (Register 18) >=20 > +// >=20 > +#define R_PHY_MDI_PAGE_800_REGISETER_18_RAH0 0x0012 >=20 > +// >=20 > +// Receive Address High - RAH PHY Address 01, Page 800, Register 19 >=20 > +// 13h (Register 19) >=20 > +// >=20 > +#define R_PHY_MDI_PAGE_800_REGISETER_19_RAH1 0x0013 >=20 > +// >=20 > +// Setting AV (BIT15 RAH is divided on two registers) >=20 > +// RAH Register 19, Page 800, BIT 31 >=20 > +// >=20 > +// Address valid (AV) >=20 > +// When this bit is set, the relevant RAL and RAH are valid >=20 > +// >=20 > +#define B_PHY_MDI_PAGE_800_REGISETER_19_RAH1_ADDRESS_VALID > BIT15 >=20 > +// >=20 > +// Page 803 Host WoL Packet >=20 > +// 6460h (803 * 32) >=20 > +// >=20 > +#define PHY_MDI_PAGE_803_HOST_WOL_PACKET 803 >=20 > +// >=20 > +// Host WoL Packet Clear - HWPC PHY Address 01, Page 803, Register 66 >=20 > +// >=20 > +#define R_PHY_MDI_PAGE_803_REGISETER_66_HWPC 0x0042 >=20 > + >=20 > + >=20 > +/** >=20 > + Change Extended Device Control Register BIT 11 to 1 which >=20 > + forces the interface between the MAC and the Phy to be on SMBus. >=20 > + Cleared on the assertion of PCI reset. >=20 > + >=20 > + @param [in] GbeBar GbE MMIO space >=20 > + >=20 > +**/ >=20 > +VOID >=20 > +GbeMdiForceMACtoSMB ( >=20 > + IN UINT32 GbeBar >=20 > + ); >=20 > + >=20 > +/** >=20 > + Test for MDIO operation complete. >=20 > + >=20 > + @param [in] GbeBar GbE MMIO space >=20 > + >=20 > + @retval EFI_SUCCESS >=20 > + @retval EFI_TIMEOUT >=20 > +**/ >=20 > +EFI_STATUS >=20 > +GbeMdiWaitReady ( >=20 > + IN UINT32 GbeBar >=20 > + ); >=20 > + >=20 > +/** >=20 > + Acquire MDIO software semaphore. >=20 > + >=20 > + 1. Ensure that MBARA offset F00h [5] =3D 1b >=20 > + 2. Poll MBARA offset F00h [5] up to 200ms >=20 > + >=20 > + @param [in] GbeBar GbE MMIO space >=20 > + >=20 > + @retval EFI_SUCCESS >=20 > + @retval EFI_TIMEOUT >=20 > +**/ >=20 > +EFI_STATUS >=20 > +GbeMdiAcquireMdio ( >=20 > + IN UINT32 GbeBar >=20 > + ); >=20 > + >=20 > +/** >=20 > + Release MDIO software semaphore by clearing MBARA offset F00h [5] >=20 > + >=20 > + @param [in] GbeBar GbE MMIO space >=20 > +**/ >=20 > +VOID >=20 > +GbeMdiReleaseMdio ( >=20 > + IN UINT32 GbeBar >=20 > + ); >=20 > + >=20 > +/** >=20 > + Sets page on MDI >=20 > + Page setting is attempted twice. >=20 > + If first attempt failes MAC and the Phy are force to be on SMBus >=20 > + >=20 > + @param [in] GbeBar GbE MMIO space >=20 > + @param [in] Data Value to write in lower 16bits. >=20 > + >=20 > + @retval EFI_SUCCESS Page setting was successfull >=20 > + @retval EFI_DEVICE_ERROR Returned if both attermps of setting page > failed >=20 > +**/ >=20 > +EFI_STATUS >=20 > +GbeMdiSetPage ( >=20 > + IN UINT32 GbeBar, >=20 > + IN UINT32 Page >=20 > + ); >=20 > + >=20 > +/** >=20 > + Sets Register in current page. >=20 > + >=20 > + @param [in] GbeBar GbE MMIO space >=20 > + @param [in] register Register number >=20 > + >=20 > + @return EFI_STATUS >=20 > +**/ >=20 > +EFI_STATUS >=20 > +GbeMdiSetRegister ( >=20 > + IN UINT32 GbeBar, >=20 > + IN UINT32 Register >=20 > + ); >=20 > + >=20 > + >=20 > +/** >=20 > + Perform MDI read. >=20 > + >=20 > + @param [in] GbeBar GbE MMIO space >=20 > + @param [in] PhyAddress Phy Address General - 02 or Specific - 01 >=20 > + @param [in] PhyRegister Phy Register >=20 > + @param [out] ReadData Return Value >=20 > + >=20 > + @retval EFI_SUCCESS Based on response from GbeMdiWaitReady >=20 > + @retval EFI_TIMEOUT Based on response from GbeMdiWaitReady >=20 > + @retval EFI_INVALID_PARAMETER If Phy Address or Register validaton > failed >=20 > +**/ >=20 > +EFI_STATUS >=20 > +GbeMdiRead ( >=20 > + IN UINT32 GbeBar, >=20 > + IN UINT32 PhyAddress, >=20 > + IN UINT32 PhyRegister, >=20 > + OUT UINT16 *ReadData >=20 > + ); >=20 > + >=20 > +/** >=20 > + Perform MDI write. >=20 > + >=20 > + @param [in] GbeBar GbE MMIO space >=20 > + @param [in] PhyAddress Phy Address General - 02 or Specific - 01 >=20 > + @param [in] PhyRegister Phy Register >=20 > + @param [in] WriteData Value to write in lower 16bits. >=20 > + >=20 > + @retval EFI_SUCCESS Based on response from GbeMdiWaitReady >=20 > + @retval EFI_TIMEOUT Based on response from GbeMdiWaitReady >=20 > + @retval EFI_INVALID_PARAMETER If Phy Address or Register validaton > failed >=20 > +**/ >=20 > +EFI_STATUS >=20 > +GbeMdiWrite ( >=20 > + IN UINT32 GbeBar, >=20 > + IN UINT32 PhyAddress, >=20 > + IN UINT32 PhyRegister, >=20 > + IN UINT32 WriteData >=20 > + ); >=20 > + >=20 > +/** >=20 > + Gets Phy Revision and Model Number >=20 > + from PHY IDENTIFIER register 2 (offset 3) >=20 > + >=20 > + @param [in] GbeBar GbE MMIO space >=20 > + @param [out] LanPhyRevision Return Value >=20 > + >=20 > + @return EFI_STATUS >=20 > + @return EFI_INVALID_PARAMETER When GbeBar is incorrect >=20 > +**/ >=20 > +EFI_STATUS >=20 > +GbeMdiGetLanPhyRevision ( >=20 > + IN UINT32 GbeBar, >=20 > + OUT UINT16 *LanPhyRevision >=20 > + ); >=20 > + >=20 > +#endif // _GBE_MDI_LIB_H_ >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Gbe/IncludePrivate/Register/G= be > Regs.h > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Gbe/IncludePrivate/Register/G= b > eRegs.h > new file mode 100644 > index 0000000000..307f1e159e > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Gbe/IncludePrivate/Register/G= b > eRegs.h > @@ -0,0 +1,68 @@ > +/** @file >=20 > + Register names for GbE device >=20 > + >=20 > + Conventions: >=20 > + >=20 > + - Register definition format: >=20 > + > Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterS > pace_RegisterName >=20 > + - Prefix: >=20 > + Definitions beginning with "R_" are registers >=20 > + Definitions beginning with "B_" are bits within registers >=20 > + Definitions beginning with "V_" are meaningful values within the bit= s >=20 > + Definitions beginning with "S_" are register size >=20 > + Definitions beginning with "N_" are the bit position >=20 > + - [GenerationName]: >=20 > + Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc= .). >=20 > + Register name without GenerationName applies to all generations. >=20 > + - [ComponentName]: >=20 > + This field indicates the component name that the register belongs to= (e.g. > PCH, SA etc.) >=20 > + Register name without ComponentName applies to all components. >=20 > + Register that is specific to -LP denoted by "_PCH_LP_" in component > name. >=20 > + - SubsystemName: >=20 > + This field indicates the subsystem name of the component that the > register belongs to >=20 > + (e.g. PCIE, USB, SATA, GPIO, PMC etc.). >=20 > + - RegisterSpace: >=20 > + MEM - MMIO space register of subsystem. >=20 > + IO - IO space register of subsystem. >=20 > + PCR - Private configuration register of subsystem. >=20 > + CFG - PCI configuration space register of subsystem. >=20 > + - RegisterName: >=20 > + Full register name. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _GBE_REGS_H_ >=20 > +#define _GBE_REGS_H_ >=20 > + >=20 > +#define R_GBE_CFG_MBARA 0x10 >=20 > +#define N_GBE_CFG_MBARA_ALIGN 17 >=20 > +#define R_GBE_CFG_PMCS 0xCC >=20 > +#define B_GBE_CFG_PMCS_PS (BIT1 | BIT0) >=20 > +#define V_GBE_CFG_PMCS_PS0 0x00 >=20 > +// >=20 > +// Gigabit Ethernet LAN Capabilities and Status Registers (Memory space) >=20 > +// >=20 > +#define R_GBE_MEM_CSR_CTRL 0 >=20 > +// >=20 > +// LANPHYPC: >=20 > +// Connects to the LCD DEVICE_OFF# signal in the >=20 > +// LAN Connected Device >=20 > +// >=20 > +#define B_GBE_MEM_CSR_CTRL_LANPHYPC_OVERRIDE BIT16 // When set > to 1 SW driver has the ability to control the LANPHYPC pin value. >=20 > +#define B_GBE_MEM_CSR_CTRL_LANPHYPC_VAL BIT17 // When set to > 1 this bit will define the value of the LANPHYPC pin. >=20 > +#define R_GBE_MEM_CSR_CTRL_EXT 0x0018 >=20 > +#define B_GBE_MEM_CSR_CTRL_EXT_LPCD BIT2 //LCD Power Cycle > Done (LPCD). This bit indicates whether LCD power cycle is done >=20 > + //- the bit is set 50/1= 00mSec after LANPHYPC pin > assertion. >=20 > +#define B_GBE_MEM_CSR_CTRL_EXT_FORCE_SMB BIT11 >=20 > +#define R_GBE_MEM_CSR_MDIC 0x0020 >=20 > +#define B_GBE_MEM_CSR_MDIC_RB BIT28 >=20 > +#define R_GBE_MEM_CSR_EXTCNF_CTRL 0x0F00 >=20 > +#define B_GBE_MEM_CSR_EXTCNF_CTRL_SWFLAG BIT5 >=20 > +#define R_GBE_MEM_CSR_RAL 0x5400 >=20 > +#define R_GBE_MEM_CSR_RAH 0x5404 >=20 > +#define B_GBE_MEM_CSR_RAH_RAH 0x0000FFFF >=20 > +#define R_GBE_MEM_CSR_WUC 0x5800 >=20 > +#define B_GBE_MEM_CSR_WUC_APME BIT0 >=20 > + >=20 > +#endif >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Gbe/Library/PeiDxeSmmGbeLib/ > GbeLib.c > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Gbe/Library/PeiDxeSmmGbeLib/ > GbeLib.c > new file mode 100644 > index 0000000000..3b51b9eb62 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Gbe/Library/PeiDxeSmmGbeLib/ > GbeLib.c > @@ -0,0 +1,121 @@ > +/** @file >=20 > + Gbe Library. >=20 > + All function in this library is available for PEI, DXE, and SMM, >=20 > + But do not support UEFI RUNTIME environment call. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +/** >=20 > + Check whether GbE region is valid >=20 > + Check SPI region directly since GbE might be disabled in SW. >=20 > + >=20 > + @retval TRUE Gbe Region is valid >=20 > + @retval FALSE Gbe Region is invalid >=20 > +**/ >=20 > +BOOLEAN >=20 > +IsGbeRegionValid ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return SpiIsGbeRegionValid (); >=20 > +} >=20 > + >=20 > +/** >=20 > + Check whether GBE controller is enabled in the platform. >=20 > + >=20 > + @retval TRUE GbE is enabled >=20 > + @retval FALSE GbE is disabled >=20 > +**/ >=20 > +BOOLEAN >=20 > +IsGbePresent ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + // >=20 > + // Check PCH Support >=20 > + // >=20 > + if (!PchIsGbeSupported ()) { >=20 > + return FALSE; >=20 > + } >=20 > + // >=20 > + // Check PMC strap/fuse >=20 > + // >=20 > + if (!PmcIsGbeSupported ()) { >=20 > + return FALSE; >=20 > + } >=20 > + // >=20 > + // Check GbE NVM >=20 > + // >=20 > + if (IsGbeRegionValid () =3D=3D FALSE) { >=20 > + return FALSE; >=20 > + } >=20 > + return TRUE; >=20 > +} >=20 > + >=20 > +/** >=20 > + Verifies Gigabit Ethernet PCI Class Code >=20 > + >=20 > + @param [in] GbePciCfgBase GbE PCI Config Space Address >=20 > + >=20 > + @retval TRUE GbE Class Code match >=20 > + @retval FALSE GbE Class Code does not match >=20 > +**/ >=20 > +BOOLEAN >=20 > +STATIC >=20 > +GbeCheckClassCode ( >=20 > + UINT64 GbePciCfgBase >=20 > + ) >=20 > +{ >=20 > + UINT8 BaseCode; >=20 > + UINT8 SubClassCode; >=20 > + >=20 > + SubClassCode =3D PciSegmentRead8 (GbePciCfgBase + > PCI_CLASSCODE_OFFSET + 1); >=20 > + BaseCode =3D PciSegmentRead8 (GbePciCfgBase + > PCI_CLASSCODE_OFFSET + 2); >=20 > + >=20 > + if ((BaseCode !=3D PCI_CLASS_NETWORK) || (SubClassCode !=3D > PCI_CLASS_NETWORK_ETHERNET)) { >=20 > + DEBUG ((DEBUG_ERROR, "GbeCheckClassCode : BaseCode(0x%x) or > ClassCode(0x%x) is not supported\n", BaseCode, SubClassCode)); >=20 > + ASSERT (FALSE); >=20 > + return FALSE; >=20 > + } >=20 > + return TRUE; >=20 > +} >=20 > + >=20 > +/** >=20 > + Checks if Gbe is Enabled or Disabled >=20 > + >=20 > + @retval BOOLEAN TRUE if device is enabled, FALSE otherwise. >=20 > +**/ >=20 > +BOOLEAN >=20 > +IsGbeEnabled ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + UINT64 GbePciBase; >=20 > + >=20 > + GbePciBase =3D GbePciCfgBase (); >=20 > + >=20 > + if (PciSegmentRead32 (GbePciBase) !=3D 0xFFFFFFFF) { >=20 > + return GbeCheckClassCode (GbePciBase); >=20 > + } >=20 > + >=20 > + return FALSE; >=20 > +} >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Gbe/Library/PeiDxeSmmGbeLib/ > PeiDxeSmmGbeLib.inf > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Gbe/Library/PeiDxeSmmGbeLib/ > PeiDxeSmmGbeLib.inf > new file mode 100644 > index 0000000000..4fef1288af > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Gbe/Library/PeiDxeSmmGbeLib/ > PeiDxeSmmGbeLib.inf > @@ -0,0 +1,43 @@ > +## @file >=20 > +# Gbe Library. >=20 > +# >=20 > +# All function in this library is available for PEI, DXE, and SMM, >=20 > +# But do not support UEFI RUNTIME environment call. >=20 > +# >=20 > +# Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > +# SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +# >=20 > +## >=20 > + >=20 > + >=20 > +[Defines] >=20 > +INF_VERSION =3D 0x00010017 >=20 > +BASE_NAME =3D PeiDxeSmmGbeLib >=20 > +FILE_GUID =3D FC022ED0-6EB3-43E1-A740-0BA27CBBD010 >=20 > +VERSION_STRING =3D 1.0 >=20 > +MODULE_TYPE =3D BASE >=20 > +LIBRARY_CLASS =3D GbeLib >=20 > + >=20 > + >=20 > +[LibraryClasses] >=20 > +BaseLib >=20 > +IoLib >=20 > +DebugLib >=20 > +PciSegmentLib >=20 > +PchInfoLib >=20 > +PchPcrLib >=20 > +PchCycleDecodingLib >=20 > +PmcPrivateLib >=20 > +SpiAccessLib >=20 > +GbeMdiLib >=20 > +PchPciBdfLib >=20 > + >=20 > + >=20 > +[Packages] >=20 > +MdePkg/MdePkg.dec >=20 > +TigerlakeSiliconPkg/SiPkg.dec >=20 > + >=20 > + >=20 > +[Sources] >=20 > +GbeLib.c >=20 > + >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Gbe/LibraryPrivate/PeiDxeSmmG > beMdiLib/GbeMdiLib.c > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Gbe/LibraryPrivate/PeiDxeSmmG > beMdiLib/GbeMdiLib.c > new file mode 100644 > index 0000000000..7917474406 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Gbe/LibraryPrivate/PeiDxeSmmG > beMdiLib/GbeMdiLib.c > @@ -0,0 +1,388 @@ > +/** @file >=20 > + Gbe MDI Library. >=20 > + All function in this library is available for PEI, DXE, and SMM, >=20 > + But do not support UEFI RUNTIME environment call. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > + >=20 > +/** >=20 > + Validates both Phy Address and Regster. >=20 > + >=20 > + @param [in] PhyAddress >=20 > + @param [in] PhyRegister >=20 > + >=20 > + @retval BOOLEAN TRUE Validation passed >=20 > + FALSE If the data is not within its range >=20 > + >=20 > +**/ >=20 > +BOOLEAN >=20 > +IsPhyAddressRegisterValid ( >=20 > + IN UINT32 PhyAddress, >=20 > + IN UINT32 PhyRegister >=20 > + ) >=20 > +{ >=20 > + if (((PhyAddress & (~B_PHY_MDI_PHY_ADDRESS_MASK)) !=3D 0) || > ((PhyRegister & (~B_PHY_MDI_PHY_REGISTER_MASK)) !=3D 0)) { >=20 > + DEBUG ((DEBUG_ERROR, "IsPhyAddressRegisterValid validation failed! > PhyAddress: 0x%08X PhyRegister: 0x%08X \n", PhyAddress, PhyRegister)); >=20 > + return FALSE; >=20 > + } >=20 > + return TRUE; >=20 > +} >=20 > + >=20 > +/** >=20 > + Change Extended Device Control Register BIT 11 to 1 which >=20 > + forces the interface between the MAC and the Phy to be on SMBus. >=20 > + Cleared on the assertion of PCI reset. >=20 > + >=20 > + @param [in] GbeBar GbE MMIO space >=20 > + >=20 > +**/ >=20 > +VOID >=20 > +GbeMdiForceMacToSmb ( >=20 > + IN UINT32 GbeBar >=20 > + ) >=20 > +{ >=20 > + MmioOr32 (GbeBar + R_GBE_MEM_CSR_CTRL_EXT, > B_GBE_MEM_CSR_CTRL_EXT_FORCE_SMB); >=20 > +} >=20 > + >=20 > +/** >=20 > + Test for MDIO operation complete. >=20 > + >=20 > + @param [in] GbeBar GbE MMIO space >=20 > + >=20 > + @retval EFI_SUCCESS >=20 > + @retval EFI_TIMEOUT >=20 > +**/ >=20 > +EFI_STATUS >=20 > +GbeMdiWaitReady ( >=20 > + IN UINT32 GbeBar >=20 > + ) >=20 > +{ >=20 > + UINT32 Count; >=20 > + >=20 > + for (Count =3D 0; Count < GBE_MAX_LOOP_TIME; ++Count) { >=20 > + if (MmioRead32 (GbeBar + R_GBE_MEM_CSR_MDIC) & > B_GBE_MEM_CSR_MDIC_RB) { >=20 > + return EFI_SUCCESS; >=20 > + } >=20 > + MicroSecondDelay (GBE_ACQUIRE_MDIO_DELAY); >=20 > + } >=20 > + DEBUG ((DEBUG_ERROR, "GbeMdiWaitReady Timeout reached. MDIO > operation failed to complete in %d micro seconds\n", > GBE_MAX_LOOP_TIME * GBE_ACQUIRE_MDIO_DELAY)); >=20 > + return EFI_TIMEOUT; >=20 > +} >=20 > + >=20 > +/** >=20 > + Acquire MDIO software semaphore. >=20 > + >=20 > + 1. Ensure that MBARA offset F00h [5] =3D 1b >=20 > + 2. Poll MBARA offset F00h [5] up to 200ms >=20 > + >=20 > + @param [in] GbeBar GbE MMIO space >=20 > + >=20 > + @retval EFI_SUCCESS >=20 > + @retval EFI_TIMEOUT >=20 > +**/ >=20 > +EFI_STATUS >=20 > +GbeMdiAcquireMdio ( >=20 > + IN UINT32 GbeBar >=20 > + ) >=20 > +{ >=20 > + UINT32 ExtCnfCtrl; >=20 > + UINT32 Count; >=20 > + >=20 > + MmioOr32 (GbeBar + R_GBE_MEM_CSR_EXTCNF_CTRL, > B_GBE_MEM_CSR_EXTCNF_CTRL_SWFLAG); >=20 > + for (Count =3D 0; Count < GBE_MAX_LOOP_TIME; ++Count) { >=20 > + ExtCnfCtrl =3D MmioRead32 (GbeBar + R_GBE_MEM_CSR_EXTCNF_CTRL); >=20 > + if (ExtCnfCtrl & B_GBE_MEM_CSR_EXTCNF_CTRL_SWFLAG) { >=20 > + return EFI_SUCCESS; >=20 > + } >=20 > + MicroSecondDelay (GBE_ACQUIRE_MDIO_DELAY); >=20 > + } >=20 > + DEBUG ((DEBUG_ERROR, "GbeMdiAcquireMdio Timeout. Unable to > acquire MDIO Semaphore in %d micro seconds\n", GBE_MAX_LOOP_TIME * > GBE_ACQUIRE_MDIO_DELAY)); >=20 > + return EFI_TIMEOUT; >=20 > +} >=20 > + >=20 > +/** >=20 > + Release MDIO software semaphore by clearing MBARA offset F00h [5] >=20 > + >=20 > + @param [in] GbeBar GbE MMIO space >=20 > +**/ >=20 > +VOID >=20 > +GbeMdiReleaseMdio ( >=20 > + IN UINT32 GbeBar >=20 > + ) >=20 > +{ >=20 > + ASSERT (MmioRead32 (GbeBar + R_GBE_MEM_CSR_EXTCNF_CTRL) & > B_GBE_MEM_CSR_EXTCNF_CTRL_SWFLAG); >=20 > + MmioAnd32 (GbeBar + R_GBE_MEM_CSR_EXTCNF_CTRL, (UINT32) > ~B_GBE_MEM_CSR_EXTCNF_CTRL_SWFLAG); >=20 > + ASSERT ((MmioRead32 (GbeBar + R_GBE_MEM_CSR_EXTCNF_CTRL) & > B_GBE_MEM_CSR_EXTCNF_CTRL_SWFLAG) =3D=3D 0); >=20 > +} >=20 > + >=20 > +/** >=20 > + Sets page on MDI >=20 > + Page setting is attempted twice. >=20 > + If first attempt failes MAC and the Phy are force to be on SMBus. >=20 > + >=20 > + Waits 4 mSec after page setting >=20 > + >=20 > + @param [in] GbeBar GbE MMIO space >=20 > + @param [in] Data Value to write in lower 16bits. >=20 > + >=20 > + @retval EFI_SUCCESS Page setting was successfull >=20 > + @retval EFI_DEVICE_ERROR Returned if both attermps of setting page > failed >=20 > +**/ >=20 > +EFI_STATUS >=20 > +GbeMdiSetPage ( >=20 > + IN UINT32 GbeBar, >=20 > + IN UINT32 Page >=20 > + ) >=20 > +{ >=20 > + EFI_STATUS Status; >=20 > + >=20 > + MmioWrite32 (GbeBar + R_GBE_MEM_CSR_MDIC, (~B_PHY_MDI_READY) > & (B_PHY_MDI_WRITE | B_PHY_MDI_PHY_ADDRESS_01 | > R_PHY_MDI_PHY_REG_SET_PAGE | ((Page * 32) & 0xFFFF))); >=20 > + >=20 > + Status =3D GbeMdiWaitReady (GbeBar); >=20 > + >=20 > + if (Status =3D=3D EFI_TIMEOUT) { >=20 > + DEBUG ((DEBUG_INFO, "GbeMdiSetPage Timeout reached. Forcing the > interface between the MAC and the Phy to be on SMBus\n")); >=20 > + GbeMdiForceMacToSmb (GbeBar); >=20 > + // >=20 > + // Retry page setting >=20 > + // >=20 > + MmioWrite32 (GbeBar + R_GBE_MEM_CSR_MDIC, > (~B_PHY_MDI_READY) & (B_PHY_MDI_WRITE | > B_PHY_MDI_PHY_ADDRESS_01 | R_PHY_MDI_PHY_REG_SET_PAGE | ((Page > * 32) & 0xFFFF))); >=20 > + Status =3D GbeMdiWaitReady (GbeBar); >=20 > + if (Status =3D=3D EFI_TIMEOUT) { >=20 > + DEBUG ((DEBUG_ERROR, "GbeMdiSetPage retry page setting > failed!\n")); >=20 > + return EFI_DEVICE_ERROR; >=20 > + } >=20 > + } >=20 > + >=20 > + // >=20 > + // Delay required for page to set properly >=20 > + // >=20 > + MicroSecondDelay (GBE_MDI_SET_PAGE_DELAY); >=20 > + >=20 > + return Status; >=20 > +} >=20 > + >=20 > +/** >=20 > + Sets Register in current page. >=20 > + >=20 > + @param [in] GbeBar GbE MMIO space >=20 > + @param [in] register Register number valid only in lower 16 Bits >=20 > + >=20 > + @return EFI_STATUS >=20 > +**/ >=20 > +EFI_STATUS >=20 > +GbeMdiSetRegister ( >=20 > + IN UINT32 GbeBar, >=20 > + IN UINT32 Register >=20 > + ) >=20 > +{ >=20 > + MmioWrite32 (GbeBar + R_GBE_MEM_CSR_MDIC, (~B_PHY_MDI_READY) > & (B_PHY_MDI_WRITE | B_PHY_MDI_PHY_ADDRESS_01 | > R_PHY_MDI_PHY_REG_SET_ADDRESS | (Register & 0xFFFF))); >=20 > + return GbeMdiWaitReady (GbeBar); >=20 > +} >=20 > + >=20 > +/** >=20 > + Perform MDI write. >=20 > + >=20 > + @param [in] GbeBar GbE MMIO space >=20 > + @param [in] PhyAddress Phy Address General - 02 or Specific - 01 >=20 > + @param [in] PhyRegister Phy Register >=20 > + @param [in] WriteData Value to write in lower 16bits. >=20 > + >=20 > + @retval EFI_SUCCESS Based on response from GbeMdiWaitReady >=20 > + @retval EFI_TIMEOUT Based on response from GbeMdiWaitReady >=20 > + @retval EFI_INVALID_PARAMETER If Phy Address or Register validaton > failed >=20 > +**/ >=20 > +EFI_STATUS >=20 > +GbeMdiWrite ( >=20 > + IN UINT32 GbeBar, >=20 > + IN UINT32 PhyAddress, >=20 > + IN UINT32 PhyRegister, >=20 > + IN UINT32 WriteData >=20 > + ) >=20 > +{ >=20 > + if(!IsPhyAddressRegisterValid (PhyAddress, PhyRegister)) { >=20 > + DEBUG ((DEBUG_ERROR, "GbeMdiWrite PhyAddressRegister validaton > failed!\n")); >=20 > + return EFI_INVALID_PARAMETER; >=20 > + } >=20 > + >=20 > + MmioWrite32 (GbeBar + R_GBE_MEM_CSR_MDIC, (~B_PHY_MDI_READY) > & (B_PHY_MDI_WRITE | PhyAddress | PhyRegister | (WriteData & 0xFFFF))); >=20 > + return GbeMdiWaitReady (GbeBar); >=20 > +} >=20 > + >=20 > +/** >=20 > + Perform MDI read. >=20 > + >=20 > + @param [in] GbeBar GbE MMIO space >=20 > + @param [in] PhyAddress Phy Address General - 02 or Specific - 01 >=20 > + @param [in] PhyRegister Phy Register >=20 > + @param [out] ReadData Return Value >=20 > + >=20 > + @retval EFI_SUCCESS Based on response from GbeMdiWaitReady >=20 > + @retval EFI_TIMEOUT Based on response from GbeMdiWaitReady >=20 > + @retval EFI_INVALID_PARAMETER If Phy Address or Register validaton > failed >=20 > +**/ >=20 > +EFI_STATUS >=20 > +GbeMdiRead ( >=20 > + IN UINT32 GbeBar, >=20 > + IN UINT32 PhyAddress, >=20 > + IN UINT32 PhyRegister, >=20 > + OUT UINT16 *ReadData >=20 > + ) >=20 > +{ >=20 > + EFI_STATUS Status; >=20 > + >=20 > + if(!IsPhyAddressRegisterValid (PhyAddress, PhyRegister)) { >=20 > + DEBUG ((DEBUG_ERROR, "GbeMdiRead PhyAddressRegister validaton > failed!\n")); >=20 > + return EFI_INVALID_PARAMETER; >=20 > + } >=20 > + >=20 > + MmioWrite32 (GbeBar + R_GBE_MEM_CSR_MDIC, (~B_PHY_MDI_READY) > & (B_PHY_MDI_READ | PhyAddress | PhyRegister)); >=20 > + Status =3D GbeMdiWaitReady (GbeBar); >=20 > + if (EFI_SUCCESS =3D=3D Status) { >=20 > + *ReadData =3D (UINT16) MmioRead32 (GbeBar + > R_GBE_MEM_CSR_MDIC); >=20 > + } >=20 > + return Status; >=20 > +} >=20 > + >=20 > +/** >=20 > + Gets Phy Revision and Model Number >=20 > + from PHY IDENTIFIER register 2 (offset 3) >=20 > + >=20 > + @param [in] GbeBar GbE MMIO space >=20 > + @param [out] LanPhyRevision Return Value >=20 > + >=20 > + @return EFI_STATUS >=20 > + @return EFI_INVALID_PARAMETER When GbeBar is incorrect >=20 > + When Phy register or address is out of b= ounds >=20 > +**/ >=20 > +EFI_STATUS >=20 > +GbeMdiGetLanPhyRevision ( >=20 > + IN UINT32 GbeBar, >=20 > + OUT UINT16 *LanPhyRevision >=20 > + ) >=20 > +{ >=20 > + EFI_STATUS Status; >=20 > + UINT8 LpcdLoop; >=20 > + UINT8 Delay; >=20 > + >=20 > + if (!((GbeBar & 0xFFFFF000) > 0)) { >=20 > + DEBUG ((DEBUG_ERROR, "GbeMdiGetLanPhyRevision GbeBar validation > failed! Bar: 0x%08X \n", GbeBar)); >=20 > + return EFI_INVALID_PARAMETER; >=20 > + } >=20 > + >=20 > + Status =3D GbeMdiAcquireMdio (GbeBar); >=20 > + if (EFI_ERROR (Status)) { >=20 > + DEBUG ((DEBUG_ERROR, "GbeMdiGetLanPhyRevision failed to aquire > MDIO semaphore. Status: %r\n", Status)); >=20 > + return Status; >=20 > + } >=20 > + >=20 > + Status =3D GbeMdiSetPage (GbeBar, > PHY_MDI_PAGE_769_PORT_CONTROL_REGISTERS); >=20 > + if (EFI_ERROR (Status)) { >=20 > + DEBUG ((DEBUG_ERROR, "GbeMdiGetLanPhyRevision failed to Set Page > 769. Status: %r\n", Status)); >=20 > + GbeMdiReleaseMdio (GbeBar); >=20 > + return Status; >=20 > + } >=20 > + >=20 > + // >=20 > + // Set register to: Custom Mode Control >=20 > + // Reduced MDIO frequency access (slow mdio) >=20 > + // BIT 10 set to 1 >=20 > + // >=20 > + Status =3D GbeMdiWrite (GbeBar, B_PHY_MDI_PHY_ADDRESS_01, > MDI_REG_SHIFT (R_PHY_MDI_PAGE_769_REGISETER_16_CMC), BIT13 | > B_PHY_MDI_PAGE_769_REGISETER_16_CMC_MDIO_FREQ_ACCESS | BIT8 | > BIT7); >=20 > + if (EFI_ERROR (Status)) { >=20 > + DEBUG ((DEBUG_ERROR, "GbeMdiGetLanPhyRevision failed to enable > slow MDIO mode. Status: %r\n", Status)); >=20 > + GbeMdiReleaseMdio (GbeBar); >=20 > + return Status; >=20 > + } >=20 > + >=20 > + // >=20 > + // Read register PHY Version from PHY IDENTIFIER 2 (offset 0x3) >=20 > + // Bits [9:4] - Device Model Number >=20 > + // Bits [3:0] - Device Revision Number >=20 > + // >=20 > + Status =3D GbeMdiRead (GbeBar, B_PHY_MDI_PHY_ADDRESS_02, > R_PHY_MDI_GENEREAL_REGISTER_03_PHY_IDENTIFIER_2, LanPhyRevision); >=20 > + >=20 > + // >=20 > + // Failed to obtain PHY REV >=20 > + // >=20 > + if (*LanPhyRevision =3D=3D 0x0) { >=20 > + if ((MmioRead32 (GbeBar + R_GBE_MEM_CSR_CTRL) & > (B_GBE_MEM_CSR_CTRL_LANPHYPC_OVERRIDE | > B_GBE_MEM_CSR_CTRL_LANPHYPC_VAL))) { >=20 > + DEBUG ((DEBUG_ERROR, "GbeMdiGetLanPhyRevision failed to read Phy > Revision. Other component tried to initialize GbE and failed.\n")); >=20 > + Status =3D EFI_DEVICE_ERROR; >=20 > + goto phy_exit; >=20 > + } >=20 > + DEBUG ((DEBUG_INFO, "GbeMdiGetLanPhyRevision failed to read > Revision. Overriding LANPHYPC\n", Status)); >=20 > + // >=20 > + // Taking over LANPHYPC >=20 > + // 1. SW signal override - 1st cycle. >=20 > + // 2. Turn LCD on - 2nd cycle. >=20 > + // >=20 > + MmioOr32 (GbeBar + R_GBE_MEM_CSR_CTRL, > B_GBE_MEM_CSR_CTRL_LANPHYPC_OVERRIDE); >=20 > + MmioOr32 (GbeBar + R_GBE_MEM_CSR_CTRL, > B_GBE_MEM_CSR_CTRL_LANPHYPC_VAL); >=20 > + >=20 > + // >=20 > + // Poll on LPCD for 100mSec >=20 > + // >=20 > + LpcdLoop =3D 101; >=20 > + while (LpcdLoop > 0) { >=20 > + if (MmioRead32 (GbeBar + R_GBE_MEM_CSR_CTRL_EXT) & > B_GBE_MEM_CSR_CTRL_EXT_LPCD) { >=20 > + break; >=20 > + } else { >=20 > + LpcdLoop--; >=20 > + MicroSecondDelay (1000); >=20 > + } >=20 > + } >=20 > + >=20 > + if (LpcdLoop > 0) { >=20 > + Delay =3D 100; >=20 > + Status =3D GbeMdiRead (GbeBar, B_PHY_MDI_PHY_ADDRESS_02, > R_PHY_MDI_GENEREAL_REGISTER_03_PHY_IDENTIFIER_2, LanPhyRevision); >=20 > + while (*LanPhyRevision =3D=3D 0 && Delay > 0) { >=20 > + Status =3D GbeMdiRead (GbeBar, B_PHY_MDI_PHY_ADDRESS_02, > R_PHY_MDI_GENEREAL_REGISTER_03_PHY_IDENTIFIER_2, LanPhyRevision); >=20 > + if (EFI_ERROR(Status)) { >=20 > + break; >=20 > + } >=20 > + MicroSecondDelay (1000); >=20 > + Delay --; >=20 > + } >=20 > + } >=20 > + // >=20 > + // Restore LANPHYPC >=20 > + // 1. Turn LCD off - 1st cycle. >=20 > + // 2. Remove SW signal override - 2nd cycle. >=20 > + // >=20 > + MmioAnd32 (GbeBar + R_GBE_MEM_CSR_CTRL, (UINT32) > ~B_GBE_MEM_CSR_CTRL_LANPHYPC_VAL); >=20 > + MmioAnd32 (GbeBar + R_GBE_MEM_CSR_CTRL, (UINT32) > ~B_GBE_MEM_CSR_CTRL_LANPHYPC_OVERRIDE); >=20 > + } >=20 > + >=20 > +phy_exit: >=20 > + if (EFI_ERROR (Status)) { >=20 > + DEBUG ((DEBUG_ERROR, "GbeMdiGetLanPhyRevision failed to read > Revision and Model Number from PHY Identifier 2. Status: %r\n", Status)); >=20 > + GbeMdiReleaseMdio (GbeBar); >=20 > + return Status; >=20 > + } >=20 > + >=20 > + // >=20 > + // Switch back to normal MDIO frequency access >=20 > + // >=20 > + Status =3D GbeMdiWrite (GbeBar, B_PHY_MDI_PHY_ADDRESS_01, > MDI_REG_SHIFT (R_PHY_MDI_PAGE_769_REGISETER_16_CMC), > (~B_PHY_MDI_PAGE_769_REGISETER_16_CMC_MDIO_FREQ_ACCESS) & > (BIT13 | BIT8 | BIT7)); >=20 > + if (EFI_ERROR (Status)) { >=20 > + DEBUG ((DEBUG_ERROR, "GbeMdiGetLanPhyRevision failed to disable > slow MDIO mode. Status: %r\n", Status)); >=20 > + } >=20 > + >=20 > + GbeMdiReleaseMdio (GbeBar); >=20 > + >=20 > + return Status; >=20 > +} >=20 > + >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Gbe/LibraryPrivate/PeiDxeSmmG > beMdiLib/PeiDxeSmmGbeMdiLib.inf > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Gbe/LibraryPrivate/PeiDxeSmmG > beMdiLib/PeiDxeSmmGbeMdiLib.inf > new file mode 100644 > index 0000000000..99a01177f6 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Gbe/LibraryPrivate/PeiDxeSmmG > beMdiLib/PeiDxeSmmGbeMdiLib.inf > @@ -0,0 +1,34 @@ > +## @file >=20 > +# Gbe MDI Library. >=20 > +# >=20 > +# All function in this library is available for PEI, DXE, and SMM, >=20 > +# But do not support UEFI RUNTIME environment call. >=20 > +# >=20 > +# Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > +# SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +# >=20 > +## >=20 > + >=20 > + >=20 > +[Defines] >=20 > +INF_VERSION =3D 0x00010017 >=20 > +BASE_NAME =3D PeiDxeSmmGbeMdiLib >=20 > +FILE_GUID =3D 0360E6F6-892A-4852-BF98-15C0D30D8A48 >=20 > +VERSION_STRING =3D 1.0 >=20 > +MODULE_TYPE =3D BASE >=20 > +LIBRARY_CLASS =3D GbeMdiLib >=20 > + >=20 > + >=20 > +[LibraryClasses] >=20 > +BaseLib >=20 > +IoLib >=20 > +DebugLib >=20 > +TimerLib >=20 > + >=20 > +[Packages] >=20 > +MdePkg/MdePkg.dec >=20 > +TigerlakeSiliconPkg/SiPkg.dec >=20 > + >=20 > + >=20 > +[Sources] >=20 > +GbeMdiLib.c >=20 > -- > 2.24.0.windows.2