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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Nate DeSimone > -----Original Message----- > From: Luo, Heng > Sent: Sunday, January 31, 2021 5:37 PM > To: devel@edk2.groups.io > Cc: Chaganty, Rangasai V ; Desimone, > Nathaniel L > Subject: [PATCH 33/40] TigerlakeSiliconPkg/Pch: Add Pch private library > instances >=20 > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3171 >=20 > Adds the following files: > * Pch/LibraryPrivate/BaseSiScheduleResetLib > * Pch/LibraryPrivate/SmmPchPrivateLib >=20 > Cc: Sai Chaganty > Cc: Nate DeSimone > Signed-off-by: Heng Luo > --- >=20 > Silicon/Intel/TigerlakeSiliconPkg/Pch/LibraryPrivate/BaseSiScheduleResetL= ib/ > BaseSiScheduleResetLib.c | 171 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++++++++++++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/Pch/LibraryPrivate/BaseSiScheduleResetL= ib/ > BaseSiScheduleResetLib.inf | 37 > +++++++++++++++++++++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/Pch/LibraryPrivate/SmmPchPrivateLib/Smm > PchPrivateLib.c | 57 > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/Pch/LibraryPrivate/SmmPchPrivateLib/Smm > PchPrivateLib.inf | 31 +++++++++++++++++++++++++++++++ > 4 files changed, 296 insertions(+) >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Pch/LibraryPrivate/BaseSiScheduleRese= tLi > b/BaseSiScheduleResetLib.c > b/Silicon/Intel/TigerlakeSiliconPkg/Pch/LibraryPrivate/BaseSiScheduleRese= tLi > b/BaseSiScheduleResetLib.c > new file mode 100644 > index 0000000000..1880244a01 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/Pch/LibraryPrivate/BaseSiScheduleRese= tLi > b/BaseSiScheduleResetLib.c > @@ -0,0 +1,171 @@ > +/** @file >=20 > + Reset scheduling library services >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +/** >=20 > + This function returns SiScheduleResetHob for library use >=20 > +**/ >=20 > +STATIC >=20 > +SI_SCHEDULE_RESET_HOB * >=20 > +SiScheduleGetResetData ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + STATIC SI_SCHEDULE_RESET_HOB *SiScheduleResetHob =3D NULL; >=20 > + SI_SCHEDULE_RESET_HOB *SiScheduleResetHobTemp; >=20 > + VOID *HobPtr; >=20 > + >=20 > + if (SiScheduleResetHob !=3D NULL) { >=20 > + return SiScheduleResetHob; >=20 > + } >=20 > + >=20 > + HobPtr =3D GetFirstGuidHob (&gSiScheduleResetHobGuid); >=20 > + if (HobPtr =3D=3D NULL) { >=20 > + SiScheduleResetHobTemp =3D BuildGuidHob (&gSiScheduleResetHobGuid, > sizeof (SI_SCHEDULE_RESET_HOB)); >=20 > + if (SiScheduleResetHobTemp =3D=3D NULL) { >=20 > + ASSERT (FALSE); >=20 > + return SiScheduleResetHobTemp; >=20 > + } >=20 > + SiScheduleResetHobTemp->ResetType =3D 0xFF; >=20 > + DEBUG ((DEBUG_INFO, "SiScheduleResetSetType : Init > SiScheduleResetHob\n")); >=20 > + } else { >=20 > + SiScheduleResetHobTemp =3D (SI_SCHEDULE_RESET_HOB*) > GET_GUID_HOB_DATA (HobPtr); >=20 > + } >=20 > + SiScheduleResetHob =3D SiScheduleResetHobTemp; >=20 > + return SiScheduleResetHobTemp; >=20 > +} >=20 > + >=20 > +/** >=20 > + This function updates the reset information in SiScheduleResetHob >=20 > + @param[in] ResetType UEFI defined reset type. >=20 > + @param[in] ResetData Optional element used to introduce a platf= orm > specific reset. >=20 > + The exact type of the reset is defined by= the EFI_GUID that > follows >=20 > + the Null-terminated Unicode string. >=20 > +**/ >=20 > +VOID >=20 > +SiScheduleResetSetType ( >=20 > + IN EFI_RESET_TYPE ResetType, >=20 > + IN PCH_RESET_DATA *ResetData OPTIONAL >=20 > + ) >=20 > +{ >=20 > + SI_SCHEDULE_RESET_HOB *SiScheduleResetHob; >=20 > + if (ResetType > EfiResetPlatformSpecific) { >=20 > + DEBUG ((DEBUG_INFO, "Unsupported Reset Type Requested\n")); >=20 > + return; >=20 > + } >=20 > + SiScheduleResetHob =3D SiScheduleGetResetData (); >=20 > + if (SiScheduleResetHob =3D=3D NULL) { >=20 > + return; >=20 > + } >=20 > + DEBUG ((DEBUG_INFO, "SiScheduleResetSetType : Current Reset Type =3D > 0x%x\n", SiScheduleResetHob->ResetType)); >=20 > + if (SiScheduleResetHob->ResetType =3D=3D ResetType) { >=20 > + DEBUG ((DEBUG_INFO, "Current Reset Type is same as requested Reset > Type\n")); >=20 > + return; >=20 > + } >=20 > + if (SiScheduleResetHob->ResetType =3D=3D 0xFF) { >=20 > + // Init Reset Type to lowest ResetType >=20 > + SiScheduleResetHob->ResetType =3D EfiResetWarm; >=20 > + } >=20 > + // >=20 > + // ResetType Priority set as : ResetPlatformSpecific(3) > ResetShutdow= n(2) > > ResetCold(0) > ResetWarm(1) >=20 > + // >=20 > + switch (ResetType) { >=20 > + case EfiResetWarm: >=20 > + break; >=20 > + >=20 > + case EfiResetCold: >=20 > + if (SiScheduleResetHob->ResetType =3D=3D EfiResetWarm) { >=20 > + SiScheduleResetHob->ResetType =3D ResetType; >=20 > + } >=20 > + break; >=20 > + >=20 > + case EfiResetShutdown: >=20 > + if (SiScheduleResetHob->ResetType < ResetType) >=20 > + SiScheduleResetHob->ResetType =3D ResetType; >=20 > + break; >=20 > + >=20 > + case EfiResetPlatformSpecific: >=20 > + SiScheduleResetHob->ResetType =3D ResetType; >=20 > + SiScheduleResetHob->ResetData =3D *ResetData; >=20 > + break; >=20 > + } >=20 > + DEBUG ((DEBUG_INFO, "SiScheduleResetSetType : New Reset Type =3D > 0x%x\n", SiScheduleResetHob->ResetType)); >=20 > +} >=20 > + >=20 > +/** >=20 > + This function returns TRUE or FALSE depending on whether a reset is > required based on SiScheduleResetHob >=20 > + >=20 > + @retval BOOLEAN The function returns FALSE if no reset is re= quired >=20 > +**/ >=20 > +BOOLEAN >=20 > +SiScheduleResetIsRequired ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + VOID *HobPtr; >=20 > + >=20 > + HobPtr =3D NULL; >=20 > + HobPtr =3D GetFirstGuidHob (&gSiScheduleResetHobGuid); >=20 > + if (HobPtr =3D=3D NULL) { >=20 > + return FALSE; >=20 > + } >=20 > + return TRUE; >=20 > +} >=20 > + >=20 > +/** >=20 > + This function performs reset based on SiScheduleResetHob >=20 > + >=20 > + @retval BOOLEAN The function returns FALSE if no reset is re= quired >=20 > +**/ >=20 > +BOOLEAN >=20 > +SiScheduleResetPerformReset ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + UINTN DataSize; >=20 > + SI_SCHEDULE_RESET_HOB *SiScheduleResetHob; >=20 > + >=20 > + if (!SiScheduleResetIsRequired ()) { >=20 > + return FALSE; >=20 > + } >=20 > + SiScheduleResetHob =3D SiScheduleGetResetData (); >=20 > + >=20 > + if (SiScheduleResetHob =3D=3D NULL) { >=20 > + return TRUE; >=20 > + } >=20 > + >=20 > + DEBUG ((DEBUG_INFO, "SiScheduleResetPerformReset : Reset Type =3D > 0x%x\n", SiScheduleResetHob->ResetType)); >=20 > + switch (SiScheduleResetHob->ResetType) { >=20 > + case EfiResetWarm: >=20 > + ResetWarm (); >=20 > + break; >=20 > + >=20 > + case EfiResetCold: >=20 > + ResetCold (); >=20 > + break; >=20 > + >=20 > + case EfiResetShutdown: >=20 > + ResetShutdown (); >=20 > + break; >=20 > + >=20 > + case EfiResetPlatformSpecific: >=20 > + DataSize =3D sizeof (PCH_RESET_DATA); >=20 > + ResetPlatformSpecific (DataSize, &SiScheduleResetHob->ResetData); >=20 > + break; >=20 > + } >=20 > + // Code should never reach here >=20 > + ASSERT (FALSE); >=20 > + return TRUE; >=20 > +} >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Pch/LibraryPrivate/BaseSiScheduleRese= tLi > b/BaseSiScheduleResetLib.inf > b/Silicon/Intel/TigerlakeSiliconPkg/Pch/LibraryPrivate/BaseSiScheduleRese= tLi > b/BaseSiScheduleResetLib.inf > new file mode 100644 > index 0000000000..4363a752a9 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/Pch/LibraryPrivate/BaseSiScheduleRese= tLi > b/BaseSiScheduleResetLib.inf > @@ -0,0 +1,37 @@ > +## @file >=20 > +# Component description file for Si Reset Schedule Library. >=20 > +# >=20 > +# Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > +# SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +# >=20 > +## >=20 > + >=20 > +[Defines] >=20 > +INF_VERSION =3D 0x00010017 >=20 > +BASE_NAME =3D BaseSiScheduleResetLib >=20 > +FILE_GUID =3D E6F3D551-36C0-4737-80C7-47FC57593163 >=20 > +VERSION_STRING =3D 1.0 >=20 > +MODULE_TYPE =3D BASE >=20 > +LIBRARY_CLASS =3D SiScheduleResetLib >=20 > +# >=20 > +# The following information is for reference only and not required by th= e > build tools. >=20 > +# >=20 > +# VALID_ARCHITECTURES =3D IA32 X64 IPF >=20 > +# >=20 > + >=20 > +[LibraryClasses] >=20 > +BaseLib >=20 > +IoLib >=20 > +DebugLib >=20 > +HobLib >=20 > +ResetSystemLib >=20 > + >=20 > +[Packages] >=20 > +MdePkg/MdePkg.dec >=20 > +TigerlakeSiliconPkg/SiPkg.dec >=20 > + >=20 > +[Guids] >=20 > +gSiScheduleResetHobGuid >=20 > + >=20 > +[Sources] >=20 > +BaseSiScheduleResetLib.c >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Pch/LibraryPrivate/SmmPchPrivateLib/S= m > mPchPrivateLib.c > b/Silicon/Intel/TigerlakeSiliconPkg/Pch/LibraryPrivate/SmmPchPrivateLib/S= m > mPchPrivateLib.c > new file mode 100644 > index 0000000000..46cf735860 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/Pch/LibraryPrivate/SmmPchPrivateLib/S= m > mPchPrivateLib.c > @@ -0,0 +1,57 @@ > +/** @file >=20 > + PCH SMM private lib. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +/** >=20 > + Set InSmm.Sts bit >=20 > +**/ >=20 > +VOID >=20 > +PchSetInSmmSts ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + UINT32 Data32; >=20 > + >=20 > + >=20 > + /// >=20 > + /// Read memory location FED30880h OR with 00000001h, place the result > in EAX, >=20 > + /// and write data to lower 32 bits of MSR 1FEh (sample code available= ) >=20 > + /// >=20 > + Data32 =3D MmioRead32 (0xFED30880); >=20 > + AsmWriteMsr32 (MSR_SPCL_CHIPSET_USAGE, Data32 | BIT0); >=20 > + /// >=20 > + /// Read FED30880h back to ensure the setting went through. >=20 > + /// >=20 > + Data32 =3D MmioRead32 (0xFED30880); >=20 > +} >=20 > + >=20 > +/** >=20 > + Clear InSmm.Sts bit >=20 > +**/ >=20 > +VOID >=20 > +PchClearInSmmSts ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + UINT32 Data32; >=20 > + >=20 > + /// >=20 > + /// Read memory location FED30880h AND with FFFFFFFEh, place the resul= t > in EAX, >=20 > + /// and write data to lower 32 bits of MSR 1FEh (sample code available= ) >=20 > + /// >=20 > + Data32 =3D MmioRead32 (0xFED30880); >=20 > + AsmWriteMsr32 (MSR_SPCL_CHIPSET_USAGE, Data32 & (UINT32) > (~BIT0)); >=20 > + /// >=20 > + /// Read FED30880h back to ensure the setting went through. >=20 > + /// >=20 > + Data32 =3D MmioRead32 (0xFED30880); >=20 > +} >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Pch/LibraryPrivate/SmmPchPrivateLib/S= m > mPchPrivateLib.inf > b/Silicon/Intel/TigerlakeSiliconPkg/Pch/LibraryPrivate/SmmPchPrivateLib/S= m > mPchPrivateLib.inf > new file mode 100644 > index 0000000000..6d4c3a5729 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/Pch/LibraryPrivate/SmmPchPrivateLib/S= m > mPchPrivateLib.inf > @@ -0,0 +1,31 @@ > +## @file >=20 > +# PCH SMM private lib. >=20 > +# >=20 > +# Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > +# SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +# >=20 > +## >=20 > + >=20 > + >=20 > +[Defines] >=20 > +INF_VERSION =3D 0x00010017 >=20 > +BASE_NAME =3D SmmPchPrivateLib >=20 > +FILE_GUID =3D FE6495FB-7AA9-4A24-BF3E-4698F7BCE0EE >=20 > +VERSION_STRING =3D 1.0 >=20 > +MODULE_TYPE =3D DXE_SMM_DRIVER >=20 > +LIBRARY_CLASS =3D SmmPchPrivateLib >=20 > + >=20 > + >=20 > +[LibraryClasses] >=20 > +BaseLib >=20 > +IoLib >=20 > +DebugLib >=20 > + >=20 > + >=20 > +[Packages] >=20 > +MdePkg/MdePkg.dec >=20 > +TigerlakeSiliconPkg/SiPkg.dec >=20 > + >=20 > + >=20 > +[Sources] >=20 > +SmmPchPrivateLib.c >=20 > -- > 2.24.0.windows.2