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X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN8PR11MB3843 Return-Path: nathaniel.l.desimone@intel.com X-OriginatorOrg: intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Nate DeSimone > -----Original Message----- > From: Luo, Heng > Sent: Sunday, January 31, 2021 5:37 PM > To: devel@edk2.groups.io > Cc: Chaganty, Rangasai V ; Desimone, > Nathaniel L > Subject: [PATCH 32/40] TigerlakeSiliconPkg/Pch: Add Pch common library > instances >=20 > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3171 >=20 > Adds the following files: > * Pch/Library/BasePchPciBdfLib > * Pch/Library/BaseResetSystemLib > * Pch/Library/DxePchPolicyLib > * Pch/Library/PeiDxeSmmPchCycleDecodingLib > * Pch/Library/PeiDxeSmmPchInfoLib >=20 > Cc: Sai Chaganty > Cc: Nate DeSimone > Signed-off-by: Heng Luo > --- >=20 > Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/BasePchPciBdfLib/BasePchPci= Bd > fLib.inf | 33 +++++++++++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/BasePchPciBdfLib/PchPciBdfL= ib. > c | 1092 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/BaseResetSystemLib/BaseRese= t > SystemLib.c | 158 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/BaseResetSystemLib/BaseRese= t > SystemLib.inf | 38 +++++++++++++++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/DxePchPolicyLib/DxePchPolic= yLi > b.c | 198 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/DxePchPolicyLib/DxePchPolic= yLi > b.inf | 43 ++++++++++++++++++++++++++++++++++= + >=20 > Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/PeiDxeSmmPchCycleDecodingLi > b/PchCycleDecodingLib.c | 587 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/PeiDxeSmmPchCycleDecodingLi > b/PeiDxeSmmPchCycleDecodingLib.inf | 42 > ++++++++++++++++++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib/PchInfo > Lib.c | 127 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib/PchInfo > LibPrivate.h | 58 > +++++++++++++++++++++++++++++++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib/PchInfo > LibTgl.c | 715 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib/PeiDxeS > mmPchInfoLibTgl.inf | 43 > +++++++++++++++++++++++++++++++++++ > 12 files changed, 3134 insertions(+) >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/BasePchPciBdfLib/BasePchP= ci > BdfLib.inf > b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/BasePchPciBdfLib/BasePchP= ci > BdfLib.inf > new file mode 100644 > index 0000000000..4f4096a409 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/BasePchPciBdfLib/BasePchP= ci > BdfLib.inf > @@ -0,0 +1,33 @@ > +## @file >=20 > +# PCH PCIe Bus Device Function Library. >=20 > +# >=20 > +# All functions from this library are available in PEI, DXE, and SMM, >=20 > +# But do not support UEFI RUNTIME environment call. >=20 > +# >=20 > +# Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > +# SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +# >=20 > +## >=20 > + >=20 > +[Defines] >=20 > +INF_VERSION =3D 0x00010017 >=20 > +BASE_NAME =3D PeiDxeSmmPchPciBdfLib >=20 > +FILE_GUID =3D ED0C4241-40FA-4A74-B061-2E45E7AAD7BA >=20 > +VERSION_STRING =3D 1.0 >=20 > +MODULE_TYPE =3D BASE >=20 > +LIBRARY_CLASS =3D PchPciBdfLib >=20 > + >=20 > +[LibraryClasses] >=20 > +BaseLib >=20 > +IoLib >=20 > +DebugLib >=20 > +PciSegmentLib >=20 > +PchInfoLib >=20 > +PchPcieRpLib >=20 > + >=20 > +[Packages] >=20 > +MdePkg/MdePkg.dec >=20 > +TigerlakeSiliconPkg/SiPkg.dec >=20 > + >=20 > +[Sources] >=20 > +PchPciBdfLib.c >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/BasePchPciBdfLib/PchPciBd= fLi > b.c > b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/BasePchPciBdfLib/PchPciBd= fLi > b.c > new file mode 100644 > index 0000000000..0db8cea4bb > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/BasePchPciBdfLib/PchPciBd= fLi > b.c > @@ -0,0 +1,1092 @@ > +/** @file >=20 > + PCH PCIe Bus Device Function Library. >=20 > + All functions from this library are available in PEI, DXE, and SMM, >=20 > + But do not support UEFI RUNTIME environment call. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +/** >=20 > + Check if a Device is present for PCH FRU >=20 > + If the data is defined for PCH RFU return it >=20 > + If the data is not defined (Device is NOT present) assert. >=20 > + >=20 > + @param[in] DataToCheck Device or Function number to check >=20 > + >=20 > + @retval Device or Function number value if defined for PCH FRU >=20 > + 0xFF if not present in PCH FRU >=20 > +**/ >=20 > +UINT8 >=20 > +CheckAndReturn ( >=20 > + UINT8 DataToCheck >=20 > + ) >=20 > +{ >=20 > + if (DataToCheck =3D=3D NOT_PRESENT) { >=20 > + ASSERT (FALSE); >=20 > + } >=20 > + return DataToCheck; >=20 > +} >=20 > + >=20 > +/** >=20 > + Get eSPI controller address that can be passed to the PCI Segment Libr= ary > functions. >=20 > + >=20 > + @retval eSPI controller address in PCI Segment Library representation >=20 > +**/ >=20 > +UINT64 >=20 > +EspiPciCfgBase ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + ASSERT (PCI_DEVICE_NUMBER_PCH_ESPI !=3D NOT_PRESENT); >=20 > + >=20 > + return PCI_SEGMENT_LIB_ADDRESS ( >=20 > + DEFAULT_PCI_SEGMENT_NUMBER_PCH, >=20 > + DEFAULT_PCI_BUS_NUMBER_PCH, >=20 > + PCI_DEVICE_NUMBER_PCH_ESPI, >=20 > + PCI_FUNCTION_NUMBER_PCH_ESPI, >=20 > + 0 >=20 > + ); >=20 > +} >=20 > + >=20 > +/** >=20 > + Returns Gigabit Ethernet PCI Device Number >=20 > + >=20 > + @retval GbE device number >=20 > +**/ >=20 > +UINT8 >=20 > +GbeDevNumber ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return CheckAndReturn (PCI_DEVICE_NUMBER_GBE); >=20 > +} >=20 > + >=20 > +/** >=20 > + Returns Gigabit Ethernet PCI Function Number >=20 > + >=20 > + @retval GbE function number >=20 > +**/ >=20 > +UINT8 >=20 > +GbeFuncNumber ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return CheckAndReturn (PCI_FUNCTION_NUMBER_GBE); >=20 > +} >=20 > + >=20 > +/** >=20 > + Get GbE controller address that can be passed to the PCI Segment Libra= ry > functions. >=20 > + >=20 > + @retval GbE controller address in PCI Segment Library representation >=20 > +**/ >=20 > +UINT64 >=20 > +GbePciCfgBase ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return PCI_SEGMENT_LIB_ADDRESS ( >=20 > + DEFAULT_PCI_SEGMENT_NUMBER_PCH, >=20 > + DEFAULT_PCI_BUS_NUMBER_PCH, >=20 > + GbeDevNumber (), >=20 > + GbeFuncNumber (), >=20 > + 0 >=20 > + ); >=20 > +} >=20 > + >=20 > +/** >=20 > + Get HDA PCI device number >=20 > + >=20 > + @retval PCI dev number >=20 > +**/ >=20 > +UINT8 >=20 > +HdaDevNumber ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_HDA); >=20 > +} >=20 > + >=20 > +/** >=20 > + Get HDA PCI function number >=20 > + >=20 > + @retval PCI fun number >=20 > +**/ >=20 > +UINT8 >=20 > +HdaFuncNumber ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return CheckAndReturn (PCI_FUNCTION_NUMBER_PCH_HDA); >=20 > +} >=20 > + >=20 > +/** >=20 > + Get HDA controller address that can be passed to the PCI Segment Libra= ry > functions. >=20 > + >=20 > + @retval HDA controller address in PCI Segment Library representation >=20 > +**/ >=20 > +UINT64 >=20 > +HdaPciCfgBase ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return PCI_SEGMENT_LIB_ADDRESS ( >=20 > + DEFAULT_PCI_SEGMENT_NUMBER_PCH, >=20 > + DEFAULT_PCI_BUS_NUMBER_PCH, >=20 > + HdaDevNumber (), >=20 > + HdaFuncNumber (), >=20 > + 0 >=20 > + ); >=20 > +} >=20 > + >=20 > +/** >=20 > + Get P2SB PCI device number >=20 > + >=20 > + @retval PCI dev number >=20 > +**/ >=20 > +UINT8 >=20 > +P2sbDevNumber ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_P2SB); >=20 > +} >=20 > + >=20 > +/** >=20 > + Get P2SB PCI function number >=20 > + >=20 > + @retval PCI fun number >=20 > +**/ >=20 > +UINT8 >=20 > +P2sbFuncNumber ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return CheckAndReturn (PCI_FUNCTION_NUMBER_PCH_P2SB); >=20 > +} >=20 > + >=20 > +/** >=20 > + Get P2SB controller address that can be passed to the PCI Segment Libr= ary > functions. >=20 > + >=20 > + @retval P2SB controller address in PCI Segment Library representation >=20 > +**/ >=20 > +UINT64 >=20 > +P2sbPciCfgBase ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return PCI_SEGMENT_LIB_ADDRESS ( >=20 > + DEFAULT_PCI_SEGMENT_NUMBER_PCH, >=20 > + DEFAULT_PCI_BUS_NUMBER_PCH, >=20 > + P2sbDevNumber (), >=20 > + P2sbFuncNumber (), >=20 > + 0 >=20 > + ); >=20 > +} >=20 > + >=20 > +/** >=20 > + Returns PCH SPI Device number >=20 > + >=20 > + @retval UINT8 PCH SPI Device number >=20 > +**/ >=20 > +UINT8 >=20 > +SpiDevNumber ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_SPI); >=20 > +} >=20 > + >=20 > +/** >=20 > + Returns PCH SPI Function number >=20 > + >=20 > + @retval UINT8 PCH SPI Function number >=20 > +**/ >=20 > +UINT8 >=20 > +SpiFuncNumber ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return CheckAndReturn (PCI_FUNCTION_NUMBER_PCH_SPI); >=20 > +} >=20 > + >=20 > +/** >=20 > + Returns PCH SPI PCI Config Space base address >=20 > + >=20 > + @retval UINT64 PCH SPI Config Space base address >=20 > +**/ >=20 > +UINT64 >=20 > +SpiPciCfgBase ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return PCI_SEGMENT_LIB_ADDRESS ( >=20 > + DEFAULT_PCI_SEGMENT_NUMBER_PCH, >=20 > + DEFAULT_PCI_BUS_NUMBER_PCH, >=20 > + SpiDevNumber (), >=20 > + SpiFuncNumber (), >=20 > + 0 >=20 > + ); >=20 > +} >=20 > + >=20 > +/** >=20 > + Get XHCI controller PCIe Device Number >=20 > + >=20 > + @retval XHCI controller PCIe Device Number >=20 > +**/ >=20 > +UINT8 >=20 > +PchXhciDevNumber ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_XHCI); >=20 > +} >=20 > + >=20 > +/** >=20 > + Get XHCI controller PCIe Function Number >=20 > + >=20 > + @retval XHCI controller PCIe Function Number >=20 > +**/ >=20 > +UINT8 >=20 > +PchXhciFuncNumber ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return CheckAndReturn (PCI_FUNCTION_NUMBER_PCH_XHCI); >=20 > +} >=20 > + >=20 > +/** >=20 > + Get XHCI controller address that can be passed to the PCI Segment Libr= ary > functions. >=20 > + >=20 > + @retval XHCI controller address in PCI Segment Library representation >=20 > +**/ >=20 > +UINT64 >=20 > +PchXhciPciCfgBase ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return PCI_SEGMENT_LIB_ADDRESS ( >=20 > + DEFAULT_PCI_SEGMENT_NUMBER_PCH, >=20 > + DEFAULT_PCI_BUS_NUMBER_PCH, >=20 > + PchXhciDevNumber (), >=20 > + PchXhciFuncNumber (), >=20 > + 0 >=20 > + ); >=20 > +} >=20 > + >=20 > +/** >=20 > + Get XDCI controller PCIe Device Number >=20 > + >=20 > + @retval XDCI controller PCIe Device Number >=20 > +**/ >=20 > +UINT8 >=20 > +PchXdciDevNumber ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_XDCI); >=20 > +} >=20 > + >=20 > +/** >=20 > + Get XDCI controller PCIe Function Number >=20 > + >=20 > + @retval XDCI controller PCIe Function Number >=20 > +**/ >=20 > +UINT8 >=20 > +PchXdciFuncNumber ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return CheckAndReturn (PCI_FUNCTION_NUMBER_PCH_XDCI); >=20 > +} >=20 > + >=20 > +/** >=20 > + Get XDCI controller address that can be passed to the PCI Segment Libr= ary > functions. >=20 > + >=20 > + @retval XDCI controller address in PCI Segment Library representation >=20 > +**/ >=20 > +UINT64 >=20 > +PchXdciPciCfgBase ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return PCI_SEGMENT_LIB_ADDRESS ( >=20 > + DEFAULT_PCI_SEGMENT_NUMBER_PCH, >=20 > + DEFAULT_PCI_BUS_NUMBER_PCH, >=20 > + PchXdciDevNumber (), >=20 > + PchXdciFuncNumber (), >=20 > + 0 >=20 > + ); >=20 > +} >=20 > + >=20 > +/** >=20 > + Return Smbus Device Number >=20 > + >=20 > + @retval Smbus Device Number >=20 > +**/ >=20 > +UINT8 >=20 > +SmbusDevNumber ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_SMBUS); >=20 > +} >=20 > + >=20 > +/** >=20 > + Return Smbus Function Number >=20 > + >=20 > + @retval Smbus Function Number >=20 > +**/ >=20 > +UINT8 >=20 > +SmbusFuncNumber ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return CheckAndReturn (PCI_FUNCTION_NUMBER_PCH_SMBUS); >=20 > +} >=20 > + >=20 > +/** >=20 > + Get SMBUS controller address that can be passed to the PCI Segment > Library functions. >=20 > + >=20 > + @retval SMBUS controller address in PCI Segment Library representation >=20 > +**/ >=20 > +UINT64 >=20 > +SmbusPciCfgBase ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return PCI_SEGMENT_LIB_ADDRESS ( >=20 > + DEFAULT_PCI_SEGMENT_NUMBER_PCH, >=20 > + DEFAULT_PCI_BUS_NUMBER_PCH, >=20 > + SmbusDevNumber (), >=20 > + SmbusFuncNumber (), >=20 > + 0 >=20 > + ); >=20 > +} >=20 > + >=20 > +/** >=20 > + Return DMA Smbus Device Number >=20 > + >=20 > + @retval DMA Smbus Device Number >=20 > +**/ >=20 > +UINT8 >=20 > +SmbusDmaDevNumber ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_DMA_SMBUS); >=20 > +} >=20 > + >=20 > +/** >=20 > + Return DMA Smbus Function Number >=20 > + >=20 > + @retval DMA Smbus Function Number >=20 > +**/ >=20 > +UINT8 >=20 > +SmbusDmaFuncNumber ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return CheckAndReturn (PCI_FUNCTION_NUMBER_PCH_DMA_SMBUS); >=20 > +} >=20 > + >=20 > +/** >=20 > + Get DMA SMBUS controller address that can be passed to the PCI Segment > Library functions. >=20 > + >=20 > + @retval DMA SMBUS controller address in PCI Segment Library > representation >=20 > +**/ >=20 > +UINT64 >=20 > +SmbusDmaPciCfgBase ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return PCI_SEGMENT_LIB_ADDRESS ( >=20 > + DEFAULT_PCI_SEGMENT_NUMBER_PCH, >=20 > + DEFAULT_PCI_BUS_NUMBER_PCH, >=20 > + SmbusDmaDevNumber (), >=20 > + SmbusDmaFuncNumber (), >=20 > + 0 >=20 > + ); >=20 > +} >=20 > + >=20 > +/** >=20 > + Get SATA controller PCIe Device Number >=20 > + >=20 > + @param[in] SataCtrlIndex SATA controller index >=20 > + >=20 > + @retval SATA controller PCIe Device Number >=20 > +**/ >=20 > +UINT8 >=20 > +SataDevNumber ( >=20 > + IN UINT32 SataCtrlIndex >=20 > + ) >=20 > +{ >=20 > + ASSERT (SataCtrlIndex < MAX_SATA_CONTROLLER); >=20 > + >=20 > + if (SataCtrlIndex =3D=3D 0) { >=20 > + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_SATA_1); >=20 > + } else if (SataCtrlIndex =3D=3D 1) { >=20 > + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_SATA_2); >=20 > + } else if (SataCtrlIndex =3D=3D 2) { >=20 > + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_SATA_3); >=20 > + } else { >=20 > + ASSERT (FALSE); >=20 > + return 0xFF; >=20 > + } >=20 > +} >=20 > + >=20 > +/** >=20 > + Get SATA controller PCIe Function Number >=20 > + >=20 > + @param[in] SataCtrlIndex SATA controller index >=20 > + >=20 > + @retval SATA controller PCIe Function Number >=20 > +**/ >=20 > +UINT8 >=20 > +SataFuncNumber ( >=20 > + IN UINT32 SataCtrlIndex >=20 > + ) >=20 > +{ >=20 > + ASSERT (SataCtrlIndex < MAX_SATA_CONTROLLER); >=20 > + >=20 > + if (SataCtrlIndex =3D=3D 0) { >=20 > + return CheckAndReturn (PCI_FUNCTION_NUMBER_PCH_SATA_1); >=20 > + } else if (SataCtrlIndex =3D=3D 1) { >=20 > + return CheckAndReturn (PCI_FUNCTION_NUMBER_PCH_SATA_2); >=20 > + } else if (SataCtrlIndex =3D=3D 2) { >=20 > + return CheckAndReturn (PCI_FUNCTION_NUMBER_PCH_SATA_3); >=20 > + } else { >=20 > + ASSERT (FALSE); >=20 > + return 0xFF; >=20 > + } >=20 > +} >=20 > + >=20 > +/** >=20 > + Get SATA controller address that can be passed to the PCI Segment Libr= ary > functions. >=20 > + >=20 > + @param[in] SataCtrlIndex SATA controller index >=20 > + >=20 > + @retval SATA controller address in PCI Segment Library representation >=20 > +**/ >=20 > +UINT64 >=20 > +SataPciCfgBase ( >=20 > + IN UINT32 SataCtrlIndex >=20 > + ) >=20 > +{ >=20 > + return PCI_SEGMENT_LIB_ADDRESS ( >=20 > + DEFAULT_PCI_SEGMENT_NUMBER_PCH, >=20 > + DEFAULT_PCI_BUS_NUMBER_PCH, >=20 > + SataDevNumber (SataCtrlIndex), >=20 > + SataFuncNumber (SataCtrlIndex), >=20 > + 0 >=20 > + ); >=20 > +} >=20 > + >=20 > +/** >=20 > + Get LPC controller PCIe Device Number >=20 > + >=20 > + @retval LPC controller PCIe Device Number >=20 > +**/ >=20 > +UINT8 >=20 > +LpcDevNumber ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_LPC); >=20 > +} >=20 > + >=20 > +/** >=20 > + Get LPC controller PCIe Function Number >=20 > + >=20 > + @retval LPC controller PCIe Function Number >=20 > +**/ >=20 > +UINT8 >=20 > +LpcFuncNumber ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return CheckAndReturn (PCI_FUNCTION_NUMBER_PCH_LPC); >=20 > +} >=20 > + >=20 > +/** >=20 > + Returns PCH LPC device PCI base address. >=20 > + >=20 > + @retval PCH LPC PCI base address. >=20 > +**/ >=20 > +UINT64 >=20 > +LpcPciCfgBase ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return PCI_SEGMENT_LIB_ADDRESS ( >=20 > + DEFAULT_PCI_SEGMENT_NUMBER_PCH, >=20 > + DEFAULT_PCI_BUS_NUMBER_PCH, >=20 > + LpcDevNumber (), >=20 > + LpcFuncNumber (), >=20 > + 0 >=20 > + ); >=20 > +} >=20 > + >=20 > +/** >=20 > + Get Thermal Device PCIe Device Number >=20 > + >=20 > + @retval Thermal Device PCIe Device Number >=20 > +**/ >=20 > +UINT8 >=20 > +ThermalDevNumber ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_THERMAL); >=20 > +} >=20 > + >=20 > +/** >=20 > + Get Thermal Device PCIe Function Number >=20 > + >=20 > + @retval Thermal Device PCIe Function Number >=20 > +**/ >=20 > +UINT8 >=20 > +ThermalFuncNumber ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return CheckAndReturn (PCI_FUNCTION_NUMBER_PCH_THERMAL); >=20 > +} >=20 > + >=20 > +/** >=20 > + Returns Thermal Device PCI base address. >=20 > + >=20 > + @retval Thermal Device PCI base address. >=20 > +**/ >=20 > +UINT64 >=20 > +ThermalPciCfgBase ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return PCI_SEGMENT_LIB_ADDRESS ( >=20 > + DEFAULT_PCI_SEGMENT_NUMBER_PCH, >=20 > + DEFAULT_PCI_BUS_NUMBER_PCH, >=20 > + ThermalDevNumber (), >=20 > + ThermalFuncNumber (), >=20 > + 0 >=20 > + ); >=20 > +} >=20 > + >=20 > +/** >=20 > + Get Serial IO I2C controller PCIe Device Number >=20 > + >=20 > + @param[in] I2cNumber Serial IO I2C controller index >=20 > + >=20 > + @retval Serial IO I2C controller PCIe Device Number >=20 > +**/ >=20 > +UINT8 >=20 > +SerialIoI2cDevNumber ( >=20 > + IN UINT8 I2cNumber >=20 > + ) >=20 > +{ >=20 > + if (GetPchMaxSerialIoI2cControllersNum () <=3D I2cNumber) { >=20 > + ASSERT (FALSE); >=20 > + return 0xFF; >=20 > + } >=20 > + switch (I2cNumber) { >=20 > + case 0: >=20 > + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C0); >=20 > + case 1: >=20 > + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C1); >=20 > + case 2: >=20 > + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C2); >=20 > + case 3: >=20 > + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C3); >=20 > + case 4: >=20 > + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C4); >=20 > + case 5: >=20 > + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C5); >=20 > + case 6: >=20 > + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C6); >=20 > + case 7: >=20 > + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C7); >=20 > + default: >=20 > + ASSERT (FALSE); >=20 > + return 0xFF; >=20 > + } >=20 > +} >=20 > + >=20 > +/** >=20 > + Get Serial IO I2C controller PCIe Function Number >=20 > + >=20 > + @param[in] I2cNumber Serial IO I2C controller index >=20 > + >=20 > + @retval Serial IO I2C controller PCIe Function Number >=20 > +**/ >=20 > +UINT8 >=20 > +SerialIoI2cFuncNumber ( >=20 > + IN UINT8 I2cNumber >=20 > + ) >=20 > +{ >=20 > + if (GetPchMaxSerialIoI2cControllersNum () <=3D I2cNumber) { >=20 > + ASSERT (FALSE); >=20 > + return 0xFF; >=20 > + } >=20 > + switch (I2cNumber) { >=20 > + case 0: >=20 > + return CheckAndReturn > (PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C0); >=20 > + case 1: >=20 > + return CheckAndReturn > (PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C1); >=20 > + case 2: >=20 > + return CheckAndReturn > (PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C2); >=20 > + case 3: >=20 > + return CheckAndReturn > (PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C3); >=20 > + case 4: >=20 > + return CheckAndReturn > (PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C4); >=20 > + case 5: >=20 > + return CheckAndReturn > (PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C5); >=20 > + case 6: >=20 > + return CheckAndReturn > (PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C6); >=20 > + case 7: >=20 > + return CheckAndReturn > (PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C7); >=20 > + default: >=20 > + ASSERT (FALSE); >=20 > + return 0xFF; >=20 > + } >=20 > +} >=20 > + >=20 > +/** >=20 > + Get Serial IO I2C controller address that can be passed to the PCI Seg= ment > Library functions. >=20 > + >=20 > + @param[in] I2cNumber Serial IO I2C controller index >=20 > + >=20 > + @retval Serial IO I2C controller address in PCI Segment Library > representation >=20 > +**/ >=20 > +UINT64 >=20 > +SerialIoI2cPciCfgBase ( >=20 > + IN UINT8 I2cNumber >=20 > + ) >=20 > +{ >=20 > + return PCI_SEGMENT_LIB_ADDRESS ( >=20 > + DEFAULT_PCI_SEGMENT_NUMBER_PCH, >=20 > + DEFAULT_PCI_BUS_NUMBER_PCH, >=20 > + SerialIoI2cDevNumber (I2cNumber), >=20 > + SerialIoI2cFuncNumber (I2cNumber), >=20 > + 0 >=20 > + ); >=20 > +} >=20 > + >=20 > +/** >=20 > + Get Serial IO SPI controller PCIe Device Number >=20 > + >=20 > + @param[in] I2cNumber Serial IO SPI controller index >=20 > + >=20 > + @retval Serial IO SPI controller PCIe Device Number >=20 > +**/ >=20 > +UINT8 >=20 > +SerialIoSpiDevNumber ( >=20 > + IN UINT8 SpiNumber >=20 > + ) >=20 > +{ >=20 > + if (GetPchMaxSerialIoSpiControllersNum () <=3D SpiNumber) { >=20 > + ASSERT (FALSE); >=20 > + return 0xFF; >=20 > + } >=20 > + >=20 > + switch (SpiNumber) { >=20 > + case 0: >=20 > + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_SERIAL_IO_SPI0); >=20 > + case 1: >=20 > + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_SERIAL_IO_SPI1); >=20 > + case 2: >=20 > + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_SERIAL_IO_SPI2); >=20 > + case 3: >=20 > + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_SERIAL_IO_SPI3); >=20 > + case 4: >=20 > + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_SERIAL_IO_SPI4); >=20 > + case 5: >=20 > + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_SERIAL_IO_SPI5); >=20 > + case 6: >=20 > + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_SERIAL_IO_SPI6); >=20 > + default: >=20 > + ASSERT (FALSE); >=20 > + return 0xFF; >=20 > + } >=20 > +} >=20 > + >=20 > +/** >=20 > + Get Serial IO SPI controller PCIe Function Number >=20 > + >=20 > + @param[in] SpiNumber Serial IO SPI controller index >=20 > + >=20 > + @retval Serial IO SPI controller PCIe Function Number >=20 > +**/ >=20 > +UINT8 >=20 > +SerialIoSpiFuncNumber ( >=20 > + IN UINT8 SpiNumber >=20 > + ) >=20 > +{ >=20 > + if (GetPchMaxSerialIoSpiControllersNum () <=3D SpiNumber) { >=20 > + ASSERT (FALSE); >=20 > + return 0xFF; >=20 > + } >=20 > + >=20 > + switch (SpiNumber) { >=20 > + case 0: >=20 > + return CheckAndReturn > (PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_SPI0); >=20 > + case 1: >=20 > + return CheckAndReturn > (PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_SPI1); >=20 > + case 2: >=20 > + return CheckAndReturn > (PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_SPI2); >=20 > + case 3: >=20 > + return CheckAndReturn > (PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_SPI3); >=20 > + case 4: >=20 > + return CheckAndReturn > (PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_SPI4); >=20 > + case 5: >=20 > + return CheckAndReturn > (PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_SPI5); >=20 > + case 6: >=20 > + return CheckAndReturn > (PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_SPI6); >=20 > + default: >=20 > + ASSERT (FALSE); >=20 > + return 0xFF; >=20 > + } >=20 > +} >=20 > + >=20 > +/** >=20 > + Get Serial IO SPI controller address that can be passed to the PCI Seg= ment > Library functions. >=20 > + >=20 > + @param[in] SpiNumber Serial IO SPI controller index >=20 > + >=20 > + @retval Serial IO SPI controller address in PCI Segment Library > representation >=20 > +**/ >=20 > +UINT64 >=20 > +SerialIoSpiPciCfgBase ( >=20 > + IN UINT8 SpiNumber >=20 > + ) >=20 > +{ >=20 > + return PCI_SEGMENT_LIB_ADDRESS ( >=20 > + DEFAULT_PCI_SEGMENT_NUMBER_PCH, >=20 > + DEFAULT_PCI_BUS_NUMBER_PCH, >=20 > + SerialIoSpiDevNumber (SpiNumber), >=20 > + SerialIoSpiFuncNumber (SpiNumber), >=20 > + 0 >=20 > + ); >=20 > +} >=20 > + >=20 > +/** >=20 > + Get Serial IO UART controller PCIe Device Number >=20 > + >=20 > + @param[in] UartNumber Serial IO UART controller index >=20 > + >=20 > + @retval Serial IO UART controller PCIe Device Number >=20 > +**/ >=20 > +UINT8 >=20 > +SerialIoUartDevNumber ( >=20 > + IN UINT8 UartNumber >=20 > + ) >=20 > +{ >=20 > + if (GetPchMaxSerialIoUartControllersNum () <=3D UartNumber) { >=20 > + ASSERT (FALSE); >=20 > + return 0xFF; >=20 > + } >=20 > + switch (UartNumber) { >=20 > + case 0: >=20 > + return CheckAndReturn > (PCI_DEVICE_NUMBER_PCH_SERIAL_IO_UART0); >=20 > + case 1: >=20 > + return CheckAndReturn > (PCI_DEVICE_NUMBER_PCH_SERIAL_IO_UART1); >=20 > + case 2: >=20 > + return CheckAndReturn > (PCI_DEVICE_NUMBER_PCH_SERIAL_IO_UART2); >=20 > + case 3: >=20 > + return CheckAndReturn > (PCI_DEVICE_NUMBER_PCH_SERIAL_IO_UART3); >=20 > + case 4: >=20 > + return CheckAndReturn > (PCI_DEVICE_NUMBER_PCH_SERIAL_IO_UART4); >=20 > + case 5: >=20 > + return CheckAndReturn > (PCI_DEVICE_NUMBER_PCH_SERIAL_IO_UART5); >=20 > + case 6: >=20 > + return CheckAndReturn > (PCI_DEVICE_NUMBER_PCH_SERIAL_IO_UART6); >=20 > + default: >=20 > + ASSERT (FALSE); >=20 > + return 0xFF; >=20 > + } >=20 > +} >=20 > + >=20 > +/** >=20 > + Get Serial IO UART controller PCIe Function Number >=20 > + >=20 > + @param[in] UartNumber Serial IO UART controller index >=20 > + >=20 > + @retval Serial IO UART controller PCIe Function Number >=20 > +**/ >=20 > +UINT8 >=20 > +SerialIoUartFuncNumber ( >=20 > + IN UINT8 UartNumber >=20 > + ) >=20 > +{ >=20 > + if (GetPchMaxSerialIoUartControllersNum () <=3D UartNumber) { >=20 > + ASSERT (FALSE); >=20 > + return 0xFF; >=20 > + } >=20 > + switch (UartNumber) { >=20 > + case 0: >=20 > + return CheckAndReturn > (PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART0); >=20 > + case 1: >=20 > + return CheckAndReturn > (PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART1); >=20 > + case 2: >=20 > + return CheckAndReturn > (PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART2); >=20 > + case 3: >=20 > + return CheckAndReturn > (PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART3); >=20 > + case 4: >=20 > + return CheckAndReturn > (PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART4); >=20 > + case 5: >=20 > + return CheckAndReturn > (PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART5); >=20 > + case 6: >=20 > + return CheckAndReturn > (PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART6); >=20 > + default: >=20 > + ASSERT (FALSE); >=20 > + return 0xFF; >=20 > + } >=20 > +} >=20 > + >=20 > +/** >=20 > + Get Serial IO UART controller address that can be passed to the PCI > Segment Library functions. >=20 > + >=20 > + @param[in] UartNumber Serial IO UART controller index >=20 > + >=20 > + @retval Serial IO UART controller address in PCI Segment Library > representation >=20 > +**/ >=20 > +UINT64 >=20 > +SerialIoUartPciCfgBase ( >=20 > + IN UINT8 UartNumber >=20 > + ) >=20 > +{ >=20 > + return PCI_SEGMENT_LIB_ADDRESS ( >=20 > + DEFAULT_PCI_SEGMENT_NUMBER_PCH, >=20 > + DEFAULT_PCI_BUS_NUMBER_PCH, >=20 > + SerialIoUartDevNumber (UartNumber), >=20 > + SerialIoUartFuncNumber (UartNumber), >=20 > + 0 >=20 > + ); >=20 > +} >=20 > + >=20 > +/** >=20 > + Get PCH PCIe controller PCIe Device Number >=20 > + >=20 > + @param[in] RpIndex Root port physical number. (0-based) >=20 > + >=20 > + @retval PCH PCIe controller PCIe Device Number >=20 > +**/ >=20 > +UINT8 >=20 > +PchPcieRpDevNumber ( >=20 > + IN UINTN RpIndex >=20 > + ) >=20 > +{ >=20 > + if (RpIndex >=3D GetPchMaxPciePortNum ()) { >=20 > + ASSERT (FALSE); >=20 > + return 0xFF; >=20 > + } >=20 > + switch (RpIndex) { >=20 > + case 0: >=20 > + return CheckAndReturn > (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_1); >=20 > + case 1: >=20 > + return CheckAndReturn > (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_2); >=20 > + case 2: >=20 > + return CheckAndReturn > (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_3); >=20 > + case 3: >=20 > + return CheckAndReturn > (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_4); >=20 > + case 4: >=20 > + return CheckAndReturn > (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_5); >=20 > + case 5: >=20 > + return CheckAndReturn > (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_6); >=20 > + case 6: >=20 > + return CheckAndReturn > (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_7); >=20 > + case 7: >=20 > + return CheckAndReturn > (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_8); >=20 > + case 8: >=20 > + return CheckAndReturn > (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_9); >=20 > + case 9: >=20 > + return CheckAndReturn > (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_10); >=20 > + case 10: >=20 > + return CheckAndReturn > (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_11); >=20 > + case 11: >=20 > + return CheckAndReturn > (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_12); >=20 > + case 12: >=20 > + return CheckAndReturn > (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_13); >=20 > + case 13: >=20 > + return CheckAndReturn > (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_14); >=20 > + case 14: >=20 > + return CheckAndReturn > (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_15); >=20 > + case 15: >=20 > + return CheckAndReturn > (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_16); >=20 > + case 16: >=20 > + return CheckAndReturn > (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_17); >=20 > + case 17: >=20 > + return CheckAndReturn > (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_18); >=20 > + case 18: >=20 > + return CheckAndReturn > (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_19); >=20 > + case 19: >=20 > + return CheckAndReturn > (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_20); >=20 > + case 20: >=20 > + return CheckAndReturn > (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_21); >=20 > + case 21: >=20 > + return CheckAndReturn > (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_22); >=20 > + case 22: >=20 > + return CheckAndReturn > (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_23); >=20 > + case 23: >=20 > + return CheckAndReturn > (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_24); >=20 > + case 24: >=20 > + return CheckAndReturn > (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_25); >=20 > + case 25: >=20 > + return CheckAndReturn > (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_26); >=20 > + case 26: >=20 > + return CheckAndReturn > (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_27); >=20 > + case 27: >=20 > + return CheckAndReturn > (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_28); >=20 > + >=20 > + default: >=20 > + ASSERT (FALSE); >=20 > + return 0xFF; >=20 > + } >=20 > +} >=20 > + >=20 > +/** >=20 > + Get PCH PCIe controller PCIe Function Number >=20 > + Note: >=20 > + For Client PCH generations Function Number can be various >=20 > + depending on "Root Port Function Swapping". For such cases >=20 > + Function Number MUST be obtain from proper register. >=20 > + For Server PCHs we have no "Root Port Function Swapping" >=20 > + and we can return fixed Function Number. >=20 > + To address this difference in this, PCH generation independent, >=20 > + library we should call specific function in PchPcieRpLib. >=20 > + >=20 > + @param[in] RpIndex Root port physical number. (0-based) >=20 > + >=20 > + @retval PCH PCIe controller PCIe Function Number >=20 > +**/ >=20 > +UINT8 >=20 > +PchPcieRpFuncNumber ( >=20 > + IN UINTN RpIndex >=20 > + ) >=20 > +{ >=20 > + UINTN Device; >=20 > + UINTN Function; >=20 > + >=20 > + GetPchPcieRpDevFun (RpIndex, &Device, &Function); >=20 > + >=20 > + return (UINT8)Function; >=20 > +} >=20 > + >=20 > +/** >=20 > + Get PCH PCIe controller address that can be passed to the PCI Segment > Library functions. >=20 > + >=20 > + @param[in] RpIndex PCH PCIe Root Port physical number. (0-based= ) >=20 > + >=20 > + @retval PCH PCIe controller address in PCI Segment Library representat= ion >=20 > +**/ >=20 > +UINT64 >=20 > +PchPcieRpPciCfgBase ( >=20 > + IN UINT32 RpIndex >=20 > + ) >=20 > +{ >=20 > + return PCI_SEGMENT_LIB_ADDRESS ( >=20 > + DEFAULT_PCI_SEGMENT_NUMBER_PCH, >=20 > + DEFAULT_PCI_BUS_NUMBER_PCH, >=20 > + PchPcieRpDevNumber (RpIndex), >=20 > + PchPcieRpFuncNumber (RpIndex), >=20 > + 0 >=20 > + ); >=20 > +} >=20 > + >=20 > +/** >=20 > + Get HECI1 PCI device number >=20 > + >=20 > + @retval PCI dev number >=20 > +**/ >=20 > +UINT8 >=20 > +PchHeci1DevNumber ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_HECI1); >=20 > +} >=20 > + >=20 > +/** >=20 > + Get HECI1 PCI function number >=20 > + >=20 > + @retval PCI fun number >=20 > +**/ >=20 > +UINT8 >=20 > +PchHeci1FuncNumber ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return CheckAndReturn (PCI_FUNCTION_NUMBER_PCH_HECI1); >=20 > +} >=20 > + >=20 > +/** >=20 > + Get HECI1 controller address that can be passed to the PCI Segment Lib= rary > functions. >=20 > + >=20 > + @retval HECI1 controller address in PCI Segment Library representation >=20 > +**/ >=20 > +UINT64 >=20 > +PchHeci1PciCfgBase ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return PCI_SEGMENT_LIB_ADDRESS ( >=20 > + DEFAULT_PCI_SEGMENT_NUMBER_PCH, >=20 > + DEFAULT_PCI_BUS_NUMBER_PCH, >=20 > + PchHeci1DevNumber (), >=20 > + PchHeci1FuncNumber (), >=20 > + 0 >=20 > + ); >=20 > +} >=20 > + >=20 > +/** >=20 > + Get HECI3 PCI device number >=20 > + >=20 > + @retval PCI dev number >=20 > +**/ >=20 > +UINT8 >=20 > +PchHeci3DevNumber ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_HECI3); >=20 > +} >=20 > + >=20 > +/** >=20 > + Get HECI3 PCI function number >=20 > + >=20 > + @retval PCI fun number >=20 > +**/ >=20 > +UINT8 >=20 > +PchHeci3FuncNumber ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return CheckAndReturn (PCI_FUNCTION_NUMBER_PCH_HECI3); >=20 > +} >=20 > + >=20 > +/** >=20 > + Get HECI3 controller address that can be passed to the PCI Segment Lib= rary > functions. >=20 > + >=20 > + @retval HECI3 controller address in PCI Segment Library representation >=20 > +**/ >=20 > +UINT64 >=20 > +PchHeci3PciCfgBase ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return PCI_SEGMENT_LIB_ADDRESS ( >=20 > + DEFAULT_PCI_SEGMENT_NUMBER_PCH, >=20 > + DEFAULT_PCI_BUS_NUMBER_PCH, >=20 > + PchHeci3DevNumber (), >=20 > + PchHeci3FuncNumber (), >=20 > + 0 >=20 > + ); >=20 > +} >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/BaseResetSystemLib/BaseRe= s > etSystemLib.c > b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/BaseResetSystemLib/BaseRe > setSystemLib.c > new file mode 100644 > index 0000000000..2ede8e0021 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/BaseResetSystemLib/BaseRe > setSystemLib.c > @@ -0,0 +1,158 @@ > +/** @file >=20 > + System reset library services. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +GLOBAL_REMOVE_IF_UNREFERENCED UINT16 > mBaseResetSystemABase; >=20 > + >=20 > +/** >=20 > + Calling this function causes a system-wide reset. This sets >=20 > + all circuitry within the system to its initial state. This type of res= et >=20 > + is asynchronous to system operation and operates without regard to >=20 > + cycle boundaries. >=20 > + >=20 > + System reset should not return, if it returns, it means the system doe= s >=20 > + not support cold reset. >=20 > +**/ >=20 > +VOID >=20 > +EFIAPI >=20 > +ResetCold ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + IoWrite8 (R_PCH_IO_RST_CNT, V_PCH_IO_RST_CNT_FULLRESET); >=20 > +} >=20 > + >=20 > +/** >=20 > + Calling this function causes a system-wide initialization. The process= ors >=20 > + are set to their initial state, and pending cycles are not corrupted. >=20 > + >=20 > + System reset should not return, if it returns, it means the system doe= s >=20 > + not support warm reset. >=20 > +**/ >=20 > +VOID >=20 > +EFIAPI >=20 > +ResetWarm ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + IoWrite8 (R_PCH_IO_RST_CNT, V_PCH_IO_RST_CNT_HARDRESET); >=20 > +} >=20 > + >=20 > +/** >=20 > + Calling this function causes the system to enter a power state equival= ent >=20 > + to the ACPI G2/S5 or G3 states. >=20 > + >=20 > + System shutdown should not return, if it returns, it means the system > does >=20 > + not support shut down reset. >=20 > +**/ >=20 > +VOID >=20 > +EFIAPI >=20 > +ResetShutdown ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + UINT16 ABase; >=20 > + UINT32 Data32; >=20 > + >=20 > + ABase =3D mBaseResetSystemABase; >=20 > + if (ABase =3D=3D 0) { >=20 > + ABase =3D PmcGetAcpiBase (); >=20 > + } >=20 > + /// >=20 > + /// Firstly, GPE0_EN should be disabled to avoid any GPI waking up the > system from S5 >=20 > + /// >=20 > + IoWrite32 (ABase + R_ACPI_IO_GPE0_EN_127_96, 0); >=20 > + >=20 > + /// >=20 > + /// Secondly, PwrSts register must be cleared >=20 > + /// >=20 > + /// Write a "1" to bit[8] of power button status register at >=20 > + /// (PM_BASE + PM1_STS_OFFSET) to clear this bit >=20 > + /// >=20 > + IoWrite16 (ABase + R_ACPI_IO_PM1_STS, > B_ACPI_IO_PM1_STS_PWRBTN); >=20 > + >=20 > + /// >=20 > + /// Finally, transform system into S5 sleep state >=20 > + /// >=20 > + Data32 =3D IoRead32 (ABase + R_ACPI_IO_PM1_CNT); >=20 > + >=20 > + Data32 =3D (UINT32) ((Data32 &~(B_ACPI_IO_PM1_CNT_SLP_TYP + > B_ACPI_IO_PM1_CNT_SLP_EN)) | V_ACPI_IO_PM1_CNT_S5); >=20 > + >=20 > + IoWrite32 (ABase + R_ACPI_IO_PM1_CNT, Data32); >=20 > + >=20 > + Data32 =3D Data32 | B_ACPI_IO_PM1_CNT_SLP_EN; >=20 > + >=20 > + IoWrite32 (ABase + R_ACPI_IO_PM1_CNT, Data32); >=20 > + >=20 > + return; >=20 > +} >=20 > + >=20 > +/** >=20 > + Calling this function causes the system to enter a power state for pla= tform > specific. >=20 > + >=20 > + @param[in] DataSize The size of ResetData in bytes. >=20 > + @param[in] ResetData Optional element used to introduce a > platform specific reset. >=20 > + The exact type of the reset is defined= by the EFI_GUID that > follows >=20 > + the Null-terminated Unicode string. >=20 > + >=20 > +**/ >=20 > +VOID >=20 > +EFIAPI >=20 > +ResetPlatformSpecific ( >=20 > + IN UINTN DataSize, >=20 > + IN VOID *ResetData OPTIONAL >=20 > + ) >=20 > +{ >=20 > + IoWrite8 (R_PCH_IO_RST_CNT, V_PCH_IO_RST_CNT_FULLRESET); >=20 > +} >=20 > + >=20 > +/** >=20 > + Calling this function causes the system to enter a power state for cap= sule > update. >=20 > + >=20 > + Reset update should not return, if it returns, it means the system doe= s >=20 > + not support capsule update. >=20 > + >=20 > +**/ >=20 > +VOID >=20 > +EFIAPI >=20 > +EnterS3WithImmediateWake ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + // >=20 > + // In case there are pending capsules to process, need to flush the ca= che. >=20 > + // >=20 > + AsmWbinvd (); >=20 > + >=20 > + ResetWarm (); >=20 > + ASSERT (FALSE); >=20 > +} >=20 > + >=20 > +/** >=20 > + The library constructuor. >=20 > + >=20 > + The function does the necessary initialization work for this library i= nstance. >=20 > + >=20 > + @retval EFI_SUCCESS The function always return EFI_SUCCESS f= or > now. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +BaseResetSystemLibConstructor ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + mBaseResetSystemABase =3D PmcGetAcpiBase (); >=20 > + >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/BaseResetSystemLib/BaseRe= s > etSystemLib.inf > b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/BaseResetSystemLib/BaseRe > setSystemLib.inf > new file mode 100644 > index 0000000000..a4f805035a > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/BaseResetSystemLib/BaseRe > setSystemLib.inf > @@ -0,0 +1,38 @@ > +## @file >=20 > +# Component description file for Intel Ich7 Reset System Library. >=20 > +# >=20 > +# Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > +# SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +# >=20 > +## >=20 > + >=20 > +[Defines] >=20 > +INF_VERSION =3D 0x00010017 >=20 > +BASE_NAME =3D BaseResetSystemLib >=20 > +FILE_GUID =3D D4FF05AA-3C7D-4B8A-A1EE-AA5EFA0B1732 >=20 > +VERSION_STRING =3D 1.0 >=20 > +MODULE_TYPE =3D BASE >=20 > +UEFI_SPECIFICATION_VERSION =3D 2.00 >=20 > +LIBRARY_CLASS =3D ResetSystemLib >=20 > +CONSTRUCTOR =3D BaseResetSystemLibConstructor >=20 > +# >=20 > +# The following information is for reference only and not required by th= e > build tools. >=20 > +# >=20 > +# VALID_ARCHITECTURES =3D IA32 X64 IPF >=20 > +# >=20 > + >=20 > +[LibraryClasses] >=20 > +IoLib >=20 > +BaseLib >=20 > +DebugLib >=20 > +PmcLib >=20 > + >=20 > + >=20 > +[Packages] >=20 > +MdePkg/MdePkg.dec >=20 > +TigerlakeSiliconPkg/SiPkg.dec >=20 > + >=20 > + >=20 > +[Sources] >=20 > +BaseResetSystemLib.c >=20 > + >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/DxePchPolicyLib/DxePchPol= ic > yLib.c > b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/DxePchPolicyLib/DxePchPol= ic > yLib.c > new file mode 100644 > index 0000000000..90aea8f420 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/DxePchPolicyLib/DxePchPol= ic > yLib.c > @@ -0,0 +1,198 @@ > +/** @file >=20 > + This file provide services for DXE phase policy default initialization >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +/** >=20 > + Load DXE Config block default for eMMC >=20 > + >=20 > + @param[in] ConfigBlockPointer Pointer to config block >=20 > +**/ >=20 > +VOID >=20 > +LoadEmmcDxeConfigDefault ( >=20 > + IN VOID *ConfigBlockPointer >=20 > + ) >=20 > +{ >=20 > + SCS_EMMC_DXE_CONFIG *EmmcDxeConfig; >=20 > + EmmcDxeConfig =3D ConfigBlockPointer; >=20 > + >=20 > + DEBUG ((DEBUG_INFO, "EmmcDxeConfig->Header.GuidHob.Name =3D > %g\n", &EmmcDxeConfig->Header.GuidHob.Name)); >=20 > + DEBUG ((DEBUG_INFO, "EmmcDxeConfig- > >Header.GuidHob.Header.HobLength =3D 0x%x\n", EmmcDxeConfig- > >Header.GuidHob.Header.HobLength)); >=20 > + >=20 > + EmmcDxeConfig->DriverStrength =3D DriverStrength40Ohm; >=20 > +} >=20 > + >=20 > +GLOBAL_REMOVE_IF_UNREFERENCED COMPONENT_BLOCK_ENTRY > mPchDxeIpBlocks [] =3D { >=20 > + {&gEmmcDxeConfigGuid, sizeof (SCS_EMMC_DXE_CONFIG), > SCS_EMMC_DXE_CONFIG_REVISION, LoadEmmcDxeConfigDefault} >=20 > +}; >=20 > + >=20 > +/** >=20 > + Print SCS_EMMC_DXE_CONFIG. >=20 > + >=20 > + @param[in] EmmcDxeConfig Pointer to a SCS_EMMC_DXE_CONFIG > that provides the eMMC settings >=20 > +**/ >=20 > +VOID >=20 > +PchPrintEmmcDxeConfig ( >=20 > + IN CONST SCS_EMMC_DXE_CONFIG *EmmcDxeConfig >=20 > + ) >=20 > +{ >=20 > + DEBUG ((DEBUG_INFO, "------------------ PCH eMMC DXE Config ----------= --- > -----\n")); >=20 > + DEBUG ((DEBUG_INFO, " DriverStrength : %d\n", EmmcDxeConfig- > >DriverStrength)); >=20 > + DEBUG ((DEBUG_INFO, " EnableSoftwareHs400Tuning: %d\n", > EmmcDxeConfig->EnableSoftwareHs400Tuning)); >=20 > + DEBUG ((DEBUG_INFO, " TuningLba : %X\n", EmmcDxeConfig- > >TuningLba)); >=20 > + DEBUG ((DEBUG_INFO, " Previous tuning success : %d\n", > EmmcDxeConfig->PreviousTuningResults.TuningSuccessful)); >=20 > + if (EmmcDxeConfig->PreviousTuningResults.TuningSuccessful) { >=20 > + DEBUG ((DEBUG_INFO, " Hs400 Rx DLL value : %X\n", EmmcDxeConfig- > >PreviousTuningResults.Hs400RxValue)); >=20 > + DEBUG ((DEBUG_INFO, " Hs400 Tx DLL value : %X\n", EmmcDxeConfig- > >PreviousTuningResults.Hs400TxValue)); >=20 > + } >=20 > +} >=20 > + >=20 > +/** >=20 > + This function prints the PCH DXE phase policy. >=20 > + >=20 > + @param[in] PchPolicy - PCH DXE Policy protocol >=20 > +**/ >=20 > +VOID >=20 > +PchPrintPolicyProtocol ( >=20 > + IN PCH_POLICY_PROTOCOL *PchPolicy >=20 > + ) >=20 > +{ >=20 > + DEBUG_CODE_BEGIN(); >=20 > + EFI_STATUS Status; >=20 > + SCS_EMMC_DXE_CONFIG *EmmcDxeConfig; >=20 > + >=20 > + // >=20 > + // Get requisite IP Config Blocks which needs to be used here >=20 > + // >=20 > + Status =3D GetConfigBlock ((VOID *) PchPolicy, &gEmmcDxeConfigGuid, > (VOID *)&EmmcDxeConfig); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + >=20 > + DEBUG ((DEBUG_INFO, "------------------------ PCH Policy (DXE) Print S= tart -- > ----------------------\n")); >=20 > + DEBUG ((DEBUG_INFO, " Revision : %x\n", PchPolicy- > >TableHeader.Header.Revision)); >=20 > + >=20 > + PchPrintEmmcDxeConfig (EmmcDxeConfig); >=20 > + GpioDxePrintConfig (PchPolicy); >=20 > + HdaDxePrintConfig (PchPolicy); >=20 > + PchPcieRpDxePrintConfig (PchPolicy); >=20 > + >=20 > + DEBUG ((DEBUG_INFO, "------------------------ PCH Policy (DXE) Print E= nd --- > -----------------------\n")); >=20 > + DEBUG_CODE_END(); >=20 > +} >=20 > + >=20 > +/** >=20 > + CreatePchDxeConfigBlocks generates the config blocksg of PCH DXE Polic= y. >=20 > + It allocates and zero out buffer, and fills in the Intel default setti= ngs. >=20 > + >=20 > + @param[out] PchPolicy The pointer to get PCH DXE Proto= col > instance >=20 > + >=20 > + @retval EFI_SUCCESS The policy default is initialize= d. >=20 > + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create > buffer >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +CreatePchDxeConfigBlocks ( >=20 > + IN OUT PCH_POLICY_PROTOCOL **DxePchPolicy >=20 > + ) >=20 > +{ >=20 > + UINT16 TotalBlockSize; >=20 > + EFI_STATUS Status; >=20 > + PCH_POLICY_PROTOCOL *PchPolicyInit; >=20 > + UINT16 RequiredSize; >=20 > + >=20 > + >=20 > + DEBUG ((DEBUG_INFO, "PCH Create Dxe Config Blocks\n")); >=20 > + >=20 > + PchPolicyInit =3D NULL; >=20 > + >=20 > + TotalBlockSize =3D GetComponentConfigBlockTotalSize > (&mPchDxeIpBlocks[0], sizeof (mPchDxeIpBlocks) / sizeof > (COMPONENT_BLOCK_ENTRY)); >=20 > + TotalBlockSize +=3D GpioDxeGetConfigBlockTotalSize(); >=20 > + TotalBlockSize +=3D HdaDxeGetConfigBlockTotalSize(); >=20 > + TotalBlockSize +=3D PchPcieRpDxeGetConfigBlockTotalSize(); >=20 > + >=20 > + DEBUG ((DEBUG_INFO, "TotalBlockSize =3D 0x%x\n", TotalBlockSize)); >=20 > + >=20 > + RequiredSize =3D sizeof (CONFIG_BLOCK_TABLE_HEADER) + TotalBlockSize; >=20 > + >=20 > + Status =3D CreateConfigBlockTable (RequiredSize, (VOID *) &PchPolicyIn= it); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + >=20 > + // >=20 > + // General initialization >=20 > + // >=20 > + PchPolicyInit->TableHeader.Header.Revision =3D > PCH_POLICY_PROTOCOL_REVISION; >=20 > + // >=20 > + // Add config blocks. >=20 > + // >=20 > + Status =3D AddComponentConfigBlocks ((VOID *) PchPolicyInit, > &mPchDxeIpBlocks[0], sizeof (mPchDxeIpBlocks) / sizeof > (COMPONENT_BLOCK_ENTRY)); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + >=20 > + Status =3D GpioDxeAddConfigBlock ((VOID *) PchPolicyInit); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + >=20 > + Status =3D HdaDxeAddConfigBlock ((VOID *) PchPolicyInit); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + >=20 > + Status =3D PchPcieRpDxeAddConfigBlock ((VOID *) PchPolicyInit); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + >=20 > + // >=20 > + // Assignment for returning SaInitPolicy config block base address >=20 > + // >=20 > + *DxePchPolicy =3D PchPolicyInit; >=20 > + return Status; >=20 > +} >=20 > + >=20 > +/** >=20 > + PchInstallPolicyProtocol installs PCH Policy. >=20 > + While installed, RC assumes the Policy is ready and finalized. So plea= se > update and override >=20 > + any setting before calling this function. >=20 > + >=20 > + @param[in] ImageHandle Image handle of this driver. >=20 > + @param[in] SaPolicy The pointer to SA Policy Protoco= l instance >=20 > + >=20 > + @retval EFI_SUCCESS The policy is installed. >=20 > + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create > buffer >=20 > + >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +PchInstallPolicyProtocol ( >=20 > + IN EFI_HANDLE ImageHandle, >=20 > + IN PCH_POLICY_PROTOCOL *PchPolicy >=20 > + ) >=20 > +{ >=20 > + >=20 > + EFI_STATUS Status; >=20 > + >=20 > + /// >=20 > + /// Print PCH DXE Policy >=20 > + /// >=20 > + PchPrintPolicyProtocol (PchPolicy); >=20 > + >=20 > + /// >=20 > + /// Install protocol to to allow access to this Policy. >=20 > + /// >=20 > + Status =3D gBS->InstallMultipleProtocolInterfaces ( >=20 > + &ImageHandle, >=20 > + &gPchPolicyProtocolGuid, >=20 > + PchPolicy, >=20 > + NULL >=20 > + ); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + >=20 > + return Status; >=20 > +} >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/DxePchPolicyLib/DxePchPol= ic > yLib.inf > b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/DxePchPolicyLib/DxePchPol= ic > yLib.inf > new file mode 100644 > index 0000000000..50e5cdacfd > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/DxePchPolicyLib/DxePchPol= ic > yLib.inf > @@ -0,0 +1,43 @@ > +## @file >=20 > +# Component description file for the PeiPchPolicy library. >=20 > +# >=20 > +# Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > +# SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +# >=20 > +## >=20 > + >=20 > + >=20 > +[Defines] >=20 > +INF_VERSION =3D 0x00010017 >=20 > +BASE_NAME =3D DxePchPolicyLib >=20 > +FILE_GUID =3D E2179D04-7026-48A5-9475-309CEA2F21A3 >=20 > +VERSION_STRING =3D 1.0 >=20 > +MODULE_TYPE =3D BASE >=20 > +LIBRARY_CLASS =3D DxePchPolicyLib >=20 > + >=20 > + >=20 > +[LibraryClasses] >=20 > +BaseMemoryLib >=20 > +UefiBootServicesTableLib >=20 > +DebugLib >=20 > +ConfigBlockLib >=20 > +SiConfigBlockLib >=20 > +PchInfoLib >=20 > +DxeGpioPolicyLib >=20 > +DxeHdaPolicyLib >=20 > +DxePchPcieRpPolicyLib >=20 > + >=20 > +[Packages] >=20 > +MdePkg/MdePkg.dec >=20 > +TigerlakeSiliconPkg/SiPkg.dec >=20 > + >=20 > + >=20 > +[Sources] >=20 > +DxePchPolicyLib.c >=20 > + >=20 > + >=20 > +[Guids] >=20 > +gEmmcDxeConfigGuid >=20 > + >=20 > +[Protocols] >=20 > +gPchPolicyProtocolGuid ## PRODUCES >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/PeiDxeSmmPchCycleDecodin > gLib/PchCycleDecodingLib.c > b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/PeiDxeSmmPchCycleDecodin > gLib/PchCycleDecodingLib.c > new file mode 100644 > index 0000000000..0927cd1ced > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/PeiDxeSmmPchCycleDecodin > gLib/PchCycleDecodingLib.c > @@ -0,0 +1,587 @@ > +/** @file >=20 > + PCH cycle decoding configuration and query library. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +typedef enum { >=20 > + SlaveLpcEspiCS0, >=20 > + SlaveEspiCS1, >=20 > + SlaveId_Max >=20 > +} SLAVE_ID_INDEX; >=20 > + >=20 > +/** >=20 > + Get PCH TCO base address. >=20 > + >=20 > + @param[out] Address Address of TCO base address. >=20 > + >=20 > + @retval EFI_SUCCESS Successfully completed. >=20 > + @retval EFI_INVALID_PARAMETER Invalid pointer passed. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +PchTcoBaseGet ( >=20 > + OUT UINT16 *Address >=20 > + ) >=20 > +{ >=20 > + if (Address =3D=3D NULL) { >=20 > + DEBUG ((DEBUG_ERROR, "PchTcoBaseGet Error. Invalid pointer.\n")); >=20 > + ASSERT (FALSE); >=20 > + return EFI_INVALID_PARAMETER; >=20 > + } >=20 > + // >=20 > + // Read "TCO Base Address" from DMI >=20 > + // Don't read TCO base address from SMBUS PCI register since SMBUS > might be disabled. >=20 > + // >=20 > + *Address =3D PchDmiGetTcoBase (); >=20 > + >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > +/** >=20 > + Set PCH LPC/eSPI and eSPI CS1# generic IO range decoding. >=20 > + >=20 > + Steps of programming generic IO range: >=20 > + 1. Program LPC/eSPI PCI Offset 84h ~ 93h (LPC, eSPI CS0#) or A4h (eSPI > CS1#) of Mask, Address, and Enable. >=20 > + 2. Program LPC/eSPI Generic IO Range in DMI >=20 > + >=20 > + @param[in] Address Address for generic IO range dec= oding. >=20 > + @param[in] Length Length of generic IO range. >=20 > + @param[in] SlaveId Slave ID (refer to SLAVE_ID_INDE= X) >=20 > + >=20 > + @retval EFI_SUCCESS Successfully completed. >=20 > + @retval EFI_INVALID_PARAMETER Invalid base address or length > passed. >=20 > + @retval EFI_OUT_OF_RESOURCES No more generic range available. >=20 > + @retval EFI_UNSUPPORTED DMI configuration is locked, >=20 > + GenIO range conflicting with oth= er eSPI CS >=20 > +**/ >=20 > +STATIC >=20 > +EFI_STATUS >=20 > +LpcEspiGenIoRangeSetHelper ( >=20 > + IN UINT32 Address, >=20 > + IN UINT32 Length, >=20 > + IN SLAVE_ID_INDEX SlaveId >=20 > + ) >=20 > +{ >=20 > + return EFI_UNSUPPORTED; >=20 > +} >=20 > + >=20 > +/** >=20 > + Set PCH LPC/eSPI generic IO range. >=20 > + For generic IO range, the base address must align to 4 and less than > 0xFFFF, and the length must be power of 2 >=20 > + and less than or equal to 256. Moreover, the address must be length > aligned. >=20 > + This function basically checks the address and length, which should no= t > overlap with all other generic ranges. >=20 > + If no more generic range register available, it returns out of resourc= e error. >=20 > + This cycle decoding is also required on DMI side >=20 > + Some IO ranges below 0x100 have fixed target. The target might be > ITSS,RTC,LPC,PMC or terminated inside P2SB >=20 > + but all predefined and can't be changed. IO range below 0x100 will be > rejected in this function except below ranges: >=20 > + 0x00-0x1F, >=20 > + 0x44-0x4B, >=20 > + 0x54-0x5F, >=20 > + 0x68-0x6F, >=20 > + 0x80-0x8F, >=20 > + 0xC0-0xFF >=20 > + Steps of programming generic IO range: >=20 > + 1. Program LPC/eSPI PCI Offset 84h ~ 93h of Mask, Address, and Enable. >=20 > + 2. Program LPC/eSPI Generic IO Range in DMI >=20 > + >=20 > + @param[in] Address Address for generic IO range bas= e address. >=20 > + @param[in] Length Length of generic IO range. >=20 > + >=20 > + @retval EFI_SUCCESS Successfully completed. >=20 > + @retval EFI_INVALID_PARAMETER Invalid base address or length > passed. >=20 > + @retval EFI_OUT_OF_RESOURCES No more generic range available. >=20 > + @retval EFI_UNSUPPORTED DMIC.SRL is set. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +PchLpcGenIoRangeSet ( >=20 > + IN UINT16 Address, >=20 > + IN UINTN Length >=20 > + ) >=20 > +{ >=20 > + return LpcEspiGenIoRangeSetHelper ((UINT32)Address, (UINT32)Length, > SlaveLpcEspiCS0); >=20 > +} >=20 > + >=20 > + >=20 > +/** >=20 > + Set PCH LPC/eSPI and eSPI CS1# memory range decoding. >=20 > + This cycle decoding is required to be set on DMI side >=20 > + Programming steps: >=20 > + 1. Program LPC/eSPI PCI Offset 98h (LPC, eSPI CS0#) or A8h (eSPI CS1#)= [0] > to [0] to disable memory decoding first before changing base address. >=20 > + 2. Program LPC/eSPI PCI Offset 98h (LPC, eSPI CS0#) or A8h (eSPI CS1#) > [31:16, 0] to [Address, 1]. >=20 > + 3. Program LPC/eSPI Memory Range in DMI >=20 > + >=20 > + @param[in] Address Address for memory for decoding. >=20 > + @param[in] RangeIndex Slave ID (refer to SLAVE_ID_INDE= X) >=20 > + >=20 > + @retval EFI_SUCCESS Successfully completed. >=20 > + @retval EFI_INVALID_PARAMETER Invalid base address or length > passed. >=20 > +**/ >=20 > +STATIC >=20 > +EFI_STATUS >=20 > +LpcEspiMemRangeSetHelper ( >=20 > + IN UINT32 Address, >=20 > + IN SLAVE_ID_INDEX SlaveId >=20 > + ) >=20 > +{ >=20 > + UINT64 LpcBase; >=20 > + EFI_STATUS Status; >=20 > + UINT32 GenMemReg; >=20 > + UINT32 MemRangeAddr; >=20 > + >=20 > + if (((Address & (~B_LPC_CFG_LGMR_MA)) !=3D 0) || (SlaveId >=3D > SlaveId_Max)) { >=20 > + DEBUG ((DEBUG_ERROR, "%a Error. Invalid Address: %x or invalid > SlaveId\n", __FUNCTION__, Address)); >=20 > + ASSERT (FALSE); >=20 > + return EFI_INVALID_PARAMETER; >=20 > + } >=20 > + >=20 > + LpcBase =3D LpcPciCfgBase (); >=20 > + >=20 > + MemRangeAddr =3D ~Address; >=20 > + if (SlaveId =3D=3D SlaveEspiCS1) { >=20 > + GenMemReg =3D R_ESPI_CFG_CS1GMR1; >=20 > + // Memory Range already decoded for LPC/eSPI? >=20 > + Status =3D PchLpcMemRangeGet (&MemRangeAddr); >=20 > + if (MemRangeAddr !=3D Address) { >=20 > + Status =3D PchDmiSetEspiCs1MemRange (Address); >=20 > + if (EFI_ERROR (Status)) { >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + return Status; >=20 > + } >=20 > + } >=20 > + } else { >=20 > + GenMemReg =3D R_LPC_CFG_LGMR; >=20 > + // Memory Range already decoded for eSPI CS1? >=20 > + Status =3D PchEspiCs1MemRangeGet (&MemRangeAddr); >=20 > + if (MemRangeAddr !=3D Address) { >=20 > + Status =3D PchDmiSetLpcMemRange (Address); >=20 > + if (EFI_ERROR (Status)) { >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + return Status; >=20 > + } >=20 > + } >=20 > + } >=20 > + >=20 > + // >=20 > + // Program LPC/eSPI PCI Offset 98h (LPC, eSPI CS0#) or A8h (eSPI CS1#)= [0] > to [0] to disable memory decoding first before changing base address. >=20 > + // >=20 > + PciSegmentAnd32 ( >=20 > + LpcBase + GenMemReg, >=20 > + (UINT32) ~B_LPC_CFG_LGMR_LMRD_EN >=20 > + ); >=20 > + // >=20 > + // Program LPC/eSPI PCI Offset 98h (LPC, eSPI CS0#) or A8h (eSPI CS1#) > [31:16, 0] to [Address, 1]. >=20 > + // >=20 > + PciSegmentWrite32 ( >=20 > + LpcBase + GenMemReg, >=20 > + (Address | B_LPC_CFG_LGMR_LMRD_EN) >=20 > + ); >=20 > + >=20 > + return Status; >=20 > +} >=20 > + >=20 > +/** >=20 > + Set PCH LPC/eSPI memory range decoding. >=20 > + This cycle decoding is required to be set on DMI side >=20 > + Programming steps: >=20 > + 1. Program LPC PCI Offset 98h [0] to [0] to disable memory decoding fi= rst > before changing base address. >=20 > + 2. Program LPC PCI Offset 98h [31:16, 0] to [Address, 1]. >=20 > + 3. Program LPC Memory Range in DMI >=20 > + >=20 > + @param[in] Address Address for memory base address. >=20 > + >=20 > + @retval EFI_SUCCESS Successfully completed. >=20 > + @retval EFI_INVALID_PARAMETER Invalid base address or length > passed. >=20 > + @retval EFI_OUT_OF_RESOURCES No more generic range available. >=20 > + @retval EFI_UNSUPPORTED DMIC.SRL is set. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +PchLpcMemRangeSet ( >=20 > + IN UINT32 Address >=20 > + ) >=20 > +{ >=20 > + return LpcEspiMemRangeSetHelper (Address, SlaveLpcEspiCS0); >=20 > +} >=20 > + >=20 > +/** >=20 > + Set PCH eSPI CS1# memory range decoding. >=20 > + This cycle decoding is required to be set on DMI side >=20 > + Programming steps: >=20 > + 1. Program eSPI PCI Offset A8h (eSPI CS1#) [0] to [0] to disable memor= y > decoding first before changing base address. >=20 > + 2. Program eSPI PCI Offset A8h (eSPI CS1#) [31:16, 0] to [Address, 1]. >=20 > + 3. Program eSPI Memory Range in DMI >=20 > + >=20 > + @param[in] Address Address for memory for decoding. >=20 > + >=20 > + @retval EFI_SUCCESS Successfully completed. >=20 > + @retval EFI_INVALID_PARAMETER Invalid base address or length > passed. >=20 > + @retval EFI_UNSUPPORTED eSPI secondary slave not support= ed >=20 > +**/ >=20 > +EFI_STATUS >=20 > +PchEspiCs1MemRangeSet ( >=20 > + IN UINT32 Address >=20 > + ) >=20 > +{ >=20 > + if (!IsEspiSecondSlaveSupported ()) { >=20 > + return EFI_UNSUPPORTED; >=20 > + } >=20 > + >=20 > + return LpcEspiMemRangeSetHelper (Address, SlaveEspiCS1); >=20 > +} >=20 > + >=20 > +/** >=20 > + Get PCH LPC/eSPI and eSPI CS1# memory range decoding address. >=20 > + >=20 > + @param[in] SlaveId Slave ID (refer to SLAVE_ID_INDE= X) >=20 > + @param[out] Address Address of LPC/eSPI or eSPI CS1#= memory > decoding base address. >=20 > + >=20 > + @retval EFI_SUCCESS Successfully completed. >=20 > + @retval EFI_INVALID_PARAMETER Invalid base address passed. >=20 > + @retval EFI_UNSUPPORTED eSPI secondary slave not support= ed >=20 > +**/ >=20 > +STATIC >=20 > +EFI_STATUS >=20 > +LpcEspiMemRangeGetHelper ( >=20 > + IN SLAVE_ID_INDEX SlaveId, >=20 > + OUT UINT32 *Address >=20 > + ) >=20 > +{ >=20 > + UINT32 GenMemReg; >=20 > + >=20 > + if ((Address =3D=3D NULL) || (SlaveId >=3D SlaveId_Max)) { >=20 > + DEBUG ((DEBUG_ERROR, "%a Error. Invalid pointer or SlaveId.\n", > __FUNCTION__)); >=20 > + ASSERT (FALSE); >=20 > + return EFI_INVALID_PARAMETER; >=20 > + } >=20 > + >=20 > + if (SlaveId =3D=3D SlaveEspiCS1) { >=20 > + GenMemReg =3D R_ESPI_CFG_CS1GMR1; >=20 > + } else { >=20 > + GenMemReg =3D R_LPC_CFG_LGMR; >=20 > + } >=20 > + *Address =3D PciSegmentRead32 (LpcPciCfgBase () + GenMemReg) & > B_LPC_CFG_LGMR_MA; >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > +/** >=20 > + Get PCH LPC/eSPI memory range decoding address. >=20 > + >=20 > + @param[out] Address Address of LPC/eSPI memory decod= ing > base address. >=20 > + >=20 > + @retval EFI_SUCCESS Successfully completed. >=20 > + @retval EFI_INVALID_PARAMETER Invalid base address passed. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +PchLpcMemRangeGet ( >=20 > + OUT UINT32 *Address >=20 > + ) >=20 > +{ >=20 > + return LpcEspiMemRangeGetHelper (SlaveLpcEspiCS0, Address); >=20 > +} >=20 > + >=20 > +/** >=20 > + Get PCH eSPI CS1# memory range decoding address. >=20 > + >=20 > + @param[out] Address Address of eSPI CS1# memory deco= ding > base address. >=20 > + >=20 > + @retval EFI_SUCCESS Successfully completed. >=20 > + @retval EFI_INVALID_PARAMETER Invalid base address passed. >=20 > + @retval EFI_UNSUPPORTED eSPI secondary slave not support= ed >=20 > +**/ >=20 > +EFI_STATUS >=20 > +PchEspiCs1MemRangeGet ( >=20 > + OUT UINT32 *Address >=20 > + ) >=20 > +{ >=20 > + if (!IsEspiSecondSlaveSupported ()) { >=20 > + return EFI_UNSUPPORTED; >=20 > + } >=20 > + >=20 > + return LpcEspiMemRangeGetHelper (SlaveEspiCS1, Address); >=20 > +} >=20 > + >=20 > +/** >=20 > + Set PCH BIOS range deocding. >=20 > + This will check General Control and Status bit 10 (GCS.BBS) to identif= y SPI > or LPC/eSPI and program BDE register accordingly. >=20 > + Please check EDS for detail of BiosDecodeEnable bit definition. >=20 > + bit 15: F8-FF Enable >=20 > + bit 14: F0-F8 Enable >=20 > + bit 13: E8-EF Enable >=20 > + bit 12: E0-E8 Enable >=20 > + bit 11: D8-DF Enable >=20 > + bit 10: D0-D7 Enable >=20 > + bit 9: C8-CF Enable >=20 > + bit 8: C0-C7 Enable >=20 > + bit 7: Legacy F Segment Enable >=20 > + bit 6: Legacy E Segment Enable >=20 > + bit 5: Reserved >=20 > + bit 4: Reserved >=20 > + bit 3: 70-7F Enable >=20 > + bit 2: 60-6F Enable >=20 > + bit 1: 50-5F Enable >=20 > + bit 0: 40-4F Enable >=20 > + This cycle decoding is also required in DMI >=20 > + Programming steps: >=20 > + 1. if GCS.BBS is 0 (SPI), program SPI offset D8h to BiosDecodeEnable. >=20 > + if GCS.BBS is 1 (LPC/eSPi), program LPC offset D8h to BiosDecodeEna= ble. >=20 > + 2. program LPC BIOS Decode Enable in DMI >=20 > + >=20 > + @param[in] BiosDecodeEnable Bios decode enable setting. >=20 > + >=20 > + @retval EFI_SUCCESS Successfully completed. >=20 > + @retval EFI_UNSUPPORTED DMIC.SRL is set. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +PchBiosDecodeEnableSet ( >=20 > + IN UINT16 BiosDecodeEnable >=20 > + ) >=20 > +{ >=20 > + UINT64 BaseAddr; >=20 > + EFI_STATUS Status; >=20 > + >=20 > + Status =3D PchDmiSetBiosDecodeEnable (BiosDecodeEnable); >=20 > + if (EFI_ERROR (Status)) { >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + return Status; >=20 > + } >=20 > + >=20 > + // >=20 > + // Check Boot BIOS Strap in DMI >=20 > + // >=20 > + if (PchDmiIsBootBiosStrapSetForSpi ()) { >=20 > + BaseAddr =3D SpiPciCfgBase (); >=20 > + // >=20 > + // If SPI, Program SPI offset D8h to BiosDecodeEnable. >=20 > + // >=20 > + PciSegmentWrite16 (BaseAddr + R_SPI_CFG_BDE, BiosDecodeEnable); >=20 > + } else { >=20 > + BaseAddr =3D LpcPciCfgBase (); >=20 > + // >=20 > + // If LPC/eSPi, program LPC offset D8h to BiosDecodeEnable. >=20 > + // >=20 > + PciSegmentWrite16 (BaseAddr + R_LPC_CFG_BDE, BiosDecodeEnable); >=20 > + } >=20 > + >=20 > + return Status; >=20 > +} >=20 > + >=20 > +/** >=20 > + Set PCH LPC/eSPI IO decode ranges. >=20 > + Program LPC/eSPI I/O Decode Ranges in DMI to the same value > programmed in LPC/eSPI PCI offset 80h. >=20 > + Please check EDS for detail of LPC/eSPI IO decode ranges bit definitio= n. >=20 > + Bit 12: FDD range >=20 > + Bit 9:8: LPT range >=20 > + Bit 6:4: ComB range >=20 > + Bit 2:0: ComA range >=20 > + >=20 > + @param[in] LpcIoDecodeRanges LPC/eSPI IO decode ranges bit > settings. >=20 > + >=20 > + @retval EFI_SUCCESS Successfully completed. >=20 > + @retval EFI_UNSUPPORTED DMIC.SRL is set. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +PchLpcIoDecodeRangesSet ( >=20 > + IN UINT16 LpcIoDecodeRanges >=20 > + ) >=20 > +{ >=20 > + UINT64 LpcBaseAddr; >=20 > + EFI_STATUS Status; >=20 > + >=20 > + // >=20 > + // Note: Inside this function, don't use debug print since it's could = used > before debug print ready. >=20 > + // >=20 > + >=20 > + LpcBaseAddr =3D LpcPciCfgBase (); >=20 > + >=20 > + // >=20 > + // check if setting is identical >=20 > + // >=20 > + if (LpcIoDecodeRanges =3D=3D PciSegmentRead16 (LpcBaseAddr + > R_LPC_CFG_IOD)) { >=20 > + return EFI_SUCCESS; >=20 > + } >=20 > + >=20 > + Status =3D PchDmiSetLpcIoDecodeRanges (LpcIoDecodeRanges); >=20 > + if (EFI_ERROR (Status)) { >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + return Status; >=20 > + } >=20 > + >=20 > + // >=20 > + // program LPC/eSPI PCI offset 80h. >=20 > + // >=20 > + PciSegmentWrite16 (LpcBaseAddr + R_LPC_CFG_IOD, > LpcIoDecodeRanges); >=20 > + >=20 > + return Status; >=20 > +} >=20 > + >=20 > +/** >=20 > + Set PCH LPC/eSPI and eSPI CS1# IO enable decoding. >=20 > + Setup I/O Enables in DMI to the same value program in LPC/eSPI PCI off= set > 82h (LPC, eSPI CS0#) or A0h (eSPI CS1#). >=20 > + Note: Bit[15:10] of the source decode register is Read-Only. The IO ra= nge > indicated by the Enables field >=20 > + in LPC/eSPI PCI offset 82h[13:10] or A0h[13:10] is always forwarded by= DMI > to subtractive agent for handling. >=20 > + Please check EDS for detail of Lpc/eSPI IO decode ranges bit definitio= n. >=20 > + >=20 > + @param[in] IoEnableDecoding LPC/eSPI IO enable decoding bit > settings. >=20 > + @param[in] SlaveId Slave ID (refer to SLAVE_ID_INDE= X) >=20 > + >=20 > + @retval EFI_SUCCESS Successfully completed. >=20 > + @retval EFI_UNSUPPORTED DMI configuration is locked >=20 > +**/ >=20 > +EFI_STATUS >=20 > +LpcEspiIoEnableDecodingSetHelper ( >=20 > + IN UINT16 IoEnableDecoding, >=20 > + IN SLAVE_ID_INDEX SlaveId >=20 > + ) >=20 > +{ >=20 > + UINT64 LpcBaseAddr; >=20 > + EFI_STATUS Status; >=20 > + UINT16 Cs1IoEnableDecodingOrg; >=20 > + UINT16 Cs0IoEnableDecodingOrg; >=20 > + UINT16 IoEnableDecodingMerged; >=20 > + >=20 > + LpcBaseAddr =3D LpcPciCfgBase (); >=20 > + >=20 > + Cs0IoEnableDecodingOrg =3D PciSegmentRead16 (LpcBaseAddr + > R_LPC_CFG_IOE); >=20 > + >=20 > + if (IsEspiSecondSlaveSupported ()) { >=20 > + Cs1IoEnableDecodingOrg =3D PciSegmentRead16 (LpcBaseAddr + > R_ESPI_CFG_CS1IORE); >=20 > + } else { >=20 > + Cs1IoEnableDecodingOrg =3D 0; >=20 > + } >=20 > + >=20 > + if (SlaveId =3D=3D SlaveEspiCS1) { >=20 > + if (IoEnableDecoding =3D=3D Cs1IoEnableDecodingOrg) { >=20 > + return EFI_SUCCESS; >=20 > + } else { >=20 > + IoEnableDecodingMerged =3D (Cs0IoEnableDecodingOrg | > IoEnableDecoding); >=20 > + } >=20 > + } else { >=20 > + if ((IoEnableDecoding | Cs1IoEnableDecodingOrg) =3D=3D > Cs0IoEnableDecodingOrg) { >=20 > + return EFI_SUCCESS; >=20 > + } else { >=20 > + IoEnableDecodingMerged =3D (Cs1IoEnableDecodingOrg | > IoEnableDecoding); >=20 > + } >=20 > + } >=20 > + >=20 > + Status =3D PchDmiSetLpcIoEnable (IoEnableDecodingMerged); >=20 > + if (EFI_ERROR (Status)) { >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + return Status; >=20 > + } >=20 > + >=20 > + // >=20 > + // program PCI offset 82h for LPC/eSPI. >=20 > + // >=20 > + PciSegmentWrite16 (LpcBaseAddr + R_LPC_CFG_IOE, > IoEnableDecodingMerged); >=20 > + >=20 > + if (SlaveId =3D=3D SlaveEspiCS1) { >=20 > + // >=20 > + // For eSPI CS1# device program eSPI PCI offset A0h. >=20 > + // >=20 > + PciSegmentWrite16 (LpcBaseAddr + R_ESPI_CFG_CS1IORE, > IoEnableDecoding); >=20 > + } >=20 > + >=20 > + return Status; >=20 > +} >=20 > + >=20 > +/** >=20 > + Set PCH LPC and eSPI CS0# IO enable decoding. >=20 > + Setup I/O Enables in DMI to the same value program in LPC/eSPI PCI off= set > 82h. >=20 > + Note: Bit[15:10] of the source decode register is Read-Only. The IO ra= nge > indicated by the Enables field >=20 > + in LPC/eSPI PCI offset 82h[13:10] is always forwarded by DMI to > subtractive agent for handling. >=20 > + Please check EDS for detail of LPC/eSPI IO decode ranges bit definitio= n. >=20 > + >=20 > + @param[in] LpcIoEnableDecoding LPC IO enable decoding bit setti= ngs. >=20 > + >=20 > + @retval EFI_SUCCESS Successfully completed. >=20 > + @retval EFI_UNSUPPORTED DMIC.SRL is set. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +PchLpcIoEnableDecodingSet ( >=20 > + IN UINT16 LpcIoEnableDecoding >=20 > + ) >=20 > +{ >=20 > + return LpcEspiIoEnableDecodingSetHelper (LpcIoEnableDecoding, > SlaveLpcEspiCS0); >=20 > +} >=20 > + >=20 > +/** >=20 > + Set PCH eSPI CS1# IO enable decoding. >=20 > + Setup I/O Enables in DMI to the same value program in eSPI PCI offset = A0h > (eSPI CS1#). >=20 > + Note: Bit[15:10] of the source decode register is Read-Only. The IO ra= nge > indicated by the Enables field >=20 > + in eSPI PCI offset A0h[13:10] is always forwarded by DMI to subtractiv= e > agent for handling. >=20 > + Please check EDS for detail of eSPI IO decode ranges bit definition. >=20 > + >=20 > + @param[in] IoEnableDecoding eSPI IO enable decoding bit sett= ings. >=20 > + >=20 > + @retval EFI_SUCCESS Successfully completed. >=20 > + @retval EFI_UNSUPPORTED DMI configuration is locked >=20 > +**/ >=20 > +EFI_STATUS >=20 > +PchEspiCs1IoEnableDecodingSet ( >=20 > + IN UINT16 IoEnableDecoding >=20 > + ) >=20 > +{ >=20 > + if (!IsEspiSecondSlaveSupported ()) { >=20 > + return EFI_UNSUPPORTED; >=20 > + } >=20 > + >=20 > + return LpcEspiIoEnableDecodingSetHelper (IoEnableDecoding, > SlaveEspiCS1); >=20 > +} >=20 > + >=20 > + >=20 > +/** >=20 > + Get IO APIC regsiters base address. >=20 > + >=20 > + @param[out] IoApicBase Buffer of IO APIC regsiter addre= ss >=20 > + >=20 > + @retval EFI_SUCCESS Successfully completed. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +PchIoApicBaseGet ( >=20 > + OUT UINT32 *IoApicBase >=20 > + ) >=20 > +{ >=20 > + *IoApicBase =3D PcdGet32 (PcdSiIoApicBaseAddress); >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > +/** >=20 > + Get HPET base address. >=20 > + >=20 > + @param[out] HpetBase Buffer of HPET base address >=20 > + >=20 > + @retval EFI_SUCCESS Successfully completed. >=20 > + @retval EFI_INVALID_PARAMETER Invalid offset passed. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +PchHpetBaseGet ( >=20 > + OUT UINT32 *HpetBase >=20 > + ) >=20 > +{ >=20 > + if (HpetBase =3D=3D NULL) { >=20 > + DEBUG ((DEBUG_ERROR, "PchHpetBaseGet Error. Invalid pointer.\n")); >=20 > + ASSERT (FALSE); >=20 > + return EFI_INVALID_PARAMETER; >=20 > + } >=20 > + >=20 > + *HpetBase =3D PcdGet32 (PcdSiHpetBaseAddress); >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/PeiDxeSmmPchCycleDecodin > gLib/PeiDxeSmmPchCycleDecodingLib.inf > b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/PeiDxeSmmPchCycleDecodin > gLib/PeiDxeSmmPchCycleDecodingLib.inf > new file mode 100644 > index 0000000000..ea6b434f29 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/PeiDxeSmmPchCycleDecodin > gLib/PeiDxeSmmPchCycleDecodingLib.inf > @@ -0,0 +1,42 @@ > +## @file >=20 > +# PCH cycle decoding Lib. >=20 > +# >=20 > +# All function in this library is available for PEI, DXE, and SMM, >=20 > +# But do not support UEFI RUNTIME environment call. >=20 > +# >=20 > +# Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > +# SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +# >=20 > +## >=20 > + >=20 > + >=20 > +[Defines] >=20 > +INF_VERSION =3D 0x00010017 >=20 > +BASE_NAME =3D PeiDxeSmmPchCycleDecodingLib >=20 > +FILE_GUID =3D 676C749F-9CD1-46B7-BAFD-4B1BC36B4C8E >=20 > +VERSION_STRING =3D 1.0 >=20 > +MODULE_TYPE =3D BASE >=20 > +LIBRARY_CLASS =3D PchCycleDecodingLib >=20 > + >=20 > + >=20 > +[LibraryClasses] >=20 > +BaseLib >=20 > +IoLib >=20 > +DebugLib >=20 > +PciSegmentLib >=20 > +PchInfoLib >=20 > +PchPcrLib >=20 > +PchDmiLib >=20 > +EspiLib >=20 > +PchPciBdfLib >=20 > + >=20 > +[Packages] >=20 > +MdePkg/MdePkg.dec >=20 > +TigerlakeSiliconPkg/SiPkg.dec >=20 > + >=20 > +[Sources] >=20 > +PchCycleDecodingLib.c >=20 > + >=20 > +[Pcd] >=20 > +gSiPkgTokenSpaceGuid.PcdSiHpetBaseAddress ## CONSUMES >=20 > +gSiPkgTokenSpaceGuid.PcdSiIoApicBaseAddress ## CONSUMES >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib/PchIn= f > oLib.c > b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib/PchIn > foLib.c > new file mode 100644 > index 0000000000..df8a23d5a3 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib/PchIn > foLib.c > @@ -0,0 +1,127 @@ > +/** @file >=20 > + Pch information library. >=20 > + >=20 > + All function in this library is available for PEI, DXE, and SMM, >=20 > + But do not support UEFI RUNTIME environment call. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include "PchInfoLibPrivate.h" >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +/** >=20 > + Return Pch Series >=20 > + >=20 > + @retval PCH_SERIES Pch Series >=20 > +**/ >=20 > +PCH_SERIES >=20 > +PchSeries ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return PCH_LP; >=20 > +} >=20 > + >=20 > +/** >=20 > + Return Pch stepping type >=20 > + >=20 > + @retval PCH_STEPPING Pch stepping type >=20 > +**/ >=20 > +PCH_STEPPING >=20 > +PchStepping ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return 0; >=20 > +} >=20 > + >=20 > +/** >=20 > + Check if this is TGL PCH generation >=20 > + >=20 > + @retval TRUE It's TGL PCH >=20 > + @retval FALSE It's not TGL PCH >=20 > +**/ >=20 > +BOOLEAN >=20 > +IsTglPch ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return (PchGeneration () =3D=3D TGL_PCH); >=20 > +} >=20 > + >=20 > +/** >=20 > + Get PCH stepping ASCII string. >=20 > + Function determines major and minor stepping versions and writes them > into a buffer. >=20 > + The return string is zero terminated >=20 > + >=20 > + @param [out] Buffer Output buffer of string >=20 > + @param [in] BufferSize Buffer size. >=20 > + Must not be less then > PCH_STEPPING_STR_LENGTH_MAX >=20 > + >=20 > + @retval EFI_SUCCESS String copied successfully >=20 > + @retval EFI_INVALID_PARAMETER The stepping is not supported, o= r > parameters are NULL >=20 > + @retval EFI_BUFFER_TOO_SMALL Input buffer size is too small >=20 > +**/ >=20 > +EFI_STATUS >=20 > +PchGetSteppingStr ( >=20 > + OUT CHAR8 *Buffer, >=20 > + IN UINT32 BufferSize >=20 > + ) >=20 > +{ >=20 > + PCH_STEPPING PchStep; >=20 > + >=20 > + PchStep =3D PchStepping (); >=20 > + >=20 > + if ((Buffer =3D=3D NULL) || (BufferSize =3D=3D 0)) { >=20 > + return EFI_INVALID_PARAMETER; >=20 > + } >=20 > + if (BufferSize < PCH_STEPPING_STR_LENGTH_MAX) { >=20 > + return EFI_BUFFER_TOO_SMALL; >=20 > + } >=20 > + >=20 > + PchPrintSteppingStr (Buffer, BufferSize, PchStep); >=20 > + >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > +/** >=20 > + Get Pch Maximum Pcie Controller Number >=20 > + >=20 > + @retval Pch Maximum Pcie Root Port Number >=20 > +**/ >=20 > +UINT8 >=20 > +GetPchMaxPcieControllerNum ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return GetPchMaxPciePortNum () / PCH_PCIE_CONTROLLER_PORTS; >=20 > +} >=20 > + >=20 > +/** >=20 > + return support status for P2SB PCR 20-bit addressing >=20 > + >=20 > + @retval TRUE >=20 > + @retval FALSE >=20 > +**/ >=20 > +BOOLEAN >=20 > +IsP2sb20bPcrSupported ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return FALSE; >=20 > +} >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib/PchIn= f > oLibPrivate.h > b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib/PchIn > foLibPrivate.h > new file mode 100644 > index 0000000000..a93c3dbafd > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib/PchIn > foLibPrivate.h > @@ -0,0 +1,58 @@ > +/** @file >=20 > + Private header for PCH Info Lib. >=20 > + >=20 > + All function in this library is available for PEI, DXE, and SMM, >=20 > + But do not support UEFI RUNTIME environment call. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +/** >=20 > + Structure for PCH SKU string mapping >=20 > +**/ >=20 > +struct PCH_SKU_STRING { >=20 > + UINT16 Id; >=20 > + CHAR8 *String; >=20 > +}; >=20 > + >=20 > +/** >=20 > + Determine Pch Series based on Device Id >=20 > + >=20 > + @param[in] LpcDeviceId Lpc Device Id >=20 > + >=20 > + @retval PCH_SERIES Pch Series >=20 > +**/ >=20 > +PCH_SERIES >=20 > +PchSeriesFromLpcDid ( >=20 > + IN UINT16 LpcDeviceId >=20 > + ); >=20 > + >=20 > +/** >=20 > +Determine Pch Generation based on Device Id >=20 > + >=20 > +@param[in] LpcDeviceId Lpc Device Id >=20 > + >=20 > +@retval PCH_GENERATION Pch Generation >=20 > +**/ >=20 > +PCH_GENERATION >=20 > +PchGenerationFromDid ( >=20 > + IN UINT16 LpcDeviceId >=20 > + ); >=20 > + >=20 > +/** >=20 > + Print Pch Stepping String >=20 > + >=20 > + @param[out] Buffer Output buffer of string >=20 > + @param[in] BufferSize Buffer Size >=20 > + @param[in] PchStep Pch Stepping Type >=20 > + >=20 > + @retval VOID >=20 > +**/ >=20 > +VOID >=20 > +PchPrintSteppingStr ( >=20 > + OUT CHAR8 *Buffer, >=20 > + IN UINT32 BufferSize, >=20 > + IN PCH_STEPPING PchStep >=20 > + ); >=20 > + >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib/PchIn= f > oLibTgl.c > b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib/PchIn > foLibTgl.c > new file mode 100644 > index 0000000000..bb3c7975e8 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib/PchIn > foLibTgl.c > @@ -0,0 +1,715 @@ > +/** @file >=20 > + Pch information library for TGL. >=20 > + >=20 > + All function in this library is available for PEI, DXE, and SMM, >=20 > + But do not support UEFI RUNTIME environment call. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include "PchInfoLibPrivate.h" >=20 > +#include >=20 > +#include >=20 > + >=20 > +/** >=20 > + Print Pch Stepping String >=20 > + >=20 > + @param[out] Buffer Output buffer of string >=20 > + @param[in] BufferSize Buffer Size >=20 > + @param[in] PchStep Pch Stepping Type >=20 > + >=20 > + @retval VOID >=20 > +**/ >=20 > +VOID >=20 > +PchPrintSteppingStr ( >=20 > + OUT CHAR8 *Buffer, >=20 > + IN UINT32 BufferSize, >=20 > + IN PCH_STEPPING PchStep >=20 > + ) >=20 > +{ >=20 > + AsciiSPrint (Buffer, BufferSize, "%c%c", 'A' + (PchStep >> 4), '0' + (= PchStep > & 0xF)); >=20 > +} >=20 > + >=20 > +/** >=20 > + Return Pch Generation >=20 > + >=20 > + @retval PCH_GENERATION Pch Generation >=20 > +**/ >=20 > +PCH_GENERATION >=20 > +PchGeneration ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return TGL_PCH; >=20 > +} >=20 > + >=20 > + >=20 > +/** >=20 > + Get PCH series ASCII string. >=20 > + >=20 > + @retval PCH Series string >=20 > +**/ >=20 > +CHAR8* >=20 > +PchGetSeriesStr ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + switch (PchSeries ()) { >=20 > + >=20 > + case PCH_LP: >=20 > + return "TGL PCH-LP"; >=20 > + >=20 > + default: >=20 > + return NULL; >=20 > + } >=20 > +} >=20 > + >=20 > +/** >=20 > + Get Pch Maximum Pcie Clock Number >=20 > + >=20 > + @retval Pch Maximum Pcie Clock Number >=20 > +**/ >=20 > +UINT8 >=20 > +GetPchMaxPcieClockNum ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return 7; >=20 > +} >=20 > + >=20 > +/** >=20 > + Get Pch Maximum Pcie ClockReq Number >=20 > + >=20 > + @retval Pch Maximum Pcie ClockReq Number >=20 > +**/ >=20 > +UINT8 >=20 > +GetPchMaxPcieClockReqNum ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return GetPchMaxPcieClockNum (); >=20 > +} >=20 > + >=20 > +/** >=20 > + Get Pch Maximum Type C Port Number >=20 > + >=20 > + @retval Pch Maximum Type C Port Number >=20 > +**/ >=20 > +UINT8 >=20 > +GetPchMaxTypeCPortNum ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + switch (PchSeries ()) { >=20 > + case PCH_LP: >=20 > + return 4; >=20 > + default: >=20 > + return 0; >=20 > + } >=20 > +} >=20 > + >=20 > +/** >=20 > + Check whether integrated LAN controller is supported by PCH Series. >=20 > + >=20 > + @retval TRUE GbE is supported in current PCH >=20 > + @retval FALSE GbE is not supported on current PCH >=20 > +**/ >=20 > +BOOLEAN >=20 > +PchIsGbeSupported ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return TRUE; >=20 > +} >=20 > + >=20 > +/** >=20 > + Check whether integrated TSN is supported by PCH Series. >=20 > + >=20 > + @retval TRUE TSN is supported in current PCH >=20 > + @retval FALSE TSN is not supported on current PCH >=20 > +**/ >=20 > +BOOLEAN >=20 > +PchIsTsnSupported ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > +#if FixedPcdGet8(PcdEmbeddedEnable) =3D=3D 0x1 >=20 > + return TRUE; >=20 > +#else >=20 > + return FALSE; >=20 > +#endif >=20 > +} >=20 > + >=20 > +/** >=20 > + Check whether ISH is supported by PCH Series. >=20 > + >=20 > + @retval TRUE ISH is supported in current PCH >=20 > + @retval FALSE ISH is not supported on current PCH >=20 > +**/ >=20 > +BOOLEAN >=20 > +PchIsIshSupported ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return TRUE; >=20 > +} >=20 > + >=20 > +/** >=20 > + Get Pch Maximum Pcie Root Port Number >=20 > + >=20 > + @retval Pch Maximum Pcie Root Port Number >=20 > +**/ >=20 > +UINT8 >=20 > +GetPchMaxPciePortNum ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + switch (PchSeries ()) { >=20 > + case PCH_LP: >=20 > + return 12; >=20 > + default: >=20 > + return 0; >=20 > + } >=20 > +} >=20 > + >=20 > +/** >=20 > + Get Pch Maximum Hda Dmic Link >=20 > + >=20 > + @retval Pch Maximum Hda Dmic Link >=20 > +**/ >=20 > +UINT8 >=20 > +GetPchHdaMaxDmicLinkNum ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return 2; >=20 > +} >=20 > + >=20 > +/** >=20 > + Get Pch Maximum Hda Sndw Link >=20 > + >=20 > + @retval Pch Maximum Hda Sndw Link >=20 > +**/ >=20 > +UINT8 >=20 > +GetPchHdaMaxSndwLinkNum ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return 4; >=20 > +} >=20 > + >=20 > +/** >=20 > + Get Pch Maximum Hda Ssp Link >=20 > + >=20 > + @retval Pch Maximum Hda Ssp Link >=20 > +**/ >=20 > +UINT8 >=20 > +GetPchHdaMaxSspLinkNum ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return 3; >=20 > +} >=20 > + >=20 > +/** >=20 > + Check if given Audio Interface is supported >=20 > + >=20 > + @param[in] AudioLinkType Link type support to be checked >=20 > + @param[in] AudioLinkIndex Link number >=20 > + >=20 > + @retval TRUE Link supported >=20 > + @retval FALSE Link not supported >=20 > +**/ >=20 > +BOOLEAN >=20 > +IsAudioInterfaceSupported ( >=20 > + IN HDAUDIO_LINK_TYPE AudioLinkType, >=20 > + IN UINT32 AudioLinkIndex >=20 > + ) >=20 > +{ >=20 > + // >=20 > + // Interfaces supported: >=20 > + // 1. HDA Link (SDI0/SDI1) >=20 > + // 2. Display Audio Link (SDI2) >=20 > + // 3. SSP[0-5] >=20 > + // 4. SNDW[1-4] >=20 > + // >=20 > + switch (AudioLinkType) { >=20 > + case HdaLink: >=20 > + case HdaIDispLink: >=20 > + return TRUE; >=20 > + case HdaDmic: >=20 > + if (AudioLinkIndex < 2) { >=20 > + return TRUE; >=20 > + } else { >=20 > + return FALSE; >=20 > + } >=20 > + case HdaSsp: >=20 > + if (AudioLinkIndex < 6) { >=20 > + return TRUE; >=20 > + } else { >=20 > + return FALSE; >=20 > + } >=20 > + case HdaSndw: >=20 > + if (AudioLinkIndex < 1) { >=20 > + return TRUE; >=20 > + } else if (AudioLinkIndex < 4) { >=20 > + return TRUE; >=20 > + } else { >=20 > + return FALSE; >=20 > + } >=20 > + default: >=20 > + return FALSE; >=20 > + } >=20 > +} >=20 > + >=20 > +/** >=20 > + Check if given Display Audio Link T-Mode is supported >=20 > + >=20 > + @param[in] Tmode T-mode support to be checked >=20 > + >=20 > + @retval TRUE T-mode supported >=20 > + @retval FALSE T-mode not supported >=20 > +**/ >=20 > +BOOLEAN >=20 > +IsAudioIDispTmodeSupported ( >=20 > + IN HDAUDIO_IDISP_TMODE Tmode >=20 > + ) >=20 > +{ >=20 > + // >=20 > + // iDisplay Audio Link T-mode support per PCH Generation/Series: >=20 > + // 1. 2T - TGL-LP/H/N >=20 > + // 2. 4T - TGL-LP (default), TGL-H, TGL-N >=20 > + // 3. 8T - TGL-H, TGL-N (default) >=20 > + // 4. 16T - TGL-H, TGL-N (not-POR) >=20 > + // >=20 > + switch (Tmode) { >=20 > + case HdaIDispMode1T: >=20 > + return FALSE; >=20 > + case HdaIDispMode2T: >=20 > + case HdaIDispMode4T: >=20 > + case HdaIDispMode8T: >=20 > + return TRUE; >=20 > + case HdaIDispMode16T: >=20 > + return FALSE; >=20 > + default: >=20 > + return FALSE; >=20 > + } >=20 > +} >=20 > + >=20 > +/** >=20 > +Get Pch Usb2 Maximum Physical Port Number >=20 > + >=20 > +@retval Pch Usb2 Maximum Physical Port Number >=20 > +**/ >=20 > +UINT8 >=20 > +GetPchUsb2MaxPhysicalPortNum( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + switch (PchSeries()) { >=20 > + case PCH_LP: >=20 > + return 10; >=20 > + default: >=20 > + return 0; >=20 > + } >=20 > +} >=20 > + >=20 > +/** >=20 > +Get Pch Maximum Usb2 Port Number of XHCI Controller >=20 > + >=20 > +@retval Pch Maximum Usb2 Port Number of XHCI Controller >=20 > +**/ >=20 > +UINT8 >=20 > +GetPchXhciMaxUsb2PortNum( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + switch (PchSeries()) { >=20 > + case PCH_LP: >=20 > + return 12; >=20 > + default: >=20 > + return 0; >=20 > + } >=20 > +} >=20 > + >=20 > +/** >=20 > +Get Pch Maximum Usb3 Port Number of XHCI Controller >=20 > + >=20 > +@retval Pch Maximum Usb3 Port Number of XHCI Controller >=20 > +**/ >=20 > +UINT8 >=20 > +GetPchXhciMaxUsb3PortNum( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + switch (PchSeries()) { >=20 > + case PCH_LP: >=20 > + return 4; >=20 > + default: >=20 > + return 0; >=20 > + } >=20 > +} >=20 > + >=20 > +/** >=20 > + Gets the maximum number of UFS controller supported by this chipset. >=20 > + >=20 > + @return Number of supported UFS controllers >=20 > +**/ >=20 > +UINT8 >=20 > +PchGetMaxUfsNum ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return 2; >=20 > +} >=20 > + >=20 > +/** >=20 > + Check if this chipset supports eMMC controller >=20 > + >=20 > + @retval BOOLEAN TRUE if supported, FALSE otherwise >=20 > +**/ >=20 > +BOOLEAN >=20 > +IsPchEmmcSupported ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return FALSE; >=20 > +} >=20 > + >=20 > +/** >=20 > + Check if this chipset supports SD controller >=20 > + >=20 > + @retval BOOLEAN TRUE if supported, FALSE otherwise >=20 > +**/ >=20 > +BOOLEAN >=20 > +IsPchSdCardSupported ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return FALSE; >=20 > +} >=20 > + >=20 > +/** >=20 > + Check if this chipset supports THC controller >=20 > + >=20 > + @retval BOOLEAN TRUE if supported, FALSE otherwise >=20 > +**/ >=20 > +BOOLEAN >=20 > +IsPchThcSupported ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return TRUE; >=20 > +} >=20 > + >=20 > +/** >=20 > + Check if this chipset supports HSIO BIOS Sync >=20 > + >=20 > + @retval BOOLEAN TRUE if supported, FALSE otherwise >=20 > +**/ >=20 > +BOOLEAN >=20 > +IsPchChipsetInitSyncSupported ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return TRUE; >=20 > +} >=20 > + >=20 > +/** >=20 > + Check if link between PCH and CPU is an P-DMI >=20 > + >=20 > + @retval TRUE P-DMI link >=20 > + @retval FALSE Not an P-DMI link >=20 > +**/ >=20 > +BOOLEAN >=20 > +IsPchWithPdmi ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return FALSE; >=20 > +} >=20 > + >=20 > +/** >=20 > + Check whether ATX Shutdown (PS_ON) is supported. >=20 > + >=20 > + @retval TRUE ATX Shutdown (PS_ON) is supported in PCH >=20 > + @retval FALSE ATX Shutdown (PS_ON) is not supported by PCH >=20 > +**/ >=20 > +BOOLEAN >=20 > +IsPchPSOnSupported ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return FALSE; >=20 > +} >=20 > + >=20 > +/** >=20 > + Check if link between PCH and CPU is an OP-DMI >=20 > + >=20 > + @retval TRUE OP-DMI link >=20 > + @retval FALSE Not an OP-DMI link >=20 > +**/ >=20 > +BOOLEAN >=20 > +IsPchWithOpdmi ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return TRUE; >=20 > +} >=20 > + >=20 > +/** >=20 > + Check if link between PCH and CPU is an F-DMI >=20 > + >=20 > + @retval TRUE F-DMI link >=20 > + @retval FALSE Not an F-DMI link >=20 > +**/ >=20 > +BOOLEAN >=20 > +IsPchWithFdmi ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return FALSE; >=20 > +} >=20 > +/** >=20 > + Get Pch Maximum ISH UART Controller number >=20 > + >=20 > + @retval Pch Maximum ISH UART controllers number >=20 > +**/ >=20 > +UINT8 >=20 > +GetPchMaxIshUartControllersNum ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return 2; >=20 > +} >=20 > + >=20 > +/** >=20 > + Get Pch Maximum ISH I2C Controller number >=20 > + >=20 > + @retval Pch Maximum ISH I2C controllers number >=20 > +**/ >=20 > +UINT8 >=20 > +GetPchMaxIshI2cControllersNum ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return 3; >=20 > +} >=20 > + >=20 > +/** >=20 > + Get Pch Maximum ISH I3C Controller number >=20 > + >=20 > + @retval Pch Maximum ISH I3C controllers number >=20 > +**/ >=20 > +UINT8 >=20 > +GetPchMaxIshI3cControllersNum ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return 0; >=20 > +} >=20 > + >=20 > +/** >=20 > + Get Pch Maximum ISH SPI Controller number >=20 > + >=20 > + @retval Pch Maximum ISH SPI controllers number >=20 > +**/ >=20 > +UINT8 >=20 > +GetPchMaxIshSpiControllersNum ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return 1; >=20 > +} >=20 > + >=20 > +/** >=20 > + Get Pch Maximum ISH SPI Controller Cs pins number >=20 > + >=20 > + @retval Pch Maximum ISH SPI controller Cs pins number >=20 > +**/ >=20 > +UINT8 >=20 > +GetPchMaxIshSpiControllerCsPinsNum ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return 1; >=20 > +} >=20 > + >=20 > +/** >=20 > + Get Pch Maximum ISH GP number >=20 > + >=20 > + @retval Pch Maximum ISH GP number >=20 > +**/ >=20 > +UINT8 >=20 > +GetPchMaxIshGpNum ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return 8; >=20 > +} >=20 > + >=20 > +/** >=20 > + Get Pch Maximum Serial IO I2C controllers number >=20 > + >=20 > + @retval Pch Maximum Serial IO I2C controllers number >=20 > +**/ >=20 > +UINT8 >=20 > +GetPchMaxSerialIoI2cControllersNum ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return 6; >=20 > +} >=20 > + >=20 > +/** >=20 > + Get Pch Maximum Serial IO SPI controllers number >=20 > + >=20 > + @retval Pch Maximum Serial IO SPI controllers number >=20 > +**/ >=20 > +UINT8 >=20 > +GetPchMaxSerialIoSpiControllersNum ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return 4; >=20 > +} >=20 > + >=20 > +/** >=20 > + Get Pch Maximum Serial IO UART controllers number >=20 > + >=20 > + @retval Pch Maximum Serial IO UART controllers number >=20 > +**/ >=20 > +UINT8 >=20 > +GetPchMaxSerialIoUartControllersNum ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return 4; >=20 > +} >=20 > + >=20 > +/** >=20 > + Get Pch Maximum Serial IO SPI Chip Selects count >=20 > + >=20 > + @retval Pch Maximum Serial IO SPI Chip Selects number >=20 > +**/ >=20 > +UINT8 >=20 > +GetPchMaxSerialIoSpiChipSelectsNum ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return 2; >=20 > +} >=20 > + >=20 > +/** >=20 > + Get Pch Maximum ME Applet count >=20 > + >=20 > + @retval Pch Maximum ME Applet number >=20 > +**/ >=20 > +UINT8 >=20 > +GetPchMaxMeAppletCount ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return 31; >=20 > +} >=20 > + >=20 > +/** >=20 > + Get Pch Maximum ME Session count >=20 > + >=20 > + @retval Pch Maximum ME Sesion number >=20 > +**/ >=20 > +UINT8 >=20 > +GetPchMaxMeSessionCount ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return 16; >=20 > +} >=20 > + >=20 > +/** >=20 > + Get Pch Maximum THC count >=20 > + >=20 > + @retval Pch Maximum THC count number >=20 > +**/ >=20 > +UINT8 >=20 > +GetPchMaxThcCount ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return 2; >=20 > +} >=20 > + >=20 > +/** >=20 > + Returns a frequency of the sosc_clk signal. >=20 > + All SATA controllers on the system are assumed to >=20 > + work on the same sosc_clk frequency. >=20 > + >=20 > + @retval Frequency of the sosc_clk signal. >=20 > +**/ >=20 > +SATA_SOSC_CLK_FREQ >=20 > +GetSataSoscClkFreq ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return SataSosc100Mhz; >=20 > +} >=20 > + >=20 > +/** >=20 > + Check if SATA support should be awake after function disable >=20 > + >=20 > + @retval TRUE >=20 > + @retval FALSE >=20 > +**/ >=20 > +BOOLEAN >=20 > +IsSataSupportWakeAfterFunctionDisable ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return TRUE; >=20 > +} >=20 > + >=20 > +/** >=20 > + Returns USB2 PHY Reference Clock frequency value used by PCH >=20 > + This defines what electrical tuning parameters shall be used >=20 > + during USB2 PHY initialization programming >=20 > + >=20 > + @retval Frequency reference clock for USB2 PHY >=20 > +**/ >=20 > +USB2_PHY_REF_FREQ >=20 > +GetUsb2PhyRefFreq ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return FREQ_19_2; >=20 > +} >=20 > + >=20 > +/** >=20 > + Check if SPI in a given PCH generation supports an Extended BIOS Range > Decode >=20 > + >=20 > + @retval TRUE or FALSE if PCH supports Extended BIOS Range Decode >=20 > +**/ >=20 > +BOOLEAN >=20 > +IsExtendedBiosRangeDecodeSupported ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return TRUE; >=20 > +} >=20 > + >=20 > +#define SPI_PCH_LP_DMI_TARGET 0x23A8 >=20 > + >=20 > +/** >=20 > + Returns DMI target for current PCH SPI >=20 > + >=20 > + @retval PCH SPI DMI target value >=20 > +**/ >=20 > +UINT16 >=20 > +GetPchSpiDmiTarget ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return SPI_PCH_LP_DMI_TARGET; >=20 > +} >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib/PeiDx > eSmmPchInfoLibTgl.inf > b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib/PeiDx > eSmmPchInfoLibTgl.inf > new file mode 100644 > index 0000000000..4b3fb988d2 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib/PeiDx > eSmmPchInfoLibTgl.inf > @@ -0,0 +1,43 @@ > +## @file >=20 > +# PCH information library for TigerLake PCH. >=20 > +# >=20 > +# All function in this library is available for PEI, DXE, and SMM, >=20 > +# But do not support UEFI RUNTIME environment call. >=20 > +# >=20 > +# Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > +# SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +# >=20 > +## >=20 > + >=20 > + >=20 > +[Defines] >=20 > +INF_VERSION =3D 0x00010017 >=20 > +BASE_NAME =3D PeiDxeSmmPchInfoLibTgl >=20 > +FILE_GUID =3D 253B9BFC-026F-4BB4-AC2C-AC167BC0F43C >=20 > +VERSION_STRING =3D 1.0 >=20 > +MODULE_TYPE =3D BASE >=20 > +LIBRARY_CLASS =3D PchInfoLib >=20 > + >=20 > + >=20 > +[LibraryClasses] >=20 > +BaseLib >=20 > +IoLib >=20 > +DebugLib >=20 > +PrintLib >=20 > +PciSegmentLib >=20 > +PchPcrLib >=20 > +PcdLib >=20 > +PchPciBdfLib >=20 > + >=20 > + >=20 > +[Packages] >=20 > +MdePkg/MdePkg.dec >=20 > +TigerlakeSiliconPkg/SiPkg.dec >=20 > + >=20 > + >=20 > +[Sources] >=20 > +PchInfoLib.c >=20 > +PchInfoLibTgl.c >=20 > + >=20 > +[Pcd] >=20 > +gSiPkgTokenSpaceGuid.PcdEmbeddedEnable ## CONSUME= S >=20 > -- > 2.24.0.windows.2