Re: [PATCH 09/40] TigerlakeSiliconPkg/Fru: Add TglCpu/Include headers

["Nate DeSimone" <nathaniel.l.desimone@intel.com>]

Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>

> -----Original Message-----
> From: Luo, Heng <heng.luo@intel.com>
> Sent: Sunday, January 31, 2021 5:36 PM
> To: devel@edk2.groups.io
> Cc: Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Desimone,
> Nathaniel L <nathaniel.l.desimone@intel.com>
> Subject: [PATCH 09/40] TigerlakeSiliconPkg/Fru: Add TglCpu/Include headers
> 
> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171
> 
> Adds the following header files:
>   * Fru/TglCpu/Include
> 
> Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
> Signed-off-by: Heng Luo <heng.luo@intel.com>
> ---
> 
> Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Include/Library/CpuPcieInfoFruL
> ib.h |  57
> +++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> 
> Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Include/Register/SaRegsHostBri
> dge.h | 145
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> +++++++++++++++++++++++++++++
>  Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Include/TcssInfo.h                  |  12
> ++++++++++++
>  3 files changed, 214 insertions(+)
> 
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Include/Library/CpuPcieInfoFr
> uLib.h
> b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Include/Library/CpuPcieInfoFr
> uLib.h
> new file mode 100644
> index 0000000000..89cf952717
> --- /dev/null
> +++
> b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Include/Library/CpuPcieInfoFr
> uLib.h
> @@ -0,0 +1,57 @@
> +/** @file
> 
> +  Header file for CpuPcieInfoFruLib.
> 
> +
> 
> +  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
> 
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> 
> +**/
> 
> +#ifndef _CPU_PCIE_INFO_FRU_LIB_H_
> 
> +#define _CPU_PCIE_INFO_FRU_LIB_H_
> 
> +
> 
> +#include <CpuPcieInfo.h>
> 
> +
> 
> +#define CPU_PCIE_MAX_ROOT_PORTS       4
> 
> +
> 
> +#define CPU_PCIE_ULT_ULX_MAX_ROOT_PORT     1
> 
> +
> 
> +#include <Library/CpuRegbarAccessLib.h>
> 
> +
> 
> +/**
> 
> +  Get CPU Maximum Pcie Root Port Number
> 
> +
> 
> +  @retval PcieMaxRootPort         Pch Maximum Pcie Root Port Number
> 
> +**/
> 
> +UINT8
> 
> +GetMaxCpuPciePortNum (
> 
> +  VOID
> 
> +  );
> 
> +
> 
> +/**
> 
> +  Get CPU Pcie Root Port Device and Function Number by Root Port physical
> Number
> 
> +
> 
> +  @param[in]  RpNumber              Root port physical number. (0-based)
> 
> +  @param[out] RpDev                 Return corresponding root port device
> number.
> 
> +  @param[out] RpFun                 Return corresponding root port function
> number.
> 
> +
> 
> +  @retval     EFI_SUCCESS           Root port device and function is retrieved
> 
> +  @retval     EFI_INVALID_PARAMETER RpNumber is invalid
> 
> +**/
> 
> +EFI_STATUS
> 
> +EFIAPI
> 
> +GetCpuPcieRpDevFun (
> 
> +  IN  UINTN   RpNumber,
> 
> +  OUT UINTN   *RpDev,
> 
> +  OUT UINTN   *RpFun
> 
> +  );
> 
> +
> 
> +/**
> 
> +  Gets pci segment base address of PCIe root port.
> 
> +
> 
> +  @param  RpIndex    Root Port Index (0 based)
> 
> +  @return PCIe port  base address.
> 
> +**/
> 
> +UINT64
> 
> +CpuPcieBase (
> 
> +  IN  UINT32   RpIndex
> 
> +  );
> 
> +
> 
> +#endif // _CPU_PCIE_INFO_FRU_LIB_H_
> 
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Include/Register/SaRegsHost
> Bridge.h
> b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Include/Register/SaRegsHost
> Bridge.h
> new file mode 100644
> index 0000000000..32e38fa072
> --- /dev/null
> +++
> b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Include/Register/SaRegsHost
> Bridge.h
> @@ -0,0 +1,145 @@
> +/** @file
> 
> +  Register names for Host Bridge block
> 
> +  <b>Conventions</b>:
> 
> +  - Prefixes:
> 
> +    - Definitions beginning with "R_" are registers
> 
> +    - Definitions beginning with "B_" are bits within registers
> 
> +    - Definitions beginning with "V_" are meaningful values of bits within the
> registers
> 
> +    - Definitions beginning with "S_" are register sizes
> 
> +    - Definitions beginning with "N_" are the bit position
> 
> +  - In general, SA registers are denoted by "_SA_" in register names
> 
> +  - Registers / bits that are different between SA generations are denoted
> by
> 
> +    "_SA_[generation_name]_" in register/bit names. e.g., "_SA_HSW_"
> 
> +  - Registers / bits that are different between SKUs are denoted by
> "_[SKU_name]"
> 
> +    at the end of the register/bit names
> 
> +  - Registers / bits of new devices introduced in a SA generation will be just
> named
> 
> +    as "_SA_" without [generation_name] inserted.
> 
> +
> 
> +  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
> 
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> 
> +**/
> 
> +#ifndef _SA_REGS_HOST_BRIDGE_H_
> 
> +#define _SA_REGS_HOST_BRIDGE_H_
> 
> +
> 
> +#define SA_SEG_NUM              0x00
> 
> +#define V_SA_DEVICE_ID_INVALID  0xFFFF
> 
> +//
> 
> +// DEVICE 0 (Memory Controller Hub)
> 
> +//
> 
> +#define SA_MC_BUS          0x00
> 
> +#define SA_MC_DEV          0x00
> 
> +#define SA_MC_FUN          0x00
> 
> +#define V_SA_MC_VID        0x8086
> 
> +#define R_SA_MC_DEVICE_ID  0x02
> 
> +#define R_SA_MC_CAPID0_B   0xE8
> 
> +
> 
> +//
> 
> +// SA DMI configuration
> 
> +//
> 
> +
> 
> +//
> 
> +// Maximum DMI lanes and bundles supported (x8 and 4 lanes)
> 
> +//
> 
> +#define SA_DMI_MAX_LANE                      0x08
> 
> +#define SA_DMI_MAX_BUNDLE                    0x04
> 
> +#define SA_DMI_MAX_LANE_VER1                 0x04
> 
> +#define SA_DMI_MAX_BUNDLE_VER1               0x02
> 
> +
> 
> +
> 
> +//
> 
> +// TigerLake Mobile SA Device IDs B0:D0:F0
> 
> +//
> 
> +#define V_SA_DEVICE_ID_MB_ULT_1 0x9A14   ///< TigerLake Ult (TGL-U
> 4+2)
> 
> +#define V_SA_DEVICE_ID_MB_ULT_2 0x9A04   ///< TigerLake Ult (TGL-U
> 2+2)
> 
> +
> 
> +#define V_SA_DEVICE_ID_MB_ULX_1 0x9A12   ///< TigerLake Ulx (TGL-Y
> 4+2)
> 
> +#define V_SA_DEVICE_ID_MB_ULX_2 0x9A02   ///< TigerLake Ulx (TGL-Y
> 2+2)
> 
> +
> 
> +/**
> 
> + <b>Description</b>:
> 
> + - This is the base address for the Host Memory Mapped Configuration
> space.  There is no physical memory within this 32KB window that can be
> addressed.  The 32KB reserved by this register does not alias to any PCI 2.3
> compliant memory mapped space.  On reset, the Host MMIO Memory
> Mapped Configuation space is disabled and must be enabled by writing a 1 to
> MCHBAREN [Dev 0, offset48h, bit 0].
> 
> + - All the bits in this register are locked in LT mode.
> 
> + - The register space contains memory control, initialization, timing, and
> buffer strength registers; clocking registers; and power and thermal
> management registers.
> 
> +**/
> 
> +#define R_SA_MCHBAR  (0x48)
> 
> +
> 
> +/**
> 
> + <b>Description</b>:
> 
> + - All the bits in this register are LT lockable.
> 
> +**/
> 
> +#define R_SA_GGC (0x50)
> 
> +
> 
> +/**
> 
> + Description of GMS (8:15)
> 
> + - This field is used to select the amount of Main Memory that is pre-
> allocated to support the Internal Graphics device in VGA (non-linear) and
> Native (linear) modes.  The BIOS ensures that memory is pre-allocated only
> when Internal graphics is enabled.
> 
> + - This register is also LT lockable.
> 
> + - Valid options are 0 (0x0) to 2048MB (0x40) in multiples of 32 MB
> 
> + - All other values are reserved
> 
> + - Hardware does not clear or set any of these bits automatically based on
> IGD being disabled/enabled.
> 
> + - BIOS Requirement: BIOS must not set this field to 0h if IVD (bit 1 of this
> register) is 0.
> 
> +**/
> 
> +#define N_SA_GGC_GMS_OFFSET  (0x8)
> 
> +#define B_SA_GGC_GMS_MASK    (0xff00)
> 
> +
> 
> +/**
> 
> + Description of GGMS (6:7)
> 
> + - This field is used to select the amount of Main Memory that is pre-
> allocated to support the Internal Graphics Translation Table.  The BIOS
> ensures that memory is pre-allocated only when Internal graphics is enabled.
> 
> + - GSM is assumed to be a contiguous physical DRAM space with DSM, and
> BIOS needs to allocate a contiguous memory chunk.  Hardware will derive the
> base of GSM from DSM only using the GSM size programmed in the register.
> 
> + - Valid options:
> 
> + - 0h: 0 MB of memory pre-allocated for GTT.
> 
> + - 1h: 2 MB of memory pre-allocated for GTT.
> 
> + - 2h: 4 MB of memory pre-allocated for GTT.
> 
> + - 3h: 8 MB of memory pre-allocated for GTT.
> 
> + - Others: Reserved
> 
> + - Hardware functionality in case of programming this value to Reserved is
> not guaranteed.
> 
> +**/
> 
> +#define N_SA_GGC_GGMS_OFFSET  (0x6)
> 
> +#define B_SA_GGC_GGMS_MASK    (0xc0)
> 
> +#define V_SA_GGC_GGMS_8MB     3
> 
> +
> 
> +/**
> 
> + Description:
> 
> + - Allows for enabling/disabling of PCI devices and functions that are within
> the CPU package. The table below the bit definitions describes the behavior
> of all combinations of transactions to devices controlled by this register.
> 
> +  All the bits in this register are LT Lockable.
> 
> +**/
> 
> +#define R_SA_DEVEN (0x54)
> 
> +
> 
> +/**
> 
> + Description of D2EN (4:4)
> 
> + - 0:  Bus 0 Device 2 is disabled and hidden
> 
> + - 1:  Bus 0 Device 2 is enabled and visible
> 
> + - This bit will remain 0 if Device 2 capability is disabled.
> 
> +**/
> 
> +#define B_SA_DEVEN_D2EN_MASK     (0x10)
> 
> +
> 
> +
> 
> +///
> 
> +/// Description:
> 
> +///  The SMRAMC register controls how accesses to Compatible SMRAM
> spaces are treated.  The Open, Close and Lock bits function only when
> G_SMRAME bit is set to 1.  Also, the Open bit must be reset before the Lock
> bit is set.
> 
> +///
> 
> +#define R_SA_SMRAMC  (0x88)
> 
> +
> 
> +///
> 
> +/// Description:
> 
> +///  This register contains the base address of stolen DRAM memory for the
> GTT. BIOS determines the base of GTT stolen memory by subtracting the GTT
> graphics stolen memory size (PCI Device 0 offset 52 bits 9:8) from the
> Graphics Base of  Data Stolen Memory (PCI Device 0 offset B0 bits 31:20).
> 
> +///
> 
> +#define R_SA_BGSM  (0xb4)
> 
> +
> 
> +
> 
> +///
> 
> +/// Description:
> 
> +///  This register contains the Top of low memory address.
> 
> +///
> 
> +#define R_SA_TOLUD (0xbc)
> 
> +
> 
> +///
> 
> +/// Description of TOLUD (20:31)
> 
> +///  This register contains bits 31 to 20 of an address one byte above the
> maximum DRAM memory below 4G that is usable by the operating system.
> Address bits 31 down to 20 programmed to 01h implies a minimum memory
> size of 1MB. Configuration software must set this value to the smaller of the
> following 2 choices: maximum amount memory in the system minus ME
> stolen memory plus one byte or the minimum address allocated for PCI
> memory. Address bits 19:0 are assumed to be 0_0000h for the purposes of
> address comparison. The Host interface positively decodes an address
> towards DRAM if the incoming address is less than the value programmed in
> this register.
> 
> +///  The Top of Low Usable DRAM is the lowest address above both
> Graphics Stolen memory and Tseg. BIOS determines the base of Graphics
> Stolen Memory by subtracting the Graphics Stolen Memory Size from TOLUD
> and further decrements by Tseg size to determine base of Tseg. All the Bits in
> this register are locked in LT mode.
> 
> +///  This register must be 1MB aligned when reclaim is enabled.
> 
> +///
> 
> +#define B_SA_TOLUD_TOLUD_MASK      (0xfff00000)
> 
> +#define R_SA_MC_CAPID0_A_OFFSET    0xE4
> 
> +#define V_SA_LTR_MAX_SNOOP_LATENCY_VALUE           0x0846  ///< Intel
> recommended maximum value for Snoop Latency (70us)
> 
> +#define V_SA_LTR_MAX_NON_SNOOP_LATENCY_VALUE       0x0846  ///<
> Intel recommended maximum value for Non-Snoop Latency (70us)
> 
> +#endif
> 
> diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Include/TcssInfo.h
> b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Include/TcssInfo.h
> new file mode 100644
> index 0000000000..cd8d57d948
> --- /dev/null
> +++ b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Include/TcssInfo.h
> @@ -0,0 +1,12 @@
> +/** @file
> 
> +  Register names for TCSS USB devices
> 
> +
> 
> +  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
> 
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> 
> +**/
> 
> +#ifndef _TCSS_INFO_H_
> 
> +#define _TCSS_INFO_H_
> 
> +
> 
> +#define MAX_ITBT_PCIE_PORT        4
> 
> +
> 
> +#endif
> 
> --
> 2.24.0.windows.2