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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Nate DeSimone > -----Original Message----- > From: Luo, Heng > Sent: Sunday, January 31, 2021 5:36 PM > To: devel@edk2.groups.io > Cc: Chaganty, Rangasai V ; Desimone, > Nathaniel L > Subject: [PATCH 09/40] TigerlakeSiliconPkg/Fru: Add TglCpu/Include header= s >=20 > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3171 >=20 > Adds the following header files: > * Fru/TglCpu/Include >=20 > Cc: Sai Chaganty > Cc: Nate DeSimone > Signed-off-by: Heng Luo > --- >=20 > Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Include/Library/CpuPcieInfoF= ruL > ib.h | 57 > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Include/Register/SaRegsHostB= ri > dge.h | 145 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Include/TcssInfo.h = | 12 > ++++++++++++ > 3 files changed, 214 insertions(+) >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Include/Library/CpuPcieInf= oFr > uLib.h > b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Include/Library/CpuPcieInf= oFr > uLib.h > new file mode 100644 > index 0000000000..89cf952717 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Include/Library/CpuPcieInf= oFr > uLib.h > @@ -0,0 +1,57 @@ > +/** @file >=20 > + Header file for CpuPcieInfoFruLib. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _CPU_PCIE_INFO_FRU_LIB_H_ >=20 > +#define _CPU_PCIE_INFO_FRU_LIB_H_ >=20 > + >=20 > +#include >=20 > + >=20 > +#define CPU_PCIE_MAX_ROOT_PORTS 4 >=20 > + >=20 > +#define CPU_PCIE_ULT_ULX_MAX_ROOT_PORT 1 >=20 > + >=20 > +#include >=20 > + >=20 > +/** >=20 > + Get CPU Maximum Pcie Root Port Number >=20 > + >=20 > + @retval PcieMaxRootPort Pch Maximum Pcie Root Port Number >=20 > +**/ >=20 > +UINT8 >=20 > +GetMaxCpuPciePortNum ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Get CPU Pcie Root Port Device and Function Number by Root Port physica= l > Number >=20 > + >=20 > + @param[in] RpNumber Root port physical number. (0-based) >=20 > + @param[out] RpDev Return corresponding root port devic= e > number. >=20 > + @param[out] RpFun Return corresponding root port funct= ion > number. >=20 > + >=20 > + @retval EFI_SUCCESS Root port device and function is ret= rieved >=20 > + @retval EFI_INVALID_PARAMETER RpNumber is invalid >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +GetCpuPcieRpDevFun ( >=20 > + IN UINTN RpNumber, >=20 > + OUT UINTN *RpDev, >=20 > + OUT UINTN *RpFun >=20 > + ); >=20 > + >=20 > +/** >=20 > + Gets pci segment base address of PCIe root port. >=20 > + >=20 > + @param RpIndex Root Port Index (0 based) >=20 > + @return PCIe port base address. >=20 > +**/ >=20 > +UINT64 >=20 > +CpuPcieBase ( >=20 > + IN UINT32 RpIndex >=20 > + ); >=20 > + >=20 > +#endif // _CPU_PCIE_INFO_FRU_LIB_H_ >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Include/Register/SaRegsHos= t > Bridge.h > b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Include/Register/SaRegsHos= t > Bridge.h > new file mode 100644 > index 0000000000..32e38fa072 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Include/Register/SaRegsHos= t > Bridge.h > @@ -0,0 +1,145 @@ > +/** @file >=20 > + Register names for Host Bridge block >=20 > + Conventions: >=20 > + - Prefixes: >=20 > + - Definitions beginning with "R_" are registers >=20 > + - Definitions beginning with "B_" are bits within registers >=20 > + - Definitions beginning with "V_" are meaningful values of bits with= in the > registers >=20 > + - Definitions beginning with "S_" are register sizes >=20 > + - Definitions beginning with "N_" are the bit position >=20 > + - In general, SA registers are denoted by "_SA_" in register names >=20 > + - Registers / bits that are different between SA generations are denot= ed > by >=20 > + "_SA_[generation_name]_" in register/bit names. e.g., "_SA_HSW_" >=20 > + - Registers / bits that are different between SKUs are denoted by > "_[SKU_name]" >=20 > + at the end of the register/bit names >=20 > + - Registers / bits of new devices introduced in a SA generation will b= e just > named >=20 > + as "_SA_" without [generation_name] inserted. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _SA_REGS_HOST_BRIDGE_H_ >=20 > +#define _SA_REGS_HOST_BRIDGE_H_ >=20 > + >=20 > +#define SA_SEG_NUM 0x00 >=20 > +#define V_SA_DEVICE_ID_INVALID 0xFFFF >=20 > +// >=20 > +// DEVICE 0 (Memory Controller Hub) >=20 > +// >=20 > +#define SA_MC_BUS 0x00 >=20 > +#define SA_MC_DEV 0x00 >=20 > +#define SA_MC_FUN 0x00 >=20 > +#define V_SA_MC_VID 0x8086 >=20 > +#define R_SA_MC_DEVICE_ID 0x02 >=20 > +#define R_SA_MC_CAPID0_B 0xE8 >=20 > + >=20 > +// >=20 > +// SA DMI configuration >=20 > +// >=20 > + >=20 > +// >=20 > +// Maximum DMI lanes and bundles supported (x8 and 4 lanes) >=20 > +// >=20 > +#define SA_DMI_MAX_LANE 0x08 >=20 > +#define SA_DMI_MAX_BUNDLE 0x04 >=20 > +#define SA_DMI_MAX_LANE_VER1 0x04 >=20 > +#define SA_DMI_MAX_BUNDLE_VER1 0x02 >=20 > + >=20 > + >=20 > +// >=20 > +// TigerLake Mobile SA Device IDs B0:D0:F0 >=20 > +// >=20 > +#define V_SA_DEVICE_ID_MB_ULT_1 0x9A14 ///< TigerLake Ult (TGL-U > 4+2) >=20 > +#define V_SA_DEVICE_ID_MB_ULT_2 0x9A04 ///< TigerLake Ult (TGL-U > 2+2) >=20 > + >=20 > +#define V_SA_DEVICE_ID_MB_ULX_1 0x9A12 ///< TigerLake Ulx (TGL-Y > 4+2) >=20 > +#define V_SA_DEVICE_ID_MB_ULX_2 0x9A02 ///< TigerLake Ulx (TGL-Y > 2+2) >=20 > + >=20 > +/** >=20 > + Description: >=20 > + - This is the base address for the Host Memory Mapped Configuration > space. There is no physical memory within this 32KB window that can be > addressed. The 32KB reserved by this register does not alias to any PCI = 2.3 > compliant memory mapped space. On reset, the Host MMIO Memory > Mapped Configuation space is disabled and must be enabled by writing a 1 = to > MCHBAREN [Dev 0, offset48h, bit 0]. >=20 > + - All the bits in this register are locked in LT mode. >=20 > + - The register space contains memory control, initialization, timing, a= nd > buffer strength registers; clocking registers; and power and thermal > management registers. >=20 > +**/ >=20 > +#define R_SA_MCHBAR (0x48) >=20 > + >=20 > +/** >=20 > + Description: >=20 > + - All the bits in this register are LT lockable. >=20 > +**/ >=20 > +#define R_SA_GGC (0x50) >=20 > + >=20 > +/** >=20 > + Description of GMS (8:15) >=20 > + - This field is used to select the amount of Main Memory that is pre- > allocated to support the Internal Graphics device in VGA (non-linear) and > Native (linear) modes. The BIOS ensures that memory is pre-allocated onl= y > when Internal graphics is enabled. >=20 > + - This register is also LT lockable. >=20 > + - Valid options are 0 (0x0) to 2048MB (0x40) in multiples of 32 MB >=20 > + - All other values are reserved >=20 > + - Hardware does not clear or set any of these bits automatically based = on > IGD being disabled/enabled. >=20 > + - BIOS Requirement: BIOS must not set this field to 0h if IVD (bit 1 of= this > register) is 0. >=20 > +**/ >=20 > +#define N_SA_GGC_GMS_OFFSET (0x8) >=20 > +#define B_SA_GGC_GMS_MASK (0xff00) >=20 > + >=20 > +/** >=20 > + Description of GGMS (6:7) >=20 > + - This field is used to select the amount of Main Memory that is pre- > allocated to support the Internal Graphics Translation Table. The BIOS > ensures that memory is pre-allocated only when Internal graphics is enabl= ed. >=20 > + - GSM is assumed to be a contiguous physical DRAM space with DSM, and > BIOS needs to allocate a contiguous memory chunk. Hardware will derive t= he > base of GSM from DSM only using the GSM size programmed in the register. >=20 > + - Valid options: >=20 > + - 0h: 0 MB of memory pre-allocated for GTT. >=20 > + - 1h: 2 MB of memory pre-allocated for GTT. >=20 > + - 2h: 4 MB of memory pre-allocated for GTT. >=20 > + - 3h: 8 MB of memory pre-allocated for GTT. >=20 > + - Others: Reserved >=20 > + - Hardware functionality in case of programming this value to Reserved = is > not guaranteed. >=20 > +**/ >=20 > +#define N_SA_GGC_GGMS_OFFSET (0x6) >=20 > +#define B_SA_GGC_GGMS_MASK (0xc0) >=20 > +#define V_SA_GGC_GGMS_8MB 3 >=20 > + >=20 > +/** >=20 > + Description: >=20 > + - Allows for enabling/disabling of PCI devices and functions that are w= ithin > the CPU package. The table below the bit definitions describes the behavi= or > of all combinations of transactions to devices controlled by this registe= r. >=20 > + All the bits in this register are LT Lockable. >=20 > +**/ >=20 > +#define R_SA_DEVEN (0x54) >=20 > + >=20 > +/** >=20 > + Description of D2EN (4:4) >=20 > + - 0: Bus 0 Device 2 is disabled and hidden >=20 > + - 1: Bus 0 Device 2 is enabled and visible >=20 > + - This bit will remain 0 if Device 2 capability is disabled. >=20 > +**/ >=20 > +#define B_SA_DEVEN_D2EN_MASK (0x10) >=20 > + >=20 > + >=20 > +/// >=20 > +/// Description: >=20 > +/// The SMRAMC register controls how accesses to Compatible SMRAM > spaces are treated. The Open, Close and Lock bits function only when > G_SMRAME bit is set to 1. Also, the Open bit must be reset before the Lo= ck > bit is set. >=20 > +/// >=20 > +#define R_SA_SMRAMC (0x88) >=20 > + >=20 > +/// >=20 > +/// Description: >=20 > +/// This register contains the base address of stolen DRAM memory for t= he > GTT. BIOS determines the base of GTT stolen memory by subtracting the GTT > graphics stolen memory size (PCI Device 0 offset 52 bits 9:8) from the > Graphics Base of Data Stolen Memory (PCI Device 0 offset B0 bits 31:20). >=20 > +/// >=20 > +#define R_SA_BGSM (0xb4) >=20 > + >=20 > + >=20 > +/// >=20 > +/// Description: >=20 > +/// This register contains the Top of low memory address. >=20 > +/// >=20 > +#define R_SA_TOLUD (0xbc) >=20 > + >=20 > +/// >=20 > +/// Description of TOLUD (20:31) >=20 > +/// This register contains bits 31 to 20 of an address one byte above t= he > maximum DRAM memory below 4G that is usable by the operating system. > Address bits 31 down to 20 programmed to 01h implies a minimum memory > size of 1MB. Configuration software must set this value to the smaller of= the > following 2 choices: maximum amount memory in the system minus ME > stolen memory plus one byte or the minimum address allocated for PCI > memory. Address bits 19:0 are assumed to be 0_0000h for the purposes of > address comparison. The Host interface positively decodes an address > towards DRAM if the incoming address is less than the value programmed in > this register. >=20 > +/// The Top of Low Usable DRAM is the lowest address above both > Graphics Stolen memory and Tseg. BIOS determines the base of Graphics > Stolen Memory by subtracting the Graphics Stolen Memory Size from TOLUD > and further decrements by Tseg size to determine base of Tseg. All the Bi= ts in > this register are locked in LT mode. >=20 > +/// This register must be 1MB aligned when reclaim is enabled. >=20 > +/// >=20 > +#define B_SA_TOLUD_TOLUD_MASK (0xfff00000) >=20 > +#define R_SA_MC_CAPID0_A_OFFSET 0xE4 >=20 > +#define V_SA_LTR_MAX_SNOOP_LATENCY_VALUE 0x0846 ///< Intel > recommended maximum value for Snoop Latency (70us) >=20 > +#define V_SA_LTR_MAX_NON_SNOOP_LATENCY_VALUE 0x0846 ///< > Intel recommended maximum value for Non-Snoop Latency (70us) >=20 > +#endif >=20 > diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Include/TcssInf= o.h > b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Include/TcssInfo.h > new file mode 100644 > index 0000000000..cd8d57d948 > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Include/TcssInfo.h > @@ -0,0 +1,12 @@ > +/** @file >=20 > + Register names for TCSS USB devices >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _TCSS_INFO_H_ >=20 > +#define _TCSS_INFO_H_ >=20 > + >=20 > +#define MAX_ITBT_PCIE_PORT 4 >=20 > + >=20 > +#endif >=20 > -- > 2.24.0.windows.2