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From: "Nate DeSimone" <nathaniel.l.desimone@intel.com>
To: "Luo, Heng" <heng.luo@intel.com>,
	"devel@edk2.groups.io" <devel@edk2.groups.io>
Cc: "Chaganty, Rangasai V" <rangasai.v.chaganty@intel.com>
Subject: Re: [PATCH 26/40] TigerlakeSiliconPkg/IpBlock: Add Sata component
Date: Thu, 4 Feb 2021 03:56:21 +0000	[thread overview]
Message-ID: <BN6PR1101MB2147570EFF64F0EF55D4E37BCDB39@BN6PR1101MB2147.namprd11.prod.outlook.com> (raw)
In-Reply-To: <20210201013657.1833-26-heng.luo@intel.com>

Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>

> -----Original Message-----
> From: Luo, Heng <heng.luo@intel.com>
> Sent: Sunday, January 31, 2021 5:37 PM
> To: devel@edk2.groups.io
> Cc: Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Desimone,
> Nathaniel L <nathaniel.l.desimone@intel.com>
> Subject: [PATCH 26/40] TigerlakeSiliconPkg/IpBlock: Add Sata component
> 
> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171
> 
> Adds the following files:
>   * IpBlock/Sata/Library
> 
> Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
> Signed-off-by: Heng Luo <heng.luo@intel.com>
> ---
> 
> Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Sata/Library/PeiDxeSmmSataLib/Pei
> DxeSmmSataLibVer2.inf |  32 ++++++++++++++++++++++++++++++++
> 
> Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Sata/Library/PeiDxeSmmSataLib/Sat
> aLib.c                | 138
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++
> 
> Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Sata/Library/PeiDxeSmmSataLib/Sat
> aLibVer2.c            |  83
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> +++++++++++++++++++++++++
>  3 files changed, 253 insertions(+)
> 
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Sata/Library/PeiDxeSmmSataLib/
> PeiDxeSmmSataLibVer2.inf
> b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Sata/Library/PeiDxeSmmSataLib/
> PeiDxeSmmSataLibVer2.inf
> new file mode 100644
> index 0000000000..1c304fed59
> --- /dev/null
> +++
> b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Sata/Library/PeiDxeSmmSataLib/
> PeiDxeSmmSataLibVer2.inf
> @@ -0,0 +1,32 @@
> +## @file
> 
> +# PEI/DXE/SMM PCH SATA library Ver2
> 
> +#
> 
> +# All function in this library is available for PEI, DXE, and SMM,
> 
> +# But do not support UEFI RUNTIME environment call.
> 
> +#
> 
> +#  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
> 
> +#  SPDX-License-Identifier: BSD-2-Clause-Patent
> 
> +#
> 
> +##
> 
> +
> 
> +[Defines]
> 
> +INF_VERSION = 0x00010017
> 
> +BASE_NAME = PeiDxeSmmPchSataLibVer2
> 
> +FILE_GUID = 2519ADE8-D971-4551-8A8E-2EB55DFC555B
> 
> +VERSION_STRING = 1.0
> 
> +MODULE_TYPE = BASE
> 
> +LIBRARY_CLASS = SataLib
> 
> +
> 
> +[LibraryClasses]
> 
> +BaseLib
> 
> +PciSegmentLib
> 
> +PchInfoLib
> 
> +PchPciBdfLib
> 
> +
> 
> +[Packages]
> 
> +MdePkg/MdePkg.dec
> 
> +TigerlakeSiliconPkg/SiPkg.dec
> 
> +
> 
> +[Sources]
> 
> +SataLib.c
> 
> +SataLibVer2.c
> 
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Sata/Library/PeiDxeSmmSataLib/
> SataLib.c
> b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Sata/Library/PeiDxeSmmSataLib/
> SataLib.c
> new file mode 100644
> index 0000000000..49cba49910
> --- /dev/null
> +++
> b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Sata/Library/PeiDxeSmmSataLib/
> SataLib.c
> @@ -0,0 +1,138 @@
> +/** @file
> 
> +  Pch SATA library.
> 
> +  All function in this library is available for PEI, DXE, and SMM,
> 
> +  But do not support UEFI RUNTIME environment call.
> 
> +
> 
> +  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
> 
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> 
> +**/
> 
> +
> 
> +#include <Base.h>
> 
> +#include <Uefi/UefiBaseType.h>
> 
> +#include <Library/IoLib.h>
> 
> +#include <Library/DebugLib.h>
> 
> +#include <Library/BaseLib.h>
> 
> +#include <Library/PciSegmentLib.h>
> 
> +#include <Library/PchInfoLib.h>
> 
> +#include <Library/SataLib.h>
> 
> +#include <Register/PchRegs.h>
> 
> +#include <Register/SataRegs.h>
> 
> +#include <Library/PchPciBdfLib.h>
> 
> +
> 
> +/**
> 
> +  Get SATA controller address that can be passed to the PCI Segment Library
> functions.
> 
> +
> 
> +  @param[in]  SataCtrlIndex       SATA controller index
> 
> +
> 
> +  @retval SATA controller address in PCI Segment Library representation
> 
> +**/
> 
> +UINT64
> 
> +SataRegBase (
> 
> +  IN UINT32      SataCtrlIndex
> 
> +  )
> 
> +{
> 
> +  ASSERT (SataCtrlIndex < MaxSataControllerNum ());
> 
> +
> 
> +  return SataPciCfgBase (SataCtrlIndex);
> 
> +}
> 
> +
> 
> +/**
> 
> +  Get SATA controller's Port Present Status
> 
> +
> 
> +  @param[in]  SataCtrlIndex       SATA controller index
> 
> +
> 
> +  @retval     Port Present Status
> 
> +**/
> 
> +UINT8
> 
> +GetSataPortPresentStatus (
> 
> +  IN UINT32  SataCtrlIndex
> 
> +  )
> 
> +{
> 
> +  ASSERT (SataCtrlIndex < MaxSataControllerNum ());
> 
> +
> 
> +  return PciSegmentRead8 (SataPciCfgBase (SataCtrlIndex) +
> R_SATA_CFG_PCS + 2);
> 
> +}
> 
> +
> 
> +/**
> 
> +  Get SATA controller Function Disable Status
> 
> +
> 
> +  @param[in]  SataCtrlIndex       SATA controller index
> 
> +
> 
> +  @retval 0 SATA Controller is not Function Disabled
> 
> +  @retval 1 SATA Controller is Function Disabled
> 
> +**/
> 
> +BOOLEAN
> 
> +SataControllerFunctionDisableStatus (
> 
> +  IN UINT32  SataCtrlIndex
> 
> +  )
> 
> +{
> 
> +  UINT32 SataGc;
> 
> +  ASSERT (SataCtrlIndex < MaxSataControllerNum ());
> 
> +  SataGc = PciSegmentRead32 (SataPciCfgBase (SataCtrlIndex) +
> R_SATA_CFG_SATAGC);
> 
> +  return !!(SataGc & BIT10);
> 
> +}
> 
> +
> 
> +/**
> 
> +  Get SATA controller ABAR size
> 
> +
> 
> +  @param[in]  SataCtrlIndex       SATA controller index
> 
> +
> 
> +  @retval SATA controller ABAR size
> 
> +**/
> 
> +UINT32
> 
> +GetSataAbarSize (
> 
> +  IN UINT32  SataCtrlIndex
> 
> +  )
> 
> +{
> 
> +  UINT32 SataGc;
> 
> +  ASSERT (SataCtrlIndex < MaxSataControllerNum ());
> 
> +  SataGc = PciSegmentRead32 (SataPciCfgBase (SataCtrlIndex) +
> R_SATA_CFG_SATAGC);
> 
> +
> 
> +  switch (SataGc & B_SATA_CFG_SATAGC_ASSEL) {
> 
> +    case V_SATA_CFG_SATAGC_ASSEL_2K:
> 
> +      return SIZE_2KB;
> 
> +      break;
> 
> +
> 
> +    case V_SATA_CFG_SATAGC_ASSEL_16K:
> 
> +      return SIZE_16KB;
> 
> +      break;
> 
> +
> 
> +    case V_SATA_CFG_SATAGC_ASSEL_32K:
> 
> +      return SIZE_32KB;
> 
> +      break;
> 
> +
> 
> +    case V_SATA_CFG_SATAGC_ASSEL_64K:
> 
> +      return SIZE_64KB;
> 
> +      break;
> 
> +
> 
> +    case V_SATA_CFG_SATAGC_ASSEL_128K:
> 
> +      return SIZE_128KB;
> 
> +      break;
> 
> +
> 
> +    case V_SATA_CFG_SATAGC_ASSEL_512K:
> 
> +      return SIZE_256KB;
> 
> +      break;
> 
> +
> 
> +    default:
> 
> +      return SIZE_2KB;
> 
> +      break;
> 
> +  }
> 
> +}
> 
> +
> 
> +/**
> 
> +  Get SATA controller AHCI base address
> 
> +
> 
> +  @param[in]  SataCtrlIndex       SATA controller index
> 
> +
> 
> +  @retval SATA controller AHCI base address
> 
> +**/
> 
> +UINT32
> 
> +GetSataAhciBase (
> 
> +  IN UINT32  SataCtrlIndex
> 
> +  )
> 
> +{
> 
> +  ASSERT (SataCtrlIndex < MaxSataControllerNum ());
> 
> +
> 
> +  return PciSegmentRead32 (SataPciCfgBase (SataCtrlIndex) +
> R_SATA_CFG_AHCI_BAR) & 0xFFFFF800;
> 
> +}
> 
> +
> 
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Sata/Library/PeiDxeSmmSataLib/
> SataLibVer2.c
> b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Sata/Library/PeiDxeSmmSataLib/
> SataLibVer2.c
> new file mode 100644
> index 0000000000..cde74e4e76
> --- /dev/null
> +++
> b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Sata/Library/PeiDxeSmmSataLib/
> SataLibVer2.c
> @@ -0,0 +1,83 @@
> +/** @file
> 
> +  Pch SATA library.
> 
> +  All function in this library is available for PEI, DXE, and SMM,
> 
> +  But do not support UEFI RUNTIME environment call.
> 
> +
> 
> +  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
> 
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> 
> +**/
> 
> +
> 
> +#include <Base.h>
> 
> +#include <Uefi/UefiBaseType.h>
> 
> +#include <Library/DebugLib.h>
> 
> +#include <Library/PchInfoLib.h>
> 
> +#include <PchLimits.h>
> 
> +#include <Register/SataRegs.h>
> 
> +#include <Library/SataLib.h>
> 
> +
> 
> +/**
> 
> +  Get Maximum Sata Controller Number
> 
> +
> 
> +  @retval Maximum Sata Controller Number
> 
> +**/
> 
> +UINT8
> 
> +MaxSataControllerNum (
> 
> +  VOID
> 
> +  )
> 
> +{
> 
> +  return 1;
> 
> +}
> 
> +
> 
> +/**
> 
> +  Get Maximum Sata Port Number
> 
> +
> 
> +  @param[in]  SataCtrlIndex       SATA controller index
> 
> +
> 
> +  @retval     Maximum Sata Port Number
> 
> +**/
> 
> +UINT8
> 
> +MaxSataPortNum (
> 
> +  IN UINT32      SataCtrlIndex
> 
> +  )
> 
> +{
> 
> +  ASSERT (SataCtrlIndex < MaxSataControllerNum ());
> 
> +
> 
> +  return 2;
> 
> +}
> 
> +
> 
> +/**
> 
> +  Check if SATA controller supports RST remapping
> 
> +
> 
> +  @param[in]  SataCtrlIndex       SATA controller index
> 
> +
> 
> +  @retval     TRUE                Controller supports remapping
> 
> +  @retval     FALSE               Controller does not support remapping
> 
> +
> 
> +**/
> 
> +BOOLEAN
> 
> +IsRemappingSupportedOnSata (
> 
> +  IN UINT32  SataCtrlIndex
> 
> +  )
> 
> +{
> 
> +  ASSERT (SataCtrlIndex < MaxSataControllerNum ());
> 
> +
> 
> +  return FALSE;
> 
> +}
> 
> +
> 
> +/**
> 
> +  Checks if SoC supports the SATA PGD power down on given
> 
> +  SATA controller.
> 
> +
> 
> +  @param[in] SataCtrlIndex  SATA controller index
> 
> +
> 
> +  @retval TRUE   SATA PGD power down supported
> 
> +  @retval FALSE  SATA PGD power down not supported
> 
> +**/
> 
> +BOOLEAN
> 
> +IsSataPowerGatingSupported (
> 
> +  IN UINT32 SataCtrlIndex
> 
> +  )
> 
> +{
> 
> +  return TRUE;
> 
> +}
> 
> +
> 
> --
> 2.24.0.windows.2


  reply	other threads:[~2021-02-04  3:56 UTC|newest]

Thread overview: 81+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-02-01  1:36 [PATCH 01/40] TigerlakeSiliconPkg: Add package and Include/ConfigBlock headers Heng Luo
2021-02-01  1:36 ` [PATCH 02/40] TigerlakeSiliconPkg/Include: Add Library, PPI and Protocol include headers Heng Luo
2021-02-04  3:51   ` Nate DeSimone
2021-02-01  1:36 ` [PATCH 03/40] TigerlakeSiliconPkg/Include: Add Pins, Register and other " Heng Luo
2021-02-04  3:52   ` Nate DeSimone
2021-02-01  1:36 ` [PATCH 04/40] TigerlakeSiliconPkg/Cpu: Add Include headers Heng Luo
2021-02-04  3:53   ` Nate DeSimone
2021-02-01  1:36 ` [PATCH 05/40] TigerlakeSiliconPkg/Pch: Add include headers Heng Luo
2021-02-04  3:53   ` Nate DeSimone
2021-02-01  1:36 ` [PATCH 06/40] TigerlakeSiliconPkg/Pch: Add IncludePrivate headers Heng Luo
2021-02-04  3:53   ` Nate DeSimone
2021-02-01  1:36 ` [PATCH 07/40] TigerlakeSiliconPkg/SystemAgent: Add include headers Heng Luo
2021-02-04  3:53   ` Nate DeSimone
2021-02-01  1:36 ` [PATCH 08/40] TigerlakeSiliconPkg/SystemAgent: Add IncludePrivate headers Heng Luo
2021-02-04  3:53   ` Nate DeSimone
2021-02-01  1:36 ` [PATCH 09/40] TigerlakeSiliconPkg/Fru: Add TglCpu/Include headers Heng Luo
2021-02-04  3:53   ` Nate DeSimone
2021-02-01  1:36 ` [PATCH 10/40] TigerlakeSiliconPkg/Fru: Add TglCpu/IncludePrivate headers Heng Luo
2021-02-04  3:53   ` Nate DeSimone
2021-02-01  1:36 ` [PATCH 11/40] TigerlakeSiliconPkg/Fru: Add TglPch/Include headers Heng Luo
2021-02-04  3:53   ` Nate DeSimone
2021-02-01  1:36 ` [PATCH 12/40] TigerlakeSiliconPkg/Fru: Add TglPch/IncludePrivate headers Heng Luo
2021-02-04  3:53   ` Nate DeSimone
2021-02-01  1:36 ` [PATCH 13/40] TigerlakeSiliconPkg/IpBlock: Add Cnvi component Heng Luo
2021-02-04  3:53   ` Nate DeSimone
2021-02-01  1:36 ` [PATCH 14/40] TigerlakeSiliconPkg/IpBlock: Add CpuPcieRp component Heng Luo
2021-02-04  3:53   ` Nate DeSimone
2021-02-01  1:36 ` [PATCH 15/40] TigerlakeSiliconPkg/IpBlock: Add Espi component Heng Luo
2021-02-04  3:54   ` Nate DeSimone
2021-02-01  1:36 ` [PATCH 16/40] TigerlakeSiliconPkg/IpBlock: Add Gbe component Heng Luo
2021-02-04  3:54   ` Nate DeSimone
2021-02-01  1:36 ` [PATCH 17/40] TigerlakeSiliconPkg/IpBlock: Add Gpio component Heng Luo
2021-02-04  3:54   ` Nate DeSimone
2021-02-01  1:36 ` [PATCH 18/40] TigerlakeSiliconPkg/IpBlock: Add Graphics component Heng Luo
2021-02-04  3:54   ` Nate DeSimone
2021-02-01  1:36 ` [PATCH 19/40] TigerlakeSiliconPkg/IpBlock: Add Hda component Heng Luo
2021-02-04  3:54   ` Nate DeSimone
2021-02-01  1:36 ` [PATCH 20/40] TigerlakeSiliconPkg/IpBlock: Add HostBridge component Heng Luo
2021-02-04  3:54   ` Nate DeSimone
2021-02-01  1:36 ` [PATCH 21/40] TigerlakeSiliconPkg/IpBlock: Add P2sb component Heng Luo
2021-02-04  3:54   ` Nate DeSimone
2021-02-01  1:36 ` [PATCH 22/40] TigerlakeSiliconPkg/IpBlock: Add PchDmi component Heng Luo
2021-02-04  3:54   ` Nate DeSimone
2021-02-01  1:36 ` [PATCH 23/40] TigerlakeSiliconPkg/IpBlock: Add PcieRp component Heng Luo
2021-02-04  3:55   ` Nate DeSimone
2021-02-01  1:36 ` [PATCH 24/40] TigerlakeSiliconPkg/IpBlock: Add Pmc component Heng Luo
2021-02-04  3:56   ` Nate DeSimone
2021-02-01  1:36 ` [PATCH 25/40] TigerlakeSiliconPkg/IpBlock: Add Psf component Heng Luo
2021-02-04  3:56   ` Nate DeSimone
2021-02-01  1:36 ` [PATCH 26/40] TigerlakeSiliconPkg/IpBlock: Add Sata component Heng Luo
2021-02-04  3:56   ` Nate DeSimone [this message]
2021-02-01  1:36 ` [PATCH 27/40] TigerlakeSiliconPkg/IpBlock: Add SerialIo component Heng Luo
2021-02-04  3:56   ` Nate DeSimone
2021-02-01  1:36 ` [PATCH 28/40] TigerlakeSiliconPkg/IpBlock: Add Smbus component Heng Luo
2021-02-04  3:56   ` Nate DeSimone
2021-02-01  1:36 ` [PATCH 29/40] TigerlakeSiliconPkg/IpBlock: Add Spi component Heng Luo
2021-02-04  3:56   ` Nate DeSimone
2021-02-01  1:36 ` [PATCH 30/40] TigerlakeSiliconPkg/IpBlock: Add Vtd component Heng Luo
2021-02-04  3:56   ` Nate DeSimone
2021-02-01  1:36 ` [PATCH 31/40] TigerlakeSiliconPkg/Library: Add package common library instances Heng Luo
2021-02-04  3:56   ` Nate DeSimone
2021-02-01  1:36 ` [PATCH 32/40] TigerlakeSiliconPkg/Pch: Add Pch " Heng Luo
2021-02-04  3:56   ` Nate DeSimone
2021-02-01  1:36 ` [PATCH 33/40] TigerlakeSiliconPkg/Pch: Add Pch private " Heng Luo
2021-02-04  3:56   ` Nate DeSimone
2021-02-01  1:36 ` [PATCH 34/40] TigerlakeSiliconPkg/SystemAgent: Add Acpi Tables and " Heng Luo
2021-02-04  3:56   ` Nate DeSimone
2021-02-01  1:36 ` [PATCH 35/40] TigerlakeSiliconPkg/Fru/TglCpu: Add CpuPcieRp and Vtd " Heng Luo
2021-02-04  3:56   ` Nate DeSimone
2021-02-01  1:36 ` [PATCH 36/40] TigerlakeSiliconPkg/Pch: Add Pch modules Heng Luo
2021-02-04  3:56   ` Nate DeSimone
2021-02-01  1:36 ` [PATCH 37/40] TigerlakeSiliconPkg/SystemAgent: Add SystemAgent modules Heng Luo
2021-02-04  3:56   ` Nate DeSimone
2021-02-01  1:36 ` [PATCH 38/40] TigerlakeSiliconPkg/Fru: Add Fru DSC files Heng Luo
2021-02-04  3:56   ` Nate DeSimone
2021-02-01  1:36 ` [PATCH 39/40] TigerlakeSiliconPkg: Add package " Heng Luo
2021-02-04  3:56   ` Nate DeSimone
2021-02-01  1:36 ` [PATCH 40/40] Maintainers.txt: Add TigerlakeSiliconPkg maintainers Heng Luo
2021-02-04  3:51   ` Nate DeSimone
2021-02-04  8:24     ` Heng Luo
2021-02-04  3:51 ` [PATCH 01/40] TigerlakeSiliconPkg: Add package and Include/ConfigBlock headers Nate DeSimone

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