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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Nate DeSimone > -----Original Message----- > From: Luo, Heng > Sent: Sunday, January 31, 2021 5:36 PM > To: devel@edk2.groups.io > Cc: Chaganty, Rangasai V ; Desimone, > Nathaniel L > Subject: [PATCH 12/40] TigerlakeSiliconPkg/Fru: Add TglPch/IncludePrivate > headers >=20 > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3171 >=20 > Adds the following header files: > * Fru/TglPch/IncludePrivate >=20 > Cc: Sai Chaganty > Cc: Nate DeSimone > Signed-off-by: Heng Luo > --- >=20 > Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/IncludePrivate/Register/PchP= crR > egs.h | 66 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++ > 1 file changed, 66 insertions(+) >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/IncludePrivate/Register/Pc= hPc > rRegs.h > b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/IncludePrivate/Register/Pc= hPc > rRegs.h > new file mode 100644 > index 0000000000..4987d21f09 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/IncludePrivate/Register/Pc= hPc > rRegs.h > @@ -0,0 +1,66 @@ > +/** @file >=20 > + Register names for PCH private chipset register >=20 > + >=20 > +Conventions: >=20 > + >=20 > + - Register definition format: >=20 > + > Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterS > pace_RegisterName >=20 > + - Prefix: >=20 > + Definitions beginning with "R_" are registers >=20 > + Definitions beginning with "B_" are bits within registers >=20 > + Definitions beginning with "V_" are meaningful values within the bit= s >=20 > + Definitions beginning with "S_" are register size >=20 > + Definitions beginning with "N_" are the bit position >=20 > + - [GenerationName]: >=20 > + Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc= .). >=20 > + Register name without GenerationName applies to all generations. >=20 > + - [ComponentName]: >=20 > + This field indicates the component name that the register belongs to= (e.g. > PCH, SA etc.) >=20 > + Register name without ComponentName applies to all components. >=20 > + Register that is specific to -LP denoted by "_PCH_LP_" in component > name. >=20 > + - SubsystemName: >=20 > + This field indicates the subsystem name of the component that the > register belongs to >=20 > + (e.g. PCIE, USB, SATA, GPIO, PMC etc.). >=20 > + - RegisterSpace: >=20 > + MEM - MMIO space register of subsystem. >=20 > + IO - IO space register of subsystem. >=20 > + PCR - Private configuration register of subsystem. >=20 > + CFG - PCI configuration space register of subsystem. >=20 > + - RegisterName: >=20 > + Full register name. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _PCH_REGS_PCR_H_ >=20 > +#define _PCH_REGS_PCR_H_ >=20 > + >=20 > +/** >=20 > + Definition for SBI PID >=20 > + The PCH_SBI_PID defines the PID for PCR MMIO programming and PCH SBI > programming as well. >=20 > +**/ >=20 > +#define PID_CNVI 0x73 >=20 > +#define PID_ICLK 0xAD >=20 > +#define PID_DMI 0x88 >=20 > +#define PID_PSTH 0x89 >=20 > +#define PID_ESPISPI 0x72 >=20 > +#define PID_SPF 0x85 >=20 > +#define PID_SPE 0x84 >=20 > +#define PID_SPD 0x83 >=20 > +#define PID_SPC 0x82 >=20 > +#define PID_SPB 0x81 >=20 > +#define PID_SPA 0x80 >=20 > +#define PID_PSF6 0x7F >=20 > +#define PID_PSF4 0xBD >=20 > +#define PID_PSF3 0xBC >=20 > +#define PID_PSF2 0xBB >=20 > +#define PID_PSF1 0xBA >=20 > +#define PID_GPIOCOM0 0x6E >=20 > +#define PID_GPIOCOM1 0x6D >=20 > +#define PID_GPIOCOM2 0x6C >=20 > +#define PID_GPIOCOM3 0x6B >=20 > +#define PID_GPIOCOM4 0x6A >=20 > +#define PID_GPIOCOM5 0x69 >=20 > +#define PID_CSME_PSF 0x8F >=20 > + >=20 > +#endif >=20 > -- > 2.24.0.windows.2