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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Nate DeSimone > -----Original Message----- > From: Luo, Heng > Sent: Sunday, January 31, 2021 5:37 PM > To: devel@edk2.groups.io > Cc: Chaganty, Rangasai V ; Desimone, > Nathaniel L > Subject: [PATCH 24/40] TigerlakeSiliconPkg/IpBlock: Add Pmc component >=20 > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3171 >=20 > Adds the following files: > * IpBlock/Pmc/IncludePrivate > * IpBlock/Pmc/Library > * IpBlock/Pmc/LibraryPrivate >=20 > Cc: Sai Chaganty > Cc: Nate DeSimone > Signed-off-by: Heng Luo > --- >=20 > Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/Library/PmcP= ri > vateLib.h | 120 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/Register/Pmc= R > egsVer2.h | 52 > ++++++++++++++++++++++++++++++++++++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/Library/PeiDxeSmmPmcLib/Pei > DxeSmmPmcLib.inf | 42 > ++++++++++++++++++++++++++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/Library/PeiDxeSmmPmcLib/P > mcLib.c | 545 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmPm > cPrivateLib/PeiDxeSmmPmcPrivateLibVer2.inf | 39 > +++++++++++++++++++++++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmPm > cPrivateLib/PeiDxeSmmPmcPrivateLibWithS3.inf | 40 > ++++++++++++++++++++++++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmPm > cPrivateLib/PmcPrivateLib.c | 166 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmPm > cPrivateLib/PmcPrivateLibWithS3.c | 122 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++ > 8 files changed, 1126 insertions(+) >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/Library/Pm= cP > rivateLib.h > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/Library/Pm= cP > rivateLib.h > new file mode 100644 > index 0000000000..0f2f251d57 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/Library/Pm= cP > rivateLib.h > @@ -0,0 +1,120 @@ > +/** @file >=20 > + Header file for private PmcLib. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _PMC_PRIVATE_LIB_H_ >=20 > +#define _PMC_PRIVATE_LIB_H_ >=20 > + >=20 > +#include >=20 > +#include "Register/PmcRegs.h" >=20 > + >=20 > +/** >=20 > + This function checks if GbE device is supported (not disabled by fuse) >=20 > + >=20 > + @retval GbE support state >=20 > +**/ >=20 > +BOOLEAN >=20 > +PmcIsGbeSupported ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + This function checks if LAN wake from DeepSx is enabled >=20 > + >=20 > + @retval Lan Wake state >=20 > +**/ >=20 > +BOOLEAN >=20 > +PmcIsLanDeepSxWakeEnabled ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + This function sets SMI Lock with S3 Boot Script programming >=20 > +**/ >=20 > +VOID >=20 > +PmcLockSmiWithS3BootScript ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + This function sets eSPI SMI Lock >=20 > + @attention This function must be called after eSPI SMI generation has > been enabled. >=20 > + This setting is required in all boot modes and before EndOfDxe. >=20 > + If set value will be restored upon S3 resume by bootscript. >=20 > +**/ >=20 > +VOID >=20 > +PmcLockEspiSmiWithS3BootScript ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + This function checks if eSPI SMI Lock is set >=20 > + >=20 > + @retval eSPI SMI Lock state >=20 > +**/ >=20 > +BOOLEAN >=20 > +PmcIsEspiSmiLockSet ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +typedef enum { >=20 > + PmcSwSmiRate1p5ms =3D 0, >=20 > + PmcSwSmiRate16ms, >=20 > + PmcSwSmiRate32ms, >=20 > + PmcSwSmiRate64ms >=20 > +} PMC_SWSMI_RATE; >=20 > + >=20 > +/** >=20 > + This function sets SW SMI Rate. >=20 > + >=20 > + @param[in] SwSmiRate Refer to PMC_SWSMI_RATE for possible > values >=20 > +**/ >=20 > +VOID >=20 > +PmcSetSwSmiRate ( >=20 > + IN PMC_SWSMI_RATE SwSmiRate >=20 > + ); >=20 > + >=20 > +typedef enum { >=20 > + PmcPeriodicSmiRate8s =3D 0, >=20 > + PmcPeriodicSmiRate16s, >=20 > + PmcPeriodicSmiRate32s, >=20 > + PmcPeriodicSmiRate64s >=20 > +} PMC_PERIODIC_SMI_RATE; >=20 > + >=20 > +/** >=20 > + This function sets Periodic SMI Rate. >=20 > + >=20 > + @param[in] PeriodicSmiRate Refer to PMC_PERIODIC_SMI_RATE for > possible values >=20 > +**/ >=20 > +VOID >=20 > +PmcSetPeriodicSmiRate ( >=20 > + IN PMC_PERIODIC_SMI_RATE PeriodicSmiRate >=20 > + ); >=20 > + >=20 > +/** >=20 > + This function reads Power Button Level >=20 > + >=20 > + @retval State of PWRBTN# signal (0: Low, 1: High) >=20 > +**/ >=20 > +UINT8 >=20 > +PmcGetPwrBtnLevel ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + This function gets Group to GPE0 configuration >=20 > + >=20 > + @param[out] GpeDw0Value GPIO Group to GPE_DW0 assignment >=20 > + @param[out] GpeDw1Value GPIO Group to GPE_DW1 assignment >=20 > + @param[out] GpeDw2Value GPIO Group to GPE_DW2 assignment >=20 > +**/ >=20 > +VOID >=20 > +PmcGetGpioGpe ( >=20 > + OUT UINT32 *GpeDw0Value, >=20 > + OUT UINT32 *GpeDw1Value, >=20 > + OUT UINT32 *GpeDw2Value >=20 > + ); >=20 > + >=20 > +#endif // _PMC_PRIVATE_LIB_H_ >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/Register/P= mc > RegsVer2.h > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/Register/P= m > cRegsVer2.h > new file mode 100644 > index 0000000000..986173dd7d > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/Register/P= m > cRegsVer2.h > @@ -0,0 +1,52 @@ > +/** @file >=20 > + Register names for Ver2 PCH PMC device >=20 > + >=20 > + Conventions: >=20 > + >=20 > + - Register definition format: >=20 > + > Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterS > pace_RegisterName >=20 > + - Prefix: >=20 > + Definitions beginning with "R_" are registers >=20 > + Definitions beginning with "B_" are bits within registers >=20 > + Definitions beginning with "V_" are meaningful values within the bit= s >=20 > + Definitions beginning with "S_" are register size >=20 > + Definitions beginning with "N_" are the bit position >=20 > + - [GenerationName]: >=20 > + Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc= .). >=20 > + Register name without GenerationName applies to all generations. >=20 > + - [ComponentName]: >=20 > + This field indicates the component name that the register belongs to= (e.g. > PCH, SA etc.) >=20 > + Register name without ComponentName applies to all components. >=20 > + Register that is specific to -LP denoted by "_PCH_LP_" in component > name. >=20 > + - SubsystemName: >=20 > + This field indicates the subsystem name of the component that the > register belongs to >=20 > + (e.g. PCIE, USB, SATA, GPIO, PMC etc.). >=20 > + - RegisterSpace: >=20 > + MEM - MMIO space register of subsystem. >=20 > + IO - IO space register of subsystem. >=20 > + PCR - Private configuration register of subsystem. >=20 > + CFG - PCI configuration space register of subsystem. >=20 > + - RegisterName: >=20 > + Full register name. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _PCH_REGS_PMC_TGL_H_ >=20 > +#define _PCH_REGS_PMC_TGL_H_ >=20 > + >=20 > +// >=20 > +// PWRM Registers >=20 > +// >=20 > +#define V_TGL_PCH_LP_PMC_PWRM_GPIO_CFG_GPP_B 0x0 >=20 > +#define V_TGL_PCH_LP_PMC_PWRM_GPIO_CFG_GPP_A 0x2 >=20 > +#define V_TGL_PCH_LP_PMC_PWRM_GPIO_CFG_GPP_R 0x3 >=20 > +#define V_TGL_PCH_LP_PMC_PWRM_GPIO_CFG_GPD 0x4 >=20 > +#define V_TGL_PCH_LP_PMC_PWRM_GPIO_CFG_GPP_S 0x5 >=20 > +#define V_TGL_PCH_LP_PMC_PWRM_GPIO_CFG_GPP_H 0x6 >=20 > +#define V_TGL_PCH_LP_PMC_PWRM_GPIO_CFG_GPP_D 0x7 >=20 > +#define V_TGL_PCH_LP_PMC_PWRM_GPIO_CFG_GPP_F 0xA >=20 > +#define V_TGL_PCH_LP_PMC_PWRM_GPIO_CFG_GPP_C 0xB >=20 > +#define V_TGL_PCH_LP_PMC_PWRM_GPIO_CFG_GPP_E 0xC >=20 > + >=20 > +#endif // _PCH_REGS_PMC_TGL_H_ >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/Library/PeiDxeSmmPmcLib/ > PeiDxeSmmPmcLib.inf > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/Library/PeiDxeSmmPmcLib/ > PeiDxeSmmPmcLib.inf > new file mode 100644 > index 0000000000..eba6db767c > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/Library/PeiDxeSmmPmcLib/ > PeiDxeSmmPmcLib.inf > @@ -0,0 +1,42 @@ > +## @file >=20 > +# PEI/DXE/SMM PCH PMC Lib. >=20 > +# >=20 > +# All function in this library is available for PEI, DXE, and SMM, >=20 > +# But do not support UEFI RUNTIME environment call. >=20 > +# >=20 > +# Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > +# SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +# >=20 > +## >=20 > + >=20 > + >=20 > +[Defines] >=20 > +INF_VERSION =3D 0x00010017 >=20 > +BASE_NAME =3D PeiDxeSmmPmcLib >=20 > +FILE_GUID =3D 9D60C364-5086-41E3-BC9D-C62AB7233DBF >=20 > +VERSION_STRING =3D 1.0 >=20 > +MODULE_TYPE =3D BASE >=20 > +LIBRARY_CLASS =3D PmcLib >=20 > + >=20 > + >=20 > +[LibraryClasses] >=20 > +BaseLib >=20 > +IoLib >=20 > +DebugLib >=20 > +PciSegmentLib >=20 > +PchCycleDecodingLib >=20 > +PchPcrLib >=20 > +PchInfoLib >=20 > +BaseMemoryLib >=20 > + >=20 > +[Packages] >=20 > +MdePkg/MdePkg.dec >=20 > +TigerlakeSiliconPkg/SiPkg.dec >=20 > + >=20 > + >=20 > +[Pcd] >=20 > +gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress >=20 > +gSiPkgTokenSpaceGuid.PcdTcoBaseAddress >=20 > + >=20 > +[Sources] >=20 > +PmcLib.c >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/Library/PeiDxeSmmPmcLib/ > PmcLib.c > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/Library/PeiDxeSmmPmcLib/ > PmcLib.c > new file mode 100644 > index 0000000000..78e596b268 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/Library/PeiDxeSmmPmcLib/ > PmcLib.c > @@ -0,0 +1,545 @@ > +/** @file >=20 > + PCH PMC Library. >=20 > + All function in this library is available for PEI, DXE, and SMM, >=20 > + But do not support UEFI RUNTIME environment call. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +/** >=20 > + Get PCH ACPI base address. >=20 > + >=20 > + @retval Address Address of PWRM base address. >=20 > +**/ >=20 > +UINT16 >=20 > +PmcGetAcpiBase ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return PcdGet16 (PcdAcpiBaseAddress); >=20 > +} >=20 > + >=20 > +/** >=20 > + Get PCH PWRM base address. >=20 > + >=20 > + @retval Address Address of PWRM base address. >=20 > +**/ >=20 > +UINT32 >=20 > +PmcGetPwrmBase ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return PCH_PWRM_BASE_ADDRESS; >=20 > +} >=20 > + >=20 > +/** >=20 > + This function enables Power Button SMI >=20 > +**/ >=20 > +VOID >=20 > +PmcEnablePowerButtonSmi ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + IoOr16 (PmcGetAcpiBase () + R_ACPI_IO_PM1_EN, > B_ACPI_IO_PM1_EN_PWRBTN); >=20 > +} >=20 > + >=20 > +/** >=20 > + This function disables Power Button SMI >=20 > +**/ >=20 > +VOID >=20 > +PmcDisablePowerButtonSmi ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + IoAnd16 (PmcGetAcpiBase () + R_ACPI_IO_PM1_EN, > (UINT16)~B_ACPI_IO_PM1_EN_PWRBTN); >=20 > +} >=20 > + >=20 > +/** >=20 > + This function reads PM Timer Count driven by 3.579545 MHz clock >=20 > + >=20 > + @retval PM Timer Count >=20 > +**/ >=20 > +UINT32 >=20 > +PmcGetTimerCount ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return IoRead32 (PmcGetAcpiBase () + R_ACPI_IO_PM1_TMR) & > B_ACPI_IO_PM1_TMR_VAL; >=20 > +} >=20 > + >=20 > +/** >=20 > + Get Sleep Type that platform has waken from >=20 > + >=20 > + @retval SleepType Sleep Type >=20 > +**/ >=20 > +PMC_SLEEP_STATE >=20 > +PmcGetSleepTypeAfterWake ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + UINT16 AcpiBase; >=20 > + UINT32 PmconA; >=20 > + >=20 > + AcpiBase =3D PmcGetAcpiBase (); >=20 > + PmconA =3D MmioRead32 (PmcGetPwrmBase () + > R_PMC_PWRM_GEN_PMCON_A); >=20 > + >=20 > + DEBUG ((DEBUG_INFO, "PWRM_PMCON_A =3D 0x%x\n", PmconA)); >=20 > + >=20 > + // >=20 > + // If Global Reset Status, Power Failure. Host Reset Status bits are s= et, > return S5 State >=20 > + // >=20 > + if ((PmconA & (B_PMC_PWRM_GEN_PMCON_A_GBL_RST_STS | > B_PMC_PWRM_GEN_PMCON_A_PWR_FLR | > B_PMC_PWRM_GEN_PMCON_A_HOST_RST_STS)) !=3D 0) { >=20 > + return PmcNotASleepState; >=20 > + } >=20 > + >=20 > + if (IoRead16 (AcpiBase + R_ACPI_IO_PM1_STS) & > B_ACPI_IO_PM1_STS_WAK) { >=20 > + switch (IoRead16 (AcpiBase + R_ACPI_IO_PM1_CNT) & > B_ACPI_IO_PM1_CNT_SLP_TYP) { >=20 > + case V_ACPI_IO_PM1_CNT_S0: >=20 > + return PmcInS0State; >=20 > + >=20 > + case V_ACPI_IO_PM1_CNT_S1: >=20 > + return PmcS1SleepState; >=20 > + >=20 > + case V_ACPI_IO_PM1_CNT_S3: >=20 > + return PmcS3SleepState; >=20 > + >=20 > + case V_ACPI_IO_PM1_CNT_S4: >=20 > + return PmcS4SleepState; >=20 > + >=20 > + case V_ACPI_IO_PM1_CNT_S5: >=20 > + return PmcS5SleepState; >=20 > + >=20 > + default: >=20 > + ASSERT (FALSE); >=20 > + return PmcUndefinedState; >=20 > + } >=20 > + } else { >=20 > + return PmcNotASleepState; >=20 > + } >=20 > +} >=20 > + >=20 > +/** >=20 > + Clear PMC Wake Status >=20 > +**/ >=20 > +VOID >=20 > +PmcClearWakeStatus ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + IoWrite16 (PmcGetAcpiBase () + R_ACPI_IO_PM1_STS, > B_ACPI_IO_PM1_STS_WAK); >=20 > +} >=20 > + >=20 > +/** >=20 > + Configure sleep state >=20 > + >=20 > + @param[in] SleepState S0/S1/S3/S4/S5, refer to PMC_SLEEP_STATE >=20 > +**/ >=20 > +VOID >=20 > +PmcSetSleepState ( >=20 > + PMC_SLEEP_STATE SleepState >=20 > + ) >=20 > +{ >=20 > + UINT16 Data16; >=20 > + >=20 > + switch (SleepState) { >=20 > + case PmcInS0State: >=20 > + Data16 =3D V_ACPI_IO_PM1_CNT_S0; >=20 > + break; >=20 > + >=20 > + case PmcS1SleepState: >=20 > + Data16 =3D V_ACPI_IO_PM1_CNT_S1; >=20 > + break; >=20 > + >=20 > + case PmcS3SleepState: >=20 > + Data16 =3D V_ACPI_IO_PM1_CNT_S3; >=20 > + break; >=20 > + >=20 > + case PmcS4SleepState: >=20 > + Data16 =3D V_ACPI_IO_PM1_CNT_S4; >=20 > + break; >=20 > + >=20 > + case PmcS5SleepState: >=20 > + Data16 =3D V_ACPI_IO_PM1_CNT_S5; >=20 > + break; >=20 > + >=20 > + default: >=20 > + ASSERT (FALSE); >=20 > + return; >=20 > + >=20 > + } >=20 > + IoAndThenOr16 (PmcGetAcpiBase () + R_ACPI_IO_PM1_CNT, (UINT16) > ~B_ACPI_IO_PM1_CNT_SLP_TYP, Data16); >=20 > +} >=20 > + >=20 > +/** >=20 > + Check if platform boots after shutdown caused by power button override > event >=20 > + >=20 > + @retval TRUE Power Button Override occurred in last system boot >=20 > + @retval FALSE Power Button Override didn't occur >=20 > +**/ >=20 > +BOOLEAN >=20 > +PmcIsPowerButtonOverrideDetected ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return ((IoRead16 (PmcGetAcpiBase () + R_ACPI_IO_PM1_STS) & > B_ACPI_IO_PM1_STS_PRBTNOR) !=3D 0); >=20 > +} >=20 > + >=20 > +/** >=20 > + This function sets tPCH25 timing >=20 > + >=20 > + @param[in] TimingValue tPCH25 timing value (10us, 100us, 1ms, 10= ms) >=20 > +**/ >=20 > +VOID >=20 > +PmcSetTPch25Timing ( >=20 > + IN PMC_TPCH25_TIMING TimingValue >=20 > + ) >=20 > +{ >=20 > + ASSERT (TimingValue <=3D PmcTPch25_10ms); >=20 > + >=20 > + MmioAndThenOr32 ( >=20 > + (UINTN) (PmcGetPwrmBase () + R_PMC_PWRM_CFG), >=20 > + (UINT32)~(B_PMC_PWRM_CFG_TIMING_TPCH25), >=20 > + TimingValue >=20 > + ); >=20 > +} >=20 > + >=20 > +/** >=20 > + This function checks if RTC Power Failure occurred by >=20 > + reading RTC_PWR_FLR bit >=20 > + >=20 > + @retval RTC Power Failure state: TRUE - Battery is always present. >=20 > + FALSE - CMOS is cleared. >=20 > +**/ >=20 > +BOOLEAN >=20 > +PmcIsRtcBatteryGood ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return ((MmioRead8 (PmcGetPwrmBase () + > R_PMC_PWRM_GEN_PMCON_B) & > B_PMC_PWRM_GEN_PMCON_B_RTC_PWR_STS) =3D=3D 0); >=20 > +} >=20 > + >=20 > +/** >=20 > + This function checks if Power Failure occurred by >=20 > + reading PWR_FLR bit >=20 > + >=20 > + @retval Power Failure state >=20 > +**/ >=20 > +BOOLEAN >=20 > +PmcIsPowerFailureDetected ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return ((MmioRead16 (PmcGetPwrmBase () + > R_PMC_PWRM_GEN_PMCON_A) & > B_PMC_PWRM_GEN_PMCON_A_PWR_FLR) !=3D 0); >=20 > +} >=20 > + >=20 > +/** >=20 > + This function checks if Power Failure occurred by >=20 > + reading SUS_PWR_FLR bit >=20 > + >=20 > + @retval SUS Power Failure state >=20 > +**/ >=20 > +BOOLEAN >=20 > +PmcIsSusPowerFailureDetected ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return ((MmioRead32 (PmcGetPwrmBase () + > R_PMC_PWRM_GEN_PMCON_A) & > B_PMC_PWRM_GEN_PMCON_A_SUS_PWR_FLR) !=3D 0); >=20 > +} >=20 > + >=20 > +/** >=20 > + This function clears Power Failure status (PWR_FLR) >=20 > +**/ >=20 > +VOID >=20 > +PmcClearPowerFailureStatus ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + // >=20 > + // Write 1 to clear PWR_FLR >=20 > + // Avoid clearing other W1C bits >=20 > + // >=20 > + MmioAndThenOr8 ( >=20 > + PmcGetPwrmBase () + R_PMC_PWRM_GEN_PMCON_A + 1, >=20 > + (UINT8) ~(B_PMC_PWRM_GEN_PMCON_A_HOST_RST_STS >> 8), >=20 > + B_PMC_PWRM_GEN_PMCON_A_PWR_FLR >> 8 >=20 > + ); >=20 > +} >=20 > + >=20 > +/** >=20 > + This function clears Global Reset status (GBL_RST_STS) >=20 > +**/ >=20 > +VOID >=20 > +PmcClearGlobalResetStatus ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + // >=20 > + // Write 1 to clear GBL_RST_STS >=20 > + // Avoid clearing other W1C bits >=20 > + // >=20 > + MmioAndThenOr8 ( >=20 > + PmcGetPwrmBase () + R_PMC_PWRM_GEN_PMCON_A + 3, >=20 > + (UINT8) ~0, >=20 > + B_PMC_PWRM_GEN_PMCON_A_GBL_RST_STS >> 24 >=20 > + ); >=20 > +} >=20 > + >=20 > +/** >=20 > + This function clears Host Reset status (HOST_RST_STS) >=20 > +**/ >=20 > +VOID >=20 > +PmcClearHostResetStatus ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + // >=20 > + // Write 1 to clear HOST_RST_STS >=20 > + // Avoid clearing other W1C bits >=20 > + // >=20 > + MmioAndThenOr8 ( >=20 > + PmcGetPwrmBase () + R_PMC_PWRM_GEN_PMCON_A + 1, >=20 > + (UINT8) ~(B_PMC_PWRM_GEN_PMCON_A_PWR_FLR >> 8), >=20 > + B_PMC_PWRM_GEN_PMCON_A_HOST_RST_STS >> 8 >=20 > + ); >=20 > +} >=20 > + >=20 > +/** >=20 > + This function clears SUS Power Failure status (SUS_PWR_FLR) >=20 > +**/ >=20 > +VOID >=20 > +PmcClearSusPowerFailureStatus ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + // >=20 > + // BIOS clears this bit by writing a '1' to it. >=20 > + // Take care of other fields, so we don't clear them accidentally. >=20 > + // >=20 > + MmioAndThenOr8 ( >=20 > + PmcGetPwrmBase () + R_PMC_PWRM_GEN_PMCON_A + 2, >=20 > + (UINT8) ~(B_PMC_PWRM_GEN_PMCON_A_MS4V >> 16), >=20 > + B_PMC_PWRM_GEN_PMCON_A_SUS_PWR_FLR >> 16 >=20 > + ); >=20 > +} >=20 > + >=20 > +/** >=20 > + This function sets state to which platform will get after power is rea= pplied >=20 > + >=20 > + @param[in] PowerStateAfterG3 0: S0 state (boot) >=20 > + 1: S5/S4 State >=20 > +**/ >=20 > +VOID >=20 > +PmcSetPlatformStateAfterPowerFailure ( >=20 > + IN UINT8 PowerStateAfterG3 >=20 > + ) >=20 > +{ >=20 > + UINT32 PchPwrmBase; >=20 > + >=20 > + PchPwrmBase =3D PmcGetPwrmBase (); >=20 > + >=20 > + if (PowerStateAfterG3) { >=20 > + MmioOr8 (PchPwrmBase + R_PMC_PWRM_GEN_PMCON_A, > B_PMC_PWRM_GEN_PMCON_A_AFTERG3_EN); >=20 > + } else { >=20 > + MmioAnd8 (PchPwrmBase + R_PMC_PWRM_GEN_PMCON_A, > (UINT8)~B_PMC_PWRM_GEN_PMCON_A_AFTERG3_EN); >=20 > + } >=20 > +} >=20 > + >=20 > +/** >=20 > + This function will set the DISB - DRAM Initialization Scratchpad Bit. >=20 > +**/ >=20 > +VOID >=20 > +PmcSetDramInitScratchpad ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + // >=20 > + // Set B_CNL_PCH_PWRM_GEN_PMCON_A_DISB. >=20 > + // NOTE: Byte access and not clear BIT18 and BIT16 (W1C bits) >=20 > + // >=20 > + MmioAndThenOr8 ( >=20 > + PmcGetPwrmBase () + R_PMC_PWRM_GEN_PMCON_A + 2, >=20 > + (UINT8) ~((B_PMC_PWRM_GEN_PMCON_A_MS4V | > B_PMC_PWRM_GEN_PMCON_A_SUS_PWR_FLR) >> 16), >=20 > + B_PMC_PWRM_GEN_PMCON_A_DISB >> 16 >=20 > + ); >=20 > +} >=20 > + >=20 > +/** >=20 > + Check global SMI enable is set >=20 > + >=20 > + @retval TRUE Global SMI enable is set >=20 > + FALSE Global SMI enable is not set >=20 > +**/ >=20 > +BOOLEAN >=20 > +PmcIsGblSmiEn ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return !!(IoRead32 (PmcGetAcpiBase () + R_ACPI_IO_SMI_EN) & > B_ACPI_IO_SMI_EN_GBL_SMI); >=20 > +} >=20 > + >=20 > +/** >=20 > + This function checks if SMI Lock is set >=20 > + >=20 > + @retval SMI Lock state >=20 > +**/ >=20 > +BOOLEAN >=20 > +PmcIsSmiLockSet ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return ((MmioRead8 ((UINTN) (PmcGetPwrmBase () + > R_PMC_PWRM_GEN_PMCON_B)) & > B_PMC_PWRM_GEN_PMCON_B_SMI_LOCK) !=3D 0); >=20 > +} >=20 > + >=20 > +/** >=20 > + This function checks if Debug Mode is locked >=20 > + >=20 > + @retval Debug Mode Lock state >=20 > +**/ >=20 > +BOOLEAN >=20 > +PmcIsDebugModeLocked ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + // >=20 > + // Get lock info from PWRMBASE + PM_CFG >=20 > + // >=20 > + return ((MmioRead32 (PmcGetPwrmBase () + R_PMC_PWRM_CFG) & > B_PMC_PWRM_CFG_DBG_MODE_LOCK) !=3D 0); >=20 > +} >=20 > + >=20 > +/** >=20 > + Check TCO second timeout status. >=20 > + >=20 > + @retval TRUE TCO reboot happened. >=20 > + @retval FALSE TCO reboot didn't happen. >=20 > +**/ >=20 > +BOOLEAN >=20 > +TcoSecondToHappened ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + /// >=20 > + /// Read the Second TO status bit >=20 > + /// >=20 > + if ((IoRead8 (PcdGet16 (PcdTcoBaseAddress) + R_TCO_IO_TCO2_STS) & > R_TCO_IO_TCO2_STS) !=3D 0) { >=20 > + return TRUE; >=20 > + } else { >=20 > + return FALSE; >=20 > + } >=20 > +} >=20 > + >=20 > +/** >=20 > + This function clears the Second TO status bit >=20 > +**/ >=20 > +VOID >=20 > +TcoClearSecondToStatus ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + IoWrite8 (PcdGet16 (PcdTcoBaseAddress) + R_TCO_IO_TCO2_STS, > B_TCO_IO_TCO2_STS_SECOND_TO); >=20 > +} >=20 > + >=20 > +/** >=20 > + Check TCO SMI ENABLE is locked >=20 > + >=20 > + @retval TRUE TCO SMI ENABLE is locked >=20 > + FALSE TCO SMI ENABLE is not locked >=20 > +**/ >=20 > +BOOLEAN >=20 > +TcoIsSmiLock ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return !!(IoRead16 (PcdGet16 (PcdTcoBaseAddress) + > R_TCO_IO_TCO1_CNT) & B_TCO_IO_TCO1_CNT_LOCK); >=20 > +} >=20 > + >=20 > +/** >=20 > + Check if user wants to turn off in PEI phase and power it off >=20 > + CAUTION: this function will potentially turn off your system >=20 > +**/ >=20 > +VOID >=20 > +CheckPowerOffNow ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + UINT16 ABase; >=20 > + UINT16 Pm1Sts; >=20 > + >=20 > + ABase =3D PmcGetAcpiBase (); >=20 > + >=20 > + // >=20 > + // Read and check the ACPI registers >=20 > + // >=20 > + Pm1Sts =3D IoRead16 (ABase + R_ACPI_IO_PM1_STS); >=20 > + >=20 > + DEBUG ((DEBUG_ERROR, "CheckPowerOffNow ()- Pm1Sts=3D 0x%04x\n", > Pm1Sts)); >=20 > + >=20 > + if ((Pm1Sts & B_ACPI_IO_PM1_STS_PWRBTN) !=3D 0) { >=20 > + IoWrite16 (ABase + R_ACPI_IO_PM1_STS, > B_ACPI_IO_PM1_STS_PWRBTN); >=20 > + IoWrite16 (ABase + R_ACPI_IO_PM1_CNT, V_ACPI_IO_PM1_CNT_S5); >=20 > + IoWrite16 (ABase + R_ACPI_IO_PM1_CNT, V_ACPI_IO_PM1_CNT_S5 | > B_ACPI_IO_PM1_CNT_SLP_EN); >=20 > + } >=20 > +} >=20 > + >=20 > +/** >=20 > + Clear any SMI status or wake status. >=20 > +**/ >=20 > +VOID >=20 > +ClearSmiAndWake ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + UINT16 ABase; >=20 > + UINT16 Pm1Sts; >=20 > + >=20 > + ABase =3D PmcGetAcpiBase (); >=20 > + >=20 > + // >=20 > + // Clear any SMI or wake state from the boot >=20 > + // >=20 > + Pm1Sts =3D B_ACPI_IO_PM1_STS_PWRBTN; >=20 > + >=20 > + IoWrite16 (ABase + R_ACPI_IO_PM1_STS, Pm1Sts); >=20 > + >=20 > + // >=20 > + // Clear the GPE and PM enable >=20 > + // >=20 > + IoWrite16 (ABase + R_ACPI_IO_PM1_EN, 0); >=20 > + IoWrite32 (ABase + R_ACPI_IO_GPE0_EN_127_96, 0); >=20 > +} >=20 > + >=20 > + >=20 > +/** >=20 > + Function to check if Dirty Warm Reset occurs >=20 > + (Global Reset has been converted to Host Reset) >=20 > + >=20 > + @reval TRUE DWR occurs >=20 > + @reval FALSE Normal boot flow >=20 > +**/ >=20 > +BOOLEAN >=20 > +PmcIsDwrBootMode ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + UINT32 PchPwrmBase; >=20 > + >=20 > + PchPwrmBase =3D PmcGetPwrmBase (); >=20 > + ASSERT (PchPwrmBase !=3D 0); >=20 > + >=20 > + return !!(MmioRead32 (PchPwrmBase + R_PMC_PWRM_HPR_CAUSE0) & > B_PMC_PWRM_HPR_CAUSE0_GBL_TO_HOST); >=20 > +} >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmP > mcPrivateLib/PeiDxeSmmPmcPrivateLibVer2.inf > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmP > mcPrivateLib/PeiDxeSmmPmcPrivateLibVer2.inf > new file mode 100644 > index 0000000000..2bd57b79f0 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmP > mcPrivateLib/PeiDxeSmmPmcPrivateLibVer2.inf > @@ -0,0 +1,39 @@ > +## @file >=20 > +# PEI/DXE/SMM PCH PMC Private Lib Ver2. >=20 > +# >=20 > +# All function in this library is available for PEI, DXE, and SMM, >=20 > +# But do not support UEFI RUNTIME environment call. >=20 > +# >=20 > +# Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > +# SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +# >=20 > +## >=20 > + >=20 > + >=20 > +[Defines] >=20 > +INF_VERSION =3D 0x00010017 >=20 > +BASE_NAME =3D PeiDxeSmmPmcPrivateLibVer2 >=20 > +FILE_GUID =3D EB69B12B-6D4C-4B12-BB31-66CBCC4C1DC7 >=20 > +VERSION_STRING =3D 1.0 >=20 > +MODULE_TYPE =3D BASE >=20 > +LIBRARY_CLASS =3D PmcPrivateLib >=20 > + >=20 > + >=20 > +[LibraryClasses] >=20 > +BaseLib >=20 > +IoLib >=20 > +DebugLib >=20 > +PmcLib >=20 > + >=20 > +[Packages] >=20 > +MdePkg/MdePkg.dec >=20 > +TigerlakeSiliconPkg/SiPkg.dec >=20 > + >=20 > + >=20 > +[Pcd] >=20 > +gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress >=20 > + >=20 > +[FixedPcd] >=20 > + >=20 > +[Sources] >=20 > +PmcPrivateLib.c >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmP > mcPrivateLib/PeiDxeSmmPmcPrivateLibWithS3.inf > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmP > mcPrivateLib/PeiDxeSmmPmcPrivateLibWithS3.inf > new file mode 100644 > index 0000000000..72a21cfe14 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmP > mcPrivateLib/PeiDxeSmmPmcPrivateLibWithS3.inf > @@ -0,0 +1,40 @@ > +## @file >=20 > +# PEI/DXE/SMM PCH private PMC Lib. >=20 > +# This part of PMC lib includes S3BootScript support >=20 > +# >=20 > +# All function in this library is available for PEI, DXE, and SMM, >=20 > +# But do not support UEFI RUNTIME environment call. >=20 > +# >=20 > +# Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > +# SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +# >=20 > +## >=20 > + >=20 > + >=20 > +[Defines] >=20 > +INF_VERSION =3D 0x00010017 >=20 > +BASE_NAME =3D PeiDxeSmmPmcPrivateLibWithS3 >=20 > +FILE_GUID =3D 5890CA5A-1955-4A02-A09C-01E4150606CC >=20 > +VERSION_STRING =3D 1.0 >=20 > +MODULE_TYPE =3D BASE >=20 > +LIBRARY_CLASS =3D PmcPrivateLibWithS3 >=20 > + >=20 > + >=20 > +[LibraryClasses] >=20 > +BaseLib >=20 > +IoLib >=20 > +DebugLib >=20 > +PciSegmentLib >=20 > +PmcLib >=20 > +PcdLib >=20 > +S3BootScriptLib >=20 > +PchPciBdfLib >=20 > + >=20 > + >=20 > +[Packages] >=20 > +MdePkg/MdePkg.dec >=20 > +TigerlakeSiliconPkg/SiPkg.dec >=20 > + >=20 > + >=20 > +[Sources] >=20 > +PmcPrivateLibWithS3.c >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmP > mcPrivateLib/PmcPrivateLib.c > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmP > mcPrivateLib/PmcPrivateLib.c > new file mode 100644 > index 0000000000..4f04765886 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmP > mcPrivateLib/PmcPrivateLib.c > @@ -0,0 +1,166 @@ > +/** @file >=20 > + PCH private PMC Library for all PCH generations. >=20 > + All function in this library is available for PEI, DXE, and SMM, >=20 > + But do not support UEFI RUNTIME environment call. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +/** >=20 > + This function checks if GbE device is supported (not disabled by fuse) >=20 > + >=20 > + @retval GbE support state >=20 > +**/ >=20 > +BOOLEAN >=20 > +PmcIsGbeSupported ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + // >=20 > + // Get fuse info from PWRMBASE + FUSE_SS_DIS_RD_2 >=20 > + // >=20 > + return ((MmioRead32 (PmcGetPwrmBase () + > R_PMC_PWRM_FUSE_DIS_RD_2) & > B_PMC_PWRM_FUSE_DIS_RD_2_GBE_FUSE_SS_DIS) =3D=3D 0); >=20 > +} >=20 > + >=20 > +/** >=20 > + This function checks if LAN wake from DeepSx is enabled >=20 > + >=20 > + @retval Lan Wake state >=20 > +**/ >=20 > +BOOLEAN >=20 > +PmcIsLanDeepSxWakeEnabled ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + // >=20 > + // Get wake info from PWRMBASE + DSX_CFG >=20 > + // >=20 > + return ((MmioRead32 (PmcGetPwrmBase () + R_PMC_PWRM_DSX_CFG) > & (UINT32) B_PMC_PWRM_DSX_CFG_LAN_WAKE_EN) !=3D 0); >=20 > +} >=20 > + >=20 > +/** >=20 > + This function checks if eSPI SMI Lock is set >=20 > + >=20 > + @retval eSPI SMI Lock state >=20 > +**/ >=20 > +BOOLEAN >=20 > +PmcIsEspiSmiLockSet ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return ((MmioRead32 ((UINTN) (PmcGetPwrmBase () + > R_PMC_PWRM_GEN_PMCON_A)) & > B_PMC_PWRM_GEN_PMCON_A_ESPI_SMI_LOCK) !=3D 0); >=20 > +} >=20 > + >=20 > +/** >=20 > + This function sets SW SMI Rate. >=20 > + >=20 > + @param[in] SwSmiRate Refer to PMC_SWSMI_RATE for possible > values >=20 > +**/ >=20 > +VOID >=20 > +PmcSetSwSmiRate ( >=20 > + IN PMC_SWSMI_RATE SwSmiRate >=20 > + ) >=20 > +{ >=20 > + UINT32 PchPwrmBase; >=20 > + STATIC UINT8 SwSmiRateRegVal[4] =3D { >=20 > + V_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL_1_5MS, >=20 > + V_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL_16MS, >=20 > + V_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL_32MS, >=20 > + V_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL_64MS >=20 > + }; >=20 > + >=20 > + ASSERT (SwSmiRate <=3D PmcSwSmiRate64ms); >=20 > + >=20 > + PchPwrmBase =3D PmcGetPwrmBase (); >=20 > + >=20 > + // >=20 > + // SWSMI_RATE_SEL BIT (PWRMBASE offset 1020h[7:6]) bits are in RTC > well >=20 > + // >=20 > + MmioAndThenOr8 ( >=20 > + PchPwrmBase + R_PMC_PWRM_GEN_PMCON_A, >=20 > + (UINT8)~B_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL, >=20 > + SwSmiRateRegVal[SwSmiRate] >=20 > + ); >=20 > +} >=20 > + >=20 > +/** >=20 > + This function sets Periodic SMI Rate. >=20 > + >=20 > + @param[in] PeriodicSmiRate Refer to PMC_PERIODIC_SMI_RATE for > possible values >=20 > +**/ >=20 > +VOID >=20 > +PmcSetPeriodicSmiRate ( >=20 > + IN PMC_PERIODIC_SMI_RATE PeriodicSmiRate >=20 > + ) >=20 > +{ >=20 > + UINT32 PchPwrmBase; >=20 > + STATIC UINT8 PeriodicSmiRateRegVal[4] =3D { >=20 > + V_PMC_PWRM_GEN_PMCON_A_PER_SMI_8S, >=20 > + V_PMC_PWRM_GEN_PMCON_A_PER_SMI_16S, >=20 > + V_PMC_PWRM_GEN_PMCON_A_PER_SMI_32S, >=20 > + V_PMC_PWRM_GEN_PMCON_A_PER_SMI_64S >=20 > + }; >=20 > + >=20 > + ASSERT (PeriodicSmiRate <=3D PmcPeriodicSmiRate64s); >=20 > + >=20 > + PchPwrmBase =3D PmcGetPwrmBase (); >=20 > + >=20 > + MmioAndThenOr8 ( >=20 > + PchPwrmBase + R_PMC_PWRM_GEN_PMCON_A, >=20 > + (UINT8)~B_PMC_PWRM_GEN_PMCON_A_PER_SMI_SEL, >=20 > + PeriodicSmiRateRegVal[PeriodicSmiRate] >=20 > + ); >=20 > +} >=20 > + >=20 > +/** >=20 > + This function reads Power Button Level >=20 > + >=20 > + @retval State of PWRBTN# signal (0: Low, 1: High) >=20 > +**/ >=20 > +UINT8 >=20 > +PmcGetPwrBtnLevel ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + if (MmioRead32 (PmcGetPwrmBase () + R_PMC_PWRM_GEN_PMCON_B) > & B_PMC_PWRM_GEN_PMCON_B_PWRBTN_LVL) { >=20 > + return 1; >=20 > + } else { >=20 > + return 0; >=20 > + } >=20 > +} >=20 > + >=20 > +/** >=20 > + This function gets Group to GPE0 configuration >=20 > + >=20 > + @param[out] GpeDw0Value GPIO Group to GPE_DW0 assignment >=20 > + @param[out] GpeDw1Value GPIO Group to GPE_DW1 assignment >=20 > + @param[out] GpeDw2Value GPIO Group to GPE_DW2 assignment >=20 > +**/ >=20 > +VOID >=20 > +PmcGetGpioGpe ( >=20 > + OUT UINT32 *GpeDw0Value, >=20 > + OUT UINT32 *GpeDw1Value, >=20 > + OUT UINT32 *GpeDw2Value >=20 > + ) >=20 > +{ >=20 > + UINT32 Data32; >=20 > + >=20 > + Data32 =3D MmioRead32 ((UINTN) (PmcGetPwrmBase () + > R_PMC_PWRM_GPIO_CFG)); >=20 > + >=20 > + *GpeDw0Value =3D ((Data32 & B_PMC_PWRM_GPIO_CFG_GPE0_DW0) >> > N_PMC_PWRM_GPIO_CFG_GPE0_DW0); >=20 > + *GpeDw1Value =3D ((Data32 & B_PMC_PWRM_GPIO_CFG_GPE0_DW1) >> > N_PMC_PWRM_GPIO_CFG_GPE0_DW1); >=20 > + *GpeDw2Value =3D ((Data32 & B_PMC_PWRM_GPIO_CFG_GPE0_DW2) >> > N_PMC_PWRM_GPIO_CFG_GPE0_DW2); >=20 > +} >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmP > mcPrivateLib/PmcPrivateLibWithS3.c > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmP > mcPrivateLib/PmcPrivateLibWithS3.c > new file mode 100644 > index 0000000000..02acd0d688 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmP > mcPrivateLib/PmcPrivateLibWithS3.c > @@ -0,0 +1,122 @@ > +/** @file >=20 > + PCH private PMC Library. >=20 > + All function in this library is available for PEI, DXE, and SMM, >=20 > + But do not support UEFI RUNTIME environment call. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +/** >=20 > + This S3 BootScript only function disables triggering Global Reset of b= oth >=20 > + the Host and the ME partitions after CF9h write of 6h or Eh. >=20 > +**/ >=20 > +VOID >=20 > +PmcDisableCf9GlobalResetInS3BootScript ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + UINT32 Data; >=20 > + >=20 > + UINT32 PchPwrmBase; >=20 > + PchPwrmBase =3D PmcGetPwrmBase (); >=20 > + >=20 > + Data =3D MmioRead32 (PchPwrmBase + R_PMC_PWRM_ETR3); >=20 > + >=20 > + Data &=3D (UINT32) ~B_PMC_PWRM_ETR3_CF9GR; >=20 > + >=20 > + S3BootScriptSaveMemWrite ( >=20 > + S3BootScriptWidthUint32, >=20 > + (UINTN) PchPwrmBase + >=20 > + R_PMC_PWRM_ETR3, >=20 > + 1, >=20 > + &Data >=20 > + ); >=20 > +} >=20 > + >=20 > +/** >=20 > + This S3 BootScript only function disables triggering Global Reset of b= oth >=20 > + the Host and the ME partitions after CF9h write of 6h or Eh. >=20 > + Global Reset configuration is locked after programming >=20 > +**/ >=20 > +VOID >=20 > +PmcDisableCf9GlobalResetWithLockInS3BootScript ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + UINT32 Data; >=20 > + >=20 > + UINT32 PchPwrmBase; >=20 > + PchPwrmBase =3D PmcGetPwrmBase (); >=20 > + >=20 > + Data =3D MmioRead32 (PchPwrmBase + R_PMC_PWRM_ETR3); >=20 > + >=20 > + Data &=3D (UINT32) ~B_PMC_PWRM_ETR3_CF9GR; >=20 > + Data |=3D (UINT32) B_PMC_PWRM_ETR3_CF9LOCK; >=20 > + >=20 > + S3BootScriptSaveMemWrite ( >=20 > + S3BootScriptWidthUint32, >=20 > + (UINTN) PchPwrmBase + >=20 > + R_PMC_PWRM_ETR3, >=20 > + 1, >=20 > + &Data >=20 > + ); >=20 > +} >=20 > + >=20 > +/** >=20 > + This function sets SMI Lock with S3 Boot Script programming >=20 > +**/ >=20 > +VOID >=20 > +PmcLockSmiWithS3BootScript ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + UINT32 PchPwrmBase; >=20 > + >=20 > + PchPwrmBase =3D PmcGetPwrmBase (); >=20 > + >=20 > + MmioOr8 ((UINTN) (PchPwrmBase + R_PMC_PWRM_GEN_PMCON_B), > B_PMC_PWRM_GEN_PMCON_B_SMI_LOCK); >=20 > + >=20 > + S3BootScriptSaveMemWrite ( >=20 > + S3BootScriptWidthUint8, >=20 > + (UINTN) (PchPwrmBase + R_PMC_PWRM_GEN_PMCON_B), >=20 > + 1, >=20 > + (VOID *) (UINTN) (PchPwrmBase + R_PMC_PWRM_GEN_PMCON_B) >=20 > + ); >=20 > +} >=20 > + >=20 > +/** >=20 > + This function sets eSPI SMI Lock >=20 > + @attention This function must be called after eSPI SMI generation has > been enabled. >=20 > + This setting is required in all boot modes and before EndOfDxe. >=20 > + If set value will be restored upon S3 resume by bootscript. >=20 > +**/ >=20 > +VOID >=20 > +PmcLockEspiSmiWithS3BootScript ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + UINT8 Data8Or; >=20 > + UINT8 Data8And; >=20 > + >=20 > + Data8Or =3D (UINT8) (B_PMC_PWRM_GEN_PMCON_A_ESPI_SMI_LOCK >> > 8); >=20 > + Data8And =3D (UINT8)~((B_PMC_PWRM_GEN_PMCON_A_PWR_FLR | > B_PMC_PWRM_GEN_PMCON_A_HOST_RST_STS) >> 8); >=20 > + >=20 > + MmioAndThenOr8 (PmcGetPwrmBase () + > R_PMC_PWRM_GEN_PMCON_A + 1, Data8And, Data8Or); >=20 > + S3BootScriptSaveMemReadWrite ( >=20 > + S3BootScriptWidthUint8, >=20 > + PmcGetPwrmBase () + R_PMC_PWRM_GEN_PMCON_A + 1, >=20 > + &Data8Or, >=20 > + &Data8And >=20 > + ); >=20 > +} >=20 > -- > 2.24.0.windows.2