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From: "Nate DeSimone" <nathaniel.l.desimone@intel.com>
To: "Luo, Heng" <heng.luo@intel.com>,
	"devel@edk2.groups.io" <devel@edk2.groups.io>
Cc: "Chaganty, Rangasai V" <rangasai.v.chaganty@intel.com>
Subject: Re: [PATCH 10/40] TigerlakeSiliconPkg/Fru: Add TglCpu/IncludePrivate headers
Date: Thu, 4 Feb 2021 03:53:43 +0000	[thread overview]
Message-ID: <BN6PR1101MB21476B0DF989BF13C0936BA4CDB39@BN6PR1101MB2147.namprd11.prod.outlook.com> (raw)
In-Reply-To: <20210201013657.1833-10-heng.luo@intel.com>

Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>

> -----Original Message-----
> From: Luo, Heng <heng.luo@intel.com>
> Sent: Sunday, January 31, 2021 5:36 PM
> To: devel@edk2.groups.io
> Cc: Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Desimone,
> Nathaniel L <nathaniel.l.desimone@intel.com>
> Subject: [PATCH 10/40] TigerlakeSiliconPkg/Fru: Add TglCpu/IncludePrivate
> headers
> 
> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171
> 
> Adds the following header files:
>   * Fru/TglCpu/IncludePrivate
> 
> Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
> Signed-off-by: Heng Luo <heng.luo@intel.com>
> ---
> 
> Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Library/VtdInitFr
> uLib.h | 18 ++++++++++++++++++
> Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Register/CpuPci
> eRegs.h  | 24 ++++++++++++++++++++++++
> 
> Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Register/IgdRegs
> .h      | 42 ++++++++++++++++++++++++++++++++++++++++++
> 
> Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Register/IpuReg
> s.h      | 31 +++++++++++++++++++++++++++++++
> 
> Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Register/VtdReg
> s.h      | 22 ++++++++++++++++++++++
>  5 files changed, 137 insertions(+)
> 
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Library/VtdInit
> FruLib.h
> b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Library/VtdInit
> FruLib.h
> new file mode 100644
> index 0000000000..a46b29cbbe
> --- /dev/null
> +++ b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Librar
> +++ y/VtdInitFruLib.h
> @@ -0,0 +1,18 @@
> +/** @file+  Vtd Initialization Fru Library header file++  Copyright (c) 2021,
> Intel Corporation. All rights reserved.<BR>+  SPDX-License-Identifier: BSD-2-
> Clause-Patent+**/+#ifndef _VTD_INIT_FRU_LIB_H_+#define
> _VTD_INIT_FRU_LIB_H_++///+/// TCSS DMA controller RMRR buffer 4MB
> for each DMA controller+///+#define RMRR_TCSS_DMA_SIZE
> 0x400000++extern UINT16  mDevEnMap[][2];+extern UINTN
> mDevEnMapSize;++#endif // _VTD_INIT_FRU_LIB_H_diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Register/CpuP
> cieRegs.h
> b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Register/CpuP
> cieRegs.h
> new file mode 100644
> index 0000000000..a571381202
> --- /dev/null
> +++ b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Regist
> +++ er/CpuPcieRegs.h
> @@ -0,0 +1,24 @@
> +/** @file+  This file contains definitions of  PCIe Configuration++  Copyright
> (c) 2021, Intel Corporation. All rights reserved.<BR>+  SPDX-License-
> Identifier: BSD-2-Clause-Patent+**/++#ifndef
> _CPU_PCIE_REGS_H_+#define _CPU_PCIE_REGS_H_++#define
> R_PCIE_LCAP                              0x4C+#define  R_PCIE_LCTL
> 0x50+#define  R_PCIE_LSTS                              0x52+#define  R_PCIE_SLCAP
> 0x54+#define  R_PCIE_SLSTS                             0x5A+#define  R_PCIE_LCTL2
> 0x70+#define  R_PCIE_MPC                               0xD8+#define
> B_PCIE_MPC_HPME                          BIT1+#define  R_PCIE_PGTHRES
> 0x5C0+#define  B_PCIE_PGTHRES_L1PGLTREN                 BIT0+#define
> R_PCIE_LCTL3                             0xA34+#define  B_PCIE_LCTL3_PE
> BIT0++#endifdiff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Register/IgdRe
> gs.h
> b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Register/IgdR
> egs.h
> new file mode 100644
> index 0000000000..f0b30107f4
> --- /dev/null
> +++ b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Regist
> +++ er/IgdRegs.h
> @@ -0,0 +1,42 @@
> +/** @file+  Register names for IGD block+  <b>Conventions</b>:+  -
> Prefixes:+    - Definitions beginning with "R_" are registers+    - Definitions
> beginning with "B_" are bits within registers+    - Definitions beginning with
> "V_" are meaningful values of bits within the registers+    - Definitions
> beginning with "S_" are register sizes+    - Definitions beginning with "N_" are
> the bit position+  - In general, SA registers are denoted by "_SA_" in register
> names+  - Registers / bits that are different between SA generations are
> denoted by+    "_SA_[generation_name]_" in register/bit names. e.g.,
> "_SA_HSW_"+  - Registers / bits that are different between SKUs are
> denoted by "_[SKU_name]"+    at the end of the register/bit names+  -
> Registers / bits of new devices introduced in a SA generation will be just
> named+    as "_SA_" without [generation_name] inserted.++  Copyright (c)
> 2021, Intel Corporation. All rights reserved.<BR>+  SPDX-License-Identifier:
> BSD-2-Clause-Patent+**/+#ifndef _IGD_REGS_H_+#define
> _IGD_REGS_H_++///+/// Device 2 Register Equates+///+//+// The following
> equates must be reviewed and revised when the specification is
> ready.+//+#define IGD_BUS_NUM          0x00+#define IGD_DEV_NUM
> 0x02+#define IGD_FUN_NUM          0x00++///+/// GTTMMADR aligned to
> 16MB (Base address = [38:24])+///+#define R_SA_IGD_GTTMMADR
> 0x10++#define R_SA_IGD_SWSCI_OFFSET      0x00E8+#define
> R_SA_IGD_ASLS_OFFSET       0x00FC  ///< ASL Storage++#endifdiff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Register/IpuR
> egs.h
> b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Register/IpuR
> egs.h
> new file mode 100644
> index 0000000000..afc72e8db0
> --- /dev/null
> +++ b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Regist
> +++ er/IpuRegs.h
> @@ -0,0 +1,31 @@
> +/** @file+  Register names for IPU block+  <b>Conventions</b>:+  -
> Prefixes:+    - Definitions beginning with "R_" are registers+    - Definitions
> beginning with "B_" are bits within registers+    - Definitions beginning with
> "V_" are meaningful values of bits within the registers+    - Definitions
> beginning with "S_" are register sizes+    - Definitions beginning with "N_" are
> the bit position+  - IPU registers are denoted by "_IPU_" in register names+  -
> Registers / bits that are different between IPU generations are denoted by+
> "_IPU_[generation_name]_" in register/bit names. e.g., "_IPU_TGL_"+  -
> Registers / bits that are different between SKUs are denoted by
> "_[SKU_name]"+    at the end of the register/bit names+  - Registers / bits of
> new devices introduced in a IPU generation will be just named+    as "_IPU_"
> without [generation_name] inserted.++  Copyright (c) 2021, Intel
> Corporation. All rights reserved.<BR>+  SPDX-License-Identifier: BSD-2-
> Clause-Patent+**/+#ifndef _IPU_REGS_H_+#define _IPU_REGS_H_++//+//
> Device 5 Equates+//+#define IPU_BUS_NUM    0x00+#define
> IPU_DEV_NUM    0x05+#define IPU_FUN_NUM    0x00++#endif  //
> _IPU_REGS_H_diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Register/VtdR
> egs.h
> b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Register/VtdR
> egs.h
> new file mode 100644
> index 0000000000..d796a44afc
> --- /dev/null
> +++ b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Regist
> +++ er/VtdRegs.h
> @@ -0,0 +1,22 @@
> +/** @file+  Register names for VTD block+  <b>Conventions</b>:+  -
> Prefixes:+    - Definitions beginning with "R_" are registers+    - Definitions
> beginning with "B_" are bits within registers+    - Definitions beginning with
> "V_" are meaningful values of bits within the registers+    - Definitions
> beginning with "S_" are register sizes+    - Definitions beginning with "N_" are
> the bit position+  Copyright (c) 2021, Intel Corporation. All rights
> reserved.<BR>+  SPDX-License-Identifier: BSD-2-Clause-Patent+**/+#ifndef
> _VTD_REGS_H_+#define _VTD_REGS_H_++///+/// Vt-d Engine base
> address.+///+#define R_MCHBAR_VTD1_OFFSET                 0x5400  ///< HW
> UNIT1 for IGD+#define R_MCHBAR_VTD3_OFFSET                 0x5410  ///< HW
> UNIT3 for all other - PEG, USB, SATA etc++#endif--
> 2.24.0.windows.2


  reply	other threads:[~2021-02-04  3:54 UTC|newest]

Thread overview: 81+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-02-01  1:36 [PATCH 01/40] TigerlakeSiliconPkg: Add package and Include/ConfigBlock headers Heng Luo
2021-02-01  1:36 ` [PATCH 02/40] TigerlakeSiliconPkg/Include: Add Library, PPI and Protocol include headers Heng Luo
2021-02-04  3:51   ` Nate DeSimone
2021-02-01  1:36 ` [PATCH 03/40] TigerlakeSiliconPkg/Include: Add Pins, Register and other " Heng Luo
2021-02-04  3:52   ` Nate DeSimone
2021-02-01  1:36 ` [PATCH 04/40] TigerlakeSiliconPkg/Cpu: Add Include headers Heng Luo
2021-02-04  3:53   ` Nate DeSimone
2021-02-01  1:36 ` [PATCH 05/40] TigerlakeSiliconPkg/Pch: Add include headers Heng Luo
2021-02-04  3:53   ` Nate DeSimone
2021-02-01  1:36 ` [PATCH 06/40] TigerlakeSiliconPkg/Pch: Add IncludePrivate headers Heng Luo
2021-02-04  3:53   ` Nate DeSimone
2021-02-01  1:36 ` [PATCH 07/40] TigerlakeSiliconPkg/SystemAgent: Add include headers Heng Luo
2021-02-04  3:53   ` Nate DeSimone
2021-02-01  1:36 ` [PATCH 08/40] TigerlakeSiliconPkg/SystemAgent: Add IncludePrivate headers Heng Luo
2021-02-04  3:53   ` Nate DeSimone
2021-02-01  1:36 ` [PATCH 09/40] TigerlakeSiliconPkg/Fru: Add TglCpu/Include headers Heng Luo
2021-02-04  3:53   ` Nate DeSimone
2021-02-01  1:36 ` [PATCH 10/40] TigerlakeSiliconPkg/Fru: Add TglCpu/IncludePrivate headers Heng Luo
2021-02-04  3:53   ` Nate DeSimone [this message]
2021-02-01  1:36 ` [PATCH 11/40] TigerlakeSiliconPkg/Fru: Add TglPch/Include headers Heng Luo
2021-02-04  3:53   ` Nate DeSimone
2021-02-01  1:36 ` [PATCH 12/40] TigerlakeSiliconPkg/Fru: Add TglPch/IncludePrivate headers Heng Luo
2021-02-04  3:53   ` Nate DeSimone
2021-02-01  1:36 ` [PATCH 13/40] TigerlakeSiliconPkg/IpBlock: Add Cnvi component Heng Luo
2021-02-04  3:53   ` Nate DeSimone
2021-02-01  1:36 ` [PATCH 14/40] TigerlakeSiliconPkg/IpBlock: Add CpuPcieRp component Heng Luo
2021-02-04  3:53   ` Nate DeSimone
2021-02-01  1:36 ` [PATCH 15/40] TigerlakeSiliconPkg/IpBlock: Add Espi component Heng Luo
2021-02-04  3:54   ` Nate DeSimone
2021-02-01  1:36 ` [PATCH 16/40] TigerlakeSiliconPkg/IpBlock: Add Gbe component Heng Luo
2021-02-04  3:54   ` Nate DeSimone
2021-02-01  1:36 ` [PATCH 17/40] TigerlakeSiliconPkg/IpBlock: Add Gpio component Heng Luo
2021-02-04  3:54   ` Nate DeSimone
2021-02-01  1:36 ` [PATCH 18/40] TigerlakeSiliconPkg/IpBlock: Add Graphics component Heng Luo
2021-02-04  3:54   ` Nate DeSimone
2021-02-01  1:36 ` [PATCH 19/40] TigerlakeSiliconPkg/IpBlock: Add Hda component Heng Luo
2021-02-04  3:54   ` Nate DeSimone
2021-02-01  1:36 ` [PATCH 20/40] TigerlakeSiliconPkg/IpBlock: Add HostBridge component Heng Luo
2021-02-04  3:54   ` Nate DeSimone
2021-02-01  1:36 ` [PATCH 21/40] TigerlakeSiliconPkg/IpBlock: Add P2sb component Heng Luo
2021-02-04  3:54   ` Nate DeSimone
2021-02-01  1:36 ` [PATCH 22/40] TigerlakeSiliconPkg/IpBlock: Add PchDmi component Heng Luo
2021-02-04  3:54   ` Nate DeSimone
2021-02-01  1:36 ` [PATCH 23/40] TigerlakeSiliconPkg/IpBlock: Add PcieRp component Heng Luo
2021-02-04  3:55   ` Nate DeSimone
2021-02-01  1:36 ` [PATCH 24/40] TigerlakeSiliconPkg/IpBlock: Add Pmc component Heng Luo
2021-02-04  3:56   ` Nate DeSimone
2021-02-01  1:36 ` [PATCH 25/40] TigerlakeSiliconPkg/IpBlock: Add Psf component Heng Luo
2021-02-04  3:56   ` Nate DeSimone
2021-02-01  1:36 ` [PATCH 26/40] TigerlakeSiliconPkg/IpBlock: Add Sata component Heng Luo
2021-02-04  3:56   ` Nate DeSimone
2021-02-01  1:36 ` [PATCH 27/40] TigerlakeSiliconPkg/IpBlock: Add SerialIo component Heng Luo
2021-02-04  3:56   ` Nate DeSimone
2021-02-01  1:36 ` [PATCH 28/40] TigerlakeSiliconPkg/IpBlock: Add Smbus component Heng Luo
2021-02-04  3:56   ` Nate DeSimone
2021-02-01  1:36 ` [PATCH 29/40] TigerlakeSiliconPkg/IpBlock: Add Spi component Heng Luo
2021-02-04  3:56   ` Nate DeSimone
2021-02-01  1:36 ` [PATCH 30/40] TigerlakeSiliconPkg/IpBlock: Add Vtd component Heng Luo
2021-02-04  3:56   ` Nate DeSimone
2021-02-01  1:36 ` [PATCH 31/40] TigerlakeSiliconPkg/Library: Add package common library instances Heng Luo
2021-02-04  3:56   ` Nate DeSimone
2021-02-01  1:36 ` [PATCH 32/40] TigerlakeSiliconPkg/Pch: Add Pch " Heng Luo
2021-02-04  3:56   ` Nate DeSimone
2021-02-01  1:36 ` [PATCH 33/40] TigerlakeSiliconPkg/Pch: Add Pch private " Heng Luo
2021-02-04  3:56   ` Nate DeSimone
2021-02-01  1:36 ` [PATCH 34/40] TigerlakeSiliconPkg/SystemAgent: Add Acpi Tables and " Heng Luo
2021-02-04  3:56   ` Nate DeSimone
2021-02-01  1:36 ` [PATCH 35/40] TigerlakeSiliconPkg/Fru/TglCpu: Add CpuPcieRp and Vtd " Heng Luo
2021-02-04  3:56   ` Nate DeSimone
2021-02-01  1:36 ` [PATCH 36/40] TigerlakeSiliconPkg/Pch: Add Pch modules Heng Luo
2021-02-04  3:56   ` Nate DeSimone
2021-02-01  1:36 ` [PATCH 37/40] TigerlakeSiliconPkg/SystemAgent: Add SystemAgent modules Heng Luo
2021-02-04  3:56   ` Nate DeSimone
2021-02-01  1:36 ` [PATCH 38/40] TigerlakeSiliconPkg/Fru: Add Fru DSC files Heng Luo
2021-02-04  3:56   ` Nate DeSimone
2021-02-01  1:36 ` [PATCH 39/40] TigerlakeSiliconPkg: Add package " Heng Luo
2021-02-04  3:56   ` Nate DeSimone
2021-02-01  1:36 ` [PATCH 40/40] Maintainers.txt: Add TigerlakeSiliconPkg maintainers Heng Luo
2021-02-04  3:51   ` Nate DeSimone
2021-02-04  8:24     ` Heng Luo
2021-02-04  3:51 ` [PATCH 01/40] TigerlakeSiliconPkg: Add package and Include/ConfigBlock headers Nate DeSimone

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