From: "Nate DeSimone" <nathaniel.l.desimone@intel.com>
To: "Luo, Heng" <heng.luo@intel.com>,
"devel@edk2.groups.io" <devel@edk2.groups.io>
Cc: "Chaganty, Rangasai V" <rangasai.v.chaganty@intel.com>
Subject: Re: [PATCH 35/40] TigerlakeSiliconPkg/Fru/TglCpu: Add CpuPcieRp and Vtd library instances
Date: Thu, 4 Feb 2021 03:56:40 +0000 [thread overview]
Message-ID: <BN6PR1101MB21476B962CC7502715B071D3CDB39@BN6PR1101MB2147.namprd11.prod.outlook.com> (raw)
In-Reply-To: <20210201013657.1833-35-heng.luo@intel.com>
Hi Heng,
Please see comments inline.
Thanks,
Nate
> -----Original Message-----
> From: Luo, Heng <heng.luo@intel.com>
> Sent: Sunday, January 31, 2021 5:37 PM
> To: devel@edk2.groups.io
> Cc: Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Desimone,
> Nathaniel L <nathaniel.l.desimone@intel.com>
> Subject: [PATCH 35/40] TigerlakeSiliconPkg/Fru/TglCpu: Add CpuPcieRp and
> Vtd library instances
>
> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171
>
> Adds the following files:
> * Fru/TglCpu/CpuPcieRp/Library/PeiDxeSmmCpuPcieInfoFruLib
> * Fru/TglCpu/Vtd/LibraryPrivate/DxeVtdInitLib
>
> Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
> Signed-off-by: Heng Luo <heng.luo@intel.com>
> ---
>
> Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/CpuPcieRp/Library/PeiDxeSmm
> CpuPcieInfoFruLib/CpuPcieInfoFruLib.c | 81
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> +++++++++++++++++++++++
>
> Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/CpuPcieRp/Library/PeiDxeSmm
> CpuPcieInfoFruLib/PeiDxeSmmCpuPcieInfoFruLib.inf | 36
> ++++++++++++++++++++++++++++++++++++
>
> Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Vtd/LibraryPrivate/DxeVtdInitLi
> b/DxeVtdInitFruLib.c | 18 ++++++++++++++++++
>
> Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Vtd/LibraryPrivate/DxeVtdInitLi
> b/DxeVtdInitFruLib.inf | 39
> +++++++++++++++++++++++++++++++++++++++
> 4 files changed, 174 insertions(+)
>
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/CpuPcieRp/Library/PeiDxeSm
> mCpuPcieInfoFruLib/CpuPcieInfoFruLib.c
> b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/CpuPcieRp/Library/PeiDxeSm
> mCpuPcieInfoFruLib/CpuPcieInfoFruLib.c
> new file mode 100644
> index 0000000000..6a9bc89ecf
> --- /dev/null
> +++
> b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/CpuPcieRp/Library/PeiDxeSm
> mCpuPcieInfoFruLib/CpuPcieInfoFruLib.c
> @@ -0,0 +1,81 @@
> +/** @file
>
> + CPU PCIe information library.
>
> +
>
> + All function in this library is available for PEI, DXE, and SMM,
>
> + But do not support UEFI RUNTIME environment call.
>
> +
>
> + Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +**/
>
> +#include <Uefi/UefiBaseType.h>
>
> +#include <Library/DebugLib.h>
>
> +#include <Library/BaseLib.h>
>
> +#include <Library/PciSegmentLib.h>
>
> +#include <Register/CpuPcieRegs.h>
>
> +#include <Library/CpuPcieInfoFruLib.h>
>
> +#include <Library/CpuPcieInitCommon.h>
>
> +#include <CpuPcieInfo.h>
>
> +#include <Register/SaRegsHostBridge.h>
>
> +#include <PcieRegs.h>
>
> +
>
> +/**
>
> + Get Maximum CPU Pcie Root Port Number
>
> +
>
> + @retval Maximum CPU Pcie Root Port Number
>
> +**/
>
> +UINT8
>
> +GetMaxCpuPciePortNum (
>
> + VOID
>
> + )
>
> +{
>
> + return CPU_PCIE_ULT_ULX_MAX_ROOT_PORT;
>
> +}
>
> +
>
> +/**
>
> + Get CPU Pcie Root Port Device and Function Number by Root Port physical
> Number
>
> +
>
> + @param[in] RpNumber Root port physical number. (0-based)
>
> + @param[out] RpDev Return corresponding root port device
> number.
>
> + @param[out] RpFun Return corresponding root port function
> number.
>
> +
>
> + @retval EFI_SUCCESS Root port device and function is retrieved
>
> + @retval EFI_INVALID_PARAMETER RpNumber is invalid
>
> +**/
>
> +EFI_STATUS
>
> +EFIAPI
>
> +GetCpuPcieRpDevFun (
>
> + IN UINTN RpNumber,
>
> + OUT UINTN *RpDev,
>
> + OUT UINTN *RpFun
>
> + )
>
> +{
>
> + if (RpNumber > GetMaxCpuPciePortNum ()) {
>
> + DEBUG ((DEBUG_ERROR, "GetCpuPcieRpDevFun invalid RpNumber %x",
> RpNumber));
>
> + ASSERT (FALSE);
>
> + return EFI_INVALID_PARAMETER;
>
> + }
>
> + //
>
> + // For TGL - U/Y only one CPU PCIE Root port is present
>
> + //
>
> + *RpDev = 6;
>
> + *RpFun = 0;
>
> + return EFI_SUCCESS;
>
> +}
>
> +/**
>
> +
>
> + Gets pci segment base address of PCIe root port.
>
> +
>
> + @param RpIndex Root Port Index (0 based)
>
> +
>
> + @return PCIe port base address.
>
> +**/
>
> +UINT64
>
> +CpuPcieBase (
>
> + IN UINT32 RpIndex
>
> + )
>
> +{
>
> + UINTN RpDevice;
>
> + UINTN RpFunction;
>
> + GetCpuPcieRpDevFun (RpIndex, &RpDevice, &RpFunction);
>
> + return PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, SA_MC_BUS,
> (UINT32) RpDevice, (UINT32) RpFunction, 0);
>
> +}
>
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/CpuPcieRp/Library/PeiDxeSm
> mCpuPcieInfoFruLib/PeiDxeSmmCpuPcieInfoFruLib.inf
> b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/CpuPcieRp/Library/PeiDxeSm
> mCpuPcieInfoFruLib/PeiDxeSmmCpuPcieInfoFruLib.inf
> new file mode 100644
> index 0000000000..b6a40b2f7c
> --- /dev/null
> +++
> b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/CpuPcieRp/Library/PeiDxeSm
> mCpuPcieInfoFruLib/PeiDxeSmmCpuPcieInfoFruLib.inf
> @@ -0,0 +1,36 @@
> +## @file
>
> +# CPU PCIe information library for TigerLake PCH.
>
> +#
>
> +# All function in this library is available for PEI, DXE, and SMM,
>
> +# But do not support UEFI RUNTIME environment call.
>
> +#
>
> +# Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
>
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +#
>
> +##
>
> +
>
> +
>
> +[Defines]
>
> +INF_VERSION = 0x00010017
>
> +BASE_NAME = PeiDxeSmmCpuPcieInfoFruLib
>
> +FILE_GUID = 59CA5352-ED46-4449-BF1C-0D0074C4D5B1
>
> +VERSION_STRING = 1.0
>
> +MODULE_TYPE = BASE
>
> +LIBRARY_CLASS = CpuPcieInfoFruLib
>
> +
>
> +
>
> +[LibraryClasses]
>
> +IoLib
>
> +BaseLib
>
> +DebugLib
>
> +PrintLib
>
> +PcdLib
>
> +ConfigBlockLib
>
> +CpuPcieInitCommonLib
>
> +
>
> +[Packages]
>
> +MdePkg/MdePkg.dec
>
> +TigerlakeSiliconPkg/SiPkg.dec
>
> +
>
> +[Sources]
>
> +CpuPcieInfoFruLib.c
>
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Vtd/LibraryPrivate/DxeVtdInit
> Lib/DxeVtdInitFruLib.c
> b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Vtd/LibraryPrivate/DxeVtdInit
> Lib/DxeVtdInitFruLib.c
> new file mode 100644
> index 0000000000..8a0a8b6335
> --- /dev/null
> +++
> b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Vtd/LibraryPrivate/DxeVtdInit
> Lib/DxeVtdInitFruLib.c
> @@ -0,0 +1,18 @@
> +/** @file
>
> + DXE Flu Library to initialize Vtd
DXE FRU Library to initialize Vtd
>
> +
>
> + Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +**/
>
> +#include <Base.h>
>
> +
>
> +/**
>
> + For device that specified by Device Num and Function Num,
>
> + mDevEnMap is used to check device presence.
>
> + 0x80 means use Device ID to detemine presence
>
> + 0x8F means force to update
>
> +
>
> + The structure is used to check if device scope is valid when update DMAR
> table
>
> +**/
>
> +UINT16 mDevEnMap[][2] = {{0x0200, 0x80}, {0x0500, 0x80}, {0x1400, 0x80},
> {0x1401, 0x80}, {0x0700, 0x80}, {0x0701, 0x80}, {0x0702, 0x80}, {0x0703, 0x80},
> {0x1302, 0x8F}, {0x1303, 0x8F}};
>
> +UINTN mDevEnMapSize = sizeof (mDevEnMap) / (sizeof (UINT16) * 2);
>
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Vtd/LibraryPrivate/DxeVtdInit
> Lib/DxeVtdInitFruLib.inf
> b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Vtd/LibraryPrivate/DxeVtdInit
> Lib/DxeVtdInitFruLib.inf
> new file mode 100644
> index 0000000000..e0aa88f68a
> --- /dev/null
> +++
> b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Vtd/LibraryPrivate/DxeVtdInit
> Lib/DxeVtdInitFruLib.inf
> @@ -0,0 +1,39 @@
> +## @file
>
> +# Library description file for DXE Phase Vtd Init
>
> +#
>
> +# Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
>
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +#
>
> +##
>
> +
>
> +
>
> +[Defines]
>
> +INF_VERSION = 0x00010017
>
> +BASE_NAME = DxeVtdInitFruLib
>
> +FILE_GUID = 18690D67-08A9-4DCE-B62D-CBE3AF7CFEE7
>
> +VERSION_STRING = 1.0
>
> +MODULE_TYPE = DXE_DRIVER
>
> +LIBRARY_CLASS = DxeVtdFruLib
>
> +
>
> +
>
> +[LibraryClasses]
>
> +UefiLib
>
> +UefiRuntimeServicesTableLib
>
> +UefiBootServicesTableLib
>
> +DebugLib
>
> +DxeSaPolicyLib
>
> +
>
> +[Packages]
>
> +MdePkg/MdePkg.dec
>
> +TigerlakeSiliconPkg/SiPkg.dec
>
> +
>
> +[Protocols]
>
> +gSaNvsAreaProtocolGuid ## CONSUMES
>
> +
>
> +[Sources]
>
> +DxeVtdInitFruLib.c
>
> +
>
> +[FixedPcd]
>
> +
>
> +[Guids]
>
> +gTcssHobGuid ## CONSUMES
>
> --
> 2.24.0.windows.2
next prev parent reply other threads:[~2021-02-04 3:56 UTC|newest]
Thread overview: 81+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-01 1:36 [PATCH 01/40] TigerlakeSiliconPkg: Add package and Include/ConfigBlock headers Heng Luo
2021-02-01 1:36 ` [PATCH 02/40] TigerlakeSiliconPkg/Include: Add Library, PPI and Protocol include headers Heng Luo
2021-02-04 3:51 ` Nate DeSimone
2021-02-01 1:36 ` [PATCH 03/40] TigerlakeSiliconPkg/Include: Add Pins, Register and other " Heng Luo
2021-02-04 3:52 ` Nate DeSimone
2021-02-01 1:36 ` [PATCH 04/40] TigerlakeSiliconPkg/Cpu: Add Include headers Heng Luo
2021-02-04 3:53 ` Nate DeSimone
2021-02-01 1:36 ` [PATCH 05/40] TigerlakeSiliconPkg/Pch: Add include headers Heng Luo
2021-02-04 3:53 ` Nate DeSimone
2021-02-01 1:36 ` [PATCH 06/40] TigerlakeSiliconPkg/Pch: Add IncludePrivate headers Heng Luo
2021-02-04 3:53 ` Nate DeSimone
2021-02-01 1:36 ` [PATCH 07/40] TigerlakeSiliconPkg/SystemAgent: Add include headers Heng Luo
2021-02-04 3:53 ` Nate DeSimone
2021-02-01 1:36 ` [PATCH 08/40] TigerlakeSiliconPkg/SystemAgent: Add IncludePrivate headers Heng Luo
2021-02-04 3:53 ` Nate DeSimone
2021-02-01 1:36 ` [PATCH 09/40] TigerlakeSiliconPkg/Fru: Add TglCpu/Include headers Heng Luo
2021-02-04 3:53 ` Nate DeSimone
2021-02-01 1:36 ` [PATCH 10/40] TigerlakeSiliconPkg/Fru: Add TglCpu/IncludePrivate headers Heng Luo
2021-02-04 3:53 ` Nate DeSimone
2021-02-01 1:36 ` [PATCH 11/40] TigerlakeSiliconPkg/Fru: Add TglPch/Include headers Heng Luo
2021-02-04 3:53 ` Nate DeSimone
2021-02-01 1:36 ` [PATCH 12/40] TigerlakeSiliconPkg/Fru: Add TglPch/IncludePrivate headers Heng Luo
2021-02-04 3:53 ` Nate DeSimone
2021-02-01 1:36 ` [PATCH 13/40] TigerlakeSiliconPkg/IpBlock: Add Cnvi component Heng Luo
2021-02-04 3:53 ` Nate DeSimone
2021-02-01 1:36 ` [PATCH 14/40] TigerlakeSiliconPkg/IpBlock: Add CpuPcieRp component Heng Luo
2021-02-04 3:53 ` Nate DeSimone
2021-02-01 1:36 ` [PATCH 15/40] TigerlakeSiliconPkg/IpBlock: Add Espi component Heng Luo
2021-02-04 3:54 ` Nate DeSimone
2021-02-01 1:36 ` [PATCH 16/40] TigerlakeSiliconPkg/IpBlock: Add Gbe component Heng Luo
2021-02-04 3:54 ` Nate DeSimone
2021-02-01 1:36 ` [PATCH 17/40] TigerlakeSiliconPkg/IpBlock: Add Gpio component Heng Luo
2021-02-04 3:54 ` Nate DeSimone
2021-02-01 1:36 ` [PATCH 18/40] TigerlakeSiliconPkg/IpBlock: Add Graphics component Heng Luo
2021-02-04 3:54 ` Nate DeSimone
2021-02-01 1:36 ` [PATCH 19/40] TigerlakeSiliconPkg/IpBlock: Add Hda component Heng Luo
2021-02-04 3:54 ` Nate DeSimone
2021-02-01 1:36 ` [PATCH 20/40] TigerlakeSiliconPkg/IpBlock: Add HostBridge component Heng Luo
2021-02-04 3:54 ` Nate DeSimone
2021-02-01 1:36 ` [PATCH 21/40] TigerlakeSiliconPkg/IpBlock: Add P2sb component Heng Luo
2021-02-04 3:54 ` Nate DeSimone
2021-02-01 1:36 ` [PATCH 22/40] TigerlakeSiliconPkg/IpBlock: Add PchDmi component Heng Luo
2021-02-04 3:54 ` Nate DeSimone
2021-02-01 1:36 ` [PATCH 23/40] TigerlakeSiliconPkg/IpBlock: Add PcieRp component Heng Luo
2021-02-04 3:55 ` Nate DeSimone
2021-02-01 1:36 ` [PATCH 24/40] TigerlakeSiliconPkg/IpBlock: Add Pmc component Heng Luo
2021-02-04 3:56 ` Nate DeSimone
2021-02-01 1:36 ` [PATCH 25/40] TigerlakeSiliconPkg/IpBlock: Add Psf component Heng Luo
2021-02-04 3:56 ` Nate DeSimone
2021-02-01 1:36 ` [PATCH 26/40] TigerlakeSiliconPkg/IpBlock: Add Sata component Heng Luo
2021-02-04 3:56 ` Nate DeSimone
2021-02-01 1:36 ` [PATCH 27/40] TigerlakeSiliconPkg/IpBlock: Add SerialIo component Heng Luo
2021-02-04 3:56 ` Nate DeSimone
2021-02-01 1:36 ` [PATCH 28/40] TigerlakeSiliconPkg/IpBlock: Add Smbus component Heng Luo
2021-02-04 3:56 ` Nate DeSimone
2021-02-01 1:36 ` [PATCH 29/40] TigerlakeSiliconPkg/IpBlock: Add Spi component Heng Luo
2021-02-04 3:56 ` Nate DeSimone
2021-02-01 1:36 ` [PATCH 30/40] TigerlakeSiliconPkg/IpBlock: Add Vtd component Heng Luo
2021-02-04 3:56 ` Nate DeSimone
2021-02-01 1:36 ` [PATCH 31/40] TigerlakeSiliconPkg/Library: Add package common library instances Heng Luo
2021-02-04 3:56 ` Nate DeSimone
2021-02-01 1:36 ` [PATCH 32/40] TigerlakeSiliconPkg/Pch: Add Pch " Heng Luo
2021-02-04 3:56 ` Nate DeSimone
2021-02-01 1:36 ` [PATCH 33/40] TigerlakeSiliconPkg/Pch: Add Pch private " Heng Luo
2021-02-04 3:56 ` Nate DeSimone
2021-02-01 1:36 ` [PATCH 34/40] TigerlakeSiliconPkg/SystemAgent: Add Acpi Tables and " Heng Luo
2021-02-04 3:56 ` Nate DeSimone
2021-02-01 1:36 ` [PATCH 35/40] TigerlakeSiliconPkg/Fru/TglCpu: Add CpuPcieRp and Vtd " Heng Luo
2021-02-04 3:56 ` Nate DeSimone [this message]
2021-02-01 1:36 ` [PATCH 36/40] TigerlakeSiliconPkg/Pch: Add Pch modules Heng Luo
2021-02-04 3:56 ` Nate DeSimone
2021-02-01 1:36 ` [PATCH 37/40] TigerlakeSiliconPkg/SystemAgent: Add SystemAgent modules Heng Luo
2021-02-04 3:56 ` Nate DeSimone
2021-02-01 1:36 ` [PATCH 38/40] TigerlakeSiliconPkg/Fru: Add Fru DSC files Heng Luo
2021-02-04 3:56 ` Nate DeSimone
2021-02-01 1:36 ` [PATCH 39/40] TigerlakeSiliconPkg: Add package " Heng Luo
2021-02-04 3:56 ` Nate DeSimone
2021-02-01 1:36 ` [PATCH 40/40] Maintainers.txt: Add TigerlakeSiliconPkg maintainers Heng Luo
2021-02-04 3:51 ` Nate DeSimone
2021-02-04 8:24 ` Heng Luo
2021-02-04 3:51 ` [PATCH 01/40] TigerlakeSiliconPkg: Add package and Include/ConfigBlock headers Nate DeSimone
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