Re: [PATCH 04/40] TigerlakeSiliconPkg/Cpu: Add Include headers

["Nate DeSimone" <nathaniel.l.desimone@intel.com>]

Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>

> -----Original Message-----
> From: Luo, Heng <heng.luo@intel.com>
> Sent: Sunday, January 31, 2021 5:36 PM
> To: devel@edk2.groups.io
> Cc: Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Desimone,
> Nathaniel L <nathaniel.l.desimone@intel.com>
> Subject: [PATCH 04/40] TigerlakeSiliconPkg/Cpu: Add Include headers
> 
> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171
> 
> Adds header files common to CPU modules.
> 
> Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
> Signed-off-by: Heng Luo <heng.luo@intel.com>
> ---
>  Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfig.h
> |  83
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> +++++++++++++++++++++++++
> 
> Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfigLibPre
> MemConfig.h | 148
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++
> 
> Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPidTestConfig.
> h         |  52
> ++++++++++++++++++++++++++++++++++++++++++++++++++++
> 
> Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPowerMgmtB
> asicConfig.h  | 226
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++
> 
> Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPowerMgmtC
> ustomConfig.h |  76
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++
> 
> Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPowerMgmtP
> sysConfig.h   |  36 ++++++++++++++++++++++++++++++++++++
> 
> Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPowerMgmtT
> estConfig.h   | 150
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++
> 
> Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuSecurityPreM
> emConfig.h  |  63
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> +++++
>  Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuTestConfig.h
> |  51 +++++++++++++++++++++++++++++++++++++++++++++++++++
>  Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/CpuAccess.h                            |
> 12 ++++++++++++
>  Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/CpuDataStruct.h                        |
> 21 +++++++++++++++++++++
>  Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/CpuPolicyCommon.h
> |  23 +++++++++++++++++++++++
>  Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/Register/CommonMsr.h
> |  18 ++++++++++++++++++
>  13 files changed, 959 insertions(+)
> 
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfig.h
> b/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfig.h
> new file mode 100644
> index 0000000000..d837500a38
> --- /dev/null
> +++
> b/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfig.h
> @@ -0,0 +1,83 @@
> +/** @file
> 
> +  CPU Config Block.
> 
> +
> 
> +  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
> 
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> 
> +**/
> 
> +#ifndef _CPU_CONFIG_H_
> 
> +#define _CPU_CONFIG_H_
> 
> +
> 
> +#define CPU_CONFIG_REVISION 3
> 
> +
> 
> +extern EFI_GUID gCpuConfigGuid;
> 
> +
> 
> +#pragma pack (push,1)
> 
> +
> 
> +/**
> 
> +  CPU Configuration Structure.
> 
> +
> 
> +  <b>Revision 1</b>:
> 
> +  - Initial version.
> 
> +  <b>Revision 2</b>:
> 
> +  - Add SmbiosType4MaxSpeedOverride.
> 
> +  <b>Revision 3</b>:
> 
> +  - Add AvxDisable & Avx3Disable.
> 
> +**/
> 
> +typedef struct {
> 
> +  CONFIG_BLOCK_HEADER   Header;                   ///< Config Block Header
> 
> +  UINT32                MicrocodePatchRegionSize;
> 
> +  EFI_PHYSICAL_ADDRESS  MicrocodePatchAddress;    ///< Pointer to
> microcode patch that is suitable for this processor.
> 
> +  /**
> 
> +    Enable or Disable Advanced Encryption Standard (AES) feature.
> 
> +    For some countries, this should be disabled for legal reasons.
> 
> +    -    0: Disable
> 
> +    - <b>1: Enable</b>
> 
> +  **/
> 
> +  UINT32 AesEnable           : 1;
> 
> +  /**
> 
> +    Enable or Disable Trusted Execution Technology (TXT) feature.
> 
> +    -    0: Disable
> 
> +    - <b>1: Enable</b>
> 
> +  **/
> 
> +  UINT32 TxtEnable           : 1;
> 
> +  UINT32 SkipMpInit          : 1;                 ///< For Fsp only, Silicon Initialization
> will skip MP Initialization (including BSP) if enabled. For non-FSP, this should
> always be 0.
> 
> +  /**
> 
> +    Enable or Disable or Auto for PPIN Support to view Protected Processor
> Inventory Number.
> 
> +    - <b>0: Disable</b>
> 
> +    -    1: Enable
> 
> +    -    2: Auto : Feature is based on End Of Manufacturing (EOM) flag. If EOM
> is set, it is disabled.
> 
> +  **/
> 
> +  UINT32 PpinSupport         : 2;
> 
> +  /**
> 
> +    Enable or Disable #AC machine check on split lock.
> 
> +    - <b>0: Disable</b>
> 
> +    -    1: Enable
> 
> +  **/
> 
> +  UINT32 AcSplitLock         : 1;
> 
> +  /**
> 
> +  Enable or Disable Avx.
> 
> +  -      1: Disable
> 
> +  -  <b> 0: Enable</b>
> 
> +  **/
> 
> +  UINT32 AvxDisable          : 1;
> 
> +  /**
> 
> +  Enable or Disable Avx3.
> 
> +  -      1: Disable
> 
> +  -  <b> 0: Enable</b>
> 
> +  **/
> 
> +  UINT32 Avx3Disable         : 1;
> 
> +  UINT32 RsvdBits            : 24;                ///< Reserved for future use
> 
> +  /**
> 
> +    Provide the option for platform to override the MaxSpeed field of Smbios
> Type 4.
> 
> +    Value 4000 means 4000MHz.
> 
> +    If this value is not zero, it dominates the field.
> 
> +    If this value is zero, CPU RC will update the field according to the max
> radio.
> 
> +    <b>default is 0.</b>
> 
> +  **/
> 
> +  UINT16 SmbiosType4MaxSpeedOverride;
> 
> +  UINT8  Reserved0[2];                            ///< Reserved for future use
> 
> +} CPU_CONFIG;
> 
> +
> 
> +#pragma pack (pop)
> 
> +
> 
> +#endif // _CPU_CONFIG_H_
> 
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfigLibPr
> eMemConfig.h
> b/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfigLibPr
> eMemConfig.h
> new file mode 100644
> index 0000000000..bf3f436ddd
> --- /dev/null
> +++
> b/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfigLibPr
> eMemConfig.h
> @@ -0,0 +1,148 @@
> +/** @file
> 
> +  CPU Security PreMemory Config Block.
> 
> +
> 
> +  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
> 
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> 
> +**/
> 
> +#ifndef _CPU_CONFIG_LIB_PREMEM_CONFIG_H_
> 
> +#define _CPU_CONFIG_LIB_PREMEM_CONFIG_H_
> 
> +
> 
> +#define CPU_CONFIG_LIB_PREMEM_CONFIG_REVISION 6
> 
> +
> 
> +extern EFI_GUID gCpuConfigLibPreMemConfigGuid;
> 
> +
> 
> +#define BOOT_FREQUENCY_MAX_BATTERY_PERF   0
> 
> +#define BOOT_FREQUENCY_MAX_NON_TURBO_PERF 1
> 
> +#define BOOT_FREQUENCY_TURBO_PERF         2
> 
> +
> 
> +#pragma pack (push,1)
> 
> +
> 
> +/**
> 
> +  CPU Config Library PreMemory Configuration Structure.
> 
> +
> 
> +  <b>Revision 1</b>:
> 
> +  - Initial version.
> 
> +  <b>Revision 2</b>:
> 
> +  - Expand the supported number of processor cores (ActiveCoreCount1).
> 
> +  <b>Revision  3</b>:
> 
> +  - Added PECI Sx and C10 Reset.
> 
> +  <b>Revision  4</b>:
> 
> +  - Added ActiveSmallCoreCount.
> 
> +  <b>Revision  5</b>:
> 
> +  - Added CrashLogGprs
> 
> +  <b>Revision  6</b>:
> 
> +  - Added ConfigTdpLevel
> 
> +**/
> 
> +typedef struct {
> 
> +  CONFIG_BLOCK_HEADER Header;            ///< Config Block Header
> 
> +  UINT32 HyperThreading             : 1; ///< Enable or Disable Hyper Threading;
> 0: Disable; <b>1: Enable</b>.
> 
> +  /**
> 
> +  Sets the boot frequency starting from reset vector.
> 
> +   - 0: Maximum battery performance.
> 
> +   - 1: Maximum non-turbo performance
> 
> +   -<b>2: Turbo performance</b>.
> 
> +  @note If Turbo is selected BIOS will start in max non-turbo mode and
> switch to Turbo mode.
> 
> +  **/
> 
> +  UINT32 BootFrequency              : 2;
> 
> +  /**
> 
> +    Number of processor cores to enable.
> 
> +    - <b> 0: All cores</b>
> 
> +    -     1: 1 core
> 
> +    -     2: 2 cores
> 
> +    -     3: 3 cores
> 
> +  **/
> 
> +  UINT32 ActiveCoreCount            : 3; ///< @deprecated due to core active
> number limitaion.
> 
> +  UINT32 JtagC10PowerGateDisable    : 1; ///< False: JTAG is power gated in
> C10 state. True: keeps the JTAG power up during C10 and deeper power
> states for debug purpose. <b>0: False<\b>; 1: True.
> 
> +  UINT32 BistOnReset                : 1; ///< <b>(Test)</b> Enable or Disable BIST
> on Reset; <b>0: Disable</b>; 1: Enable.
> 
> +  /**
> 
> +    Enable or Disable Virtual Machine Extensions (VMX) feature.
> 
> +    -    0: Disable
> 
> +    - <b>1: Enable</b>
> 
> +  **/
> 
> +  UINT32 VmxEnable                  : 1;
> 
> +  /**
> 
> +  Processor Early Power On Configuration FCLK setting.
> 
> +   - <b>0: 800 MHz (ULT/ULX)</b>.
> 
> +   - <b>1: 1 GHz (DT/Halo)</b>. Not supported on ULT/ULX.
> 
> +   - 2: 400 MHz.
> 
> +   - 3: Reserved.
> 
> +  **/
> 
> +  UINT32 FClkFrequency              : 2;
> 
> +  /**
> 
> +  Enable or Disable CrashLog feature
> 
> +    -    0: Disable
> 
> +    - <b>1: Enable</b>
> 
> +  **/
> 
> +  UINT32 CrashLogEnable              : 1;
> 
> +
> 
> +  /**
> 
> +  Enable or Disable Total Memory Encryption (TME) feature.
> 
> +    - <b>0: Disable</b>
> 
> +    -    1: Enable
> 
> +  **/
> 
> +  UINT32 TmeEnable                  : 1;
> 
> +
> 
> +  UINT32 DebugInterfaceEnable       : 2; ///< Enable or Disable processor
> debug features; 0: Disable; 1: Enable; <b>2: No Change</b>.
> 
> +  UINT32 DebugInterfaceLockEnable   : 1; ///< Lock or Unlock debug
> interface features; 0: Disable; <b>1: Enable</b>.
> 
> +
> 
> +  /**
> 
> +    Number of big cores in processor to enable. And support up to 16 cores.
> 
> +    - <b> 0: All cores</b>
> 
> +    -     1: 1 core
> 
> +    -     2: 2 cores
> 
> +    -     3: 3 cores
> 
> +  **/
> 
> +  UINT32 ActiveCoreCount1           : 4;
> 
> +
> 
> +  /**
> 
> +  Enables a mailbox command to resolve rare PECI related Sx issues.
> 
> +  @note This should only be used on systems that observe PECI Sx issues.
> 
> +  - <b>0: Disable</b>
> 
> +  -    1: Enable
> 
> +  **/
> 
> +  UINT32 PeciSxReset                : 1;
> 
> +
> 
> +  /**
> 
> +  Enables the mailbox command to resolve PECI reset issues during Pkg-C10
> exit.
> 
> +  If Enabled, BIOS will send the CPU message to disable peci reset on C10
> exit.
> 
> +  The default value is <b>1: Enable</b> for CML, and <b>0: Disable</b> for
> all other CPU's
> 
> +  - 0: Disable
> 
> +  - 1: Enable
> 
> +  **/
> 
> +  UINT32 PeciC10Reset               : 1;
> 
> +
> 
> +  /**
> 
> +    Number of small cores in processor to enable. And support the enabling
> of up to 63 cores.
> 
> +    - <b> 0: All cores</b>
> 
> +    -     1: 1 core
> 
> +    -     2: 2 cores
> 
> +    -     3: 3 cores
> 
> +  **/
> 
> +  UINT32 ActiveSmallCoreCount       : 6;
> 
> +
> 
> +  /**
> 
> +  Enable or Disable CrashLog GPRs dump
> 
> +    - <b>0: Disable</b>
> 
> +    -    1: Gprs Enabled, Smm Gprs Enabled
> 
> +         2: Gprs Enabled, Smm Gprs Disabled
> 
> +  **/
> 
> +  UINT32 CrashLogGprs               : 2;
> 
> +
> 
> +  UINT32 RsvdBits                   : 2;
> 
> +
> 
> +  /**
> 
> +    CpuRatio - Max non-turbo ratio (Flexible Ratio Boot) is set to CpuRatio.
> <b>0: Disabled</b> If disabled, doesn't override max-non turbo ratio.
> 
> +  **/
> 
> +  UINT8  CpuRatio;
> 
> +  /**
> 
> +    Configuration for boot TDP selection; <b>0: TDP Nominal</b>; 1: TDP
> Down; 2: TDP Up.
> 
> +  **/
> 
> +  UINT8  ConfigTdpLevel;
> 
> +  UINT8  Reserved[2];                    ///< Reserved for alignment
> 
> +  UINT32 ElixirSpringsPatchAddr;         ///< Address of Elixir Springs Patch(es)
> 
> +  UINT32 ElixirSpringsPatchSize;         ///< Elixir Springs Patch(es) Size.
> 
> +} CPU_CONFIG_LIB_PREMEM_CONFIG;
> 
> +
> 
> +#pragma pack (pop)
> 
> +
> 
> +#endif // _CPU_CONFIG_LIB_PREMEM_CONFIG_H_
> 
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPidTestConf
> ig.h
> b/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPidTestConf
> ig.h
> new file mode 100644
> index 0000000000..4fcb92cb27
> --- /dev/null
> +++
> b/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPidTestConf
> ig.h
> @@ -0,0 +1,52 @@
> +/** @file
> 
> +  CPU PID Config Block.
> 
> +
> 
> +  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
> 
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> 
> +**/
> 
> +#ifndef _CPU_PID_TEST_CONFIG_H_
> 
> +#define _CPU_PID_TEST_CONFIG_H_
> 
> +
> 
> +#define CPU_PID_TEST_CONFIG_REVISION 1
> 
> +
> 
> +extern EFI_GUID gCpuPidTestConfigGuid;
> 
> +
> 
> +#pragma pack (push,1)
> 
> +
> 
> +/**
> 
> +  PID Tuning Configuration Structure.
> 
> +  Domain is mapped to Kp = 0, Ki = 1, Kd = 2.
> 
> +
> 
> +  <b>Revision 1</b>:
> 
> +  - Initial version.
> 
> +**/
> 
> +typedef struct {
> 
> +  CONFIG_BLOCK_HEADER   Header;                   ///< Config Block Header
> 
> +  UINT16  Ratl[3];                                ///< RATL setting, in 1/256 units. Range is 0
> - 65280
> 
> +  UINT16  VrTdcVr0[3];                            ///< VR Thermal Design Current for
> VR0. In 1/256 units. Range is 0 - 65280
> 
> +  UINT16  VrTdcVr1[3];                            ///< VR Thermal Design Current for
> VR1. In 1/256 units. Range is 0 - 65280
> 
> +  UINT16  VrTdcVr2[3];                            ///< VR Thermal Design Current for
> VR2. In 1/256 units. Range is 0 - 65280
> 
> +  UINT16  VrTdcVr3[3];                            ///< VR Thermal Design Current for
> VR3. In 1/256 units. Range is 0 - 65280
> 
> +  UINT16  PbmPsysPl1Msr[3];                       ///< Power Budget Management
> Psys PL1 MSR. In 1/256 units. Range is 0 - 65280
> 
> +  UINT16  PbmPsysPl1MmioPcs[3];                   ///< Power Budget
> Management Psys PL1 MMIO/PCS. In 1/256 units. Range is 0 - 65280
> 
> +  UINT16  PbmPsysPl2Msr[3];                       ///< Power Budget Management
> Psys PL2 MSR. In 1/256 units. Range is 0 - 65280
> 
> +  UINT16  PbmPsysPl2MmioPcs[3];                   ///< Power Budget
> Management Psys PL2 MMIO/PCS. In 1/256 units. Range is 0 - 65280
> 
> +  UINT16  PbmPkgPl1Msr[3];                        ///< Power Budget Management
> Package PL1 MSR. In 1/256 units. Range is 0 - 65280
> 
> +  UINT16  PbmPkgPl1MmioPcs[3];                    ///< Power Budget
> Management Package PL1 MMIO/PCS. In 1/256 units. Range is 0 - 65280
> 
> +  UINT16  PbmPkgPl2Msr[3];                        ///< Power Budget Management
> Package PL2 MSR. In 1/256 units. Range is 0 - 65280
> 
> +  UINT16  PbmPkgPl2MmioPcs[3];                    ///< Power Budget
> Management Package PL2 MMIO/PCS. In 1/256 units. Range is 0 - 65280
> 
> +  UINT16  DdrPl1Msr[3];                           ///< DDR PL1 MSR. In 1/256 units.
> Range is 0 - 65280
> 
> +  UINT16  DdrPl1MmioPcs[3];                       ///< DDR PL1 MMIO/PCS. In 1/256
> units. Range is 0 - 65280
> 
> +  UINT16  DdrPl2Msr[3];                           ///< DDR PL2 MSR. In 1/256 units.
> Range is 0 - 65280
> 
> +  UINT16  DdrPl2MmioPcs[3];                       ///< DDR PL2 MMIO/PCS. In 1/256
> units. Range is 0 - 65280
> 
> +  /**
> 
> +  Enable or Disable PID Tuning programming flow.
> 
> +  If disabled, all other policies in this config block are ignored.
> 
> +  **/
> 
> +  UINT8   PidTuning;
> 
> +  UINT8   Rsvd;                                   ///< Reserved for DWORD alignment.
> 
> +} CPU_PID_TEST_CONFIG;
> 
> +
> 
> +#pragma pack (pop)
> 
> +
> 
> +#endif // _CPU_PID_TEST_CONFIG_H_
> 
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPowerMgm
> tBasicConfig.h
> b/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPowerMgm
> tBasicConfig.h
> new file mode 100644
> index 0000000000..0255d49bdf
> --- /dev/null
> +++
> b/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPowerMgm
> tBasicConfig.h
> @@ -0,0 +1,226 @@
> +/** @file
> 
> +  CPU Power Management Basic Config Block.
> 
> +
> 
> +  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
> 
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> 
> +**/
> 
> +#ifndef _CPU_POWER_MGMT_BASIC_CONFIG_H_
> 
> +#define _CPU_POWER_MGMT_BASIC_CONFIG_H_
> 
> +
> 
> +#define CPU_POWER_MGMT_BASIC_CONFIG_REVISION 5
> 
> +
> 
> +extern EFI_GUID gCpuPowerMgmtBasicConfigGuid;
> 
> +
> 
> +#pragma pack (push,1)
> 
> +
> 
> +/**
> 
> +  CPU Power Management Basic Configuration Structure.
> 
> +
> 
> +  <b>Revision 1</b>:
> 
> +  - Initial version.
> 
> +  <b>Revision 2</b>:
> 
> +  - Changed EnableItbm default to be disable
> 
> +  - Deprecated EnableItbmDriver due to Platform doesn't have ITBMT OS
> driver
> 
> +  <b>Revision 3</b>:
> 
> +  - Add ApplyConfigTdp for TDP initialization settings based on non-cTDP or
> cTDP
> 
> +  <b>Revision 4</b>:
> 
> +  - Add Hwp Lock support
> 
> +  <b>Revision 5</b>:
> 
> +  - Add VccInDemotionOverride and VccInDemotionMs
> 
> +**/
> 
> +typedef struct {
> 
> +  CONFIG_BLOCK_HEADER   Header;                   ///< Config Block Header
> 
> +  /**
> 
> +  Sets the boot frequency starting from reset vector.
> 
> +   - 0: Maximum battery performance.
> 
> +   - 1: Maximum non-turbo performance.
> 
> +   - <b>2: Turbo performance.</b>
> 
> +  @note If Turbo is selected BIOS will start in max non-turbo mode and
> switch to Turbo mode.
> 
> +  **/
> 
> +  UINT32 BootFrequency                  : 2;       //@deprecated
> 
> +  UINT32 SkipSetBootPState              : 1;      ///< Choose whether to skip
> SetBootPState function for all APs; <b>0: Do not skip</b>; 1: Skip.
> 
> +  /**
> 
> +  Enable or Disable Intel Speed Shift Technology.
> 
> +  Enabling allows for processor control of P-state transitions.
> 
> +  0: Disable; <b>1: Enable;</b> Bit 1 is ignored.
> 
> +  @note Currently this feature is recommended to be enabled only on
> win10
> 
> +  **/
> 
> +  UINT32 Hwp                            : 2;
> 
> +  /**
> 
> +  Hardware Duty Cycle Control configuration. 0: Disabled; <b>1: Enabled</b>
> 2-3:Reserved
> 
> +  HDC enables the processor to autonomously force components to enter
> into an idle state to lower effective frequency.
> 
> +  This allows for increased package level C6 residency.
> 
> +  @note Currently this feature is recommended to be enabled only on
> win10
> 
> +  **/
> 
> +  UINT32 HdcControl                     : 2;
> 
> +  UINT32 PowerLimit2                    : 1;      ///< Enable or Disable short duration
> Power Limit (PL2). 0: Disable; <b>1: Enable</b>
> 
> +  UINT32 TurboPowerLimitLock            : 1;      ///< MSR 0x610[63] and
> 0x618[63]: Locks all Turbo power limit settings to read-only; <b>0:
> Disable</b>; 1: Enable (Lock).
> 
> +  UINT32 PowerLimit3DutyCycle           : 8;      ///< Package PL3 Duty Cycle.
> Specifies the PL3 duty cycle percentage, Range 0-100. <b>Default: 0</b>.
> 
> +  UINT32 PowerLimit3Lock                : 1;      ///< Package PL3 MSR 615h lock;
> <b>0: Disable</b>; 1: Enable (Lock).
> 
> +  UINT32 PowerLimit4Lock                : 1;      ///< Package PL4 MSR 601h lock;
> <b>0: Disable</b>; 1: Enable (Lock).
> 
> +  /**
> 
> +  Tcc Offset Clamp for Runtime Average Temperature Limit (RATL) allows
> CPU to throttle below P1.
> 
> +  For Y SKU, the recommended default for this policy is <b>1: Enabled</b>,
> which indicates throttling below P1 is allowed.
> 
> +  For all other SKUs the recommended default are  <b>0: Disabled</b>.
> 
> +  **/
> 
> +  UINT32 TccOffsetClamp                 : 1;
> 
> +  UINT32 TccOffsetLock                  : 1;      ///< Tcc Offset Lock for Runtime
> Average Temperature Limit (RATL) to lock temperature target MSR 1A2h; 0:
> Disabled; <b>1: Enabled (Lock)</b>.
> 
> +  UINT32 TurboMode                      : 1;      ///< Enable or Disable Turbo Mode.
> Disable; <b>1: Enable</b>
> 
> +  UINT32 HwpInterruptControl            : 1;      ///< Set HW P-State Interrupts
> Enabled  for MISC_PWR_MGMT MSR 0x1AA[7]; <b>0: Disable</b>; 1:
> Enable.
> 
> +  UINT32 ApplyConfigTdp                 : 1;      ///< Switch TDP applied setting
> based on non-cTDP or TDP; 0: non-cTDP; <b>1: cTDP</b>.
> 
> +  UINT32 HwpLock                        : 1;      ///< HWP Lock in MISC PWR MGMT
> MSR 1AAh; <b>0: Disable</b>; 1: Enable (Lock).
> 
> +  UINT32 VccInDemotionOverride          : 1;      ///< Enable VccIn Demotion
> Override configuration. <b>0: Disable</b>; 1: Enable.
> 
> +  UINT32 RsvdBits                       : 6;      ///< Reserved for future use.
> 
> +
> 
> +  /**
> 
> +   1-Core Ratio Limit: LFM to Fused 1-Core Ratio Limit. For overclocking parts:
> LFM to Fused 1-Core Ratio Limit + OC Bins.
> 
> +   Note: OC Bins = 7 means fully unlocked, so range is LFM to 83.
> 
> +     - This 1-Core Ratio Limit Must be greater than or equal to 2-Core Ratio
> Limit, 3-Core Ratio Limit, 4-Core Ratio Limit.
> 
> +  **/
> 
> +  UINT8  OneCoreRatioLimit;
> 
> +  /**
> 
> +   2-Core Ratio Limit: LFM to Fused 2-Core Ratio Limit, For overclocking part:
> LFM to Fused 2-Core Ratio Limit + OC Bins.
> 
> +   Note: OC Bins = 7 means fully unlocked, so range is LFM to 83.
> 
> +     - This 2-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.
> 
> +  **/
> 
> +  UINT8  TwoCoreRatioLimit;
> 
> +  /**
> 
> +   3-Core Ratio Limit: LFM to Fused 3-Core Ratio Limit, For overclocking part:
> LFM to Fused 3-Core Ratio Limit + OC Bins.
> 
> +   Note: OC Bins = 7 means fully unlocked, so range is LFM to 83.
> 
> +     - This 3-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.
> 
> +  **/
> 
> +  UINT8  ThreeCoreRatioLimit;
> 
> +  /**
> 
> +   4-Core Ratio Limit: LFM to Fused 4-Core Ratio Limit, For overclocking part:
> LFM to Fused 4-Core Ratio Limit + OC Bins.
> 
> +   Note: OC Bins = 7 means fully unlocked, so range is LFM to 83.
> 
> +     - This 4-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.
> 
> +  **/
> 
> +  UINT8  FourCoreRatioLimit;
> 
> +  /**
> 
> +   5-Core Ratio Limit: LFM to Fused 5-Core Ratio Limit, For overclocking part:
> LFM to Fused 5-Core Ratio Limit + OC Bins.
> 
> +   Note: OC Bins = 7 means fully unlocked, so range is LFM to 83.
> 
> +     - This 5-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.
> 
> +  **/
> 
> +  UINT8  FiveCoreRatioLimit;
> 
> +  /**
> 
> +   6-Core Ratio Limit: LFM to Fused 6-Core Ratio Limit, For overclocking part:
> LFM to Fused 6-Core Ratio Limit + OC Bins.
> 
> +   Note: OC Bins = 7 means fully unlocked, so range is LFM to 83.
> 
> +     - This 6-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.
> 
> +  **/
> 
> +  UINT8  SixCoreRatioLimit;
> 
> +  /**
> 
> +   7-Core Ratio Limit: LFM to Fused 7-Core Ratio Limit, For overclocking part:
> LFM to Fused 7-Core Ratio Limit + OC Bins.
> 
> +   Note: OC Bins = 7 means fully unlocked, so range is LFM to 83.
> 
> +     - This 7-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.
> 
> +  **/
> 
> +  UINT8  SevenCoreRatioLimit;
> 
> +  /**
> 
> +   8-Core Ratio Limit: LFM to Fused 8-Core Ratio Limit, For overclocking part:
> LFM to Fused 8-Core Ratio Limit + OC Bins.
> 
> +   Note: OC Bins = 7 means fully unlocked, so range is LFM to 83.
> 
> +     - This 8-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.
> 
> +  **/
> 
> +  UINT8  EightCoreRatioLimit;
> 
> +  /**
> 
> +  TCC Activation Offset. Offset from factory set TCC activation temperature
> at which the Thermal Control Circuit must be activated.
> 
> +  TCC will be activated at (TCC Activation Temperature - TCC Activation
> Offset), in degrees Celcius.
> 
> +  For Y SKU, the recommended default for this policy is  <b>10</b>
> 
> +  For all other SKUs the recommended default are <b>0</b>, causing TCC to
> activate at TCC Activation temperature.
> 
> +  @note The policy is recommended for validation purpose only.
> 
> +  **/
> 
> +  UINT8  TccActivationOffset;
> 
> +  /**
> 
> +  Intel Turbo Boost Max Technology 3.0
> 
> +  Enabling it on processors with OS support will allow OS to exploit the
> diversity in max turbo frequency of the cores.
> 
> +  <b>0: Disable</b>; 1: Enable;
> 
> +  **/
> 
> +  UINT8  EnableItbm                     : 1;
> 
> +  /**
> 
> +  @deprecated: Platform doesn't have Intel Turbo Boost Max Technology
> 3.0 Driver
> 
> +  Enabling it will load the driver upon ACPI device with HID = INT3510.
> 
> +  <b> 0: Disable;</b> 1: Enable;
> 
> +  **/
> 
> +  UINT8  EnableItbmDriver               : 1;
> 
> +  /**
> 
> +  Per Core P State OS control mode
> 
> +  Disabling will set PCU_MISC_CONFIG (Command 0x06) Bit 31 = 1. When
> set, the highest core request is used for all other core requests.
> 
> +  0: Disable;<b> 1: Enable;</b>
> 
> +  **/
> 
> +  UINT8  EnablePerCorePState            : 1;
> 
> +  /**
> 
> +  HwP Autonomous Per Core P State
> 
> +  Disabling will set Bit 30 = 1, command 0x11. When set, autonomous will
> request the same value
> 
> +  for all cores all the time.
> 
> +  0: Disable;<b> 1: Enable;</b>
> 
> +  **/
> 
> +  UINT8  EnableHwpAutoPerCorePstate     : 1;
> 
> +  /**
> 
> +  HwP Autonomous EPP grouping.
> 
> +  Disabling will set Bit 29 = 1, command 0x11. When set, autonomous will not
> necesarrily request the same value
> 
> +  for all cores with same EPP.
> 
> +  Enabling will clean Bit 29 = 0, command 0x11. Autonomous will request
> same values for all cores with same EPP.
> 
> +  0: Disable;<b> 1: Enable;</b>
> 
> +  **/
> 
> +  UINT8  EnableHwpAutoEppGrouping       : 1;
> 
> +  /**
> 
> +  EPB override over PECI
> 
> +  Enable by sending pcode command 0x2b , subcommand 0x3 to 1.
> 
> +  This will allow OOB EPB PECI override control.
> 
> +  <b>0: Disable;</b> 1: Enable;
> 
> +  **/
> 
> +  UINT8  EnableEpbPeciOverride          : 1;
> 
> +  /**
> 
> +  Support for Fast MSR for IA32_HWP_REQUEST.
> 
> +  On systems with HwP enabled, if this feature is available as indicated by
> MSR 0x65F[0] = 1,
> 
> +  set MSR 0x657[0] = 1.
> 
> +  0: Disable; <b> 1: Enable;</b>
> 
> +  **/
> 
> +  UINT8  EnableFastMsrHwpReq            : 1;
> 
> +  UINT8  ReservedBits1                  : 1;      ///< Reserved for future use.
> 
> +  UINT8  MinRingRatioLimit;                       ///< Minimum Ring Ratio Limit. Range
> from 0 to Max Turbo Ratio. 0 = AUTO/HW Default
> 
> +  UINT8  MaxRingRatioLimit;                       ///< Maximum Ring Ratio Limit.
> Range from 0 to Max Turbo Ratio. 0 = AUTO/HW Default
> 
> +  /**
> 
> +  Package Long duration turbo mode power limit (PL1).
> 
> +  Default is the TDP power limit of processor. Units are based on
> POWER_MGMT_CONFIG.CustomPowerUnit.
> 
> +  **/
> 
> +  UINT16 PowerLimit1;
> 
> +  /**
> 
> +  Package Short duration turbo mode power limit (PL2). Allows for short
> excursions above TDP power limit.
> 
> +  Default = 1.25 * TDP Power Limit. Units are based on
> POWER_MGMT_CONFIG.CustomPowerUnit.
> 
> +  **/
> 
> +  UINT16 PowerLimit2Power;
> 
> +  /**
> 
> +  Package PL3 power limit. PL3 is the CPU Peak Power Occurences Limit.
> 
> +  <b>Default: 0</b>. Range 0-65535. Units are based on
> POWER_MGMT_CONFIG.CustomPowerUnit.
> 
> +  **/
> 
> +  UINT16 PowerLimit3;
> 
> +  /**
> 
> +  Package PL4 power limit. PL4 is a Preemptive CPU Package Peak Power
> Limit, it will never be exceeded.
> 
> +  Power is premptively lowered before limit is reached. <b>Default: 0</b>.
> Range 0-65535.
> 
> +  Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.
> 
> +  **/
> 
> +  UINT16 PowerLimit4;
> 
> +  /**
> 
> +  Package Long duration turbo mode power limit (PL1) time window in
> seconds.
> 
> +  Used in calculating the average power over time.
> 
> +  Mobile: <b> 28s</b>
> 
> +  Desktop: <b> 8s</b>
> 
> +  Range: 0 - 128s
> 
> +  **/
> 
> +  UINT32 PowerLimit1Time;
> 
> +  UINT32 PowerLimit3Time;                         ///< Package PL3 time window.
> Range from 3ms to 64ms.
> 
> +  /**
> 
> +  Tcc Offset Time Window can range from 5ms to 448000ms for Runtime
> Average Temperature Limit (RATL).
> 
> +  For Y SKU, the recommended default for this policy is <b>5000: 5
> seconds</b>, For all other SKUs the recommended default are <b>0:
> Disabled</b>
> 
> +  **/
> 
> +  UINT32 TccOffsetTimeWindowForRatl;
> 
> +  /**
> 
> +  Customize the VccIn Demotion in ms accordingly. Values used by OEM
> expected to be in lower end of 1-30 ms range.
> 
> +  Value 1 means 1ms, value 2 means 2ms, and so on. Value 0 will disable
> VccIn Demotion knob.
> 
> +  <b> It's 30ms by silicon default</b>.
> 
> +  **/
> 
> +  UINT32 VccInDemotionMs;
> 
> +} CPU_POWER_MGMT_BASIC_CONFIG;
> 
> +
> 
> +#pragma pack (pop)
> 
> +
> 
> +#endif // _CPU_POWER_MGMT_BASIC_CONFIG_H_
> 
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPowerMgm
> tCustomConfig.h
> b/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPowerMgm
> tCustomConfig.h
> new file mode 100644
> index 0000000000..e1a5bcc684
> --- /dev/null
> +++
> b/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPowerMgm
> tCustomConfig.h
> @@ -0,0 +1,76 @@
> +/** @file
> 
> +  CPU Power Managment Custom Config Block.
> 
> +
> 
> +  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
> 
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> 
> +**/
> 
> +#ifndef _CPU_POWER_MGMT_CUSTOM_CONFIG_H_
> 
> +#define _CPU_POWER_MGMT_CUSTOM_CONFIG_H_
> 
> +
> 
> +#define CPU_POWER_MGMT_CUSTOM_CONFIG_REVISION 1
> 
> +
> 
> +extern EFI_GUID gCpuPowerMgmtCustomConfigGuid;
> 
> +
> 
> +#pragma pack (push,1)
> 
> +
> 
> +///
> 
> +/// Defines the maximum number of custom ratio states supported.
> 
> +///
> 
> +#define MAX_CUSTOM_RATIO_TABLE_ENTRIES    40
> 
> +#define MAX_16_CUSTOM_RATIO_TABLE_ENTRIES 16
> 
> +
> 
> +///
> 
> +/// Defines the maximum number of custom ConfigTdp entries supported.
> 
> +/// @warning: Changing this define would cause DWORD alignment issues
> in policy structures.
> 
> +///
> 
> +#define MAX_CUSTOM_CTDP_ENTRIES 3
> 
> +
> 
> +///
> 
> +/// This structure is used to describe the custom processor ratio table
> desired by the platform.
> 
> +///
> 
> +typedef struct {
> 
> +  UINT8  MaxRatio;                                           ///< The maximum ratio of the
> custom ratio table.
> 
> +  UINT8  NumberOfEntries;                                    ///< The number of custom
> ratio state entries, ranges from 2 to 40 for a valid custom ratio table.
> 
> +  UINT8  Rsvd0[2];                                           ///< Reserved for DWORD
> alignment.
> 
> +  UINT32 Cpuid;                                              ///< The CPU ID for which this custom
> ratio table applies.
> 
> +  UINT8  StateRatio[MAX_CUSTOM_RATIO_TABLE_ENTRIES];         ///< The
> processor ratios in the custom ratio table.
> 
> +  ///
> 
> +  /// If there are more than 16 total entries in the StateRatio table, then use
> these 16 entries to fill max 16 table.
> 
> +  /// @note If NumberOfEntries is 16 or less, or the first entry of this table is
> 0, then this table is ignored,
> 
> +  /// and up to the top 16 values from the StateRatio table is used instead.
> 
> +  ///
> 
> +  UINT8  StateRatioMax16[MAX_16_CUSTOM_RATIO_TABLE_ENTRIES];
> 
> +#if ((MAX_CUSTOM_RATIO_TABLE_ENTRIES +
> MAX_16_CUSTOM_RATIO_TABLE_ENTRIES) % 4)
> 
> +  UINT8  Rsvd1[4 - ((MAX_CUSTOM_RATIO_TABLE_ENTRIES +
> MAX_16_CUSTOM_RATIO_TABLE_ENTRIES) % 4)];  ///< If needed, add
> padding for dword alignment.
> 
> +#endif
> 
> +} PPM_CUSTOM_RATIO_TABLE;
> 
> +
> 
> +///
> 
> +/// PPM Custom ConfigTdp Settings
> 
> +///
> 
> +typedef struct _PPM_CUSTOM_CTDP_TABLE {
> 
> +  UINT32 CustomPowerLimit1Time      :  8;            ///< Short term Power Limit
> time window value for custom cTDP level.
> 
> +  UINT32 CustomTurboActivationRatio :  8;            ///< Turbo Activation Ratio
> for custom cTDP level.
> 
> +  UINT32 RsvdBits                   : 16;            ///< Bits reserved for DWORD
> alignment.
> 
> +  UINT16 CustomPowerLimit1;                          ///< Short term Power Limit
> value for custom cTDP level. Units are based on
> POWER_MGMT_CONFIG.CustomPowerUnit.
> 
> +  UINT16 CustomPowerLimit2;                          ///< Long term Power Limit value
> for custom cTDP level. Units are based on
> POWER_MGMT_CONFIG.CustomPowerUnit.
> 
> +} PPM_CUSTOM_CTDP_TABLE;
> 
> +
> 
> +/**
> 
> +  CPU Power Management Custom Configuration Structure.
> 
> +
> 
> +  <b>Revision 1</b>:
> 
> +  - Initial version.
> 
> +**/
> 
> +typedef struct {
> 
> +  CONFIG_BLOCK_HEADER    Header;                                                ///< Config
> Block Header
> 
> +  PPM_CUSTOM_RATIO_TABLE CustomRatioTable;                                      ///<
> Custom Processor Ratio Table Instance
> 
> +  PPM_CUSTOM_CTDP_TABLE
> CustomConfigTdpTable[MAX_CUSTOM_CTDP_ENTRIES];         ///< Custom
> ConfigTdp Settings Instance
> 
> +  UINT32                 ConfigTdpLock  : 1;                                    ///< Lock the
> ConfigTdp mode settings from runtime changes; <b>0: Disable</b>; 1:
> Enable.
> 
> +  UINT32                 ConfigTdpBios  : 1;                                    ///< Configure
> whether to load Configurable TDP SSDT; <b>0: Disable</b>; 1: Enable.
> 
> +  UINT32                 RsvdBits       : 30;                                   ///< Reserved for future
> use
> 
> +} CPU_POWER_MGMT_CUSTOM_CONFIG;
> 
> +
> 
> +#pragma pack (pop)
> 
> +
> 
> +#endif // _CPU_POWER_MGMT_CUSTOM_CONFIG_H_
> 
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPowerMgm
> tPsysConfig.h
> b/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPowerMgm
> tPsysConfig.h
> new file mode 100644
> index 0000000000..f1ceb8f43b
> --- /dev/null
> +++
> b/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPowerMgm
> tPsysConfig.h
> @@ -0,0 +1,36 @@
> +/** @file
> 
> +  CPU Power Management Psys(Platform) Config Block.
> 
> +
> 
> +  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
> 
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> 
> +**/
> 
> +#ifndef _CPU_POWER_MGMT_PSYS_CONFIG_H_
> 
> +#define _CPU_POWER_MGMT_PSYS_CONFIG_H_
> 
> +
> 
> +#define CPU_POWER_MGMT_PSYS_CONFIG_REVISION 1
> 
> +
> 
> +extern EFI_GUID gCpuPowerMgmtPsysConfigGuid;
> 
> +
> 
> +#pragma pack (push,1)
> 
> +
> 
> +/**
> 
> +  CPU Power Management Psys(Platform) Configuration Structure.
> 
> +
> 
> +  <b>Revision 1</b>:
> 
> +  - Initial version.
> 
> +**/
> 
> +typedef struct {
> 
> +  CONFIG_BLOCK_HEADER   Header;                   ///< Config Block Header
> 
> +  UINT32 PsysPowerLimit1       : 1;               ///< MSR 0x65C[15]: PL1 Enable
> activates the PL1 value to limit average platform power
> 
> +  UINT32 PsysPowerLimit1Time   : 8;               ///< MSR 0x65C[23:17]: PL1
> timewindow in seconds.
> 
> +  UINT32 PsysPowerLimit2       : 1;               ///< MSR 0x65C[47]: PL2 Enable
> activates the PL2 value to limit average platform power
> 
> +  UINT32 RsvdBits              : 22;              ///< Reserved for future use.
> 
> +  UINT16 PsysPowerLimit1Power;                    ///< MSR 0x65C[14:0]: Platform
> PL1 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.
> 
> +  UINT16 PsysPowerLimit2Power;                    ///< MSR 0x65C[46:32]]:
> Platform PL2 power. Units are based on
> POWER_MGMT_CONFIG.CustomPowerUnit.
> 
> +  UINT16 PsysPmax;                                ///< PCODE MMIO Mailbox: Platform
> Power Pmax. <b>0 - Auto</b> Specified in 1/8 Watt increments. 0-1024
> Watts. Value of 800 = 100W.
> 
> +  UINT8  Rsvd[2];                                 ///< Reserved for future use and config
> block alignment
> 
> +} CPU_POWER_MGMT_PSYS_CONFIG;
> 
> +
> 
> +#pragma pack (pop)
> 
> +
> 
> +#endif // _CPU_POWER_MGMT_PSYS_CONFIG_H_
> 
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPowerMgm
> tTestConfig.h
> b/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPowerMgm
> tTestConfig.h
> new file mode 100644
> index 0000000000..bd641f27c5
> --- /dev/null
> +++
> b/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPowerMgm
> tTestConfig.h
> @@ -0,0 +1,150 @@
> +/** @file
> 
> +  CPU Power Management Test Config Block.
> 
> +
> 
> +  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
> 
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> 
> +**/
> 
> +#ifndef _CPU_POWER_MGMT_TEST_CONFIG_H_
> 
> +#define _CPU_POWER_MGMT_TEST_CONFIG_H_
> 
> +
> 
> +#define CPU_POWER_MGMT_TEST_CONFIG_REVISION 4
> 
> +
> 
> +extern EFI_GUID gCpuPowerMgmtTestConfigGuid;
> 
> +
> 
> +#pragma pack (push,1)
> 
> +
> 
> +///
> 
> +/// PPM Package C State Limit
> 
> +///
> 
> +typedef enum {
> 
> +  PkgC0C1                 = 0,
> 
> +  PkgC2,
> 
> +  PkgC3,
> 
> +  PkgC6,
> 
> +  PkgC7,
> 
> +  PkgC7s,
> 
> +  PkgC8,
> 
> +  PkgC9,
> 
> +  PkgC10,
> 
> +  PkgCMax,
> 
> +  PkgCpuDefault = 254,
> 
> +  PkgAuto = 255
> 
> +} MAX_PKG_C_STATE;
> 
> +
> 
> +///
> 
> +/// PPM Package C State Time Limit
> 
> +///
> 
> +typedef enum {
> 
> +  TimeUnit1ns             = 0,
> 
> +  TimeUnit32ns,
> 
> +  TimeUnit1024ns,
> 
> +  TimeUnit32768ns,
> 
> +  TimeUnit1048576ns,
> 
> +  TimeUnit33554432ns,
> 
> +  TimeUnitMax
> 
> +} C_STATE_TIME_UNIT;
> 
> +
> 
> +///
> 
> +/// Custom Power Units. User can choose to enter in watts or 125 milliwatt
> increments.
> 
> +///
> 
> +typedef enum {
> 
> +  PowerUnitWatts = 0,     ///< in Watts.
> 
> +  PowerUnit125MilliWatts, ///< in 125 milliwatt increments. Example: 90
> power units times 125 mW equals 11.250 W.
> 
> +  PowerUnitMax
> 
> +} CUSTOM_POWER_UNIT;
> 
> +
> 
> +///
> 
> +/// PPM Interrupt Redirection Mode Selection
> 
> +///
> 
> +typedef enum {
> 
> +  PpmIrmFixedPriority     = 0,
> 
> +  PpmIrmRoundRobin,
> 
> +  PpmIrmHashVector,
> 
> +  PpmIrmReserved1,
> 
> +  PpmIrmReserved2,
> 
> +  PpmIrmReserved3,
> 
> +  PpmIrmReserved4,
> 
> +  PpmIrmNoChange
> 
> +} PPM_IRM_SETTING;
> 
> +
> 
> +/**
> 
> +  CPU Power Management Test Configuration Structure.
> 
> +
> 
> +  <b>Revision 1</b>:
> 
> +  - Initial version.
> 
> +  <b>Revision 2</b>:
> 
> +  - Add  CstateLatencyControl0TimeUnit for WHL only
> 
> +  - Add  CstateLatencyControl0Irtl for WHL only
> 
> +  <b>Revision 3</b>:
> 
> +  - Change C State LatencyContol to Auto as default.
> 
> +  <b>Revision 4</b>:
> 
> +  - Deprecate ConfigTdpLevel. Move to premem.
> 
> +**/
> 
> +typedef struct {
> 
> +  CONFIG_BLOCK_HEADER   Header;                    ///< Offset 0-27  Config Block
> Header
> 
> +  UINT32 Eist                          : 1;        ///< Offset 28-31 Enable or Disable Intel
> SpeedStep Technology. 0: Disable; <b>1: Enable</b>
> 
> +  UINT32 EnergyEfficientPState         : 1;        ///<              Enable or Disable
> Energy Efficient P-state will be applied in Turbo mode. Disable; <b>1:
> Enable</b>
> 
> +  UINT32 EnergyEfficientTurbo          : 1;        ///<              Enable or Disable
> Energy Efficient Turbo, will be applied in Turbo mode. Disable; <b>1:
> Enable</b>
> 
> +  UINT32 TStates                       : 1;        ///<              Enable or Disable T states;
> <b>0: Disable</b>; 1: Enable.
> 
> +  UINT32 BiProcHot                     : 1;        ///<              Enable or Disable Bi-
> Directional PROCHOT#; 0: Disable; <b>1: Enable</b>.
> 
> +  UINT32 DisableProcHotOut             : 1;        ///<              Enable or Disable
> PROCHOT# signal being driven externally; 0: Disable; <b>1: Enable</b>.
> 
> +  UINT32 ProcHotResponse               : 1;        ///<              Enable or Disable
> PROCHOT# Response; <b>0: Disable</b>; 1: Enable.
> 
> +  UINT32 DisableVrThermalAlert         : 1;        ///<              Enable or Disable VR
> Thermal Alert; <b>0: Disable</b>; 1: Enable.
> 
> +  UINT32 EnableAllThermalFunctions     : 1;        ///<              Enable or Disable
> Thermal Reporting through ACPI tables; 0: Disable; <b>1: Enable</b>.
> 
> +  UINT32 ThermalMonitor                : 1;        ///<              Enable or Disable
> Thermal Monitor; 0: Disable; <b>1: Enable</b>.
> 
> +  UINT32 Cx                            : 1;        ///<              Enable or Disable CPU power
> states (C-states). 0: Disable; <b>1: Enable</b>
> 
> +  UINT32 PmgCstCfgCtrlLock             : 1;        ///<              If enabled, sets MSR
> 0xE2[15]; 0: Disable; <b>1: Enable</b>.
> 
> +  UINT32 C1e                           : 1;        ///<              Enable or Disable Enhanced C-
> states. 0: Disable; <b>1: Enable</b>
> 
> +  UINT32 C1AutoDemotion                : 1;        ///<              Enable or Disable C6/C7
> auto demotion to C1. 0: Disabled; <b>1: C1 Auto demotion</b>
> 
> +  UINT32 C1UnDemotion                  : 1;        ///<              Enable or Disable
> C1UnDemotion. 0: Disabled; <b>1: C1 Auto undemotion</b>
> 
> +  UINT32 C3AutoDemotion                : 1;        ///<              [CoffeeLake Only]
> Enable or Disable C6/C7 auto demotion to C3  0: Disabled; <b>1: C3 Auto
> demotion</b>
> 
> +  UINT32 C3UnDemotion                  : 1;        ///<              [CoffeeLake Only]
> Enable or Disable C3UnDemotion. 0: Disabled; <b>1: C3 Auto
> undemotion</b>
> 
> +  UINT32 PkgCStateDemotion             : 1;        ///<              Enable or Disable
> Package Cstate Demotion. Disable; <b>1: Enable</b> [WhiskeyLake]
> <b>Disable</b>; 1: Enable
> 
> +  UINT32 PkgCStateUnDemotion           : 1;        ///<              Enable or Disable
> Package Cstate UnDemotion. Disable; <b>1: Enable</b> [WhiskeyLake]
> <b>Disable</b>; 1: Enable
> 
> +  UINT32 CStatePreWake                 : 1;        ///<              Enable or Disable
> CState-Pre wake. Disable; <b>1: Enable</b>
> 
> +  UINT32 TimedMwait                    : 1;        ///<              Enable or Disable
> TimedMwait Support. <b>Disable</b>; 1: Enable
> 
> +  UINT32 CstCfgCtrIoMwaitRedirection   : 1;        ///<              Enable or Disable
> IO to MWAIT redirection; <b>0: Disable</b>; 1: Enable.
> 
> +  UINT32 ProcHotLock                   : 1;        ///<              If enabled, sets MSR
> 0x1FC[23]; <b>0: Disable</b>; 1: Enable.
> 
> +  UINT32 RaceToHalt                    : 1;        ///<              Enable or Disable Race To
> Halt feature; 0: Disable; <b>1: Enable </b>. RTH will dynamically increase CPU
> frequency in order to enter pkg C-State faster to reduce overall power. (RTH
> is controlled through MSR 1FC bit 20)
> 
> +  UINT32 ConfigTdpLevel                : 8;        ///<              @deprecated. Move to
> premem phase.
> 
> +  UINT16 CstateLatencyControl1Irtl;                ///< Offset 32-33 Interrupt
> Response Time Limit of LatencyContol1 MSR 0x60B[9:0].<b>0 is Auto</b>.
> 
> +  UINT16 CstateLatencyControl2Irtl;                ///< Offset 34-35 Interrupt
> Response Time Limit of LatencyContol2 MSR 0x60C[9:0].<b>0 is Auto</b>.
> 
> +  UINT16 CstateLatencyControl3Irtl;                ///< Offset 36-37 Interrupt
> Response Time Limit of LatencyContol3 MSR 0x633[9:0].<b>0 is Auto</b>.
> 
> +  UINT16 CstateLatencyControl4Irtl;                ///< Offset 38-39 Interrupt
> Response Time Limit of LatencyContol4 MSR 0x634[9:0].<b>0 is Auto</b>.
> 
> +  UINT16 CstateLatencyControl5Irtl;                ///< Offset 40-41 Interrupt
> Response Time Limit of LatencyContol5 MSR 0x635[9:0].<b>0 is Auto</b>.
> 
> +  // Due to the removal of CstateLatencyControl0Irtl, PkgCStateLimit is not
> aligned to 32-bit address.
> 
> +  UINT8  Rsvd1[2];                                 ///< Offset 42-43 Reserved for config
> block alignment.
> 
> +  MAX_PKG_C_STATE   PkgCStateLimit;                ///< Offset 44    This field is
> used to set the Max Pkg Cstate. Default set to Auto which limits the Max Pkg
> Cstate to deep C-state.
> 
> +  /**
> 
> +     @todo: The following enums have to be replaced with policies.
> 
> +  **/
> 
> +  C_STATE_TIME_UNIT Reserved;                      ///< Offset 45    Reserved for
> config block alignment.
> 
> +  C_STATE_TIME_UNIT CstateLatencyControl1TimeUnit; ///< Offset 46
> TimeUnit for Latency Control1 MSR 0x60B[12:10]; <b>2: 1024ns</b>.
> 
> +  C_STATE_TIME_UNIT CstateLatencyControl2TimeUnit; ///< Offset 47
> TimeUnit for Latency Control2 MSR 0x60C[12:10]; <b>2: 1024ns</b>.
> 
> +  C_STATE_TIME_UNIT CstateLatencyControl3TimeUnit; ///< Offset 48
> TimeUnit for Latency Control3 MSR 0x633[12:10]; <b>2: 1024ns</b>.
> 
> +  C_STATE_TIME_UNIT CstateLatencyControl4TimeUnit; ///< Offset 49
> TimeUnit for Latency Control4 MSR 0x634[12:10]; <b>2: 1024ns</b>.
> 
> +  C_STATE_TIME_UNIT CstateLatencyControl5TimeUnit; ///< Offset 50
> TimeUnit for Latency Control5 MSR 0x635[12:10]; <b>2: 1024ns</b>.
> 
> +  /**
> 
> +  Offset 51  Default power unit in watts or in 125 milliwatt increments.
> 
> +  - 0: PowerUnitWatts.
> 
> +  - <b>1: PowerUnit125MilliWatts</b>.
> 
> +  **/
> 
> +  CUSTOM_POWER_UNIT CustomPowerUnit;
> 
> +  /**
> 
> +  Offset 52  Interrupt Redirection Mode Select.
> 
> +   - 0: Fixed priority.             //Default under CNL.
> 
> +   - 1: Round robin.
> 
> +   - 2: Hash vector.
> 
> +   - 4: PAIR with fixed priority.   //Default under KBL, not available under CNL.
> 
> +   - 5: PAIR with round robin.      //Not available under CNL.
> 
> +   - 6: PAIR with hash vector.      //Not available under CNL.
> 
> +   - 7: No change.
> 
> +  **/
> 
> +  PPM_IRM_SETTING      PpmIrmSetting;
> 
> +  // Move the padding to previous offset to align the structure at 32-bit
> address.
> 
> +  UINT8  Rsvd[4];                                 ///< Offset 53-56 Reserved for future use
> and config block alignment
> 
> +} CPU_POWER_MGMT_TEST_CONFIG;
> 
> +
> 
> +#pragma pack (pop)
> 
> +
> 
> +#endif // _CPU_POWER_MGMT_TEST_CONFIG_H_
> 
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuSecurityPre
> MemConfig.h
> b/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuSecurityPre
> MemConfig.h
> new file mode 100644
> index 0000000000..24614fe497
> --- /dev/null
> +++
> b/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuSecurityPre
> MemConfig.h
> @@ -0,0 +1,63 @@
> +/** @file
> 
> +  CPU Security PreMemory Config Block.
> 
> +
> 
> +  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
> 
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> 
> +**/
> 
> +#ifndef _CPU_SECURITY_PREMEM_CONFIG_H_
> 
> +#define _CPU_SECURITY_PREMEM_CONFIG_H_
> 
> +
> 
> +#define CPU_SECURITY_PREMEM_CONFIG_REVISION 1
> 
> +
> 
> +extern EFI_GUID gCpuSecurityPreMemConfigGuid;
> 
> +
> 
> +#pragma pack (push,1)
> 
> +
> 
> +/**
> 
> +  CPU Security PreMemory Configuration Structure.
> 
> +
> 
> +  <b>Revision 1</b>:
> 
> +  - Initial version.
> 
> +**/
> 
> +typedef struct {
> 
> +  CONFIG_BLOCK_HEADER Header;                      ///< Config Block Header
> 
> +  UINT32              PrmrrSize;                   ///< PRMRR Size.<b>Software Control:
> 0x0</b>  32MB: 0x2000000, 64MB: 0x4000000, 128 MB: 0x8000000, 256 MB:
> 0x10000000, 512 MB: 0x20000000
> 
> +  UINT16              BiosSize;                    ///< Flash information for BIOS Guard:
> BIOS Size in KB.
> 
> +  UINT8               Reserved[2];                 ///< Reserved for future use
> 
> +/**
> 
> +   Enable or Disable BIOS Guard; 0: Disable; <b>1: Enable</b>.
> 
> +    - This is an optional feature and can be opted out.
> 
> +    - If this policy is set to Disabled, the policies in the BIOS_GUARD_CONFIG
> will be ignored.
> 
> +    - If PeiBiosGuardLibNull is used, this policy will have no effect.
> 
> +**/
> 
> +  UINT32              BiosGuard               :  1;
> 
> +  UINT32              BiosGuardToolsInterface :  1; ///< BIOS Guard Tools
> Interface; <b>0: Disable</b>, 1:Enable
> 
> +/**
> 
> +   Enable or Disable Software Guard Extensions; <b>0: Disable</b>; 1:
> Enable.
> 
> +    - This is an optional feature and can be opted out.
> 
> +    - If this policy is set to Disabled, the policies in the CPU_SGX_CONFIG will
> be ignored.
> 
> +    - If BaseSoftwareGuardLibNull is used, this policy will have no effect.
> 
> +**/
> 
> +  UINT32              EnableSgx               :  1;
> 
> +/**
> 
> +   Enable or Disable Trusted Execution Technology; <b>0: Disable</b>; 1:
> Enable.
> 
> +    - This is an optional feature and can be opted out.
> 
> +    - If this policy is set to Disabled, the policies in the
> CPU_TXT_PREMEM_CONFIG will be ignored.
> 
> +    - If PeiTxtLibNull is used, this policy will have no effect.
> 
> +**/
> 
> +  UINT32              Txt                     :  1;
> 
> +  UINT32              SkipStopPbet            :  1; ///< <b>(Test)</b> Skip Stop PBET
> Timer; <b>0: Disable</b>; 1: Enable.
> 
> +  ///
> 
> +  /// <b>(Test)</b> This policy indicates whether or not BIOS should allocate
> PRMRR memory for C6DRAM power gating feature.
> 
> +  ///  - 0: Don't allocate any PRMRR memory for C6DRAM power gating
> feature.
> 
> +  ///  - <b>1: Allocate PRMRR memory for C6DRAM power gating
> feature</b>.
> 
> +  ///
> 
> +  UINT32              EnableC6Dram            :  1;
> 
> +  UINT32              ResetAux                :  1; ///< <b>(Test)</b> Reset Auxiliary
> content, <b>0: Disabled</b>, 1: Enabled
> 
> +  UINT32              TxtAcheckRequest        :  1; ///< <b>(Test)</b>
> AcheckRequest <b>0: Disabled</b>, 1: Enabled. When Enabled, it will call
> Acheck regardless of crashcode value
> 
> +  UINT32              RsvdBits                : 24; ///< Reserved for future use
> 
> +} CPU_SECURITY_PREMEM_CONFIG;
> 
> +
> 
> +#pragma pack (pop)
> 
> +
> 
> +#endif // _CPU_SECURITY_CONFIG_H_
> 
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuTestConfig.
> h
> b/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuTestConfig.
> h
> new file mode 100644
> index 0000000000..ee946290e0
> --- /dev/null
> +++
> b/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuTestConfig.
> h
> @@ -0,0 +1,51 @@
> +/** @file
> 
> +  CPU Test Config Block.
> 
> +
> 
> +  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
> 
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> 
> +**/
> 
> +#ifndef _CPU_TEST_CONFIG_H_
> 
> +#define _CPU_TEST_CONFIG_H_
> 
> +
> 
> +#define CPU_TEST_CONFIG_REVISION 2
> 
> +
> 
> +extern EFI_GUID gCpuTestConfigGuid;
> 
> +
> 
> +#pragma pack (push,1)
> 
> +
> 
> +/**
> 
> +  CPU Test Configuration Structure.
> 
> +
> 
> +  <b>Revision 1</b>:
> 
> +  - Initial version.
> 
> +  <b>Revision 2</b>:
> 
> +  - Removed Voltage Optimization feature.
> 
> +**/
> 
> +typedef struct {
> 
> +  CONFIG_BLOCK_HEADER   Header;                   ///< Config Block Header
> 
> +  UINT32                MlcStreamerPrefetcher           : 1;     ///< Enable or Disable
> MLC Streamer Prefetcher; 0: Disable; <b>1: Enable</b>.
> 
> +  UINT32                MlcSpatialPrefetcher            : 1;     ///< Enable or Disable MLC
> Spatial Prefetcher; 0: Disable; <b>1: Enable</b>.
> 
> +  UINT32                MonitorMwaitEnable              : 1;     ///< Enable or Disable
> Monitor /MWAIT instructions; 0: Disable; <b>1: Enable</b>.
> 
> +  UINT32                MachineCheckEnable              : 1;     ///< Enable or Disable
> initialization of machine check registers; 0: Disable; <b>1: Enable</b>.
> 
> +  UINT32                ProcessorTraceOutputScheme      : 1;     ///< Control on
> Processor Trace output scheme; <b>0: Single Range Output</b>; 1: ToPA
> Output.
> 
> +  UINT32                ProcessorTraceEnable            : 1;     ///< Enable or Disable
> Processor Trace feature; <b>0: Disable</b>; 1: Enable.
> 
> +  UINT32                ThreeStrikeCounterDisable       : 1;     ///< Disable Three
> strike counter; <b>0: FALSE</b>; 1: TRUE.
> 
> +  UINT32                RsvdBits                        : 25;     ///< Reserved for future use
> 
> +  /**
> 
> +     Base address of memory region allocated for Processor Trace.
> 
> +     Processor Trace requires 2^N alignment and size in bytes per thread,
> from 4KB to 128MB.
> 
> +     - <b>NULL: Disable</b>
> 
> +  **/
> 
> +  EFI_PHYSICAL_ADDRESS  ProcessorTraceMemBase;
> 
> +  /**
> 
> +     Length in bytes of memory region allocated for Processor Trace.
> 
> +     Processor Trace requires 2^N alignment and size in bytes per thread,
> from 4KB to 128MB.
> 
> +     - <b>0: Disable</b>
> 
> +  **/
> 
> +  UINT32                ProcessorTraceMemLength;
> 
> +  UINT8                 Reserved0[4];
> 
> +} CPU_TEST_CONFIG;
> 
> +
> 
> +#pragma pack (pop)
> 
> +
> 
> +#endif // _CPU_TEST_CONFIG_H_
> 
> diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/CpuAccess.h
> b/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/CpuAccess.h
> new file mode 100644
> index 0000000000..5d5e4df071
> --- /dev/null
> +++ b/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/CpuAccess.h
> @@ -0,0 +1,12 @@
> +/** @file
> 
> +  Macros to simplify and abstract the interface to CPU configuration.
> 
> +
> 
> +  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
> 
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> 
> +**/
> 
> +#ifndef _CPUACCESS_H_
> 
> +#define _CPUACCESS_H_
> 
> +
> 
> +#include "CpuDataStruct.h"
> 
> +
> 
> +#endif
> 
> diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/CpuDataStruct.h
> b/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/CpuDataStruct.h
> new file mode 100644
> index 0000000000..ba9a840e54
> --- /dev/null
> +++ b/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/CpuDataStruct.h
> @@ -0,0 +1,21 @@
> +/** @file
> 
> +  This file declares various data structures used in CPU reference code.
> 
> +
> 
> +  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
> 
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> 
> +**/
> 
> +
> 
> +#ifndef _CPU_DATA_STRUCT_H
> 
> +#define _CPU_DATA_STRUCT_H
> 
> +
> 
> +///
> 
> +/// Structure to hold the return value of AsmCpuid instruction
> 
> +///
> 
> +typedef struct {
> 
> +  UINT32 RegEax; ///< Value of EAX.
> 
> +  UINT32 RegEbx; ///< Value of EBX.
> 
> +  UINT32 RegEcx; ///< Value of ECX.
> 
> +  UINT32 RegEdx; ///< Value of EDX.
> 
> +} EFI_CPUID_REGISTER;
> 
> +
> 
> +#endif
> 
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/CpuPolicyCommon.h
> b/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/CpuPolicyCommon.h
> new file mode 100644
> index 0000000000..1178f68d0c
> --- /dev/null
> +++ b/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/CpuPolicyCommon.h
> @@ -0,0 +1,23 @@
> +/** @file
> 
> +  CPU Policy Structure definition which will contain several config blocks
> during runtime.
> 
> +
> 
> +  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
> 
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> 
> +**/
> 
> +#ifndef _CPU_POLICY_COMMON_H_
> 
> +#define _CPU_POLICY_COMMON_H_
> 
> +
> 
> +#include <ConfigBlock.h>
> 
> +#include <ConfigBlock/CpuConfig.h>
> 
> +#include <ConfigBlock/CpuPidTestConfig.h>
> 
> +#include <ConfigBlock/CpuPowerMgmtBasicConfig.h>
> 
> +#include <ConfigBlock/CpuPowerMgmtCustomConfig.h>
> 
> +#include <ConfigBlock/CpuPowerMgmtPsysConfig.h>
> 
> +#include <ConfigBlock/CpuPowerMgmtTestConfig.h>
> 
> +#include <ConfigBlock/VoltageRegulator/CpuPowerMgmtVrConfig.h>
> 
> +#include <ConfigBlock/CpuTestConfig.h>
> 
> +#include <ConfigBlock/CpuSecurityPreMemConfig.h>
> 
> +#include <ConfigBlock/CpuConfigLibPreMemConfig.h>
> 
> +#include <OverclockingConfig.h>
> 
> +
> 
> +#endif // _CPU_POLICY_COMMON_H_
> 
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/Register/CommonMsr.h
> b/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/Register/CommonMsr.h
> new file mode 100644
> index 0000000000..a2cd1db1d6
> --- /dev/null
> +++ b/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/Register/CommonMsr.h
> @@ -0,0 +1,18 @@
> +
> 
> +/** @file
> 
> +  CommonMsr.h
> 
> +
> 
> +  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
> 
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> 
> +**/
> 
> +
> 
> +#ifndef _COMMONMSR_h
> 
> +#define _COMMONMSR_h
> 
> +#include <Base.h>
> 
> +
> 
> +/**
> 
> +  Special Chipset Usage MSR
> 
> +**/
> 
> +#define MSR_SPCL_CHIPSET_USAGE 0x000001FE
> 
> +
> 
> +#endif /* _COMMONMSR_h */
> 
> --
> 2.24.0.windows.2