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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Nate DeSimone > -----Original Message----- > From: Luo, Heng > Sent: Sunday, January 31, 2021 5:36 PM > To: devel@edk2.groups.io > Cc: Chaganty, Rangasai V ; Desimone, > Nathaniel L > Subject: [PATCH 04/40] TigerlakeSiliconPkg/Cpu: Add Include headers >=20 > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3171 >=20 > Adds header files common to CPU modules. >=20 > Cc: Sai Chaganty > Cc: Nate DeSimone > Signed-off-by: Heng Luo > --- > Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfig.h > | 83 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfigLibPre > MemConfig.h | 148 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPidTestConfi= g. > h | 52 > ++++++++++++++++++++++++++++++++++++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPowerMgmtB > asicConfig.h | 226 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPowerMgmtC > ustomConfig.h | 76 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPowerMgmtP > sysConfig.h | 36 ++++++++++++++++++++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPowerMgmtT > estConfig.h | 150 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuSecurityPreM > emConfig.h | 63 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++ > Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuTestConfig.= h > | 51 +++++++++++++++++++++++++++++++++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/CpuAccess.h = | > 12 ++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/CpuDataStruct.h = | > 21 +++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/CpuPolicyCommon.h > | 23 +++++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/Register/CommonMsr.h > | 18 ++++++++++++++++++ > 13 files changed, 959 insertions(+) >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfig.h > b/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfig.h > new file mode 100644 > index 0000000000..d837500a38 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfig.h > @@ -0,0 +1,83 @@ > +/** @file >=20 > + CPU Config Block. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _CPU_CONFIG_H_ >=20 > +#define _CPU_CONFIG_H_ >=20 > + >=20 > +#define CPU_CONFIG_REVISION 3 >=20 > + >=20 > +extern EFI_GUID gCpuConfigGuid; >=20 > + >=20 > +#pragma pack (push,1) >=20 > + >=20 > +/** >=20 > + CPU Configuration Structure. >=20 > + >=20 > + Revision 1: >=20 > + - Initial version. >=20 > + Revision 2: >=20 > + - Add SmbiosType4MaxSpeedOverride. >=20 > + Revision 3: >=20 > + - Add AvxDisable & Avx3Disable. >=20 > +**/ >=20 > +typedef struct { >=20 > + CONFIG_BLOCK_HEADER Header; ///< Config Block Head= er >=20 > + UINT32 MicrocodePatchRegionSize; >=20 > + EFI_PHYSICAL_ADDRESS MicrocodePatchAddress; ///< Pointer to > microcode patch that is suitable for this processor. >=20 > + /** >=20 > + Enable or Disable Advanced Encryption Standard (AES) feature. >=20 > + For some countries, this should be disabled for legal reasons. >=20 > + - 0: Disable >=20 > + - 1: Enable >=20 > + **/ >=20 > + UINT32 AesEnable : 1; >=20 > + /** >=20 > + Enable or Disable Trusted Execution Technology (TXT) feature. >=20 > + - 0: Disable >=20 > + - 1: Enable >=20 > + **/ >=20 > + UINT32 TxtEnable : 1; >=20 > + UINT32 SkipMpInit : 1; ///< For Fsp only, Sil= icon Initialization > will skip MP Initialization (including BSP) if enabled. For non-FSP, this= should > always be 0. >=20 > + /** >=20 > + Enable or Disable or Auto for PPIN Support to view Protected Process= or > Inventory Number. >=20 > + - 0: Disable >=20 > + - 1: Enable >=20 > + - 2: Auto : Feature is based on End Of Manufacturing (EOM) flag. = If EOM > is set, it is disabled. >=20 > + **/ >=20 > + UINT32 PpinSupport : 2; >=20 > + /** >=20 > + Enable or Disable #AC machine check on split lock. >=20 > + - 0: Disable >=20 > + - 1: Enable >=20 > + **/ >=20 > + UINT32 AcSplitLock : 1; >=20 > + /** >=20 > + Enable or Disable Avx. >=20 > + - 1: Disable >=20 > + - 0: Enable >=20 > + **/ >=20 > + UINT32 AvxDisable : 1; >=20 > + /** >=20 > + Enable or Disable Avx3. >=20 > + - 1: Disable >=20 > + - 0: Enable >=20 > + **/ >=20 > + UINT32 Avx3Disable : 1; >=20 > + UINT32 RsvdBits : 24; ///< Reserved for futu= re use >=20 > + /** >=20 > + Provide the option for platform to override the MaxSpeed field of Sm= bios > Type 4. >=20 > + Value 4000 means 4000MHz. >=20 > + If this value is not zero, it dominates the field. >=20 > + If this value is zero, CPU RC will update the field according to the= max > radio. >=20 > + default is 0. >=20 > + **/ >=20 > + UINT16 SmbiosType4MaxSpeedOverride; >=20 > + UINT8 Reserved0[2]; ///< Reserved for futu= re use >=20 > +} CPU_CONFIG; >=20 > + >=20 > +#pragma pack (pop) >=20 > + >=20 > +#endif // _CPU_CONFIG_H_ >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfigLibP= r > eMemConfig.h > b/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfigLibP= r > eMemConfig.h > new file mode 100644 > index 0000000000..bf3f436ddd > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfigLibP= r > eMemConfig.h > @@ -0,0 +1,148 @@ > +/** @file >=20 > + CPU Security PreMemory Config Block. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _CPU_CONFIG_LIB_PREMEM_CONFIG_H_ >=20 > +#define _CPU_CONFIG_LIB_PREMEM_CONFIG_H_ >=20 > + >=20 > +#define CPU_CONFIG_LIB_PREMEM_CONFIG_REVISION 6 >=20 > + >=20 > +extern EFI_GUID gCpuConfigLibPreMemConfigGuid; >=20 > + >=20 > +#define BOOT_FREQUENCY_MAX_BATTERY_PERF 0 >=20 > +#define BOOT_FREQUENCY_MAX_NON_TURBO_PERF 1 >=20 > +#define BOOT_FREQUENCY_TURBO_PERF 2 >=20 > + >=20 > +#pragma pack (push,1) >=20 > + >=20 > +/** >=20 > + CPU Config Library PreMemory Configuration Structure. >=20 > + >=20 > + Revision 1: >=20 > + - Initial version. >=20 > + Revision 2: >=20 > + - Expand the supported number of processor cores (ActiveCoreCount1). >=20 > + Revision 3: >=20 > + - Added PECI Sx and C10 Reset. >=20 > + Revision 4: >=20 > + - Added ActiveSmallCoreCount. >=20 > + Revision 5: >=20 > + - Added CrashLogGprs >=20 > + Revision 6: >=20 > + - Added ConfigTdpLevel >=20 > +**/ >=20 > +typedef struct { >=20 > + CONFIG_BLOCK_HEADER Header; ///< Config Block Header >=20 > + UINT32 HyperThreading : 1; ///< Enable or Disable Hyper Th= reading; > 0: Disable; 1: Enable. >=20 > + /** >=20 > + Sets the boot frequency starting from reset vector. >=20 > + - 0: Maximum battery performance. >=20 > + - 1: Maximum non-turbo performance >=20 > + -2: Turbo performance. >=20 > + @note If Turbo is selected BIOS will start in max non-turbo mode and > switch to Turbo mode. >=20 > + **/ >=20 > + UINT32 BootFrequency : 2; >=20 > + /** >=20 > + Number of processor cores to enable. >=20 > + - 0: All cores >=20 > + - 1: 1 core >=20 > + - 2: 2 cores >=20 > + - 3: 3 cores >=20 > + **/ >=20 > + UINT32 ActiveCoreCount : 3; ///< @deprecated due to core ac= tive > number limitaion. >=20 > + UINT32 JtagC10PowerGateDisable : 1; ///< False: JTAG is power gated= in > C10 state. True: keeps the JTAG power up during C10 and deeper power > states for debug purpose. 0: False<\b>; 1: True. >=20 > + UINT32 BistOnReset : 1; ///< (Test) Enable or Di= sable BIST > on Reset; 0: Disable; 1: Enable. >=20 > + /** >=20 > + Enable or Disable Virtual Machine Extensions (VMX) feature. >=20 > + - 0: Disable >=20 > + - 1: Enable >=20 > + **/ >=20 > + UINT32 VmxEnable : 1; >=20 > + /** >=20 > + Processor Early Power On Configuration FCLK setting. >=20 > + - 0: 800 MHz (ULT/ULX). >=20 > + - 1: 1 GHz (DT/Halo). Not supported on ULT/ULX. >=20 > + - 2: 400 MHz. >=20 > + - 3: Reserved. >=20 > + **/ >=20 > + UINT32 FClkFrequency : 2; >=20 > + /** >=20 > + Enable or Disable CrashLog feature >=20 > + - 0: Disable >=20 > + - 1: Enable >=20 > + **/ >=20 > + UINT32 CrashLogEnable : 1; >=20 > + >=20 > + /** >=20 > + Enable or Disable Total Memory Encryption (TME) feature. >=20 > + - 0: Disable >=20 > + - 1: Enable >=20 > + **/ >=20 > + UINT32 TmeEnable : 1; >=20 > + >=20 > + UINT32 DebugInterfaceEnable : 2; ///< Enable or Disable processo= r > debug features; 0: Disable; 1: Enable; 2: No Change. >=20 > + UINT32 DebugInterfaceLockEnable : 1; ///< Lock or Unlock debug > interface features; 0: Disable; 1: Enable. >=20 > + >=20 > + /** >=20 > + Number of big cores in processor to enable. And support up to 16 cor= es. >=20 > + - 0: All cores >=20 > + - 1: 1 core >=20 > + - 2: 2 cores >=20 > + - 3: 3 cores >=20 > + **/ >=20 > + UINT32 ActiveCoreCount1 : 4; >=20 > + >=20 > + /** >=20 > + Enables a mailbox command to resolve rare PECI related Sx issues. >=20 > + @note This should only be used on systems that observe PECI Sx issues. >=20 > + - 0: Disable >=20 > + - 1: Enable >=20 > + **/ >=20 > + UINT32 PeciSxReset : 1; >=20 > + >=20 > + /** >=20 > + Enables the mailbox command to resolve PECI reset issues during Pkg-C1= 0 > exit. >=20 > + If Enabled, BIOS will send the CPU message to disable peci reset on C1= 0 > exit. >=20 > + The default value is 1: Enable for CML, and 0: Disable f= or > all other CPU's >=20 > + - 0: Disable >=20 > + - 1: Enable >=20 > + **/ >=20 > + UINT32 PeciC10Reset : 1; >=20 > + >=20 > + /** >=20 > + Number of small cores in processor to enable. And support the enabli= ng > of up to 63 cores. >=20 > + - 0: All cores >=20 > + - 1: 1 core >=20 > + - 2: 2 cores >=20 > + - 3: 3 cores >=20 > + **/ >=20 > + UINT32 ActiveSmallCoreCount : 6; >=20 > + >=20 > + /** >=20 > + Enable or Disable CrashLog GPRs dump >=20 > + - 0: Disable >=20 > + - 1: Gprs Enabled, Smm Gprs Enabled >=20 > + 2: Gprs Enabled, Smm Gprs Disabled >=20 > + **/ >=20 > + UINT32 CrashLogGprs : 2; >=20 > + >=20 > + UINT32 RsvdBits : 2; >=20 > + >=20 > + /** >=20 > + CpuRatio - Max non-turbo ratio (Flexible Ratio Boot) is set to CpuRa= tio. > 0: Disabled If disabled, doesn't override max-non turbo ratio. >=20 > + **/ >=20 > + UINT8 CpuRatio; >=20 > + /** >=20 > + Configuration for boot TDP selection; 0: TDP Nominal; 1: TDP > Down; 2: TDP Up. >=20 > + **/ >=20 > + UINT8 ConfigTdpLevel; >=20 > + UINT8 Reserved[2]; ///< Reserved for alignment >=20 > + UINT32 ElixirSpringsPatchAddr; ///< Address of Elixir Springs = Patch(es) >=20 > + UINT32 ElixirSpringsPatchSize; ///< Elixir Springs Patch(es) S= ize. >=20 > +} CPU_CONFIG_LIB_PREMEM_CONFIG; >=20 > + >=20 > +#pragma pack (pop) >=20 > + >=20 > +#endif // _CPU_CONFIG_LIB_PREMEM_CONFIG_H_ >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPidTestCon= f > ig.h > b/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPidTestCon= f > ig.h > new file mode 100644 > index 0000000000..4fcb92cb27 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPidTestCon= f > ig.h > @@ -0,0 +1,52 @@ > +/** @file >=20 > + CPU PID Config Block. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _CPU_PID_TEST_CONFIG_H_ >=20 > +#define _CPU_PID_TEST_CONFIG_H_ >=20 > + >=20 > +#define CPU_PID_TEST_CONFIG_REVISION 1 >=20 > + >=20 > +extern EFI_GUID gCpuPidTestConfigGuid; >=20 > + >=20 > +#pragma pack (push,1) >=20 > + >=20 > +/** >=20 > + PID Tuning Configuration Structure. >=20 > + Domain is mapped to Kp =3D 0, Ki =3D 1, Kd =3D 2. >=20 > + >=20 > + Revision 1: >=20 > + - Initial version. >=20 > +**/ >=20 > +typedef struct { >=20 > + CONFIG_BLOCK_HEADER Header; ///< Config Block Head= er >=20 > + UINT16 Ratl[3]; ///< RATL setting, in = 1/256 units. Range is 0 > - 65280 >=20 > + UINT16 VrTdcVr0[3]; ///< VR Thermal Design= Current for > VR0. In 1/256 units. Range is 0 - 65280 >=20 > + UINT16 VrTdcVr1[3]; ///< VR Thermal Design= Current for > VR1. In 1/256 units. Range is 0 - 65280 >=20 > + UINT16 VrTdcVr2[3]; ///< VR Thermal Design= Current for > VR2. In 1/256 units. Range is 0 - 65280 >=20 > + UINT16 VrTdcVr3[3]; ///< VR Thermal Design= Current for > VR3. In 1/256 units. Range is 0 - 65280 >=20 > + UINT16 PbmPsysPl1Msr[3]; ///< Power Budget Mana= gement > Psys PL1 MSR. In 1/256 units. Range is 0 - 65280 >=20 > + UINT16 PbmPsysPl1MmioPcs[3]; ///< Power Budget > Management Psys PL1 MMIO/PCS. In 1/256 units. Range is 0 - 65280 >=20 > + UINT16 PbmPsysPl2Msr[3]; ///< Power Budget Mana= gement > Psys PL2 MSR. In 1/256 units. Range is 0 - 65280 >=20 > + UINT16 PbmPsysPl2MmioPcs[3]; ///< Power Budget > Management Psys PL2 MMIO/PCS. In 1/256 units. Range is 0 - 65280 >=20 > + UINT16 PbmPkgPl1Msr[3]; ///< Power Budget Mana= gement > Package PL1 MSR. In 1/256 units. Range is 0 - 65280 >=20 > + UINT16 PbmPkgPl1MmioPcs[3]; ///< Power Budget > Management Package PL1 MMIO/PCS. In 1/256 units. Range is 0 - 65280 >=20 > + UINT16 PbmPkgPl2Msr[3]; ///< Power Budget Mana= gement > Package PL2 MSR. In 1/256 units. Range is 0 - 65280 >=20 > + UINT16 PbmPkgPl2MmioPcs[3]; ///< Power Budget > Management Package PL2 MMIO/PCS. In 1/256 units. Range is 0 - 65280 >=20 > + UINT16 DdrPl1Msr[3]; ///< DDR PL1 MSR. In 1= /256 units. > Range is 0 - 65280 >=20 > + UINT16 DdrPl1MmioPcs[3]; ///< DDR PL1 MMIO/PCS.= In 1/256 > units. Range is 0 - 65280 >=20 > + UINT16 DdrPl2Msr[3]; ///< DDR PL2 MSR. In 1= /256 units. > Range is 0 - 65280 >=20 > + UINT16 DdrPl2MmioPcs[3]; ///< DDR PL2 MMIO/PCS.= In 1/256 > units. Range is 0 - 65280 >=20 > + /** >=20 > + Enable or Disable PID Tuning programming flow. >=20 > + If disabled, all other policies in this config block are ignored. >=20 > + **/ >=20 > + UINT8 PidTuning; >=20 > + UINT8 Rsvd; ///< Reserved for DWOR= D alignment. >=20 > +} CPU_PID_TEST_CONFIG; >=20 > + >=20 > +#pragma pack (pop) >=20 > + >=20 > +#endif // _CPU_PID_TEST_CONFIG_H_ >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPowerMgm > tBasicConfig.h > b/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPowerMgm > tBasicConfig.h > new file mode 100644 > index 0000000000..0255d49bdf > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPowerMgm > tBasicConfig.h > @@ -0,0 +1,226 @@ > +/** @file >=20 > + CPU Power Management Basic Config Block. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _CPU_POWER_MGMT_BASIC_CONFIG_H_ >=20 > +#define _CPU_POWER_MGMT_BASIC_CONFIG_H_ >=20 > + >=20 > +#define CPU_POWER_MGMT_BASIC_CONFIG_REVISION 5 >=20 > + >=20 > +extern EFI_GUID gCpuPowerMgmtBasicConfigGuid; >=20 > + >=20 > +#pragma pack (push,1) >=20 > + >=20 > +/** >=20 > + CPU Power Management Basic Configuration Structure. >=20 > + >=20 > + Revision 1: >=20 > + - Initial version. >=20 > + Revision 2: >=20 > + - Changed EnableItbm default to be disable >=20 > + - Deprecated EnableItbmDriver due to Platform doesn't have ITBMT OS > driver >=20 > + Revision 3: >=20 > + - Add ApplyConfigTdp for TDP initialization settings based on non-cTDP= or > cTDP >=20 > + Revision 4: >=20 > + - Add Hwp Lock support >=20 > + Revision 5: >=20 > + - Add VccInDemotionOverride and VccInDemotionMs >=20 > +**/ >=20 > +typedef struct { >=20 > + CONFIG_BLOCK_HEADER Header; ///< Config Block Head= er >=20 > + /** >=20 > + Sets the boot frequency starting from reset vector. >=20 > + - 0: Maximum battery performance. >=20 > + - 1: Maximum non-turbo performance. >=20 > + - 2: Turbo performance. >=20 > + @note If Turbo is selected BIOS will start in max non-turbo mode and > switch to Turbo mode. >=20 > + **/ >=20 > + UINT32 BootFrequency : 2; //@deprecated >=20 > + UINT32 SkipSetBootPState : 1; ///< Choose whether to= skip > SetBootPState function for all APs; 0: Do not skip; 1: Skip. >=20 > + /** >=20 > + Enable or Disable Intel Speed Shift Technology. >=20 > + Enabling allows for processor control of P-state transitions. >=20 > + 0: Disable; 1: Enable; Bit 1 is ignored. >=20 > + @note Currently this feature is recommended to be enabled only on > win10 >=20 > + **/ >=20 > + UINT32 Hwp : 2; >=20 > + /** >=20 > + Hardware Duty Cycle Control configuration. 0: Disabled; 1: Enabled<= /b> > 2-3:Reserved >=20 > + HDC enables the processor to autonomously force components to enter > into an idle state to lower effective frequency. >=20 > + This allows for increased package level C6 residency. >=20 > + @note Currently this feature is recommended to be enabled only on > win10 >=20 > + **/ >=20 > + UINT32 HdcControl : 2; >=20 > + UINT32 PowerLimit2 : 1; ///< Enable or Disable= short duration > Power Limit (PL2). 0: Disable; 1: Enable >=20 > + UINT32 TurboPowerLimitLock : 1; ///< MSR 0x610[63] and > 0x618[63]: Locks all Turbo power limit settings to read-only; 0: > Disable; 1: Enable (Lock). >=20 > + UINT32 PowerLimit3DutyCycle : 8; ///< Package PL3 Duty = Cycle. > Specifies the PL3 duty cycle percentage, Range 0-100. Default: 0. >=20 > + UINT32 PowerLimit3Lock : 1; ///< Package PL3 MSR 6= 15h lock; > 0: Disable; 1: Enable (Lock). >=20 > + UINT32 PowerLimit4Lock : 1; ///< Package PL4 MSR 6= 01h lock; > 0: Disable; 1: Enable (Lock). >=20 > + /** >=20 > + Tcc Offset Clamp for Runtime Average Temperature Limit (RATL) allows > CPU to throttle below P1. >=20 > + For Y SKU, the recommended default for this policy is 1: Enabled, > which indicates throttling below P1 is allowed. >=20 > + For all other SKUs the recommended default are 0: Disabled. >=20 > + **/ >=20 > + UINT32 TccOffsetClamp : 1; >=20 > + UINT32 TccOffsetLock : 1; ///< Tcc Offset Lock f= or Runtime > Average Temperature Limit (RATL) to lock temperature target MSR 1A2h; 0: > Disabled; 1: Enabled (Lock). >=20 > + UINT32 TurboMode : 1; ///< Enable or Disable= Turbo Mode. > Disable; 1: Enable >=20 > + UINT32 HwpInterruptControl : 1; ///< Set HW P-State In= terrupts > Enabled for MISC_PWR_MGMT MSR 0x1AA[7]; 0: Disable; 1: > Enable. >=20 > + UINT32 ApplyConfigTdp : 1; ///< Switch TDP applie= d setting > based on non-cTDP or TDP; 0: non-cTDP; 1: cTDP. >=20 > + UINT32 HwpLock : 1; ///< HWP Lock in MISC = PWR MGMT > MSR 1AAh; 0: Disable; 1: Enable (Lock). >=20 > + UINT32 VccInDemotionOverride : 1; ///< Enable VccIn Demo= tion > Override configuration. 0: Disable; 1: Enable. >=20 > + UINT32 RsvdBits : 6; ///< Reserved for futu= re use. >=20 > + >=20 > + /** >=20 > + 1-Core Ratio Limit: LFM to Fused 1-Core Ratio Limit. For overclocking= parts: > LFM to Fused 1-Core Ratio Limit + OC Bins. >=20 > + Note: OC Bins =3D 7 means fully unlocked, so range is LFM to 83. >=20 > + - This 1-Core Ratio Limit Must be greater than or equal to 2-Core R= atio > Limit, 3-Core Ratio Limit, 4-Core Ratio Limit. >=20 > + **/ >=20 > + UINT8 OneCoreRatioLimit; >=20 > + /** >=20 > + 2-Core Ratio Limit: LFM to Fused 2-Core Ratio Limit, For overclocking= part: > LFM to Fused 2-Core Ratio Limit + OC Bins. >=20 > + Note: OC Bins =3D 7 means fully unlocked, so range is LFM to 83. >=20 > + - This 2-Core Ratio Limit Must be Less than or equal to 1-Core Rati= o Limit. >=20 > + **/ >=20 > + UINT8 TwoCoreRatioLimit; >=20 > + /** >=20 > + 3-Core Ratio Limit: LFM to Fused 3-Core Ratio Limit, For overclocking= part: > LFM to Fused 3-Core Ratio Limit + OC Bins. >=20 > + Note: OC Bins =3D 7 means fully unlocked, so range is LFM to 83. >=20 > + - This 3-Core Ratio Limit Must be Less than or equal to 1-Core Rati= o Limit. >=20 > + **/ >=20 > + UINT8 ThreeCoreRatioLimit; >=20 > + /** >=20 > + 4-Core Ratio Limit: LFM to Fused 4-Core Ratio Limit, For overclocking= part: > LFM to Fused 4-Core Ratio Limit + OC Bins. >=20 > + Note: OC Bins =3D 7 means fully unlocked, so range is LFM to 83. >=20 > + - This 4-Core Ratio Limit Must be Less than or equal to 1-Core Rati= o Limit. >=20 > + **/ >=20 > + UINT8 FourCoreRatioLimit; >=20 > + /** >=20 > + 5-Core Ratio Limit: LFM to Fused 5-Core Ratio Limit, For overclocking= part: > LFM to Fused 5-Core Ratio Limit + OC Bins. >=20 > + Note: OC Bins =3D 7 means fully unlocked, so range is LFM to 83. >=20 > + - This 5-Core Ratio Limit Must be Less than or equal to 1-Core Rati= o Limit. >=20 > + **/ >=20 > + UINT8 FiveCoreRatioLimit; >=20 > + /** >=20 > + 6-Core Ratio Limit: LFM to Fused 6-Core Ratio Limit, For overclocking= part: > LFM to Fused 6-Core Ratio Limit + OC Bins. >=20 > + Note: OC Bins =3D 7 means fully unlocked, so range is LFM to 83. >=20 > + - This 6-Core Ratio Limit Must be Less than or equal to 1-Core Rati= o Limit. >=20 > + **/ >=20 > + UINT8 SixCoreRatioLimit; >=20 > + /** >=20 > + 7-Core Ratio Limit: LFM to Fused 7-Core Ratio Limit, For overclocking= part: > LFM to Fused 7-Core Ratio Limit + OC Bins. >=20 > + Note: OC Bins =3D 7 means fully unlocked, so range is LFM to 83. >=20 > + - This 7-Core Ratio Limit Must be Less than or equal to 1-Core Rati= o Limit. >=20 > + **/ >=20 > + UINT8 SevenCoreRatioLimit; >=20 > + /** >=20 > + 8-Core Ratio Limit: LFM to Fused 8-Core Ratio Limit, For overclocking= part: > LFM to Fused 8-Core Ratio Limit + OC Bins. >=20 > + Note: OC Bins =3D 7 means fully unlocked, so range is LFM to 83. >=20 > + - This 8-Core Ratio Limit Must be Less than or equal to 1-Core Rati= o Limit. >=20 > + **/ >=20 > + UINT8 EightCoreRatioLimit; >=20 > + /** >=20 > + TCC Activation Offset. Offset from factory set TCC activation temperat= ure > at which the Thermal Control Circuit must be activated. >=20 > + TCC will be activated at (TCC Activation Temperature - TCC Activation > Offset), in degrees Celcius. >=20 > + For Y SKU, the recommended default for this policy is 10 >=20 > + For all other SKUs the recommended default are 0, causing TCC t= o > activate at TCC Activation temperature. >=20 > + @note The policy is recommended for validation purpose only. >=20 > + **/ >=20 > + UINT8 TccActivationOffset; >=20 > + /** >=20 > + Intel Turbo Boost Max Technology 3.0 >=20 > + Enabling it on processors with OS support will allow OS to exploit the > diversity in max turbo frequency of the cores. >=20 > + 0: Disable; 1: Enable; >=20 > + **/ >=20 > + UINT8 EnableItbm : 1; >=20 > + /** >=20 > + @deprecated: Platform doesn't have Intel Turbo Boost Max Technology > 3.0 Driver >=20 > + Enabling it will load the driver upon ACPI device with HID =3D INT3510= . >=20 > + 0: Disable; 1: Enable; >=20 > + **/ >=20 > + UINT8 EnableItbmDriver : 1; >=20 > + /** >=20 > + Per Core P State OS control mode >=20 > + Disabling will set PCU_MISC_CONFIG (Command 0x06) Bit 31 =3D 1. When > set, the highest core request is used for all other core requests. >=20 > + 0: Disable; 1: Enable; >=20 > + **/ >=20 > + UINT8 EnablePerCorePState : 1; >=20 > + /** >=20 > + HwP Autonomous Per Core P State >=20 > + Disabling will set Bit 30 =3D 1, command 0x11. When set, autonomous wi= ll > request the same value >=20 > + for all cores all the time. >=20 > + 0: Disable; 1: Enable; >=20 > + **/ >=20 > + UINT8 EnableHwpAutoPerCorePstate : 1; >=20 > + /** >=20 > + HwP Autonomous EPP grouping. >=20 > + Disabling will set Bit 29 =3D 1, command 0x11. When set, autonomous wi= ll not > necesarrily request the same value >=20 > + for all cores with same EPP. >=20 > + Enabling will clean Bit 29 =3D 0, command 0x11. Autonomous will reques= t > same values for all cores with same EPP. >=20 > + 0: Disable; 1: Enable; >=20 > + **/ >=20 > + UINT8 EnableHwpAutoEppGrouping : 1; >=20 > + /** >=20 > + EPB override over PECI >=20 > + Enable by sending pcode command 0x2b , subcommand 0x3 to 1. >=20 > + This will allow OOB EPB PECI override control. >=20 > + 0: Disable; 1: Enable; >=20 > + **/ >=20 > + UINT8 EnableEpbPeciOverride : 1; >=20 > + /** >=20 > + Support for Fast MSR for IA32_HWP_REQUEST. >=20 > + On systems with HwP enabled, if this feature is available as indicated= by > MSR 0x65F[0] =3D 1, >=20 > + set MSR 0x657[0] =3D 1. >=20 > + 0: Disable; 1: Enable; >=20 > + **/ >=20 > + UINT8 EnableFastMsrHwpReq : 1; >=20 > + UINT8 ReservedBits1 : 1; ///< Reserved for futu= re use. >=20 > + UINT8 MinRingRatioLimit; ///< Minimum Ring Rati= o Limit. Range > from 0 to Max Turbo Ratio. 0 =3D AUTO/HW Default >=20 > + UINT8 MaxRingRatioLimit; ///< Maximum Ring Rati= o Limit. > Range from 0 to Max Turbo Ratio. 0 =3D AUTO/HW Default >=20 > + /** >=20 > + Package Long duration turbo mode power limit (PL1). >=20 > + Default is the TDP power limit of processor. Units are based on > POWER_MGMT_CONFIG.CustomPowerUnit. >=20 > + **/ >=20 > + UINT16 PowerLimit1; >=20 > + /** >=20 > + Package Short duration turbo mode power limit (PL2). Allows for short > excursions above TDP power limit. >=20 > + Default =3D 1.25 * TDP Power Limit. Units are based on > POWER_MGMT_CONFIG.CustomPowerUnit. >=20 > + **/ >=20 > + UINT16 PowerLimit2Power; >=20 > + /** >=20 > + Package PL3 power limit. PL3 is the CPU Peak Power Occurences Limit. >=20 > + Default: 0. Range 0-65535. Units are based on > POWER_MGMT_CONFIG.CustomPowerUnit. >=20 > + **/ >=20 > + UINT16 PowerLimit3; >=20 > + /** >=20 > + Package PL4 power limit. PL4 is a Preemptive CPU Package Peak Power > Limit, it will never be exceeded. >=20 > + Power is premptively lowered before limit is reached. Default: 0. > Range 0-65535. >=20 > + Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. >=20 > + **/ >=20 > + UINT16 PowerLimit4; >=20 > + /** >=20 > + Package Long duration turbo mode power limit (PL1) time window in > seconds. >=20 > + Used in calculating the average power over time. >=20 > + Mobile: 28s >=20 > + Desktop: 8s >=20 > + Range: 0 - 128s >=20 > + **/ >=20 > + UINT32 PowerLimit1Time; >=20 > + UINT32 PowerLimit3Time; ///< Package PL3 time = window. > Range from 3ms to 64ms. >=20 > + /** >=20 > + Tcc Offset Time Window can range from 5ms to 448000ms for Runtime > Average Temperature Limit (RATL). >=20 > + For Y SKU, the recommended default for this policy is 5000: 5 > seconds, For all other SKUs the recommended default are 0: > Disabled >=20 > + **/ >=20 > + UINT32 TccOffsetTimeWindowForRatl; >=20 > + /** >=20 > + Customize the VccIn Demotion in ms accordingly. Values used by OEM > expected to be in lower end of 1-30 ms range. >=20 > + Value 1 means 1ms, value 2 means 2ms, and so on. Value 0 will disable > VccIn Demotion knob. >=20 > + It's 30ms by silicon default. >=20 > + **/ >=20 > + UINT32 VccInDemotionMs; >=20 > +} CPU_POWER_MGMT_BASIC_CONFIG; >=20 > + >=20 > +#pragma pack (pop) >=20 > + >=20 > +#endif // _CPU_POWER_MGMT_BASIC_CONFIG_H_ >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPowerMgm > tCustomConfig.h > b/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPowerMgm > tCustomConfig.h > new file mode 100644 > index 0000000000..e1a5bcc684 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPowerMgm > tCustomConfig.h > @@ -0,0 +1,76 @@ > +/** @file >=20 > + CPU Power Managment Custom Config Block. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _CPU_POWER_MGMT_CUSTOM_CONFIG_H_ >=20 > +#define _CPU_POWER_MGMT_CUSTOM_CONFIG_H_ >=20 > + >=20 > +#define CPU_POWER_MGMT_CUSTOM_CONFIG_REVISION 1 >=20 > + >=20 > +extern EFI_GUID gCpuPowerMgmtCustomConfigGuid; >=20 > + >=20 > +#pragma pack (push,1) >=20 > + >=20 > +/// >=20 > +/// Defines the maximum number of custom ratio states supported. >=20 > +/// >=20 > +#define MAX_CUSTOM_RATIO_TABLE_ENTRIES 40 >=20 > +#define MAX_16_CUSTOM_RATIO_TABLE_ENTRIES 16 >=20 > + >=20 > +/// >=20 > +/// Defines the maximum number of custom ConfigTdp entries supported. >=20 > +/// @warning: Changing this define would cause DWORD alignment issues > in policy structures. >=20 > +/// >=20 > +#define MAX_CUSTOM_CTDP_ENTRIES 3 >=20 > + >=20 > +/// >=20 > +/// This structure is used to describe the custom processor ratio table > desired by the platform. >=20 > +/// >=20 > +typedef struct { >=20 > + UINT8 MaxRatio; ///< The ma= ximum ratio of the > custom ratio table. >=20 > + UINT8 NumberOfEntries; ///< The nu= mber of custom > ratio state entries, ranges from 2 to 40 for a valid custom ratio table. >=20 > + UINT8 Rsvd0[2]; ///< Reserv= ed for DWORD > alignment. >=20 > + UINT32 Cpuid; ///< The CP= U ID for which this custom > ratio table applies. >=20 > + UINT8 StateRatio[MAX_CUSTOM_RATIO_TABLE_ENTRIES]; ///< The > processor ratios in the custom ratio table. >=20 > + /// >=20 > + /// If there are more than 16 total entries in the StateRatio table, t= hen use > these 16 entries to fill max 16 table. >=20 > + /// @note If NumberOfEntries is 16 or less, or the first entry of this= table is > 0, then this table is ignored, >=20 > + /// and up to the top 16 values from the StateRatio table is used inst= ead. >=20 > + /// >=20 > + UINT8 StateRatioMax16[MAX_16_CUSTOM_RATIO_TABLE_ENTRIES]; >=20 > +#if ((MAX_CUSTOM_RATIO_TABLE_ENTRIES + > MAX_16_CUSTOM_RATIO_TABLE_ENTRIES) % 4) >=20 > + UINT8 Rsvd1[4 - ((MAX_CUSTOM_RATIO_TABLE_ENTRIES + > MAX_16_CUSTOM_RATIO_TABLE_ENTRIES) % 4)]; ///< If needed, add > padding for dword alignment. >=20 > +#endif >=20 > +} PPM_CUSTOM_RATIO_TABLE; >=20 > + >=20 > +/// >=20 > +/// PPM Custom ConfigTdp Settings >=20 > +/// >=20 > +typedef struct _PPM_CUSTOM_CTDP_TABLE { >=20 > + UINT32 CustomPowerLimit1Time : 8; ///< Short term Pow= er Limit > time window value for custom cTDP level. >=20 > + UINT32 CustomTurboActivationRatio : 8; ///< Turbo Activati= on Ratio > for custom cTDP level. >=20 > + UINT32 RsvdBits : 16; ///< Bits reserved = for DWORD > alignment. >=20 > + UINT16 CustomPowerLimit1; ///< Short term Pow= er Limit > value for custom cTDP level. Units are based on > POWER_MGMT_CONFIG.CustomPowerUnit. >=20 > + UINT16 CustomPowerLimit2; ///< Long term Powe= r Limit value > for custom cTDP level. Units are based on > POWER_MGMT_CONFIG.CustomPowerUnit. >=20 > +} PPM_CUSTOM_CTDP_TABLE; >=20 > + >=20 > +/** >=20 > + CPU Power Management Custom Configuration Structure. >=20 > + >=20 > + Revision 1: >=20 > + - Initial version. >=20 > +**/ >=20 > +typedef struct { >=20 > + CONFIG_BLOCK_HEADER Header; = ///< Config > Block Header >=20 > + PPM_CUSTOM_RATIO_TABLE CustomRatioTable; = ///< > Custom Processor Ratio Table Instance >=20 > + PPM_CUSTOM_CTDP_TABLE > CustomConfigTdpTable[MAX_CUSTOM_CTDP_ENTRIES]; ///< Custom > ConfigTdp Settings Instance >=20 > + UINT32 ConfigTdpLock : 1; = ///< Lock the > ConfigTdp mode settings from runtime changes; 0: Disable; 1: > Enable. >=20 > + UINT32 ConfigTdpBios : 1; = ///< Configure > whether to load Configurable TDP SSDT; 0: Disable; 1: Enable. >=20 > + UINT32 RsvdBits : 30; = ///< Reserved for future > use >=20 > +} CPU_POWER_MGMT_CUSTOM_CONFIG; >=20 > + >=20 > +#pragma pack (pop) >=20 > + >=20 > +#endif // _CPU_POWER_MGMT_CUSTOM_CONFIG_H_ >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPowerMgm > tPsysConfig.h > b/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPowerMgm > tPsysConfig.h > new file mode 100644 > index 0000000000..f1ceb8f43b > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPowerMgm > tPsysConfig.h > @@ -0,0 +1,36 @@ > +/** @file >=20 > + CPU Power Management Psys(Platform) Config Block. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _CPU_POWER_MGMT_PSYS_CONFIG_H_ >=20 > +#define _CPU_POWER_MGMT_PSYS_CONFIG_H_ >=20 > + >=20 > +#define CPU_POWER_MGMT_PSYS_CONFIG_REVISION 1 >=20 > + >=20 > +extern EFI_GUID gCpuPowerMgmtPsysConfigGuid; >=20 > + >=20 > +#pragma pack (push,1) >=20 > + >=20 > +/** >=20 > + CPU Power Management Psys(Platform) Configuration Structure. >=20 > + >=20 > + Revision 1: >=20 > + - Initial version. >=20 > +**/ >=20 > +typedef struct { >=20 > + CONFIG_BLOCK_HEADER Header; ///< Config Block Head= er >=20 > + UINT32 PsysPowerLimit1 : 1; ///< MSR 0x65C[15]: PL= 1 Enable > activates the PL1 value to limit average platform power >=20 > + UINT32 PsysPowerLimit1Time : 8; ///< MSR 0x65C[23:17]:= PL1 > timewindow in seconds. >=20 > + UINT32 PsysPowerLimit2 : 1; ///< MSR 0x65C[47]: PL= 2 Enable > activates the PL2 value to limit average platform power >=20 > + UINT32 RsvdBits : 22; ///< Reserved for futu= re use. >=20 > + UINT16 PsysPowerLimit1Power; ///< MSR 0x65C[14:0]: = Platform > PL1 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. >=20 > + UINT16 PsysPowerLimit2Power; ///< MSR 0x65C[46:32]]= : > Platform PL2 power. Units are based on > POWER_MGMT_CONFIG.CustomPowerUnit. >=20 > + UINT16 PsysPmax; ///< PCODE MMIO Mailbo= x: Platform > Power Pmax. 0 - Auto Specified in 1/8 Watt increments. 0-1024 > Watts. Value of 800 =3D 100W. >=20 > + UINT8 Rsvd[2]; ///< Reserved for futu= re use and config > block alignment >=20 > +} CPU_POWER_MGMT_PSYS_CONFIG; >=20 > + >=20 > +#pragma pack (pop) >=20 > + >=20 > +#endif // _CPU_POWER_MGMT_PSYS_CONFIG_H_ >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPowerMgm > tTestConfig.h > b/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPowerMgm > tTestConfig.h > new file mode 100644 > index 0000000000..bd641f27c5 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPowerMgm > tTestConfig.h > @@ -0,0 +1,150 @@ > +/** @file >=20 > + CPU Power Management Test Config Block. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _CPU_POWER_MGMT_TEST_CONFIG_H_ >=20 > +#define _CPU_POWER_MGMT_TEST_CONFIG_H_ >=20 > + >=20 > +#define CPU_POWER_MGMT_TEST_CONFIG_REVISION 4 >=20 > + >=20 > +extern EFI_GUID gCpuPowerMgmtTestConfigGuid; >=20 > + >=20 > +#pragma pack (push,1) >=20 > + >=20 > +/// >=20 > +/// PPM Package C State Limit >=20 > +/// >=20 > +typedef enum { >=20 > + PkgC0C1 =3D 0, >=20 > + PkgC2, >=20 > + PkgC3, >=20 > + PkgC6, >=20 > + PkgC7, >=20 > + PkgC7s, >=20 > + PkgC8, >=20 > + PkgC9, >=20 > + PkgC10, >=20 > + PkgCMax, >=20 > + PkgCpuDefault =3D 254, >=20 > + PkgAuto =3D 255 >=20 > +} MAX_PKG_C_STATE; >=20 > + >=20 > +/// >=20 > +/// PPM Package C State Time Limit >=20 > +/// >=20 > +typedef enum { >=20 > + TimeUnit1ns =3D 0, >=20 > + TimeUnit32ns, >=20 > + TimeUnit1024ns, >=20 > + TimeUnit32768ns, >=20 > + TimeUnit1048576ns, >=20 > + TimeUnit33554432ns, >=20 > + TimeUnitMax >=20 > +} C_STATE_TIME_UNIT; >=20 > + >=20 > +/// >=20 > +/// Custom Power Units. User can choose to enter in watts or 125 milliwa= tt > increments. >=20 > +/// >=20 > +typedef enum { >=20 > + PowerUnitWatts =3D 0, ///< in Watts. >=20 > + PowerUnit125MilliWatts, ///< in 125 milliwatt increments. Example: 90 > power units times 125 mW equals 11.250 W. >=20 > + PowerUnitMax >=20 > +} CUSTOM_POWER_UNIT; >=20 > + >=20 > +/// >=20 > +/// PPM Interrupt Redirection Mode Selection >=20 > +/// >=20 > +typedef enum { >=20 > + PpmIrmFixedPriority =3D 0, >=20 > + PpmIrmRoundRobin, >=20 > + PpmIrmHashVector, >=20 > + PpmIrmReserved1, >=20 > + PpmIrmReserved2, >=20 > + PpmIrmReserved3, >=20 > + PpmIrmReserved4, >=20 > + PpmIrmNoChange >=20 > +} PPM_IRM_SETTING; >=20 > + >=20 > +/** >=20 > + CPU Power Management Test Configuration Structure. >=20 > + >=20 > + Revision 1: >=20 > + - Initial version. >=20 > + Revision 2: >=20 > + - Add CstateLatencyControl0TimeUnit for WHL only >=20 > + - Add CstateLatencyControl0Irtl for WHL only >=20 > + Revision 3: >=20 > + - Change C State LatencyContol to Auto as default. >=20 > + Revision 4: >=20 > + - Deprecate ConfigTdpLevel. Move to premem. >=20 > +**/ >=20 > +typedef struct { >=20 > + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Con= fig Block > Header >=20 > + UINT32 Eist : 1; ///< Offset 28-31 Ena= ble or Disable Intel > SpeedStep Technology. 0: Disable; 1: Enable >=20 > + UINT32 EnergyEfficientPState : 1; ///< Ena= ble or Disable > Energy Efficient P-state will be applied in Turbo mode. Disable; 1: > Enable >=20 > + UINT32 EnergyEfficientTurbo : 1; ///< Ena= ble or Disable > Energy Efficient Turbo, will be applied in Turbo mode. Disable; 1: > Enable >=20 > + UINT32 TStates : 1; ///< Ena= ble or Disable T states; > 0: Disable; 1: Enable. >=20 > + UINT32 BiProcHot : 1; ///< Ena= ble or Disable Bi- > Directional PROCHOT#; 0: Disable; 1: Enable. >=20 > + UINT32 DisableProcHotOut : 1; ///< Ena= ble or Disable > PROCHOT# signal being driven externally; 0: Disable; 1: Enable. >=20 > + UINT32 ProcHotResponse : 1; ///< Ena= ble or Disable > PROCHOT# Response; 0: Disable; 1: Enable. >=20 > + UINT32 DisableVrThermalAlert : 1; ///< Ena= ble or Disable VR > Thermal Alert; 0: Disable; 1: Enable. >=20 > + UINT32 EnableAllThermalFunctions : 1; ///< Ena= ble or Disable > Thermal Reporting through ACPI tables; 0: Disable; 1: Enable. >=20 > + UINT32 ThermalMonitor : 1; ///< Ena= ble or Disable > Thermal Monitor; 0: Disable; 1: Enable. >=20 > + UINT32 Cx : 1; ///< Ena= ble or Disable CPU power > states (C-states). 0: Disable; 1: Enable >=20 > + UINT32 PmgCstCfgCtrlLock : 1; ///< If = enabled, sets MSR > 0xE2[15]; 0: Disable; 1: Enable. >=20 > + UINT32 C1e : 1; ///< Ena= ble or Disable Enhanced C- > states. 0: Disable; 1: Enable >=20 > + UINT32 C1AutoDemotion : 1; ///< Ena= ble or Disable C6/C7 > auto demotion to C1. 0: Disabled; 1: C1 Auto demotion >=20 > + UINT32 C1UnDemotion : 1; ///< Ena= ble or Disable > C1UnDemotion. 0: Disabled; 1: C1 Auto undemotion >=20 > + UINT32 C3AutoDemotion : 1; ///< [Co= ffeeLake Only] > Enable or Disable C6/C7 auto demotion to C3 0: Disabled; 1: C3 Auto > demotion >=20 > + UINT32 C3UnDemotion : 1; ///< [Co= ffeeLake Only] > Enable or Disable C3UnDemotion. 0: Disabled; 1: C3 Auto > undemotion >=20 > + UINT32 PkgCStateDemotion : 1; ///< Ena= ble or Disable > Package Cstate Demotion. Disable; 1: Enable [WhiskeyLake] > Disable; 1: Enable >=20 > + UINT32 PkgCStateUnDemotion : 1; ///< Ena= ble or Disable > Package Cstate UnDemotion. Disable; 1: Enable [WhiskeyLake] > Disable; 1: Enable >=20 > + UINT32 CStatePreWake : 1; ///< Ena= ble or Disable > CState-Pre wake. Disable; 1: Enable >=20 > + UINT32 TimedMwait : 1; ///< Ena= ble or Disable > TimedMwait Support. Disable; 1: Enable >=20 > + UINT32 CstCfgCtrIoMwaitRedirection : 1; ///< Ena= ble or Disable > IO to MWAIT redirection; 0: Disable; 1: Enable. >=20 > + UINT32 ProcHotLock : 1; ///< If = enabled, sets MSR > 0x1FC[23]; 0: Disable; 1: Enable. >=20 > + UINT32 RaceToHalt : 1; ///< Ena= ble or Disable Race To > Halt feature; 0: Disable; 1: Enable . RTH will dynamically increas= e CPU > frequency in order to enter pkg C-State faster to reduce overall power. (= RTH > is controlled through MSR 1FC bit 20) >=20 > + UINT32 ConfigTdpLevel : 8; ///< @de= precated. Move to > premem phase. >=20 > + UINT16 CstateLatencyControl1Irtl; ///< Offset 32-33 Int= errupt > Response Time Limit of LatencyContol1 MSR 0x60B[9:0].0 is Auto. >=20 > + UINT16 CstateLatencyControl2Irtl; ///< Offset 34-35 Int= errupt > Response Time Limit of LatencyContol2 MSR 0x60C[9:0].0 is Auto. >=20 > + UINT16 CstateLatencyControl3Irtl; ///< Offset 36-37 Int= errupt > Response Time Limit of LatencyContol3 MSR 0x633[9:0].0 is Auto. >=20 > + UINT16 CstateLatencyControl4Irtl; ///< Offset 38-39 Int= errupt > Response Time Limit of LatencyContol4 MSR 0x634[9:0].0 is Auto. >=20 > + UINT16 CstateLatencyControl5Irtl; ///< Offset 40-41 Int= errupt > Response Time Limit of LatencyContol5 MSR 0x635[9:0].0 is Auto. >=20 > + // Due to the removal of CstateLatencyControl0Irtl, PkgCStateLimit is = not > aligned to 32-bit address. >=20 > + UINT8 Rsvd1[2]; ///< Offset 42-43 Res= erved for config > block alignment. >=20 > + MAX_PKG_C_STATE PkgCStateLimit; ///< Offset 44 Thi= s field is > used to set the Max Pkg Cstate. Default set to Auto which limits the Max = Pkg > Cstate to deep C-state. >=20 > + /** >=20 > + @todo: The following enums have to be replaced with policies. >=20 > + **/ >=20 > + C_STATE_TIME_UNIT Reserved; ///< Offset 45 Res= erved for > config block alignment. >=20 > + C_STATE_TIME_UNIT CstateLatencyControl1TimeUnit; ///< Offset 46 > TimeUnit for Latency Control1 MSR 0x60B[12:10]; 2: 1024ns. >=20 > + C_STATE_TIME_UNIT CstateLatencyControl2TimeUnit; ///< Offset 47 > TimeUnit for Latency Control2 MSR 0x60C[12:10]; 2: 1024ns. >=20 > + C_STATE_TIME_UNIT CstateLatencyControl3TimeUnit; ///< Offset 48 > TimeUnit for Latency Control3 MSR 0x633[12:10]; 2: 1024ns. >=20 > + C_STATE_TIME_UNIT CstateLatencyControl4TimeUnit; ///< Offset 49 > TimeUnit for Latency Control4 MSR 0x634[12:10]; 2: 1024ns. >=20 > + C_STATE_TIME_UNIT CstateLatencyControl5TimeUnit; ///< Offset 50 > TimeUnit for Latency Control5 MSR 0x635[12:10]; 2: 1024ns. >=20 > + /** >=20 > + Offset 51 Default power unit in watts or in 125 milliwatt increments. >=20 > + - 0: PowerUnitWatts. >=20 > + - 1: PowerUnit125MilliWatts. >=20 > + **/ >=20 > + CUSTOM_POWER_UNIT CustomPowerUnit; >=20 > + /** >=20 > + Offset 52 Interrupt Redirection Mode Select. >=20 > + - 0: Fixed priority. //Default under CNL. >=20 > + - 1: Round robin. >=20 > + - 2: Hash vector. >=20 > + - 4: PAIR with fixed priority. //Default under KBL, not available u= nder CNL. >=20 > + - 5: PAIR with round robin. //Not available under CNL. >=20 > + - 6: PAIR with hash vector. //Not available under CNL. >=20 > + - 7: No change. >=20 > + **/ >=20 > + PPM_IRM_SETTING PpmIrmSetting; >=20 > + // Move the padding to previous offset to align the structure at 32-bi= t > address. >=20 > + UINT8 Rsvd[4]; ///< Offset 53-56 Rese= rved for future use > and config block alignment >=20 > +} CPU_POWER_MGMT_TEST_CONFIG; >=20 > + >=20 > +#pragma pack (pop) >=20 > + >=20 > +#endif // _CPU_POWER_MGMT_TEST_CONFIG_H_ >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuSecurityPr= e > MemConfig.h > b/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuSecurityPr= e > MemConfig.h > new file mode 100644 > index 0000000000..24614fe497 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuSecurityPr= e > MemConfig.h > @@ -0,0 +1,63 @@ > +/** @file >=20 > + CPU Security PreMemory Config Block. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _CPU_SECURITY_PREMEM_CONFIG_H_ >=20 > +#define _CPU_SECURITY_PREMEM_CONFIG_H_ >=20 > + >=20 > +#define CPU_SECURITY_PREMEM_CONFIG_REVISION 1 >=20 > + >=20 > +extern EFI_GUID gCpuSecurityPreMemConfigGuid; >=20 > + >=20 > +#pragma pack (push,1) >=20 > + >=20 > +/** >=20 > + CPU Security PreMemory Configuration Structure. >=20 > + >=20 > + Revision 1: >=20 > + - Initial version. >=20 > +**/ >=20 > +typedef struct { >=20 > + CONFIG_BLOCK_HEADER Header; ///< Config Block Hea= der >=20 > + UINT32 PrmrrSize; ///< PRMRR Size.So= ftware Control: > 0x0 32MB: 0x2000000, 64MB: 0x4000000, 128 MB: 0x8000000, 256 MB: > 0x10000000, 512 MB: 0x20000000 >=20 > + UINT16 BiosSize; ///< Flash informatio= n for BIOS Guard: > BIOS Size in KB. >=20 > + UINT8 Reserved[2]; ///< Reserved for fut= ure use >=20 > +/** >=20 > + Enable or Disable BIOS Guard; 0: Disable; 1: Enable. >=20 > + - This is an optional feature and can be opted out. >=20 > + - If this policy is set to Disabled, the policies in the BIOS_GUARD_= CONFIG > will be ignored. >=20 > + - If PeiBiosGuardLibNull is used, this policy will have no effect. >=20 > +**/ >=20 > + UINT32 BiosGuard : 1; >=20 > + UINT32 BiosGuardToolsInterface : 1; ///< BIOS Guard Tool= s > Interface; 0: Disable, 1:Enable >=20 > +/** >=20 > + Enable or Disable Software Guard Extensions; 0: Disable; 1: > Enable. >=20 > + - This is an optional feature and can be opted out. >=20 > + - If this policy is set to Disabled, the policies in the CPU_SGX_CON= FIG will > be ignored. >=20 > + - If BaseSoftwareGuardLibNull is used, this policy will have no effe= ct. >=20 > +**/ >=20 > + UINT32 EnableSgx : 1; >=20 > +/** >=20 > + Enable or Disable Trusted Execution Technology; 0: Disable; 1: > Enable. >=20 > + - This is an optional feature and can be opted out. >=20 > + - If this policy is set to Disabled, the policies in the > CPU_TXT_PREMEM_CONFIG will be ignored. >=20 > + - If PeiTxtLibNull is used, this policy will have no effect. >=20 > +**/ >=20 > + UINT32 Txt : 1; >=20 > + UINT32 SkipStopPbet : 1; ///< (Test) S= kip Stop PBET > Timer; 0: Disable; 1: Enable. >=20 > + /// >=20 > + /// (Test) This policy indicates whether or not BIOS should all= ocate > PRMRR memory for C6DRAM power gating feature. >=20 > + /// - 0: Don't allocate any PRMRR memory for C6DRAM power gating > feature. >=20 > + /// - 1: Allocate PRMRR memory for C6DRAM power gating > feature. >=20 > + /// >=20 > + UINT32 EnableC6Dram : 1; >=20 > + UINT32 ResetAux : 1; ///< (Test) R= eset Auxiliary > content, 0: Disabled, 1: Enabled >=20 > + UINT32 TxtAcheckRequest : 1; ///< (Test) > AcheckRequest 0: Disabled, 1: Enabled. When Enabled, it will call > Acheck regardless of crashcode value >=20 > + UINT32 RsvdBits : 24; ///< Reserved for fu= ture use >=20 > +} CPU_SECURITY_PREMEM_CONFIG; >=20 > + >=20 > +#pragma pack (pop) >=20 > + >=20 > +#endif // _CPU_SECURITY_CONFIG_H_ >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuTestConfig= . > h > b/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuTestConfig= . > h > new file mode 100644 > index 0000000000..ee946290e0 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuTestConfig= . > h > @@ -0,0 +1,51 @@ > +/** @file >=20 > + CPU Test Config Block. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _CPU_TEST_CONFIG_H_ >=20 > +#define _CPU_TEST_CONFIG_H_ >=20 > + >=20 > +#define CPU_TEST_CONFIG_REVISION 2 >=20 > + >=20 > +extern EFI_GUID gCpuTestConfigGuid; >=20 > + >=20 > +#pragma pack (push,1) >=20 > + >=20 > +/** >=20 > + CPU Test Configuration Structure. >=20 > + >=20 > + Revision 1: >=20 > + - Initial version. >=20 > + Revision 2: >=20 > + - Removed Voltage Optimization feature. >=20 > +**/ >=20 > +typedef struct { >=20 > + CONFIG_BLOCK_HEADER Header; ///< Config Block Head= er >=20 > + UINT32 MlcStreamerPrefetcher : 1; ///< En= able or Disable > MLC Streamer Prefetcher; 0: Disable; 1: Enable. >=20 > + UINT32 MlcSpatialPrefetcher : 1; ///< En= able or Disable MLC > Spatial Prefetcher; 0: Disable; 1: Enable. >=20 > + UINT32 MonitorMwaitEnable : 1; ///< En= able or Disable > Monitor /MWAIT instructions; 0: Disable; 1: Enable. >=20 > + UINT32 MachineCheckEnable : 1; ///< En= able or Disable > initialization of machine check registers; 0: Disable; 1: Enable. >=20 > + UINT32 ProcessorTraceOutputScheme : 1; ///< Co= ntrol on > Processor Trace output scheme; 0: Single Range Output; 1: ToPA > Output. >=20 > + UINT32 ProcessorTraceEnable : 1; ///< En= able or Disable > Processor Trace feature; 0: Disable; 1: Enable. >=20 > + UINT32 ThreeStrikeCounterDisable : 1; ///< Di= sable Three > strike counter; 0: FALSE; 1: TRUE. >=20 > + UINT32 RsvdBits : 25; ///< R= eserved for future use >=20 > + /** >=20 > + Base address of memory region allocated for Processor Trace. >=20 > + Processor Trace requires 2^N alignment and size in bytes per thread= , > from 4KB to 128MB. >=20 > + - NULL: Disable >=20 > + **/ >=20 > + EFI_PHYSICAL_ADDRESS ProcessorTraceMemBase; >=20 > + /** >=20 > + Length in bytes of memory region allocated for Processor Trace. >=20 > + Processor Trace requires 2^N alignment and size in bytes per thread= , > from 4KB to 128MB. >=20 > + - 0: Disable >=20 > + **/ >=20 > + UINT32 ProcessorTraceMemLength; >=20 > + UINT8 Reserved0[4]; >=20 > +} CPU_TEST_CONFIG; >=20 > + >=20 > +#pragma pack (pop) >=20 > + >=20 > +#endif // _CPU_TEST_CONFIG_H_ >=20 > diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/CpuAccess.h > b/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/CpuAccess.h > new file mode 100644 > index 0000000000..5d5e4df071 > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/CpuAccess.h > @@ -0,0 +1,12 @@ > +/** @file >=20 > + Macros to simplify and abstract the interface to CPU configuration. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _CPUACCESS_H_ >=20 > +#define _CPUACCESS_H_ >=20 > + >=20 > +#include "CpuDataStruct.h" >=20 > + >=20 > +#endif >=20 > diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/CpuDataStruct.= h > b/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/CpuDataStruct.h > new file mode 100644 > index 0000000000..ba9a840e54 > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/CpuDataStruct.h > @@ -0,0 +1,21 @@ > +/** @file >=20 > + This file declares various data structures used in CPU reference code. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +#ifndef _CPU_DATA_STRUCT_H >=20 > +#define _CPU_DATA_STRUCT_H >=20 > + >=20 > +/// >=20 > +/// Structure to hold the return value of AsmCpuid instruction >=20 > +/// >=20 > +typedef struct { >=20 > + UINT32 RegEax; ///< Value of EAX. >=20 > + UINT32 RegEbx; ///< Value of EBX. >=20 > + UINT32 RegEcx; ///< Value of ECX. >=20 > + UINT32 RegEdx; ///< Value of EDX. >=20 > +} EFI_CPUID_REGISTER; >=20 > + >=20 > +#endif >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/CpuPolicyCommon.h > b/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/CpuPolicyCommon.h > new file mode 100644 > index 0000000000..1178f68d0c > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/CpuPolicyCommon.h > @@ -0,0 +1,23 @@ > +/** @file >=20 > + CPU Policy Structure definition which will contain several config bloc= ks > during runtime. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _CPU_POLICY_COMMON_H_ >=20 > +#define _CPU_POLICY_COMMON_H_ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +#endif // _CPU_POLICY_COMMON_H_ >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/Register/CommonMsr.h > b/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/Register/CommonMsr.h > new file mode 100644 > index 0000000000..a2cd1db1d6 > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/Register/CommonMsr.h > @@ -0,0 +1,18 @@ > + >=20 > +/** @file >=20 > + CommonMsr.h >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +#ifndef _COMMONMSR_h >=20 > +#define _COMMONMSR_h >=20 > +#include >=20 > + >=20 > +/** >=20 > + Special Chipset Usage MSR >=20 > +**/ >=20 > +#define MSR_SPCL_CHIPSET_USAGE 0x000001FE >=20 > + >=20 > +#endif /* _COMMONMSR_h */ >=20 > -- > 2.24.0.windows.2