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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Nate DeSimone > -----Original Message----- > From: Luo, Heng > Sent: Sunday, January 31, 2021 5:36 PM > To: devel@edk2.groups.io > Cc: Chaganty, Rangasai V ; Desimone, > Nathaniel L > Subject: [PATCH 07/40] TigerlakeSiliconPkg/SystemAgent: Add include > headers >=20 > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3171 >=20 > Adds the following header files: > * SystemAgent/Include >=20 > Cc: Sai Chaganty > Cc: Nate DeSimone > Signed-off-by: Heng Luo > --- >=20 > Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/ConfigBlock/Memory > DxeConfig.h | 123 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/ConfigBlock/PcieDxe > Config.h | 114 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/ConfigBlock/PramPre > MemConfig.h | 34 ++++++++++++++++++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/ConfigBlock/SaMiscP > eiConfig.h | 24 ++++++++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/ConfigBlock/SaMiscP > eiPreMemConfig.h | 104 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/Library/SaPlatformL= ib > .h | 48 ++++++++++++++++++++++++++++++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/MemInfoHob.h > | 264 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/Protocol/SaPolicy.= h > | 61 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++ > 8 files changed, 772 insertions(+) >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/ConfigBlock/Memo > ryDxeConfig.h > b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/ConfigBlock/Memo > ryDxeConfig.h > new file mode 100644 > index 0000000000..451e295b49 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/ConfigBlock/Memo > ryDxeConfig.h > @@ -0,0 +1,123 @@ > +/** @file >=20 > + Memory DXE Policy definitions >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _MEMORY_DXE_CONFIG_H_ >=20 > +#define _MEMORY_DXE_CONFIG_H_ >=20 > + >=20 > +#pragma pack(push, 1) >=20 > + >=20 > +#define MEMORY_DXE_CONFIG_REVISION 1 >=20 > + >=20 > +typedef struct _MEMORY_DXE_CONFIG MEMORY_DXE_CONFIG; >=20 > + >=20 > +/** >=20 > + Retrieves the OEM custom string for the SMBIOS Type 17 Table > DeviceLocator field. >=20 > + Implementation of this function is optional, if this function pointer = is NULL > then >=20 > + the reference implementation of DeviceLocator will be used. >=20 > + >=20 > + @param[in] This A pointer to this instance o= f > MEMORY_DXE_CONFIG. >=20 > + @param[in] Controller Desired Controller to get a = DeviceLocator > string for. >=20 > + @param[in] Dimm Desired DIMM to get a Device= Locator > string for. >=20 > + @param[in] MdSocket 0 =3D Memory Down, 1 =3D Soc= keted. >=20 > + >=20 > + @retval The DeviceLocator string >=20 > + @retval NULL If the return value is NULL,= the default value > will be used. >=20 > +**/ >=20 > +typedef >=20 > +CHAR8* >=20 > +(EFIAPI *MEMORY_DXE_CONFIG_GET_DEVICE_LOCATOR_STRING)( >=20 > + IN CONST MEMORY_DXE_CONFIG *This, >=20 > + IN UINT8 Controller, >=20 > + IN UINT8 Dimm, >=20 > + IN UINT8 MdSocket >=20 > + ); >=20 > + >=20 > +/** >=20 > + Retrieves the OEM custom string for the SMBIOS Type 17 Table > BankLocator field. >=20 > + Implementation of this function is optional, if this function pointer = is NULL > then >=20 > + the reference implementation of DeviceLocator will be used. >=20 > + >=20 > + @param[in] This A pointer to this instance o= f > MEMORY_DXE_CONFIG. >=20 > + @param[in] Controller Desired Controller to get a = BankLocator > string for. >=20 > + @param[in] Dimm Desired DIMM to get a BankLo= cator string > for. >=20 > + @param[in] MdSocket 0 =3D Memory Down, 1 =3D Soc= keted. >=20 > + >=20 > + @retval The BankLocator string >=20 > + @retval NULL If the return value is NULL,= the default value > will be used. >=20 > +**/ >=20 > +typedef >=20 > +CHAR8* >=20 > +(EFIAPI *MEMORY_DXE_CONFIG_GET_BANK_LOCATOR_STRING)( >=20 > + IN CONST MEMORY_DXE_CONFIG *This, >=20 > + IN UINT8 Controller, >=20 > + IN UINT8 Dimm, >=20 > + IN UINT8 MdSocket >=20 > + ); >=20 > + >=20 > +/** >=20 > + The Memory Configuration includes DIMM SPD address Map and DIMM > Slot Mechanical present bit map. >=20 > + The data elements should be initialized by a Platform Module.\n >=20 > + Revision 1: >=20 > + - Initial version. >=20 > +**/ >=20 > +struct _MEMORY_DXE_CONFIG { >=20 > + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27: Conf= ig Block > Header >=20 > +/** >=20 > + Offset 28: >=20 > + Dimm SPD address >=20 > + Only Server support 2 channels * 3 slots per channel =3D 6 sockets tot= ally >=20 > + The Desktop and mobile only support 2 channels * 2 slots per channel = =3D 4 > sockets totally >=20 > + So there is mapping rule here for Desktop and mobile that there are no > more 4 DIMMS totally in a system: >=20 > + Channel A/ Slot 0 --> Dimm 0 --> SpdAddressTable[0] >=20 > + Channel A/ Slot 1 --> Dimm 1 --> SpdAddressTable[1] >=20 > + Channel B/ Slot 0 --> Dimm 2 --> SpdAddressTable[2] >=20 > + Channel B/ Slot 1 --> Dimm 3 --> SpdAddressTable[3] >=20 > + Refer to SmbiosMemory.c for use >=20 > + If change the mapping rule, please update the Revision number. >=20 > +**/ >=20 > + UINT8 *SpdAddressTable; >=20 > +/** >=20 > + Offset 36: >=20 > + Channel A DIMM Slot Mechanical present bit map, bit 0 -> DIMM 0, bit 1= -> > DIMM1, ... >=20 > + if the bit is 1, the related DIMM slot is present. >=20 > + E.g. if channel A has 2 DIMMs, ChannelASlotMap =3D 0x03; >=20 > + E.g. if channel A has only 1 DIMMs, ChannelASlotMap =3D 0x01; >=20 > + Refer to SmbiosMemory.c >=20 > +**/ >=20 > + UINT8 ChannelASlotMap; >=20 > +/** >=20 > + Offset 37: >=20 > + Channel B DIMM Slot Mechanical present bit map, bit 0 -> DIMM 0, bit 1= -> > DIMM1, ... >=20 > + if the bit is 1, the related DIMM slot is present. >=20 > + E.g. if channel B has 2 DIMMs, ChannelBSlotMap =3D 0x03; >=20 > + E.g. if channel B has only 1 DIMMs, ChannelBSlotMap =3D 0x01; >=20 > + Refer to SmbiosMemory.c >=20 > +**/ >=20 > + UINT8 ChannelBSlotMap; >=20 > +/** >=20 > + Offset 38: >=20 > + MRC execution time measurement: 0=3DDisable, 1=3DEnable >=20 > +**/ >=20 > + UINT8 MrcTimeMeasure; >=20 > +/** >=20 > + Offset 39: >=20 > + Fast boot: 0=3DDisable, 1=3DEnable >=20 > +**/ >=20 > + UINT8 MrcFastBoot; >=20 > +/** >=20 > + Offset 40: >=20 > + Retrieves the OEM custom string for the SMBIOS Type 17 Table > DeviceLocator field. >=20 > +**/ >=20 > + MEMORY_DXE_CONFIG_GET_DEVICE_LOCATOR_STRING > GetDeviceLocatorString; >=20 > +/** >=20 > + Offset 48: >=20 > + Retrieves the OEM custom string for the SMBIOS Type 17 Table > BankLocator field. >=20 > +**/ >=20 > + MEMORY_DXE_CONFIG_GET_BANK_LOCATOR_STRING > GetBankLocatorString; >=20 > +}; >=20 > +#pragma pack(pop) >=20 > + >=20 > +#endif // _MEMORY_DXE_CONFIG_H_ >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/ConfigBlock/PcieD= x > eConfig.h > b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/ConfigBlock/PcieD= x > eConfig.h > new file mode 100644 > index 0000000000..799121f1ab > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/ConfigBlock/PcieD= x > eConfig.h > @@ -0,0 +1,114 @@ > +/** @file >=20 > + PCIE DXE policy definitions >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _PCIE_DXE_CONFIG_H_ >=20 > +#define _PCIE_DXE_CONFIG_H_ >=20 > + >=20 > +#include "CpuPcieInfo.h" >=20 > + >=20 > +#pragma pack(push, 1) >=20 > + >=20 > +#define PCIE_DXE_CONFIG_REVISION 2 >=20 > + >=20 > +typedef struct { >=20 > + UINT16 VendorId; ///< Offset 0 PCI Config space offset 0 >=20 > + UINT16 DeviceId; ///< Offset 2 PCI Config space offset 2 >=20 > +/** >=20 > + Offset 4: >=20 > + SnoopLatency bit definition >=20 > + Note: All Reserved bits must be set to 0 >=20 > + >=20 > + BIT[15] - When set to 1b, indicates that the values in bits 9:0 ar= e valid >=20 > + When clear values in bits 9:0 will be ignored >=20 > + BIT[14] - Should be set to 0b >=20 > + BIT[13] - Reserved >=20 > + BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in t= hese bits >=20 > + 000b - 1 ns >=20 > + 001b - 32 ns >=20 > + 010b - 1024 ns >=20 > + 011b - 32,768 ns >=20 > + 100b - 1,048,576 ns >=20 > + 101b - 33,554,432 ns >=20 > + 110b - Reserved >=20 > + 111b - Reserved >=20 > + BITS[9:0] - Snoop Latency Value. The value in these bits will be mul= tiplied > with >=20 > + the scale in bits 12:10 >=20 > +**/ >=20 > + UINT16 SnoopLatency; >=20 > +/** >=20 > + Offset 6: >=20 > + NonSnoopLatency bit definition >=20 > + Note: All Reserved bits must be set to 0 >=20 > + >=20 > + BIT[15] - When set to 1b, indicates that the values in bits 9:0 ar= e valid >=20 > + When clear values in bits 9:0 will be ignored >=20 > + BIT[14] - Should be set to 0b >=20 > + BIT[13] - Reserved >=20 > + BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in t= hese bits >=20 > + 000b - 1 ns >=20 > + 001b - 32 ns >=20 > + 010b - 1024 ns >=20 > + 011b - 32,768 ns >=20 > + 100b - 1,048,576 ns >=20 > + 101b - 33,554,432 ns >=20 > + 110b - Reserved >=20 > + 111b - Reserved >=20 > + BITS[9:0] - Non Snoop Latency Value. The value in these bits will be > multiplied with >=20 > + the scale in bits 12:10 >=20 > +**/ >=20 > + UINT16 NonSnoopLatency; >=20 > + UINT8 RevId; ///< Offset 8 PCI Config space offset 8; 0xFF mean= s all > steppings >=20 > + UINT8 Rsvd0[3]; ///< Offset 9 >=20 > +} PCIE_LTR_DEV_INFO; >=20 > + >=20 > +/// >=20 > +/// PCIE Power Optimizer config >=20 > +/// >=20 > +typedef struct { >=20 > + UINT16 LtrMaxSnoopLatency; ///< Offset 0 LTR Maximum Snoop Latency: > 0x0846=3D70us >=20 > + UINT16 LtrMaxNoSnoopLatency; ///< Offset 2 LTR Maximum Non-Snoop > Latency: 0x0846=3D70us >=20 > + UINT8 ObffEnable; ///< Offset 4 LTR enable/disable: 0=3DDi= sable, > 1=3DEnable >=20 > + UINT8 LtrEnable; ///< Offset 5 LTR enable/disable: 0=3DDi= sable, > 1=3DEnable >=20 > + UINT8 Rsvd0[2]; ///< Offset 6 Reserved >=20 > +} CPU_PCIE_PWR_OPT; >=20 > + >=20 > + >=20 > +/** >=20 > + The PCI Express Configuration info includes PCI Resources Range Base a= nd > Limits and the control >=20 > + for PEG ASPM. >=20 > + The data elements should be initialized by a Platform Module.\n >=20 > + @note Optional. These policies will be ignored if there is no P= EG > port present on board. >=20 > + Revision 1: >=20 > + - Initial version. >=20 > + Revision 2: >=20 > + - Adding PEG RTD3 Support Setup Variable >=20 > + Revision 3: >=20 > + - Adding CPU PCIE RTD3 Support Setup Variable >=20 > + - Deprecating PEG RTD3 Support Setup Variable >=20 > + Revision 4: >=20 > + - Deprecating CPU PCIE RTD3 Support Setup Variable >=20 > +**/ >=20 > +typedef struct { >=20 > + CONFIG_BLOCK_HEADER Header; ///< Offset 0= -27 Config > Block Header >=20 > +/** >=20 > + Offset 28: This field is used to describe the ASPM control for PEG Por= ts\n >=20 > + 0=3DASPM Disabled, 1=3DASPM L0s Enabled, 2=3DASPM L1 Enabled, 3=3DASPM > L0sL1 Enabled, 4=3DASPM AUTO >=20 > +**/ >=20 > + UINT8 PegAspm[SA_PEG_MAX_FUN]; >=20 > +/** >=20 > + Offset 32: PCIe Hot Plug Enable/Disable. It has 2 policies. >=20 > + - Disabled (0x0) : No hotplug. >=20 > + - Enabled (0x1) : Bios assist hotplug. >=20 > +**/ >=20 > + UINT8 PegRootPortHPE[SA_PEG_MAX_FUN]; >=20 > + CPU_PCIE_PWR_OPT PegPwrOpt[SA_PEG_MAX_FUN]; ///< Offset > 36: This field is used to describe the PCIe LTR/OBFF relevant settings >=20 > + UINT32 PegRtd3; /// Deprecate= d Policy >=20 > + UINT8 CpuPcieRtd3; ///< Enable/Di= sable RTD3 Support > for CPU PCIE. 0=3DDisable and 1=3DEnable (default) // Deprecated Policy >=20 > + UINT8 Rsvd3[3]; >=20 > +} PCIE_DXE_CONFIG; >=20 > +#pragma pack(pop) >=20 > + >=20 > +#endif // _PCIE_DXE_CONFIG_H_ >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/ConfigBlock/PramP > reMemConfig.h > b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/ConfigBlock/PramP > reMemConfig.h > new file mode 100644 > index 0000000000..8947e80b22 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/ConfigBlock/PramP > reMemConfig.h > @@ -0,0 +1,34 @@ > +/** @file >=20 > + Policy definition for Persisted Ram (Pram) Config Block >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _PRAM_PREMEM_CONFIG__H_ >=20 > +#define _PRAM_PREMEM_CONFIG__H_ >=20 > +#pragma pack(push, 1) >=20 > + >=20 > +#define PRAM_PREMEM_CONFIG_REVISION 1 >=20 > + >=20 > +/** >=20 > + Defines Pram configuration parameters.\n >=20 > + Revision 1: >=20 > + - Initial version. >=20 > +**/ >=20 > +typedef struct { >=20 > + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header >=20 > + /** >=20 > + Offset 28: >=20 > + Size of Pram >=20 > + If disabled, or if PcdSaOcEnable is disabled, all other policies in th= is config > block are ignored. >=20 > + 0=3DDisable, >=20 > + 1=3D4MB, >=20 > + 2=3D16MB, >=20 > + 3=3D64MB >=20 > + **/ >=20 > + UINT8 Pram; >=20 > + UINT8 Rsvd[3]; ///< Offset 29 Reserved for DWORD alig= nment >=20 > +} PRAM_PREMEM_CONFIG; >=20 > +#pragma pack(pop) >=20 > + >=20 > +#endif // _PRAM_CONFIG_H_ >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/ConfigBlock/SaMis= c > PeiConfig.h > b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/ConfigBlock/SaMis > cPeiConfig.h > new file mode 100644 > index 0000000000..203d894df9 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/ConfigBlock/SaMis > cPeiConfig.h > @@ -0,0 +1,24 @@ > +/** @file >=20 > + Policy details for miscellaneous configuration in System Agent >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _SA_MISC_PEI_CONFIG_H_ >=20 > +#define _SA_MISC_PEI_CONFIG_H_ >=20 > + >=20 > +#pragma pack(push, 1) >=20 > + >=20 > +#define SA_MISC_PEI_CONFIG_REVISION 1 >=20 > + >=20 > +/** >=20 > + This configuration block is to configure SA Miscellaneous variables du= ring > PEI Post-Mem.\n >=20 > + Revision 1: >=20 > + - Initial version. >=20 > +**/ >=20 > +typedef struct { >=20 > + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Blo= ck > Header >=20 > +} SA_MISC_PEI_CONFIG; >=20 > +#pragma pack(pop) >=20 > + >=20 > +#endif // _SA_MISC_PEI_CONFIG_H_ >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/ConfigBlock/SaMis= c > PeiPreMemConfig.h > b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/ConfigBlock/SaMis > cPeiPreMemConfig.h > new file mode 100644 > index 0000000000..8c660b31a9 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/ConfigBlock/SaMis > cPeiPreMemConfig.h > @@ -0,0 +1,104 @@ > +/** @file >=20 > + Policy details for miscellaneous configuration in System Agent >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _SA_MISC_PEI_PREMEM_CONFIG_H_ >=20 > +#define _SA_MISC_PEI_PREMEM_CONFIG_H_ >=20 > + >=20 > +#pragma pack(push, 1) >=20 > + >=20 > +#ifndef MEM_CFG_MAX_SOCKETS >=20 > +#define MEM_CFG_MAX_SOCKETS 16 >=20 > +#endif >=20 > + >=20 > +#define SA_MISC_PEI_PREMEM_CONFIG_REVISION 2 >=20 > + >=20 > +/** >=20 > + This configuration block is to configure SA Miscellaneous variables du= ring > PEI Pre-Mem phase like programming >=20 > + different System Agent BARs, TsegSize, MmioSize required etc. >=20 > + Revision 1: >=20 > + - Initial version. >=20 > + Revision 2: >=20 > + - Deprecate IedSize. >=20 > +**/ >=20 > +typedef struct { >=20 > + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Blo= ck > Header >=20 > + /** >=20 > + Offset 28 Memory DIMMs' SPD address for reading SPD data. >=20 > + TGL Mapping >=20 > + 0 - Controller 0 Channel 0 Dimm 0 - DDR4 - DDR5 - LPDDR4 - LPDDR5 >=20 > + 1 - Controller 0 Channel 0 Dimm 1 - DDR4 >=20 > + 2 - Controller 0 Channel 1 Dimm 0 -------- DDR5 - LPDDR4 - LPDDR5 >=20 > + 3 - Controller 0 Channel 1 Dimm 1 -------- DDR5 2DPC >=20 > + 4 - Controller 0 Channel 2 Dimm 0 --------------- LPDDR4 - LPDDR5 >=20 > + 6 - Controller 0 Channel 3 Dimm 0 --------------- LPDDR4 - LPDDR5 >=20 > + 8 - Controller 1 Channel 0 Dimm 0 - DDR4 - DDR5 - LPDDR4 - LPDDR5 >=20 > + 9 - Controller 1 Channel 0 Dimm 1 - DDR4 >=20 > + 10 - Controller 1 Channel 1 Dimm 0 -------- DDR5 - LPDDR4 - LPDDR5 >=20 > + 11 - Controller 1 Channel 1 Dimm 1 -------- DDR5 2DPC >=20 > + 12 - Controller 1 Channel 2 Dimm 0 --------------- LPDDR4 - LPDDR5 >=20 > + 14 - Controller 1 Channel 3 Dimm 0 --------------- LPDDR4 - LPDDR5 >=20 > + **/ >=20 > + UINT8 SpdAddressTable[MEM_CFG_MAX_SOCKETS]; >=20 > + VOID *S3DataPtr; ///< Offset 44 Memory data = save pointer > for S3 resume. The memory space should be allocated and filled with prope= r > S3 resume data on a resume path >=20 > + UINT32 SmbusBar; ///< Offset 48 Address of S= ystem Agent > SMBUS BAR: 0xEFA0 >=20 > + /** >=20 > + Offset 52 Size of TSEG in bytes. (Must be power of 2) >=20 > + 0x400000: 4MB for Release build (When IED enabled, it will be > 8MB) >=20 > + 0x1000000 : 16MB for Debug build (Regardless IED enabled or dis= abled) >=20 > + **/ >=20 > + UINT32 TsegSize; >=20 > + /** >=20 > + Offset 56 >=20 > + (Test) Size of IED region in bytes. >=20 > + 0 : IED Disabled (no memory occupied) >=20 > + 0x400000 : 4MB SMM memory occupied by IED (Part of TSEG) >=20 > + Note: Enabling IED may also enlarge TsegSize together. >=20 > + @deprecated >=20 > + **/ >=20 > + UINT32 IedSize; >=20 > + UINT32 SkipExtGfxScan:1; ///< (Test) OFfset 6= 0:0 :1=3DSkip > External Gfx Device Scan; 0=3DScan for external graphics devices. = Set > this policy to skip External Graphics card scanning if the platform uses = Internal > Graphics only. >=20 > + UINT32 BdatEnable:1; ///< Offset 60:1 :This fiel= d enables the > generation of the BIOS DATA ACPI Tables: 0=3DFALSE, 1=3DTRUE. >=20 > + UINT32 TxtImplemented:1; ///< OFfset 60:2 :This fiel= d currently is > used to tell MRC if it should run after TXT initializatoin completed: = 0=3DRun > without waiting for TXT, 1=3DRun after TXT initialization by callback >=20 > + /** >=20 > + Offset 60:3 : >=20 > + (Test) Scan External Discrete Graphics Devices for Legacy Only > VGA OpROMs >=20 > + >=20 > + When enabled, if the primary graphics device is an external discrete > graphics device, Si will scan the >=20 > + graphics device for legacy only VGA OpROMs. >=20 > + >=20 > + This is intended to ease the implementation of a BIOS feature to > automatically enable CSM if the Primary Gfx device >=20 > + only supports Legacy VBIOS (No UEFI GOP Present). Otherwise disablin= g > CSM won't result in no video being displayed. >=20 > + This is useful for platforms that implement PCIe slots that allow the= end > user to install an arbitrary Gfx device. >=20 > + >=20 > + This setting will only take effect if SkipExtGfxScan =3D=3D 0. It is= ignored > otherwise. >=20 > + >=20 > + - Disabled (0x0) : Don't Scan for Legacy Only VGA OpROMs (Defa= ult) >=20 > + - Enabled (0x1) : Scan External Gfx for Legacy Only VGA OpROM >=20 > + **/ >=20 > + UINT32 ScanExtGfxForLegacyOpRom:1; >=20 > + UINT32 RsvdBits0 :28; ///< Offset 60:4 :Reserved = for future use >=20 > + UINT8 UserBd; ///< Offset 64 0=3DMobil= e/Mobile > Halo, 1=3DDesktop/DT Halo, 5=3DULT/ULX/Mobile Halo, 7=3DUP Server >=20 > + UINT8 LockPTMregs; ///< (Test) Offset 6= 5 Lock PCU > Thermal Management registers: 0=3DFALSE, 1=3DTRUE >=20 > + UINT8 BdatTestType; ///< Offset 66 When BdatEna= ble is set to > TRUE, this option selects the type of data which will be populated in the= BIOS > Data ACPI Tables: 0=3DRMT, 1=3DRMT Per Bit, 2=3DMargin 2D. >=20 > + UINT8 CridEnable; ///< Offset 67 For Platform= s supporting > Intel(R) SIPP, this policy is use control enable/disable Compatibility Re= vision > ID (CRID) feature: 0=3DFALSE, 1=3DTRUE >=20 > + UINT32 AcpiReservedMemorySize; ///< Offset 68 The Size of = a > Reserved memory buffer allocated in previous boot for S3 resume used. > Originally it is retrieved from AcpiVariableCompatibility variable. >=20 > + UINT32 OpRomScanTempMmioBar; ///< (Test) Offset 7= 2 > Temporary address to MMIO map OpROMs during VGA scanning. Used for > ScanExtGfxForLegacyOpRom feature. MUST BE 16MB ALIGNED! >=20 > + UINT32 OpRomScanTempMmioLimit; ///< (Test) Offset 7= 6 > Limit address for OpROM MMIO range. Used for > ScanExtGfxForLegacyOpRom feature. (OpROMScanTempMmioLimit - > OpRomScanTempMmioBar) MUST BE >=3D 16MB! >=20 > + UINT64 AcpiReservedMemoryBase; ///< Offset 80 The Base add= ress > of a Reserved memory buffer allocated in previous boot for S3 resume used= . > Originally it is retrieved from AcpiVariableCompatibility variable. >=20 > + UINT64 SystemMemoryLength; ///< Offset 88 Total system > memory length from previous boot, this is required for S3 resume. Origina= lly > it is retrieved from AcpiVariableCompatibility variable. >=20 > + >=20 > + UINT8 WrcFeatureEnable; ///< Offset 96: Enable/Dis= able WRC > (Write Cache) feature of IOP. When enabled, supports IO devices allocatin= g > onto the ring and into LLC. >=20 > + UINT8 Reserved1[3]; ///< Reserved for config b= lock alignment. >=20 > + >=20 > + >=20 > + // Since the biggest element is UINT64, this structure should be align= ed > with 64 bits. >=20 > + UINT8 Rsvd[4]; ///< Reserved for config bl= ock alignment. >=20 > + >=20 > + >=20 > +} SA_MISC_PEI_PREMEM_CONFIG; >=20 > +#pragma pack(pop) >=20 > + >=20 > +#endif // _SA_MISC_PEI_PREMEM_CONFIG_H_ >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/Library/SaPlatfor= m > Lib.h > b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/Library/SaPlatfor= m > Lib.h > new file mode 100644 > index 0000000000..daf3746605 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/Library/SaPlatfor= m > Lib.h > @@ -0,0 +1,48 @@ > +/** @file >=20 > + Header file for SaPlatformLib. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +#ifndef _SA_PLATFORM_LIB_H_ >=20 > +#define _SA_PLATFORM_LIB_H_ >=20 > + >=20 > + >=20 > +/** >=20 > + Checks if SKU is Mobile >=20 > + >=20 > + @retval FALSE SKU is not Mobile >=20 > + @retval TRUE SKU is Mobile >=20 > +**/ >=20 > +BOOLEAN >=20 > +EFIAPI >=20 > +IsMobileSku ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Checks if SKU is Desktop >=20 > + >=20 > + @retval FALSE SKU is not Desktop >=20 > + @retval TRUE SKU is Desktop >=20 > +**/ >=20 > +BOOLEAN >=20 > +EFIAPI >=20 > +IsDesktopSku ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Checks if SKU is Server >=20 > + >=20 > + @retval FALSE SKU is not Server >=20 > + @retval TRUE SKU is Server >=20 > +**/ >=20 > +BOOLEAN >=20 > +EFIAPI >=20 > +IsServerSku ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +#endif >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/MemInfoHob.h > b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/MemInfoHob.h > new file mode 100644 > index 0000000000..b50d7e5188 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/MemInfoHob.h > @@ -0,0 +1,264 @@ > +/** @file >=20 > + This file contains definitions required for creation of >=20 > + Memory S3 Save data, Memory Info data and Memory Platform >=20 > + data hobs. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _MEM_INFO_HOB_H_ >=20 > +#define _MEM_INFO_HOB_H_ >=20 > + >=20 > +#pragma pack (push, 1) >=20 > + >=20 > +extern EFI_GUID gSiMemoryS3DataGuid; >=20 > +extern EFI_GUID gSiMemoryInfoDataGuid; >=20 > +extern EFI_GUID gSiMemoryPlatformDataGuid; >=20 > + >=20 > +#define MAX_TRACE_CACHE_TYPE 3 >=20 > + >=20 > +#define MAX_NODE 2 >=20 > +#define MAX_CH 4 >=20 > +#define MAX_DIMM 2 >=20 > + >=20 > +/// >=20 > +/// Host reset states from MRC. >=20 > +/// >=20 > +#define WARM_BOOT 2 >=20 > + >=20 > +#define R_MC_CHNL_RANK_PRESENT 0x7C >=20 > +#define B_RANK0_PRS BIT0 >=20 > +#define B_RANK1_PRS BIT1 >=20 > +#define B_RANK2_PRS BIT4 >=20 > +#define B_RANK3_PRS BIT5 >=20 > + >=20 > +// @todo remove and use the MdePkg\Include\Pi\PiHob.h >=20 > +#if !defined(_PEI_HOB_H_) && !defined(__PI_HOB_H__) >=20 > +#ifndef __HOB__H__ >=20 > +typedef struct _EFI_HOB_GENERIC_HEADER { >=20 > + UINT16 HobType; >=20 > + UINT16 HobLength; >=20 > + UINT32 Reserved; >=20 > +} EFI_HOB_GENERIC_HEADER; >=20 > + >=20 > +typedef struct _EFI_HOB_GUID_TYPE { >=20 > + EFI_HOB_GENERIC_HEADER Header; >=20 > + EFI_GUID Name; >=20 > + /// >=20 > + /// Guid specific data goes here >=20 > + /// >=20 > +} EFI_HOB_GUID_TYPE; >=20 > +#endif >=20 > +#endif >=20 > + >=20 > +/// >=20 > +/// Defines taken from MRC so avoid having to include MrcInterface.h >=20 > +/// >=20 > + >=20 > +// >=20 > +// Matches MAX_SPD_SAVE define in MRC >=20 > +// >=20 > +#ifndef MAX_SPD_SAVE >=20 > +#define MAX_SPD_SAVE 29 >=20 > +#endif >=20 > + >=20 > +// >=20 > +// MRC version description. >=20 > +// >=20 > +typedef struct { >=20 > + UINT8 Major; ///< Major version number >=20 > + UINT8 Minor; ///< Minor version number >=20 > + UINT8 Rev; ///< Revision number >=20 > + UINT8 Build; ///< Build number >=20 > +} SiMrcVersion; >=20 > + >=20 > +// >=20 > +// Matches MrcDimmSts enum in MRC >=20 > +// >=20 > +#ifndef DIMM_ENABLED >=20 > +#define DIMM_ENABLED 0 // DIMM/rank Pair is enabled, presence will > be detected. >=20 > +#endif >=20 > +#ifndef DIMM_DISABLED >=20 > +#define DIMM_DISABLED 1 // DIMM/rank Pair is disabled, regardless of > presence. >=20 > +#endif >=20 > +#ifndef DIMM_PRESENT >=20 > +#define DIMM_PRESENT 2 // There is a DIMM present in the slot/rank > pair and it will be used. >=20 > +#endif >=20 > +#ifndef DIMM_NOT_PRESENT >=20 > +#define DIMM_NOT_PRESENT 3 // There is no DIMM present in the > slot/rank pair. >=20 > +#endif >=20 > + >=20 > +// >=20 > +// Matches MrcBootMode enum in MRC >=20 > +// >=20 > +#ifndef __MRC_BOOT_MODE__ >=20 > +#define __MRC_BOOT_MODE__ //The below values are origina= ted > from MrcCommonTypes.h >=20 > + #ifndef INT32_MAX >=20 > + #define INT32_MAX (0x7FFFFFFF) >=20 > + #endif //INT32_MAX >=20 > +typedef enum { >=20 > + bmCold, ///< Cold boot >=20 > + bmWarm, ///< Warm boot >=20 > + bmS3, ///< S3 resume >=20 > + bmFast, ///< Fast boot >=20 > + MrcBootModeMax, ///< MRC_BOOT_MODE enumeration > maximum value. >=20 > + MrcBootModeDelim =3D INT32_MAX ///< This value ensures the = enum > size is consistent on both sides of the PPI. >=20 > +} MRC_BOOT_MODE; >=20 > +#endif //__MRC_BOOT_MODE__ >=20 > + >=20 > +// >=20 > +// Matches MrcDdrType enum in MRC >=20 > +// >=20 > +#ifndef MRC_DDR_TYPE_DDR4 >=20 > +#define MRC_DDR_TYPE_DDR4 0 >=20 > +#endif >=20 > +#ifndef MRC_DDR_TYPE_DDR3 >=20 > +#define MRC_DDR_TYPE_DDR3 1 >=20 > +#endif >=20 > +#ifndef MRC_DDR_TYPE_LPDDR3 >=20 > +#define MRC_DDR_TYPE_LPDDR3 2 >=20 > +#endif >=20 > +#ifndef MRC_DDR_TYPE_LPDDR4 >=20 > +#define MRC_DDR_TYPE_LPDDR4 3 >=20 > +#endif >=20 > +#ifndef MRC_DDR_TYPE_WIO2 >=20 > +#define MRC_DDR_TYPE_WIO2 4 >=20 > +#endif >=20 > +#ifndef MRC_DDR_TYPE_UNKNOWN >=20 > +#define MRC_DDR_TYPE_UNKNOWN 5 >=20 > +#endif >=20 > + >=20 > +#define MAX_PROFILE_NUM 4 // number of memory profiles supported >=20 > +#define MAX_XMP_PROFILE_NUM 2 // number of XMP profiles supported >=20 > + >=20 > +// >=20 > +// DIMM timings >=20 > +// >=20 > +typedef struct { >=20 > + UINT32 tCK; ///< Memory cycle time, in femtoseconds. >=20 > + UINT16 NMode; ///< Number of tCK cycles for the channel DIMM's > command rate mode. >=20 > + UINT16 tCL; ///< Number of tCK cycles for the channel DIMM's CAS > latency. >=20 > + UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's > minimum CAS write latency time. >=20 > + UINT16 tFAW; ///< Number of tCK cycles for the channel DIMM's > minimum four activate window delay time. >=20 > + UINT16 tRAS; ///< Number of tCK cycles for the channel DIMM's > minimum active to precharge delay time. >=20 > + UINT16 tRCDtRP; ///< Number of tCK cycles for the channel DIMM's > minimum RAS# to CAS# delay time and Row Precharge delay time. >=20 > + UINT16 tREFI; ///< Number of tCK cycles for the channel DIMM's > minimum Average Periodic Refresh Interval. >=20 > + UINT16 tRFC; ///< Number of tCK cycles for the channel DIMM's > minimum refresh recovery delay time. >=20 > + UINT16 tRFCpb; ///< Number of tCK cycles for the channel DIMM's > minimum per bank refresh recovery delay time. >=20 > + UINT16 tRFC2; ///< Number of tCK cycles for the channel DIMM's > minimum refresh recovery delay time. >=20 > + UINT16 tRFC4; ///< Number of tCK cycles for the channel DIMM's > minimum refresh recovery delay time. >=20 > + UINT16 tRPab; ///< Number of tCK cycles for the channel DIMM's > minimum row precharge delay time for all banks. >=20 > + UINT16 tRRD; ///< Number of tCK cycles for the channel DIMM's > minimum row active to row active delay time. >=20 > + UINT16 tRRD_L; ///< Number of tCK cycles for the channel DIMM's > minimum row active to row active delay time for same bank groups. >=20 > + UINT16 tRRD_S; ///< Number of tCK cycles for the channel DIMM's > minimum row active to row active delay time for different bank groups. >=20 > + UINT16 tRTP; ///< Number of tCK cycles for the channel DIMM's > minimum internal read to precharge command delay time. >=20 > + UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's > minimum write recovery time. >=20 > + UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's > minimum internal write to read command delay time. >=20 > + UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's > minimum internal write to read command delay time for same bank groups. >=20 > + UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's > minimum internal write to read command delay time for different bank > groups. >=20 > + UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's > minimum CAS-to-CAS delay for same bank group. >=20 > +} MRC_CH_TIMING; >=20 > + >=20 > +/// >=20 > +/// Memory SMBIOS & OC Memory Data Hob >=20 > +/// >=20 > +typedef struct { >=20 > + UINT8 Status; ///< See MrcDimmStatus for t= he definition of > this field. >=20 > + UINT8 DimmId; >=20 > + UINT32 DimmCapacity; ///< DIMM size in MBytes. >=20 > + UINT16 MfgId; >=20 > + UINT8 ModulePartNum[20]; ///< Module part number for = DDR3 is > 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 byt= es >=20 > + UINT8 RankInDimm; ///< The number of ranks in = this DIMM. >=20 > + UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType > information needed for SMBIOS structure creation. >=20 > + UINT8 SpdModuleType; ///< Save SPD ModuleType inf= ormation > needed for SMBIOS structure creation. >=20 > + UINT8 SpdModuleMemoryBusWidth; ///< Save SPD > ModuleMemoryBusWidth information needed for SMBIOS structure > creation. >=20 > + UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing > information needed for SMBIOS structure creation. >=20 > + UINT16 Speed; ///< The maximum capable spe= ed of the > device, in MHz >=20 > + UINT8 MdSocket; ///< MdSocket: 0 =3D Memory = Down, 1 =3D > Socketed. Needed for SMBIOS structure creation. >=20 > +} DIMM_INFO; >=20 > + >=20 > +typedef struct { >=20 > + UINT8 Status; ///< Indicates whether this = channel should be > used. >=20 > + UINT8 ChannelId; >=20 > + UINT8 DimmCount; ///< Number of valid DIMMs t= hat exist in > the channel. >=20 > + MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing > values. >=20 > + DIMM_INFO DimmInfo[MAX_DIMM]; ///< Save the DIMM output > characteristics. >=20 > +} CHANNEL_INFO; >=20 > + >=20 > +typedef struct { >=20 > + UINT8 Status; ///< Indicates whether this = controller should > be used. >=20 > + UINT16 DeviceId; ///< The PCI device id of th= is memory > controller. >=20 > + UINT8 RevisionId; ///< The PCI revision id of = this memory > controller. >=20 > + UINT8 ChannelCount; ///< Number of valid channel= s that exist > on the controller. >=20 > + CHANNEL_INFO ChannelInfo[MAX_CH]; ///< The following are > channel level definitions. >=20 > +} CONTROLLER_INFO; >=20 > + >=20 > +typedef struct { >=20 > + UINT64 BaseAddress; ///< Trace Base Address >=20 > + UINT64 TotalSize; ///< Total Trace Region of Same Cache type >=20 > + UINT8 CacheType; ///< Trace Cache Type >=20 > + UINT8 ErrorCode; ///< Trace Region Allocation Fail Error code >=20 > + UINT8 Rsvd[2]; >=20 > +} PSMI_MEM_INFO; >=20 > + >=20 > +typedef struct { >=20 > + UINT8 Revision; >=20 > + UINT16 DataWidth; ///< Data width, in bits, of= this memory > device >=20 > + /** As defined in SMBIOS 3.0 spec >=20 > + Section 7.18.2 and Table 75 >=20 > + **/ >=20 > + UINT8 MemoryType; ///< DDR type: DDR3, DDR4, o= r LPDDR3 >=20 > + UINT16 MaximumMemoryClockSpeed;///< The maximum capable > speed of the device, in megahertz (MHz) >=20 > + UINT16 ConfiguredMemoryClockSpeed; ///< The configured cloc= k > speed to the memory device, in megahertz (MHz) >=20 > + /** As defined in SMBIOS 3.0 spec >=20 > + Section 7.17.3 and Table 72 >=20 > + **/ >=20 > + UINT8 ErrorCorrectionType; >=20 > + >=20 > + SiMrcVersion Version; >=20 > + BOOLEAN EccSupport; >=20 > + UINT8 MemoryProfile; >=20 > + UINT32 TotalPhysicalMemorySize; >=20 > + UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the > tCK value read from SPD XMP profiles if they exist. >=20 > + UINT8 XmpProfileEnable; ///< If XMP capab= le DIMMs are > detected, this will indicate which XMP Profiles are common among all > DIMMs. >=20 > + UINT8 Ratio; >=20 > + UINT8 RefClk; >=20 > + UINT32 VddVoltage[MAX_PROFILE_NUM]; >=20 > + CONTROLLER_INFO Controller[MAX_NODE]; >=20 > +} MEMORY_INFO_DATA_HOB; >=20 > + >=20 > +/** >=20 > + Memory Platform Data Hob >=20 > + >=20 > + Revision 1: >=20 > + - Initial version. >=20 > + Revision 2: >=20 > + - Added TsegBase, PrmrrSize, PrmrrBase, Gttbase, MmioSize, > PciEBaseAddress fields >=20 > +**/ >=20 > +typedef struct { >=20 > + UINT8 Revision; >=20 > + UINT8 Reserved[3]; >=20 > + UINT32 BootMode; >=20 > + UINT32 TsegSize; >=20 > + UINT32 TsegBase; >=20 > + UINT32 PrmrrSize; >=20 > + UINT64 PrmrrBase; >=20 > + UINT32 PramSize; >=20 > + UINT64 PramBase; >=20 > + UINT64 DismLimit; >=20 > + UINT64 DismBase; >=20 > + UINT32 GttBase; >=20 > + UINT32 MmioSize; >=20 > + UINT32 PciEBaseAddress; >=20 > + PSMI_MEM_INFO PsmiInfo[MAX_TRACE_CACHE_TYPE]; >=20 > +} MEMORY_PLATFORM_DATA; >=20 > + >=20 > +typedef struct { >=20 > + EFI_HOB_GUID_TYPE EfiHobGuidType; >=20 > + MEMORY_PLATFORM_DATA Data; >=20 > + UINT8 *Buffer; >=20 > +} MEMORY_PLATFORM_DATA_HOB; >=20 > + >=20 > +#pragma pack (pop) >=20 > + >=20 > +#endif // _MEM_INFO_HOB_H_ >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/Protocol/SaPolicy= .h > b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/Protocol/SaPolicy= .h > new file mode 100644 > index 0000000000..4ff2578038 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/Protocol/SaPolicy= .h > @@ -0,0 +1,61 @@ > +/** @file >=20 > + Interface definition details between System Agent and platform drivers > during DXE phase. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _SA_POLICY_H_ >=20 > +#define _SA_POLICY_H_ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +/// >=20 > +/// Extern the GUID for protocol users. >=20 > +/// >=20 > +extern EFI_GUID gSaPolicyProtocolGuid; >=20 > +extern EFI_GUID gGraphicsDxeConfigGuid; >=20 > +extern EFI_GUID gPcieDxeConfigGuid; >=20 > +extern EFI_GUID gMemoryDxeConfigGuid; >=20 > +extern EFI_GUID gVtdDxeConfigGuid; >=20 > + >=20 > +/** >=20 > + Don't change the original SA_POLICY_PROTOCOL_REVISION macro, > external >=20 > + modules maybe have consumed this macro in their source code. Directly >=20 > + update the SA_POLICY_PROTOCOL_REVISION version number may cause > those >=20 > + external modules to auto mark themselves wrong version info. >=20 > + Always create new version macro for new Policy protocol interface. >=20 > +**/ >=20 > +#define SA_POLICY_PROTOCOL_REVISION 1 >=20 > + >=20 > +#define CPU_PCIE_DEV_END_OF_TABLE 0xFFFF >=20 > + >=20 > +#define LTR_MAX_SNOOP_LATENCY_VALUE 0x0846 ///< Intel > recommended maximum value for Snoop Latency >=20 > +#define LTR_MAX_NON_SNOOP_LATENCY_VALUE 0x0846 ///< Intel > recommended maximum value for Non-Snoop Latency >=20 > + >=20 > + >=20 > +/** >=20 > + SA DXE Policy >=20 > + >=20 > + The SA_POLICY_PROTOCOL producer drvier is recommended to >=20 > + set all the SA_POLICY_PROTOCOL size buffer zero before init any member > parameter, >=20 > + this clear step can make sure no random value for those unknow new > version parameters. >=20 > + >=20 > + Make sure to update the Revision if any change to the protocol, includi= ng > the existing >=20 > + internal structure definations.\n >=20 > + Note: Here revision will be bumped up when adding/removing any config > block under this structure.\n >=20 > + Revision 1: >=20 > + - Initial version. >=20 > +**/ >=20 > +typedef struct { >=20 > + CONFIG_BLOCK_TABLE_HEADER TableHeader; ///< Offset 0-31 >=20 > +/* >=20 > + Individual Config Block Structures are added here in memory as part of > AddConfigBlock() >=20 > +*/ >=20 > +} SA_POLICY_PROTOCOL; >=20 > + >=20 > +#endif >=20 > -- > 2.24.0.windows.2