Re: [PATCH 22/40] TigerlakeSiliconPkg/IpBlock: Add PchDmi component

["Nate DeSimone" <nathaniel.l.desimone@intel.com>]

Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>

> -----Original Message-----
> From: Luo, Heng <heng.luo@intel.com>
> Sent: Sunday, January 31, 2021 5:37 PM
> To: devel@edk2.groups.io
> Cc: Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Desimone,
> Nathaniel L <nathaniel.l.desimone@intel.com>
> Subject: [PATCH 22/40] TigerlakeSiliconPkg/IpBlock: Add PchDmi component
> 
> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171
> 
> Adds the following files:
>   * IpBlock/PchDmi/IncludePrivate
>   * IpBlock/PchDmi/LibraryPrivate
> 
> Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
> Signed-off-by: Heng Luo <heng.luo@intel.com>
> ---
> 
> Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/IncludePrivate/Library/Pch
> DmiLib.h                             | 175
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> +
> 
> Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmm
> PchDmiLib/PchDmi14.c                   |  50
> ++++++++++++++++++++++++++++++++++++++++++++++++++
> 
> Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmm
> PchDmiLib/PchDmi14.h                   |  34
> ++++++++++++++++++++++++++++++++++
> 
> Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmm
> PchDmiLib/PchDmiLib.c                  | 269
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> +++++++++++++++++++++++++++++++++++++
> 
> Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmm
> PchDmiLib/PchDmiWithS3Lib.c            |  73
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> +++++++++++++++
> 
> Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmm
> PchDmiLib/PeiDxeSmmPchDmiLib.inf       |  42
> ++++++++++++++++++++++++++++++++++++++++++
> 
> Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmm
> PchDmiLib/PeiDxeSmmPchDmiWithS3Lib.inf |  41
> +++++++++++++++++++++++++++++++++++++++++
>  7 files changed, 684 insertions(+)
> 
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/IncludePrivate/Library/Pc
> hDmiLib.h
> b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/IncludePrivate/Library/Pc
> hDmiLib.h
> new file mode 100644
> index 0000000000..77db69c75a
> --- /dev/null
> +++
> b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/IncludePrivate/Library/Pc
> hDmiLib.h
> @@ -0,0 +1,175 @@
> +/** @file
> 
> +  Header file for PchDmiLib.
> 
> +
> 
> +  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
> 
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> 
> +**/
> 
> +#ifndef _PCH_DMI_LIB_H_
> 
> +#define _PCH_DMI_LIB_H_
> 
> +
> 
> +/**
> 
> +  This function checks if DMI Secured Register Lock (SRL) is set
> 
> +
> 
> +  @retval SRL state
> 
> +**/
> 
> +BOOLEAN
> 
> +IsPchDmiLocked (
> 
> +  VOID
> 
> +  );
> 
> +
> 
> +/**
> 
> +  Get PCH TCO base address.
> 
> +
> 
> +  @retval Address                   Address of TCO base address.
> 
> +**/
> 
> +UINT16
> 
> +PchDmiGetTcoBase (
> 
> +  VOID
> 
> +  );
> 
> +
> 
> +/**
> 
> +  Set PCH LPC/eSPI generic IO range decoding in DMI
> 
> +
> 
> +  @param[in] Address                    Address for generic IO range base address.
> 
> +  @param[in] Length                     Length of generic IO range.
> 
> +  @param[in] RangeIndex                 Index of choosen range
> 
> +
> 
> +  @retval EFI_SUCCESS                   Successfully completed.
> 
> +  @retval EFI_UNSUPPORTED               DMIC.SRL is set.
> 
> +**/
> 
> +EFI_STATUS
> 
> +PchDmiSetLpcGenIoRange (
> 
> +  IN  UINT32                            Address,
> 
> +  IN  UINT32                            Length,
> 
> +  IN  UINT32                            RangeIndex
> 
> +  );
> 
> +
> 
> +/**
> 
> +  Set PCH eSPI eSPI CS1# generic IO range decoding in DMI
> 
> +
> 
> +  @param[in] Address                    Address for generic IO range base address.
> 
> +  @param[in] Length                     Length of generic IO range.
> 
> +
> 
> +  @retval EFI_SUCCESS                   Successfully completed.
> 
> +  @retval EFI_UNSUPPORTED               DMIC.SRL is set.
> 
> +**/
> 
> +EFI_STATUS
> 
> +PchDmiSetEspiCs1GenIoRange (
> 
> +  IN  UINT32                            Address,
> 
> +  IN  UINT32                            Length
> 
> +  );
> 
> +
> 
> +/**
> 
> +  Set PCH LPC/eSPI memory range decoding in DMI
> 
> +
> 
> +  @param[in] Address                    Address for memory base address.
> 
> +
> 
> +  @retval EFI_SUCCESS                   Successfully completed.
> 
> +  @retval EFI_UNSUPPORTED               DMIC.SRL is set.
> 
> +**/
> 
> +EFI_STATUS
> 
> +PchDmiSetLpcMemRange (
> 
> +  IN  UINT32                            Address
> 
> +  );
> 
> +
> 
> +/**
> 
> +  Set PCH eSPI CS1# memory range decoding in DMI
> 
> +
> 
> +  @param[in] Address                    Address for memory base address.
> 
> +
> 
> +  @retval EFI_SUCCESS                   Successfully completed.
> 
> +  @retval EFI_UNSUPPORTED               DMIC.SRL is set.
> 
> +**/
> 
> +EFI_STATUS
> 
> +PchDmiSetEspiCs1MemRange (
> 
> +  IN  UINT32                            Address
> 
> +  );
> 
> +
> 
> +/**
> 
> +  Check if Boot BIOS Strap is set for SPI.
> 
> +
> 
> +  @retval TRUE                Boot BIOS Strap set for SPI
> 
> +  @retval FALSE               Boot BIOS Strap set for LPC/eSPI
> 
> +**/
> 
> +BOOLEAN
> 
> +PchDmiIsBootBiosStrapSetForSpi (
> 
> +  VOID
> 
> +  );
> 
> +
> 
> +/**
> 
> +  Set PCH BIOS range decoding in DMI
> 
> +  Please check EDS for detail of BiosDecodeEnable bit definition.
> 
> +    bit 15: F8-FF Enable
> 
> +    bit 14: F0-F8 Enable
> 
> +    bit 13: E8-EF Enable
> 
> +    bit 12: E0-E8 Enable
> 
> +    bit 11: D8-DF Enable
> 
> +    bit 10: D0-D7 Enable
> 
> +    bit  9: C8-CF Enable
> 
> +    bit  8: C0-C7 Enable
> 
> +    bit  7: Legacy F Segment Enable
> 
> +    bit  6: Legacy E Segment Enable
> 
> +    bit  5: Reserved
> 
> +    bit  4: Reserved
> 
> +    bit  3: 70-7F Enable
> 
> +    bit  2: 60-6F Enable
> 
> +    bit  1: 50-5F Enable
> 
> +    bit  0: 40-4F Enable
> 
> +
> 
> +  @param[in] BiosDecodeEnable           Bios decode enable setting.
> 
> +
> 
> +  @retval EFI_SUCCESS                   Successfully completed.
> 
> +  @retval EFI_UNSUPPORTED               DMIC.SRL is set.
> 
> +**/
> 
> +EFI_STATUS
> 
> +PchDmiSetBiosDecodeEnable (
> 
> +  IN  UINT16                            BiosDecodeEnable
> 
> +  );
> 
> +
> 
> +/**
> 
> +  Set PCH LPC/eSPI IO decode ranges in DMI
> 
> +  Please check EDS for detail of LPC/eSPI IO decode ranges bit definition.
> 
> +  Bit  12: FDD range
> 
> +  Bit 9:8: LPT range
> 
> +  Bit 6:4: ComB range
> 
> +  Bit 2:0: ComA range
> 
> +
> 
> +  @param[in] LpcIoDecodeRanges          LPC/eSPI IO decode ranges bit
> settings.
> 
> +
> 
> +  @retval EFI_SUCCESS                   Successfully completed.
> 
> +  @retval EFI_UNSUPPORTED               DMIC.SRL is set.
> 
> +**/
> 
> +EFI_STATUS
> 
> +PchDmiSetLpcIoDecodeRanges (
> 
> +  IN  UINT16                            LpcIoDecodeRanges
> 
> +  );
> 
> +
> 
> +/**
> 
> +  Set PCH LPC/eSPI IO enable decoding in DMI
> 
> +
> 
> +  @param[in] LpcIoEnableDecoding        LPC/eSPI IO enable decoding bit
> settings.
> 
> +
> 
> +  @retval EFI_SUCCESS                   Successfully completed.
> 
> +  @retval EFI_UNSUPPORTED               DMIC.SRL is set.
> 
> +**/
> 
> +EFI_STATUS
> 
> +PchDmiSetLpcIoEnable (
> 
> +  IN  UINT16                            LpcIoEnableDecoding
> 
> +  );
> 
> +
> 
> +/**
> 
> +  Configure PCH DMI Lock
> 
> +**/
> 
> +VOID
> 
> +PchDmiSetLockWithS3BootScript (
> 
> +  VOID
> 
> +  );
> 
> +
> 
> +/**
> 
> +  Set BIOS interface Lock-Down
> 
> +**/
> 
> +VOID
> 
> +PchDmiSetBiosLockDownWithS3BootScript (
> 
> +  VOID
> 
> +  );
> 
> +#endif // _PCH_DMI_LIB_H_
> 
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSm
> mPchDmiLib/PchDmi14.c
> b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSm
> mPchDmiLib/PchDmi14.c
> new file mode 100644
> index 0000000000..60bc29c431
> --- /dev/null
> +++
> b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSm
> mPchDmiLib/PchDmi14.c
> @@ -0,0 +1,50 @@
> +/** @file
> 
> +  This file contains functions for PCH DMI SIP14
> 
> +
> 
> +  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
> 
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> 
> +**/
> 
> +
> 
> +#include <Base.h>
> 
> +#include <Uefi/UefiBaseType.h>
> 
> +#include <Library/IoLib.h>
> 
> +#include <Library/DebugLib.h>
> 
> +#include <Library/BaseLib.h>
> 
> +#include <Library/PchInfoLib.h>
> 
> +#include <Library/PchPcrLib.h>
> 
> +#include <Library/PchDmiLib.h>
> 
> +#include <Library/PchCycleDecodingLib.h>
> 
> +#include <Library/PchPcrLib.h>
> 
> +#include <Library/PchInfoLib.h>
> 
> +#include <Register/PchDmiRegs.h>
> 
> +#include <Register/PchDmi14Regs.h>
> 
> +#include <Register/PchPcrRegs.h>
> 
> +
> 
> +/**
> 
> +  This function checks if DMI SIP14 Secured Register Lock (SRL) is set
> 
> +
> 
> +  @retval SRL state
> 
> +**/
> 
> +BOOLEAN
> 
> +IsPchDmi14Locked (
> 
> +  VOID
> 
> +  )
> 
> +{
> 
> +  return ((PchPcrRead32 (PID_DMI, R_PCH_DMI14_PCR_DMIC) &
> B_PCH_DMI14_PCR_DMIC_SRL) != 0);
> 
> +}
> 
> +
> 
> +/**
> 
> + Secure Register Lock data
> 
> +
> 
> + @param[out] SrlRegOffset        Register offset holding Secure Register Lock
> setting
> 
> + @param[out] SrlRegMask          Mask for Secure Register Lock setting
> 
> +**/
> 
> +VOID
> 
> +PchDmi14SrlRegData (
> 
> +  OUT UINT16  *SrlRegOffset,
> 
> +  OUT UINT32  *SrlRegMask
> 
> +  )
> 
> +{
> 
> +  *SrlRegMask = B_PCH_DMI14_PCR_DMIC_SRL;
> 
> +  *SrlRegOffset = R_PCH_DMI14_PCR_DMIC;
> 
> +}
> 
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSm
> mPchDmiLib/PchDmi14.h
> b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSm
> mPchDmiLib/PchDmi14.h
> new file mode 100644
> index 0000000000..4c19ad82d7
> --- /dev/null
> +++
> b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSm
> mPchDmiLib/PchDmi14.h
> @@ -0,0 +1,34 @@
> +/** @file
> 
> +  Internal header file for PCH DMI library for SIP14
> 
> +
> 
> +  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
> 
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> 
> +**/
> 
> +#ifndef __PCH_DMI_14_H__
> 
> +#define __PCH_DMI_14_H__
> 
> +
> 
> +#include <Library/PchDmiLib.h>
> 
> +
> 
> +/**
> 
> +  This function checks if DMI SIP14 Secured Register Lock (SRL) is set
> 
> +
> 
> +  @retval SRL state
> 
> +**/
> 
> +BOOLEAN
> 
> +IsPchDmi14Locked (
> 
> +  VOID
> 
> +  );
> 
> +
> 
> +/**
> 
> + Secure Register Lock data
> 
> +
> 
> + @param[out] SrlRegOffset        Register offset holding Secure Register Lock
> setting
> 
> + @param[out] SrlRegMask          Mask for Secure Register Lock setting
> 
> +**/
> 
> +VOID
> 
> +PchDmi14SrlRegData (
> 
> +  OUT UINT16  *SrlRegOffset,
> 
> +  OUT UINT32  *SrlRegMask
> 
> +  );
> 
> +
> 
> +#endif
> 
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSm
> mPchDmiLib/PchDmiLib.c
> b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSm
> mPchDmiLib/PchDmiLib.c
> new file mode 100644
> index 0000000000..972e5145aa
> --- /dev/null
> +++
> b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSm
> mPchDmiLib/PchDmiLib.c
> @@ -0,0 +1,269 @@
> +/** @file
> 
> +  PCH DMI library.
> 
> +
> 
> +  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
> 
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> 
> +**/
> 
> +#include <Base.h>
> 
> +#include <Uefi/UefiBaseType.h>
> 
> +#include <Library/IoLib.h>
> 
> +#include <Library/DebugLib.h>
> 
> +#include <Library/BaseLib.h>
> 
> +#include <Library/PchInfoLib.h>
> 
> +#include <Library/PchPcrLib.h>
> 
> +#include <Library/PchDmiLib.h>
> 
> +#include <Library/PchCycleDecodingLib.h>
> 
> +#include <Register/PchPcrRegs.h>
> 
> +#include <Register/PchDmiRegs.h>
> 
> +#include <Register/PchRegsLpc.h>
> 
> +
> 
> +#include "PchDmi14.h"
> 
> +
> 
> +/**
> 
> +  This function checks if DMI Secured Register Lock (SRL) is set
> 
> +
> 
> +  @retval SRL state
> 
> +**/
> 
> +BOOLEAN
> 
> +IsPchDmiLocked (
> 
> +  VOID
> 
> +  )
> 
> +{
> 
> +  return IsPchDmi14Locked ();
> 
> +}
> 
> +
> 
> +/**
> 
> +  Get PCH TCO base address.
> 
> +
> 
> +  @retval Address                   Address of TCO base address.
> 
> +**/
> 
> +UINT16
> 
> +PchDmiGetTcoBase (
> 
> +  VOID
> 
> +  )
> 
> +{
> 
> +  //
> 
> +  // Read "TCO Base Address" PCR[DMI] + 2778h[15:5]
> 
> +  //
> 
> +  return (PchPcrRead16 (PID_DMI, R_PCH_DMI_PCR_TCOBASE) &
> B_PCH_DMI_PCR_TCOBASE_TCOBA);
> 
> +}
> 
> +
> 
> +/**
> 
> +  Set PCH LPC/eSPI generic IO range decoding in DMI
> 
> +
> 
> +  @param[in] Address                    Address for generic IO range base address.
> 
> +  @param[in] Length                     Length of generic IO range.
> 
> +  @param[in] RangeIndex                 Index of choosen range
> 
> +
> 
> +  @retval EFI_SUCCESS                   Successfully completed.
> 
> +  @retval EFI_UNSUPPORTED               DMIC.SRL is set.
> 
> +**/
> 
> +EFI_STATUS
> 
> +PchDmiSetLpcGenIoRange (
> 
> +  IN  UINT32                            Address,
> 
> +  IN  UINT32                            Length,
> 
> +  IN  UINT32                            RangeIndex
> 
> +  )
> 
> +{
> 
> +  return EFI_UNSUPPORTED;
> 
> +}
> 
> +
> 
> +/**
> 
> +  Set PCH eSPI eSPI CS1# generic IO range decoding in DMI
> 
> +
> 
> +  @param[in] Address                    Address for generic IO range base address.
> 
> +  @param[in] Length                     Length of generic IO range.
> 
> +
> 
> +  @retval EFI_SUCCESS                   Successfully completed.
> 
> +  @retval EFI_UNSUPPORTED               DMIC.SRL is set.
> 
> +**/
> 
> +EFI_STATUS
> 
> +PchDmiSetEspiCs1GenIoRange (
> 
> +  IN  UINT32                            Address,
> 
> +  IN  UINT32                            Length
> 
> +  )
> 
> +{
> 
> +  return EFI_UNSUPPORTED;
> 
> +}
> 
> +
> 
> +/**
> 
> +  Set PCH LPC/eSPI memory range decoding in DMI
> 
> +
> 
> +  @param[in] Address                    Address for memory base address.
> 
> +
> 
> +  @retval EFI_SUCCESS                   Successfully completed.
> 
> +  @retval EFI_UNSUPPORTED               DMIC.SRL is set.
> 
> +**/
> 
> +EFI_STATUS
> 
> +PchDmiSetLpcMemRange (
> 
> +  IN  UINT32                            Address
> 
> +  )
> 
> +{
> 
> +  if (IsPchDmiLocked ()) {
> 
> +    DEBUG ((DEBUG_ERROR, "%a Error. DMI is locked.\n", __FUNCTION__));
> 
> +    ASSERT (FALSE);
> 
> +    return EFI_UNSUPPORTED;
> 
> +  }
> 
> +
> 
> +  //
> 
> +  // Program LPC Memory Range, PCR[DMI] + 2740h to the same value
> programmed in LPC/eSPI PCI Offset 98h.
> 
> +  //
> 
> +  PchPcrWrite32 (
> 
> +    PID_DMI, R_PCH_DMI_PCR_LPCGMR,
> 
> +    (Address | B_LPC_CFG_LGMR_LMRD_EN)
> 
> +    );
> 
> +
> 
> +  return EFI_SUCCESS;
> 
> +}
> 
> +
> 
> +/**
> 
> +  Set PCH eSPI CS1# memory range decoding in DMI
> 
> +
> 
> +  @param[in] Address                    Address for memory base address.
> 
> +
> 
> +  @retval EFI_SUCCESS                   Successfully completed.
> 
> +  @retval EFI_UNSUPPORTED               DMIC.SRL is set.
> 
> +**/
> 
> +EFI_STATUS
> 
> +PchDmiSetEspiCs1MemRange (
> 
> +  IN  UINT32                            Address
> 
> +  )
> 
> +{
> 
> +  if (IsPchDmiLocked ()) {
> 
> +    DEBUG ((DEBUG_ERROR, "%a Error. DMI is locked.\n", __FUNCTION__));
> 
> +    ASSERT (FALSE);
> 
> +    return EFI_UNSUPPORTED;
> 
> +  }
> 
> +
> 
> +  //
> 
> +  // Program LPC Memory Range, PCR[DMI] + 27C0h to the same value
> programmed in eSPI PCI Offset A8h.
> 
> +  //
> 
> +  PchPcrWrite32 (
> 
> +    PID_DMI, R_PCH_DMI_PCR_SEGMR,
> 
> +    (Address | B_LPC_CFG_LGMR_LMRD_EN)
> 
> +    );
> 
> +
> 
> +  return EFI_SUCCESS;
> 
> +}
> 
> +
> 
> +/**
> 
> +  Check if Boot BIOS Strap is set for SPI.
> 
> +
> 
> +  @retval TRUE                Boot BIOS Strap set for SPI
> 
> +  @retval FALSE               Boot BIOS Strap set for LPC/eSPI
> 
> +**/
> 
> +BOOLEAN
> 
> +PchDmiIsBootBiosStrapSetForSpi (
> 
> +  VOID
> 
> +  )
> 
> +{
> 
> +  //
> 
> +  // Check General Control and Status (GCS) [10]
> 
> +  // '0': SPI
> 
> +  // '1': LPC/eSPI
> 
> +  //
> 
> +  return ((PchPcrRead32 (PID_DMI, R_PCH_DMI_PCR_GCS) &
> B_PCH_DMI_PCR_BBS) != B_PCH_DMI_PCR_BBS);
> 
> +}
> 
> +
> 
> +/**
> 
> +  Set PCH BIOS range decoding in DMI
> 
> +  Please check EDS for detail of BiosDecodeEnable bit definition.
> 
> +    bit 15: F8-FF Enable
> 
> +    bit 14: F0-F8 Enable
> 
> +    bit 13: E8-EF Enable
> 
> +    bit 12: E0-E8 Enable
> 
> +    bit 11: D8-DF Enable
> 
> +    bit 10: D0-D7 Enable
> 
> +    bit  9: C8-CF Enable
> 
> +    bit  8: C0-C7 Enable
> 
> +    bit  7: Legacy F Segment Enable
> 
> +    bit  6: Legacy E Segment Enable
> 
> +    bit  5: Reserved
> 
> +    bit  4: Reserved
> 
> +    bit  3: 70-7F Enable
> 
> +    bit  2: 60-6F Enable
> 
> +    bit  1: 50-5F Enable
> 
> +    bit  0: 40-4F Enable
> 
> +
> 
> +  @param[in] BiosDecodeEnable           Bios decode enable setting.
> 
> +
> 
> +  @retval EFI_SUCCESS                   Successfully completed.
> 
> +  @retval EFI_UNSUPPORTED               DMIC.SRL is set.
> 
> +**/
> 
> +EFI_STATUS
> 
> +PchDmiSetBiosDecodeEnable (
> 
> +  IN  UINT16                            BiosDecodeEnable
> 
> +  )
> 
> +{
> 
> +  if (IsPchDmiLocked ()) {
> 
> +    ASSERT (FALSE);
> 
> +    return EFI_UNSUPPORTED;
> 
> +  }
> 
> +
> 
> +  //
> 
> +  // program LPC BIOS Decode Enable, PCR[DMI] + 2744h to the same value
> programmed in LPC or SPI Offset D8h.
> 
> +  //
> 
> +  PchPcrWrite16 (PID_DMI, R_PCH_DMI_PCR_LPCBDE, BiosDecodeEnable);
> 
> +  return EFI_SUCCESS;
> 
> +}
> 
> +
> 
> +/**
> 
> +  Set PCH LPC/eSPI IO decode ranges in DMI
> 
> +  Please check EDS for detail of LPC/eSPI IO decode ranges bit definition.
> 
> +  Bit  12: FDD range
> 
> +  Bit 9:8: LPT range
> 
> +  Bit 6:4: ComB range
> 
> +  Bit 2:0: ComA range
> 
> +
> 
> +  @param[in] LpcIoDecodeRanges          LPC/eSPI IO decode ranges bit
> settings.
> 
> +
> 
> +  @retval EFI_SUCCESS                   Successfully completed.
> 
> +  @retval EFI_UNSUPPORTED               DMIC.SRL is set.
> 
> +**/
> 
> +EFI_STATUS
> 
> +PchDmiSetLpcIoDecodeRanges (
> 
> +  IN  UINT16                            LpcIoDecodeRanges
> 
> +  )
> 
> +{
> 
> +  //
> 
> +  // This cycle decoding is only allowed to set when DMI is not locked.
> 
> +  //
> 
> +  if (IsPchDmiLocked ()) {
> 
> +    ASSERT (FALSE);
> 
> +    return EFI_UNSUPPORTED;
> 
> +  }
> 
> +
> 
> +  //
> 
> +  // program LPC I/O Decode Ranges, PCR[DMI] + 2770h[15:0] to the same
> value programmed in LPC/eSPI PCI offset 80h.
> 
> +  //
> 
> +  PchPcrWrite16 (PID_DMI, R_PCH_DMI_PCR_LPCIOD,
> LpcIoDecodeRanges);
> 
> +  return EFI_SUCCESS;
> 
> +}
> 
> +
> 
> +/**
> 
> +  Set PCH LPC/eSPI IO enable decoding in DMI
> 
> +
> 
> +  @param[in] LpcIoEnableDecoding        LPC/eSPI IO enable decoding bit
> settings.
> 
> +
> 
> +  @retval EFI_SUCCESS                   Successfully completed.
> 
> +  @retval EFI_UNSUPPORTED               DMIC.SRL is set.
> 
> +**/
> 
> +EFI_STATUS
> 
> +PchDmiSetLpcIoEnable (
> 
> +  IN  UINT16                            LpcIoEnableDecoding
> 
> +  )
> 
> +{
> 
> +  //
> 
> +  // This cycle decoding is only allowed to set when DMI is not locked.
> 
> +  //
> 
> +  if (IsPchDmiLocked ()) {
> 
> +    ASSERT (FALSE);
> 
> +    return EFI_UNSUPPORTED;
> 
> +  }
> 
> +
> 
> +  //
> 
> +  // program LPC I/O Decode Ranges, PCR[DMI] + 2774h[15:0] to the same
> value programmed in LPC/eSPI PCI offset 82h.
> 
> +  //
> 
> +  PchPcrWrite16 (PID_DMI, R_PCH_DMI_PCR_LPCIOE,
> LpcIoEnableDecoding);
> 
> +  return EFI_SUCCESS;
> 
> +}
> 
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSm
> mPchDmiLib/PchDmiWithS3Lib.c
> b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSm
> mPchDmiLib/PchDmiWithS3Lib.c
> new file mode 100644
> index 0000000000..7d6801ee57
> --- /dev/null
> +++
> b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSm
> mPchDmiLib/PchDmiWithS3Lib.c
> @@ -0,0 +1,73 @@
> +/** @file
> 
> +  PCH DMI library with S3 boot script support.
> 
> +
> 
> +  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
> 
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> 
> +**/
> 
> +#include <Base.h>
> 
> +#include <Uefi/UefiBaseType.h>
> 
> +#include <Library/IoLib.h>
> 
> +#include <Library/DebugLib.h>
> 
> +#include <Library/BaseLib.h>
> 
> +#include <Library/PchPcrLib.h>
> 
> +#include <Library/PchInfoLib.h>
> 
> +#include <Library/S3BootScriptLib.h>
> 
> +#include <Register/PchPcrRegs.h>
> 
> +#include <Register/PchDmiRegs.h>
> 
> +
> 
> +#include "PchDmi14.h"
> 
> +
> 
> +/**
> 
> +  Configure DMI Lock
> 
> +**/
> 
> +VOID
> 
> +PchDmiSetLockWithS3BootScript (
> 
> +  VOID
> 
> +  )
> 
> +{
> 
> +  UINT32  Data32Or;
> 
> +  UINT32  Data32And;
> 
> +  UINT16  Address;
> 
> +
> 
> +  Data32And = 0xFFFFFFFF;
> 
> +
> 
> +  PchDmi14SrlRegData (&Address, &Data32Or);
> 
> +
> 
> +  PchPcrAndThenOr32 (
> 
> +    PID_DMI, Address,
> 
> +    Data32And,
> 
> +    Data32Or
> 
> +    );
> 
> +  PCH_PCR_BOOT_SCRIPT_READ_WRITE (
> 
> +    S3BootScriptWidthUint32,
> 
> +    PID_DMI, Address,
> 
> +    &Data32Or,
> 
> +    &Data32And
> 
> +    );
> 
> +}
> 
> +
> 
> +/**
> 
> +  Set BIOS interface Lock-Down
> 
> +**/
> 
> +VOID
> 
> +PchDmiSetBiosLockDownWithS3BootScript (
> 
> +  VOID
> 
> +  )
> 
> +{
> 
> +  UINT32  Data32Or;
> 
> +  UINT32  Data32And;
> 
> +
> 
> +  //
> 
> +  // Set BIOS Lock-Down (BILD)
> 
> +  // When set, prevents GCS.BBS from being changed
> 
> +  //
> 
> +  Data32And = 0xFFFFFFFF;
> 
> +  Data32Or = B_PCH_DMI_PCR_BILD;
> 
> +  PchPcrAndThenOr32 (PID_DMI, R_PCH_DMI_PCR_GCS, Data32And,
> Data32Or);
> 
> +  PCH_PCR_BOOT_SCRIPT_READ_WRITE (
> 
> +    S3BootScriptWidthUint32,
> 
> +    PID_DMI, R_PCH_DMI_PCR_GCS,
> 
> +    &Data32Or,
> 
> +    &Data32And
> 
> +    );
> 
> +}
> 
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSm
> mPchDmiLib/PeiDxeSmmPchDmiLib.inf
> b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSm
> mPchDmiLib/PeiDxeSmmPchDmiLib.inf
> new file mode 100644
> index 0000000000..d33310dd76
> --- /dev/null
> +++
> b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSm
> mPchDmiLib/PeiDxeSmmPchDmiLib.inf
> @@ -0,0 +1,42 @@
> +## @file
> 
> +#  Component description file for the PeiDxeSmmPchDmiLib
> 
> +#
> 
> +#  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
> 
> +#  SPDX-License-Identifier: BSD-2-Clause-Patent
> 
> +#
> 
> +##
> 
> +
> 
> +[Defines]
> 
> +INF_VERSION                    = 0x00010017
> 
> +BASE_NAME                      = PeiDxeSmmPchDmiLib
> 
> +FILE_GUID                      = 067DC1C4-2668-4F06-9921-307514B66B34
> 
> +VERSION_STRING                 = 1.0
> 
> +MODULE_TYPE                    = BASE
> 
> +LIBRARY_CLASS                  = PchDmiLib
> 
> +#
> 
> +# The following information is for reference only and not required by the
> build tools.
> 
> +#
> 
> +#  VALID_ARCHITECTURES           = IA32 X64
> 
> +#
> 
> +
> 
> +[LibraryClasses]
> 
> +  BaseLib
> 
> +  IoLib
> 
> +  DebugLib
> 
> +  PchInfoLib
> 
> +  PchPcrLib
> 
> +
> 
> +[Packages]
> 
> +  MdePkg/MdePkg.dec
> 
> +  TigerlakeSiliconPkg/SiPkg.dec
> 
> +
> 
> +
> 
> +[Sources]
> 
> +  PchDmiLib.c
> 
> +  PchDmi14.c
> 
> +  PchDmi14.h
> 
> +
> 
> +[Guids]
> 
> +  gPchDmiConfigGuid         ## CONSUMES
> 
> +
> 
> +[Pcd]
> 
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSm
> mPchDmiLib/PeiDxeSmmPchDmiWithS3Lib.inf
> b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSm
> mPchDmiLib/PeiDxeSmmPchDmiWithS3Lib.inf
> new file mode 100644
> index 0000000000..9381a7b5fd
> --- /dev/null
> +++
> b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSm
> mPchDmiLib/PeiDxeSmmPchDmiWithS3Lib.inf
> @@ -0,0 +1,41 @@
> +## @file
> 
> +#  Component description file for the PeiDxeSmmPchDmiWithS3Lib
> 
> +#
> 
> +#  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
> 
> +#  SPDX-License-Identifier: BSD-2-Clause-Patent
> 
> +#
> 
> +##
> 
> +
> 
> +[Defines]
> 
> +INF_VERSION                    = 0x00010017
> 
> +BASE_NAME                      = PeiDxeSmmPchDmiWithS3Lib
> 
> +FILE_GUID                      = 32CCA047-6AF0-46FF-83DA-32BA62484075
> 
> +VERSION_STRING                 = 1.0
> 
> +MODULE_TYPE                    = BASE
> 
> +LIBRARY_CLASS                  = PchDmiWithS3Lib
> 
> +#
> 
> +# The following information is for reference only and not required by the
> build tools.
> 
> +#
> 
> +#  VALID_ARCHITECTURES           = IA32 X64
> 
> +#
> 
> +
> 
> +[LibraryClasses]
> 
> +  BaseLib
> 
> +  IoLib
> 
> +  DebugLib
> 
> +  PchPcrLib
> 
> +  PchInfoLib
> 
> +  S3BootScriptLib
> 
> +  PchDmiLib
> 
> +
> 
> +
> 
> +[Packages]
> 
> +  MdePkg/MdePkg.dec
> 
> +  TigerlakeSiliconPkg/SiPkg.dec
> 
> +
> 
> +
> 
> +[Sources]
> 
> +  PchDmiWithS3Lib.c
> 
> +  PchDmi14.h
> 
> +
> 
> +[pcd]
> 
> --
> 2.24.0.windows.2