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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Nate DeSimone > -----Original Message----- > From: Luo, Heng > Sent: Sunday, January 31, 2021 5:37 PM > To: devel@edk2.groups.io > Cc: Chaganty, Rangasai V ; Desimone, > Nathaniel L > Subject: [PATCH 22/40] TigerlakeSiliconPkg/IpBlock: Add PchDmi component >=20 > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3171 >=20 > Adds the following files: > * IpBlock/PchDmi/IncludePrivate > * IpBlock/PchDmi/LibraryPrivate >=20 > Cc: Sai Chaganty > Cc: Nate DeSimone > Signed-off-by: Heng Luo > --- >=20 > Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/IncludePrivate/Library/P= ch > DmiLib.h | 175 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > + >=20 > Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmm > PchDmiLib/PchDmi14.c | 50 > ++++++++++++++++++++++++++++++++++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmm > PchDmiLib/PchDmi14.h | 34 > ++++++++++++++++++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmm > PchDmiLib/PchDmiLib.c | 269 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmm > PchDmiLib/PchDmiWithS3Lib.c | 73 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmm > PchDmiLib/PeiDxeSmmPchDmiLib.inf | 42 > ++++++++++++++++++++++++++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmm > PchDmiLib/PeiDxeSmmPchDmiWithS3Lib.inf | 41 > +++++++++++++++++++++++++++++++++++++++++ > 7 files changed, 684 insertions(+) >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/IncludePrivate/Library= /Pc > hDmiLib.h > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/IncludePrivate/Library= /Pc > hDmiLib.h > new file mode 100644 > index 0000000000..77db69c75a > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/IncludePrivate/Library= /Pc > hDmiLib.h > @@ -0,0 +1,175 @@ > +/** @file >=20 > + Header file for PchDmiLib. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _PCH_DMI_LIB_H_ >=20 > +#define _PCH_DMI_LIB_H_ >=20 > + >=20 > +/** >=20 > + This function checks if DMI Secured Register Lock (SRL) is set >=20 > + >=20 > + @retval SRL state >=20 > +**/ >=20 > +BOOLEAN >=20 > +IsPchDmiLocked ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Get PCH TCO base address. >=20 > + >=20 > + @retval Address Address of TCO base address. >=20 > +**/ >=20 > +UINT16 >=20 > +PchDmiGetTcoBase ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Set PCH LPC/eSPI generic IO range decoding in DMI >=20 > + >=20 > + @param[in] Address Address for generic IO range bas= e address. >=20 > + @param[in] Length Length of generic IO range. >=20 > + @param[in] RangeIndex Index of choosen range >=20 > + >=20 > + @retval EFI_SUCCESS Successfully completed. >=20 > + @retval EFI_UNSUPPORTED DMIC.SRL is set. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +PchDmiSetLpcGenIoRange ( >=20 > + IN UINT32 Address, >=20 > + IN UINT32 Length, >=20 > + IN UINT32 RangeIndex >=20 > + ); >=20 > + >=20 > +/** >=20 > + Set PCH eSPI eSPI CS1# generic IO range decoding in DMI >=20 > + >=20 > + @param[in] Address Address for generic IO range bas= e address. >=20 > + @param[in] Length Length of generic IO range. >=20 > + >=20 > + @retval EFI_SUCCESS Successfully completed. >=20 > + @retval EFI_UNSUPPORTED DMIC.SRL is set. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +PchDmiSetEspiCs1GenIoRange ( >=20 > + IN UINT32 Address, >=20 > + IN UINT32 Length >=20 > + ); >=20 > + >=20 > +/** >=20 > + Set PCH LPC/eSPI memory range decoding in DMI >=20 > + >=20 > + @param[in] Address Address for memory base address. >=20 > + >=20 > + @retval EFI_SUCCESS Successfully completed. >=20 > + @retval EFI_UNSUPPORTED DMIC.SRL is set. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +PchDmiSetLpcMemRange ( >=20 > + IN UINT32 Address >=20 > + ); >=20 > + >=20 > +/** >=20 > + Set PCH eSPI CS1# memory range decoding in DMI >=20 > + >=20 > + @param[in] Address Address for memory base address. >=20 > + >=20 > + @retval EFI_SUCCESS Successfully completed. >=20 > + @retval EFI_UNSUPPORTED DMIC.SRL is set. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +PchDmiSetEspiCs1MemRange ( >=20 > + IN UINT32 Address >=20 > + ); >=20 > + >=20 > +/** >=20 > + Check if Boot BIOS Strap is set for SPI. >=20 > + >=20 > + @retval TRUE Boot BIOS Strap set for SPI >=20 > + @retval FALSE Boot BIOS Strap set for LPC/eSPI >=20 > +**/ >=20 > +BOOLEAN >=20 > +PchDmiIsBootBiosStrapSetForSpi ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Set PCH BIOS range decoding in DMI >=20 > + Please check EDS for detail of BiosDecodeEnable bit definition. >=20 > + bit 15: F8-FF Enable >=20 > + bit 14: F0-F8 Enable >=20 > + bit 13: E8-EF Enable >=20 > + bit 12: E0-E8 Enable >=20 > + bit 11: D8-DF Enable >=20 > + bit 10: D0-D7 Enable >=20 > + bit 9: C8-CF Enable >=20 > + bit 8: C0-C7 Enable >=20 > + bit 7: Legacy F Segment Enable >=20 > + bit 6: Legacy E Segment Enable >=20 > + bit 5: Reserved >=20 > + bit 4: Reserved >=20 > + bit 3: 70-7F Enable >=20 > + bit 2: 60-6F Enable >=20 > + bit 1: 50-5F Enable >=20 > + bit 0: 40-4F Enable >=20 > + >=20 > + @param[in] BiosDecodeEnable Bios decode enable setting. >=20 > + >=20 > + @retval EFI_SUCCESS Successfully completed. >=20 > + @retval EFI_UNSUPPORTED DMIC.SRL is set. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +PchDmiSetBiosDecodeEnable ( >=20 > + IN UINT16 BiosDecodeEnable >=20 > + ); >=20 > + >=20 > +/** >=20 > + Set PCH LPC/eSPI IO decode ranges in DMI >=20 > + Please check EDS for detail of LPC/eSPI IO decode ranges bit definitio= n. >=20 > + Bit 12: FDD range >=20 > + Bit 9:8: LPT range >=20 > + Bit 6:4: ComB range >=20 > + Bit 2:0: ComA range >=20 > + >=20 > + @param[in] LpcIoDecodeRanges LPC/eSPI IO decode ranges bit > settings. >=20 > + >=20 > + @retval EFI_SUCCESS Successfully completed. >=20 > + @retval EFI_UNSUPPORTED DMIC.SRL is set. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +PchDmiSetLpcIoDecodeRanges ( >=20 > + IN UINT16 LpcIoDecodeRanges >=20 > + ); >=20 > + >=20 > +/** >=20 > + Set PCH LPC/eSPI IO enable decoding in DMI >=20 > + >=20 > + @param[in] LpcIoEnableDecoding LPC/eSPI IO enable decoding bit > settings. >=20 > + >=20 > + @retval EFI_SUCCESS Successfully completed. >=20 > + @retval EFI_UNSUPPORTED DMIC.SRL is set. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +PchDmiSetLpcIoEnable ( >=20 > + IN UINT16 LpcIoEnableDecoding >=20 > + ); >=20 > + >=20 > +/** >=20 > + Configure PCH DMI Lock >=20 > +**/ >=20 > +VOID >=20 > +PchDmiSetLockWithS3BootScript ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Set BIOS interface Lock-Down >=20 > +**/ >=20 > +VOID >=20 > +PchDmiSetBiosLockDownWithS3BootScript ( >=20 > + VOID >=20 > + ); >=20 > +#endif // _PCH_DMI_LIB_H_ >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeS= m > mPchDmiLib/PchDmi14.c > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeS= m > mPchDmiLib/PchDmi14.c > new file mode 100644 > index 0000000000..60bc29c431 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeS= m > mPchDmiLib/PchDmi14.c > @@ -0,0 +1,50 @@ > +/** @file >=20 > + This file contains functions for PCH DMI SIP14 >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +/** >=20 > + This function checks if DMI SIP14 Secured Register Lock (SRL) is set >=20 > + >=20 > + @retval SRL state >=20 > +**/ >=20 > +BOOLEAN >=20 > +IsPchDmi14Locked ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return ((PchPcrRead32 (PID_DMI, R_PCH_DMI14_PCR_DMIC) & > B_PCH_DMI14_PCR_DMIC_SRL) !=3D 0); >=20 > +} >=20 > + >=20 > +/** >=20 > + Secure Register Lock data >=20 > + >=20 > + @param[out] SrlRegOffset Register offset holding Secure Register= Lock > setting >=20 > + @param[out] SrlRegMask Mask for Secure Register Lock setting >=20 > +**/ >=20 > +VOID >=20 > +PchDmi14SrlRegData ( >=20 > + OUT UINT16 *SrlRegOffset, >=20 > + OUT UINT32 *SrlRegMask >=20 > + ) >=20 > +{ >=20 > + *SrlRegMask =3D B_PCH_DMI14_PCR_DMIC_SRL; >=20 > + *SrlRegOffset =3D R_PCH_DMI14_PCR_DMIC; >=20 > +} >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeS= m > mPchDmiLib/PchDmi14.h > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeS= m > mPchDmiLib/PchDmi14.h > new file mode 100644 > index 0000000000..4c19ad82d7 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeS= m > mPchDmiLib/PchDmi14.h > @@ -0,0 +1,34 @@ > +/** @file >=20 > + Internal header file for PCH DMI library for SIP14 >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef __PCH_DMI_14_H__ >=20 > +#define __PCH_DMI_14_H__ >=20 > + >=20 > +#include >=20 > + >=20 > +/** >=20 > + This function checks if DMI SIP14 Secured Register Lock (SRL) is set >=20 > + >=20 > + @retval SRL state >=20 > +**/ >=20 > +BOOLEAN >=20 > +IsPchDmi14Locked ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Secure Register Lock data >=20 > + >=20 > + @param[out] SrlRegOffset Register offset holding Secure Register= Lock > setting >=20 > + @param[out] SrlRegMask Mask for Secure Register Lock setting >=20 > +**/ >=20 > +VOID >=20 > +PchDmi14SrlRegData ( >=20 > + OUT UINT16 *SrlRegOffset, >=20 > + OUT UINT32 *SrlRegMask >=20 > + ); >=20 > + >=20 > +#endif >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeS= m > mPchDmiLib/PchDmiLib.c > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeS= m > mPchDmiLib/PchDmiLib.c > new file mode 100644 > index 0000000000..972e5145aa > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeS= m > mPchDmiLib/PchDmiLib.c > @@ -0,0 +1,269 @@ > +/** @file >=20 > + PCH DMI library. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +#include "PchDmi14.h" >=20 > + >=20 > +/** >=20 > + This function checks if DMI Secured Register Lock (SRL) is set >=20 > + >=20 > + @retval SRL state >=20 > +**/ >=20 > +BOOLEAN >=20 > +IsPchDmiLocked ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return IsPchDmi14Locked (); >=20 > +} >=20 > + >=20 > +/** >=20 > + Get PCH TCO base address. >=20 > + >=20 > + @retval Address Address of TCO base address. >=20 > +**/ >=20 > +UINT16 >=20 > +PchDmiGetTcoBase ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + // >=20 > + // Read "TCO Base Address" PCR[DMI] + 2778h[15:5] >=20 > + // >=20 > + return (PchPcrRead16 (PID_DMI, R_PCH_DMI_PCR_TCOBASE) & > B_PCH_DMI_PCR_TCOBASE_TCOBA); >=20 > +} >=20 > + >=20 > +/** >=20 > + Set PCH LPC/eSPI generic IO range decoding in DMI >=20 > + >=20 > + @param[in] Address Address for generic IO range bas= e address. >=20 > + @param[in] Length Length of generic IO range. >=20 > + @param[in] RangeIndex Index of choosen range >=20 > + >=20 > + @retval EFI_SUCCESS Successfully completed. >=20 > + @retval EFI_UNSUPPORTED DMIC.SRL is set. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +PchDmiSetLpcGenIoRange ( >=20 > + IN UINT32 Address, >=20 > + IN UINT32 Length, >=20 > + IN UINT32 RangeIndex >=20 > + ) >=20 > +{ >=20 > + return EFI_UNSUPPORTED; >=20 > +} >=20 > + >=20 > +/** >=20 > + Set PCH eSPI eSPI CS1# generic IO range decoding in DMI >=20 > + >=20 > + @param[in] Address Address for generic IO range bas= e address. >=20 > + @param[in] Length Length of generic IO range. >=20 > + >=20 > + @retval EFI_SUCCESS Successfully completed. >=20 > + @retval EFI_UNSUPPORTED DMIC.SRL is set. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +PchDmiSetEspiCs1GenIoRange ( >=20 > + IN UINT32 Address, >=20 > + IN UINT32 Length >=20 > + ) >=20 > +{ >=20 > + return EFI_UNSUPPORTED; >=20 > +} >=20 > + >=20 > +/** >=20 > + Set PCH LPC/eSPI memory range decoding in DMI >=20 > + >=20 > + @param[in] Address Address for memory base address. >=20 > + >=20 > + @retval EFI_SUCCESS Successfully completed. >=20 > + @retval EFI_UNSUPPORTED DMIC.SRL is set. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +PchDmiSetLpcMemRange ( >=20 > + IN UINT32 Address >=20 > + ) >=20 > +{ >=20 > + if (IsPchDmiLocked ()) { >=20 > + DEBUG ((DEBUG_ERROR, "%a Error. DMI is locked.\n", __FUNCTION__)); >=20 > + ASSERT (FALSE); >=20 > + return EFI_UNSUPPORTED; >=20 > + } >=20 > + >=20 > + // >=20 > + // Program LPC Memory Range, PCR[DMI] + 2740h to the same value > programmed in LPC/eSPI PCI Offset 98h. >=20 > + // >=20 > + PchPcrWrite32 ( >=20 > + PID_DMI, R_PCH_DMI_PCR_LPCGMR, >=20 > + (Address | B_LPC_CFG_LGMR_LMRD_EN) >=20 > + ); >=20 > + >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > +/** >=20 > + Set PCH eSPI CS1# memory range decoding in DMI >=20 > + >=20 > + @param[in] Address Address for memory base address. >=20 > + >=20 > + @retval EFI_SUCCESS Successfully completed. >=20 > + @retval EFI_UNSUPPORTED DMIC.SRL is set. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +PchDmiSetEspiCs1MemRange ( >=20 > + IN UINT32 Address >=20 > + ) >=20 > +{ >=20 > + if (IsPchDmiLocked ()) { >=20 > + DEBUG ((DEBUG_ERROR, "%a Error. DMI is locked.\n", __FUNCTION__)); >=20 > + ASSERT (FALSE); >=20 > + return EFI_UNSUPPORTED; >=20 > + } >=20 > + >=20 > + // >=20 > + // Program LPC Memory Range, PCR[DMI] + 27C0h to the same value > programmed in eSPI PCI Offset A8h. >=20 > + // >=20 > + PchPcrWrite32 ( >=20 > + PID_DMI, R_PCH_DMI_PCR_SEGMR, >=20 > + (Address | B_LPC_CFG_LGMR_LMRD_EN) >=20 > + ); >=20 > + >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > +/** >=20 > + Check if Boot BIOS Strap is set for SPI. >=20 > + >=20 > + @retval TRUE Boot BIOS Strap set for SPI >=20 > + @retval FALSE Boot BIOS Strap set for LPC/eSPI >=20 > +**/ >=20 > +BOOLEAN >=20 > +PchDmiIsBootBiosStrapSetForSpi ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + // >=20 > + // Check General Control and Status (GCS) [10] >=20 > + // '0': SPI >=20 > + // '1': LPC/eSPI >=20 > + // >=20 > + return ((PchPcrRead32 (PID_DMI, R_PCH_DMI_PCR_GCS) & > B_PCH_DMI_PCR_BBS) !=3D B_PCH_DMI_PCR_BBS); >=20 > +} >=20 > + >=20 > +/** >=20 > + Set PCH BIOS range decoding in DMI >=20 > + Please check EDS for detail of BiosDecodeEnable bit definition. >=20 > + bit 15: F8-FF Enable >=20 > + bit 14: F0-F8 Enable >=20 > + bit 13: E8-EF Enable >=20 > + bit 12: E0-E8 Enable >=20 > + bit 11: D8-DF Enable >=20 > + bit 10: D0-D7 Enable >=20 > + bit 9: C8-CF Enable >=20 > + bit 8: C0-C7 Enable >=20 > + bit 7: Legacy F Segment Enable >=20 > + bit 6: Legacy E Segment Enable >=20 > + bit 5: Reserved >=20 > + bit 4: Reserved >=20 > + bit 3: 70-7F Enable >=20 > + bit 2: 60-6F Enable >=20 > + bit 1: 50-5F Enable >=20 > + bit 0: 40-4F Enable >=20 > + >=20 > + @param[in] BiosDecodeEnable Bios decode enable setting. >=20 > + >=20 > + @retval EFI_SUCCESS Successfully completed. >=20 > + @retval EFI_UNSUPPORTED DMIC.SRL is set. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +PchDmiSetBiosDecodeEnable ( >=20 > + IN UINT16 BiosDecodeEnable >=20 > + ) >=20 > +{ >=20 > + if (IsPchDmiLocked ()) { >=20 > + ASSERT (FALSE); >=20 > + return EFI_UNSUPPORTED; >=20 > + } >=20 > + >=20 > + // >=20 > + // program LPC BIOS Decode Enable, PCR[DMI] + 2744h to the same value > programmed in LPC or SPI Offset D8h. >=20 > + // >=20 > + PchPcrWrite16 (PID_DMI, R_PCH_DMI_PCR_LPCBDE, BiosDecodeEnable); >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > +/** >=20 > + Set PCH LPC/eSPI IO decode ranges in DMI >=20 > + Please check EDS for detail of LPC/eSPI IO decode ranges bit definitio= n. >=20 > + Bit 12: FDD range >=20 > + Bit 9:8: LPT range >=20 > + Bit 6:4: ComB range >=20 > + Bit 2:0: ComA range >=20 > + >=20 > + @param[in] LpcIoDecodeRanges LPC/eSPI IO decode ranges bit > settings. >=20 > + >=20 > + @retval EFI_SUCCESS Successfully completed. >=20 > + @retval EFI_UNSUPPORTED DMIC.SRL is set. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +PchDmiSetLpcIoDecodeRanges ( >=20 > + IN UINT16 LpcIoDecodeRanges >=20 > + ) >=20 > +{ >=20 > + // >=20 > + // This cycle decoding is only allowed to set when DMI is not locked. >=20 > + // >=20 > + if (IsPchDmiLocked ()) { >=20 > + ASSERT (FALSE); >=20 > + return EFI_UNSUPPORTED; >=20 > + } >=20 > + >=20 > + // >=20 > + // program LPC I/O Decode Ranges, PCR[DMI] + 2770h[15:0] to the same > value programmed in LPC/eSPI PCI offset 80h. >=20 > + // >=20 > + PchPcrWrite16 (PID_DMI, R_PCH_DMI_PCR_LPCIOD, > LpcIoDecodeRanges); >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > +/** >=20 > + Set PCH LPC/eSPI IO enable decoding in DMI >=20 > + >=20 > + @param[in] LpcIoEnableDecoding LPC/eSPI IO enable decoding bit > settings. >=20 > + >=20 > + @retval EFI_SUCCESS Successfully completed. >=20 > + @retval EFI_UNSUPPORTED DMIC.SRL is set. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +PchDmiSetLpcIoEnable ( >=20 > + IN UINT16 LpcIoEnableDecoding >=20 > + ) >=20 > +{ >=20 > + // >=20 > + // This cycle decoding is only allowed to set when DMI is not locked. >=20 > + // >=20 > + if (IsPchDmiLocked ()) { >=20 > + ASSERT (FALSE); >=20 > + return EFI_UNSUPPORTED; >=20 > + } >=20 > + >=20 > + // >=20 > + // program LPC I/O Decode Ranges, PCR[DMI] + 2774h[15:0] to the same > value programmed in LPC/eSPI PCI offset 82h. >=20 > + // >=20 > + PchPcrWrite16 (PID_DMI, R_PCH_DMI_PCR_LPCIOE, > LpcIoEnableDecoding); >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeS= m > mPchDmiLib/PchDmiWithS3Lib.c > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeS= m > mPchDmiLib/PchDmiWithS3Lib.c > new file mode 100644 > index 0000000000..7d6801ee57 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeS= m > mPchDmiLib/PchDmiWithS3Lib.c > @@ -0,0 +1,73 @@ > +/** @file >=20 > + PCH DMI library with S3 boot script support. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +#include "PchDmi14.h" >=20 > + >=20 > +/** >=20 > + Configure DMI Lock >=20 > +**/ >=20 > +VOID >=20 > +PchDmiSetLockWithS3BootScript ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + UINT32 Data32Or; >=20 > + UINT32 Data32And; >=20 > + UINT16 Address; >=20 > + >=20 > + Data32And =3D 0xFFFFFFFF; >=20 > + >=20 > + PchDmi14SrlRegData (&Address, &Data32Or); >=20 > + >=20 > + PchPcrAndThenOr32 ( >=20 > + PID_DMI, Address, >=20 > + Data32And, >=20 > + Data32Or >=20 > + ); >=20 > + PCH_PCR_BOOT_SCRIPT_READ_WRITE ( >=20 > + S3BootScriptWidthUint32, >=20 > + PID_DMI, Address, >=20 > + &Data32Or, >=20 > + &Data32And >=20 > + ); >=20 > +} >=20 > + >=20 > +/** >=20 > + Set BIOS interface Lock-Down >=20 > +**/ >=20 > +VOID >=20 > +PchDmiSetBiosLockDownWithS3BootScript ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + UINT32 Data32Or; >=20 > + UINT32 Data32And; >=20 > + >=20 > + // >=20 > + // Set BIOS Lock-Down (BILD) >=20 > + // When set, prevents GCS.BBS from being changed >=20 > + // >=20 > + Data32And =3D 0xFFFFFFFF; >=20 > + Data32Or =3D B_PCH_DMI_PCR_BILD; >=20 > + PchPcrAndThenOr32 (PID_DMI, R_PCH_DMI_PCR_GCS, Data32And, > Data32Or); >=20 > + PCH_PCR_BOOT_SCRIPT_READ_WRITE ( >=20 > + S3BootScriptWidthUint32, >=20 > + PID_DMI, R_PCH_DMI_PCR_GCS, >=20 > + &Data32Or, >=20 > + &Data32And >=20 > + ); >=20 > +} >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeS= m > mPchDmiLib/PeiDxeSmmPchDmiLib.inf > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeS= m > mPchDmiLib/PeiDxeSmmPchDmiLib.inf > new file mode 100644 > index 0000000000..d33310dd76 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeS= m > mPchDmiLib/PeiDxeSmmPchDmiLib.inf > @@ -0,0 +1,42 @@ > +## @file >=20 > +# Component description file for the PeiDxeSmmPchDmiLib >=20 > +# >=20 > +# Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > +# SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +# >=20 > +## >=20 > + >=20 > +[Defines] >=20 > +INF_VERSION =3D 0x00010017 >=20 > +BASE_NAME =3D PeiDxeSmmPchDmiLib >=20 > +FILE_GUID =3D 067DC1C4-2668-4F06-9921-307514B66B34 >=20 > +VERSION_STRING =3D 1.0 >=20 > +MODULE_TYPE =3D BASE >=20 > +LIBRARY_CLASS =3D PchDmiLib >=20 > +# >=20 > +# The following information is for reference only and not required by th= e > build tools. >=20 > +# >=20 > +# VALID_ARCHITECTURES =3D IA32 X64 >=20 > +# >=20 > + >=20 > +[LibraryClasses] >=20 > + BaseLib >=20 > + IoLib >=20 > + DebugLib >=20 > + PchInfoLib >=20 > + PchPcrLib >=20 > + >=20 > +[Packages] >=20 > + MdePkg/MdePkg.dec >=20 > + TigerlakeSiliconPkg/SiPkg.dec >=20 > + >=20 > + >=20 > +[Sources] >=20 > + PchDmiLib.c >=20 > + PchDmi14.c >=20 > + PchDmi14.h >=20 > + >=20 > +[Guids] >=20 > + gPchDmiConfigGuid ## CONSUMES >=20 > + >=20 > +[Pcd] >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeS= m > mPchDmiLib/PeiDxeSmmPchDmiWithS3Lib.inf > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeS= m > mPchDmiLib/PeiDxeSmmPchDmiWithS3Lib.inf > new file mode 100644 > index 0000000000..9381a7b5fd > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeS= m > mPchDmiLib/PeiDxeSmmPchDmiWithS3Lib.inf > @@ -0,0 +1,41 @@ > +## @file >=20 > +# Component description file for the PeiDxeSmmPchDmiWithS3Lib >=20 > +# >=20 > +# Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > +# SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +# >=20 > +## >=20 > + >=20 > +[Defines] >=20 > +INF_VERSION =3D 0x00010017 >=20 > +BASE_NAME =3D PeiDxeSmmPchDmiWithS3Lib >=20 > +FILE_GUID =3D 32CCA047-6AF0-46FF-83DA-32BA62484075 >=20 > +VERSION_STRING =3D 1.0 >=20 > +MODULE_TYPE =3D BASE >=20 > +LIBRARY_CLASS =3D PchDmiWithS3Lib >=20 > +# >=20 > +# The following information is for reference only and not required by th= e > build tools. >=20 > +# >=20 > +# VALID_ARCHITECTURES =3D IA32 X64 >=20 > +# >=20 > + >=20 > +[LibraryClasses] >=20 > + BaseLib >=20 > + IoLib >=20 > + DebugLib >=20 > + PchPcrLib >=20 > + PchInfoLib >=20 > + S3BootScriptLib >=20 > + PchDmiLib >=20 > + >=20 > + >=20 > +[Packages] >=20 > + MdePkg/MdePkg.dec >=20 > + TigerlakeSiliconPkg/SiPkg.dec >=20 > + >=20 > + >=20 > +[Sources] >=20 > + PchDmiWithS3Lib.c >=20 > + PchDmi14.h >=20 > + >=20 > +[pcd] >=20 > -- > 2.24.0.windows.2