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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hi Heng, Please see comments inline. Thanks, Nate > -----Original Message----- > From: Luo, Heng > Sent: Sunday, January 31, 2021 5:37 PM > To: devel@edk2.groups.io > Cc: Chaganty, Rangasai V ; Desimone, > Nathaniel L > Subject: [PATCH 39/40] TigerlakeSiliconPkg: Add package DSC files >=20 > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3171 >=20 > Cc: Sai Chaganty > Cc: Nate DeSimone > Signed-off-by: Heng Luo > --- > Silicon/Intel/TigerlakeSiliconPkg/SiPkgBuildOption.dsc | 122 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++ > Silicon/Intel/TigerlakeSiliconPkg/SiPkgCommonLib.dsc | 49 > +++++++++++++++++++++++++++++++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/SiPkgDxe.dsc | 47 > +++++++++++++++++++++++++++++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/SiPkgDxeLib.dsc | 40 > ++++++++++++++++++++++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/SiPkgPei.dsc | 20 > ++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/SiPkgPeiLib.dsc | 20 > ++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/TigerlakeSiliconPkg.dsc | 229 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++++++++++++++++++++++++++++ > 7 files changed, 527 insertions(+) >=20 > diff --git a/Silicon/Intel/TigerlakeSiliconPkg/SiPkgBuildOption.dsc > b/Silicon/Intel/TigerlakeSiliconPkg/SiPkgBuildOption.dsc > new file mode 100644 > index 0000000000..51c40812ea > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/SiPkgBuildOption.dsc > @@ -0,0 +1,122 @@ > +## @file >=20 > +# Silicon build option configuration file. >=20 > +# >=20 > +# Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > +# SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +# >=20 > +## >=20 > + >=20 > +[BuildOptions] >=20 > +# Define Build Options both for EDK and EDKII drivers. >=20 > + >=20 > + DEFINE PCH_BUILD_OPTIONS =3D -DPCH_TGL >=20 > +# >=20 > +# SA >=20 > +# >=20 > +!if gSiPkgTokenSpaceGuid.PcdBdatEnable =3D=3D TRUE >=20 > + DEFINE BDAT_BUILD_OPTION =3D -DBDAT_SUPPORT=3D1 >=20 > +!else >=20 > + DEFINE BDAT_BUILD_OPTION =3D >=20 > +!endif >=20 > + >=20 > + DEFINE SLE_BUILD_OPTIONS =3D >=20 > +!if $(TARGET) =3D=3D RELEASE >=20 > +!if gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable =3D=3D TRUE >=20 > + DEFINE DEBUG_BUILD_OPTIONS =3D >=20 > +!else >=20 > + # MDEPKG_NDEBUG is introduced for the intention >=20 > + # of size reduction when compiler optimization is disabled. If > MDEPKG_NDEBUG is >=20 > + # defined, then debug and assert related macros wrapped by it are the > NULL implementations. >=20 > + DEFINE DEBUG_BUILD_OPTIONS =3D -DMDEPKG_NDEBUG >=20 > +!endif >=20 > +!else >=20 > + DEFINE DEBUG_BUILD_OPTIONS =3D >=20 > +!endif >=20 > + >=20 > +!if ($(TARGET) =3D=3D RELEASE) AND > (gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable =3D=3D TRUE) >=20 > + DEFINE RELEASE_CATALOG_BUILD_OPTIONS =3D -DRELEASE_CATALOG >=20 > +!else >=20 > + DEFINE RELEASE_CATALOG_BUILD_OPTIONS =3D >=20 > +!endif >=20 > + >=20 > +!if gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable =3D=3D FALSE >=20 > + DEFINE OPTIMIZE_DISABLE_OPTIONS =3D -Od -GL- >=20 > +!else >=20 > + DEFINE OPTIMIZE_DISABLE_OPTIONS =3D >=20 > +!endif >=20 > + >=20 > + DEFINE HSLE_BUILD_OPTIONS =3D >=20 > + >=20 > + >=20 > + DEFINE CPU_FLAGS =3D -DCPU_ICL -DCPU_TGL >=20 > + >=20 > + >=20 > + DEFINE RESTRICTED_OPTION =3D >=20 > + >=20 > +!if gSiPkgTokenSpaceGuid.PcdMrcTraceMessageSupported =3D=3D FALSE >=20 > + *_*_*_MRC_NDEBUG =3D -DMDEPKG_NDEBUG >=20 > +!endif >=20 > + >=20 > +DEFINE DSC_SIPKG_FEATURE_BUILD_OPTIONS =3D $(BDAT_BUILD_OPTION) > $(DEBUG_BUILD_OPTIONS) >=20 > +DEFINE DSC_SIPKG_FEATURE_BUILD_OPTIONS =3D > $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(PCH_BUILD_OPTIONS) > $(CPU_FLAGS) $(HSLE_BUILD_OPTIONS) >=20 > + >=20 > +!if gSiPkgTokenSpaceGuid.PcdSourceDebugEnable =3D=3D TRUE >=20 > + *_*_X64_GENFW_FLAGS =3D --keepexceptiontable >=20 > +!endif >=20 > + >=20 > +[BuildOptions.Common.EDKII] >=20 > + >=20 > +# >=20 > +# For IA32 Global Build Flag >=20 > +# >=20 > + *_*_IA32_CC_FLAGS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) -D > PI_SPECIFICATION_VERSION=3D0x00010015 -DASF_PEI >=20 > + *_*_IA32_VFRPP_FLAGS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) >=20 > + *_*_IA32_APP_FLAGS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) >=20 > + *_*_IA32_ASLPP_FLAGS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) >=20 > + *_*_IA32_ASLCC_FLAGS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) >=20 > + >=20 > +# >=20 > +# For IA32 Specific Build Flag >=20 > +# >=20 > +GCC: *_*_IA32_PP_FLAGS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) >=20 > +MSFT: *_*_IA32_ASM_FLAGS =3D > $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) >=20 > +MSFT: *_*_IA32_CC_FLAGS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) > $(OPTIMIZE_DISABLE_OPTIONS) -D > PI_SPECIFICATION_VERSION=3D0x00010015 -DASF_PEI /w34668 >=20 > +MSFT: *_*_IA32_VFRPP_FLAGS =3D > $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS) >=20 > +MSFT: *_*_IA32_APP_FLAGS =3D > $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS) >=20 > +MSFT: *_*_IA32_ASLPP_FLAGS =3D > $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS) >=20 > +MSFT: *_*_IA32_ASLCC_FLAGS =3D > $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS) >=20 > + >=20 > +# >=20 > +# For X64 Global Build Flag >=20 > +# >=20 > + *_*_X64_CC_FLAGS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) -D > PI_SPECIFICATION_VERSION=3D0x00010015 >=20 > + *_*_X64_VFRPP_FLAGS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) >=20 > + *_*_X64_APP_FLAGS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) >=20 > + *_*_X64_ASLPP_FLAGS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) >=20 > + *_*_X64_ASLCC_FLAGS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) >=20 > + >=20 > +# >=20 > +# For X64 Specific Build Flag >=20 > +# >=20 > +GCC: *_*_X64_PP_FLAGS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) >=20 > +MSFT: *_*_X64_ASM_FLAGS =3D > $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) >=20 > +MSFT: *_*_X64_CC_FLAGS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) > $(OPTIMIZE_DISABLE_OPTIONS) -D > PI_SPECIFICATION_VERSION=3D0x00010015 /w34668 >=20 > +MSFT: *_*_X64_VFRPP_FLAGS =3D > $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS) >=20 > +MSFT: *_*_X64_APP_FLAGS =3D > $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS) >=20 > +MSFT: *_*_X64_ASLPP_FLAGS =3D > $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) >=20 > +MSFT: *_*_X64_ASLCC_FLAGS =3D > $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) >=20 > + >=20 > +# >=20 > +# For Xcode Specific Build Flag >=20 > +# >=20 > +# Override assembly code build order >=20 > +*_XCODE5_*_*_BUILDRULEORDER =3D nasm S s >=20 > +# Align 47bfbd7f8069e523798ef973c8eb0abd5c6b0746 to fix the usage of > VA_START in undefined way >=20 > +*_XCODE5_*_CC_FLAGS =3D -Wno-varargs >=20 > + >=20 > +# Force PE/COFF sections to be aligned at 4KB boundaries to support page > level protection of runtime modules >=20 > +[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER] >=20 > + MSFT: *_*_*_DLINK_FLAGS =3D /ALIGN:4096 >=20 > + GCC: *_GCC*_*_DLINK_FLAGS =3D -z common-page-size=3D0x1000 >=20 > + >=20 > + >=20 > diff --git a/Silicon/Intel/TigerlakeSiliconPkg/SiPkgCommonLib.dsc > b/Silicon/Intel/TigerlakeSiliconPkg/SiPkgCommonLib.dsc > new file mode 100644 > index 0000000000..d93ecfc9d6 > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/SiPkgCommonLib.dsc > @@ -0,0 +1,49 @@ > +## @file >=20 > +# Component description file for the TigerLake silicon package both Pei= and > Dxe libraries DSC file. >=20 > +# >=20 > +# Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > +# SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +# >=20 > +## >=20 > + >=20 > +# >=20 > +# Set PCH generation according PCD. >=20 > +# The DEFINE will be used to select PCH library INF file corresponding t= o PCH > generation >=20 > +# >=20 > +DEFINE PCH =3D Cnl This define is not used. Please delete it. >=20 > + >=20 > +# >=20 > +# FRUs >=20 > +# >=20 > +!include $(PLATFORM_SI_PACKAGE)/Fru/TglCpu/CommonLib.dsc >=20 > +!include $(PLATFORM_SI_PACKAGE)/Fru/TglPch/CommonLib.dsc >=20 > + >=20 > +# >=20 > +# Common >=20 > +# >=20 > + > MmPciLib|$(PLATFORM_SI_PACKAGE)/Library/PeiDxeSmmMmPciLib/PeiDx > eSmmMmPciLib.inf >=20 > + > PciSegmentLib|$(PLATFORM_SI_PACKAGE)/Library/BasePciSegmentMultiSe > gLibPci/BasePciSegmentMultiSegLibPci.inf >=20 > + >=20 > +# >=20 > +# Pch >=20 > +# >=20 > + > PchCycleDecodingLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmP > chCycleDecodingLib/PeiDxeSmmPchCycleDecodingLib.inf >=20 > + > PchInfoLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmPchInfoLib/ > PeiDxeSmmPchInfoLibTgl.inf >=20 > + > CpuPcieInitCommonLib|$(PLATFORM_SI_PACKAGE)/IpBlock/CpuPcieRp/Libr > ary/PeiDxeSmmCpuPcieInitCommonLib/PeiDxeSmmCpuPcieInitCommonLib.i > nf >=20 > + > CpuPcieRpLib|$(PLATFORM_SI_PACKAGE)/IpBlock/CpuPcieRp/Library/PeiDx > eSmmCpuPcieRpLib/PeiDxeSmmCpuPcieRpLib.inf >=20 > + >=20 > + > SerialIoAccessLib|$(PLATFORM_SI_PACKAGE)/IpBlock/SerialIo/Library/PeiDx > eSmmSerialIoAccessLib/PeiDxeSmmSerialIoAccessLib.inf >=20 > + > SerialIoPrivateLib|$(PLATFORM_SI_PACKAGE)/IpBlock/SerialIo/LibraryPrivat > e/PeiDxeSmmSerialIoPrivateLib/PeiDxeSmmSerialIoPrivateLibVer2.inf >=20 > + > ResetSystemLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/BaseResetSystem > Lib/BaseResetSystemLib.inf >=20 > + #private >=20 > + > GpioPrivateLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Gpio/LibraryPrivate/Pei > DxeSmmGpioPrivateLib/PeiDxeSmmGpioPrivateLibVer2.inf >=20 > + >=20 > + > SiScheduleResetLib|$(PLATFORM_SI_PACKAGE)/Pch/LibraryPrivate/BaseSiS > cheduleResetLib/BaseSiScheduleResetLib.inf >=20 > + > PchPciBdfLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/BasePchPciBdfLib/Bas > ePchPciBdfLib.inf >=20 > + > PcieRpLib|$(PLATFORM_SI_PACKAGE)/IpBlock/PcieRp/LibraryPrivate/PcieCli > entRpLib/PcieClientRpLib.inf >=20 > + >=20 > +# >=20 > +# SA >=20 > +# >=20 > + > SaPlatformLib|$(PLATFORM_SI_PACKAGE)/SystemAgent/Library/PeiDxeSm > mSaPlatformLib/PeiDxeSmmSaPlatformLib.inf >=20 > + > CpuRegbarAccessLib|$(PLATFORM_SI_PACKAGE)/IpBlock/P2sb/Library/PeiD > xeSmmCpuRegbarAccessLib/PeiDxeSmmCpuRegbarAccessLib.inf >=20 > diff --git a/Silicon/Intel/TigerlakeSiliconPkg/SiPkgDxe.dsc > b/Silicon/Intel/TigerlakeSiliconPkg/SiPkgDxe.dsc > new file mode 100644 > index 0000000000..1a08fbc24c > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/SiPkgDxe.dsc > @@ -0,0 +1,47 @@ > +## @file >=20 > +# Component description file for the TigerLake silicon package DXE driv= ers. >=20 > +# >=20 > +# Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > +# SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +# >=20 > +## >=20 > + >=20 > +# >=20 > +# FRUs >=20 > +# >=20 > +!include $(PLATFORM_SI_PACKAGE)/Fru/TglCpu/Dxe.dsc >=20 > +!include $(PLATFORM_SI_PACKAGE)/Fru/TglPch/Dxe.dsc >=20 > + >=20 > +# >=20 > +# Common >=20 > +# >=20 > + >=20 > +# >=20 > +# Pch >=20 > +# >=20 > + $(PLATFORM_SI_PACKAGE)/Pch/PchInit/Dxe/PchInitDxeTgl.inf >=20 > + > $(PLATFORM_SI_PACKAGE)/Pch/SmmControl/RuntimeDxe/SmmControl.inf >=20 > + >=20 > + > $(PLATFORM_SI_PACKAGE)/Pch/PchSmiDispatcher/Smm/PchSmiDispatcher. > inf{ >=20 > + >=20 > + > #SmiHandlerProfileLib|MdeModulePkg/Library/SmmSmiHandlerProfileLib/S > mmSmiHandlerProfileLib.inf >=20 > + > SmiHandlerProfileLib|MdePkg/Library/SmiHandlerProfileLibNull/SmiHandler > ProfileLibNull.inf >=20 > + } >=20 > + $(PLATFORM_SI_PACKAGE)/Pch/PchInit/Smm/PchInitSmm.inf >=20 > + >=20 > +# >=20 > +# SystemAgent >=20 > +# >=20 > + >=20 > + $(PLATFORM_SI_PACKAGE)/SystemAgent/SaInit/Dxe/SaInitDxe.inf >=20 > + >=20 > + $(PLATFORM_SI_PACKAGE)/SystemAgent/SaInit/Smm/SaLateInitSmm.inf > { >=20 > + >=20 > + > S3BootScriptLib|MdePkg/Library/BaseS3BootScriptLibNull/BaseS3BootScriptL > ibNull.inf >=20 > + } >=20 > + >=20 > +!if gSiPkgTokenSpaceGuid.PcdAcpiEnable =3D=3D TRUE >=20 > + $(PLATFORM_SI_PACKAGE)/SystemAgent/AcpiTables/SaSsdt/SaSsdt.inf >=20 > + $(PLATFORM_SI_PACKAGE)/IpBlock/Graphics/AcpiTables/IgfxSsdt.inf >=20 > +!endif >=20 > + >=20 > diff --git a/Silicon/Intel/TigerlakeSiliconPkg/SiPkgDxeLib.dsc > b/Silicon/Intel/TigerlakeSiliconPkg/SiPkgDxeLib.dsc > new file mode 100644 > index 0000000000..210fb37332 > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/SiPkgDxeLib.dsc > @@ -0,0 +1,40 @@ > +## @file >=20 > +# Component description file for the TigerLake silicon package DXE libr= aries. >=20 > +# >=20 > +# Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > +# SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +# >=20 > +## >=20 > + >=20 > +# >=20 > +# Silicon Init Dxe Library >=20 > +# >=20 > + >=20 > +# >=20 > +# FRUs >=20 > +# >=20 > +!include $(PLATFORM_SI_PACKAGE)/Fru/TglCpu/DxeLib.dsc >=20 > +!include $(PLATFORM_SI_PACKAGE)/Fru/TglPch/DxeLib.dsc >=20 > + >=20 > +# >=20 > +# Common >=20 > +# >=20 > +SiConfigBlockLib|$(PLATFORM_SI_PACKAGE)/Library/BaseSiConfigBlockLib/ > BaseSiConfigBlockLib.inf >=20 > + >=20 > +# >=20 > +# Pch >=20 > +# >=20 > +DxePchPolicyLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/DxePchPolicyLib/ > DxePchPolicyLib.inf >=20 > +SmmPchPrivateLib|$(PLATFORM_SI_PACKAGE)/Pch/LibraryPrivate/SmmPc > hPrivateLib/SmmPchPrivateLib.inf >=20 > + >=20 > +# >=20 > +# SystemAgent >=20 > +# >=20 > +DxeSaPolicyLib|$(PLATFORM_SI_PACKAGE)/SystemAgent/Library/DxeSaP > olicyLib/DxeSaPolicyLib.inf >=20 > +DxeVtdPolicyLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Vtd/LibraryPrivate/D > xeVtdPolicyLib/DxeVtdPolicyLib.inf >=20 > + >=20 > +# >=20 > +# CPU PCIe IpBlock >=20 > +# >=20 > + >=20 > +DxeCpuPcieRpLib|$(PLATFORM_SI_PACKAGE)/IpBlock/CpuPcieRp/LibraryP > rivate/DxeCpuPcieRpLib/DxeCpuPcieRpLib.inf >=20 > diff --git a/Silicon/Intel/TigerlakeSiliconPkg/SiPkgPei.dsc > b/Silicon/Intel/TigerlakeSiliconPkg/SiPkgPei.dsc > new file mode 100644 > index 0000000000..15fc5685a5 > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/SiPkgPei.dsc > @@ -0,0 +1,20 @@ > +## @file >=20 > +# Component description file for the TigerLake silicon package PEI driv= ers. >=20 > +# >=20 > +# Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > +# SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +# >=20 > +## >=20 > + >=20 > +# >=20 > +# Common >=20 > +# >=20 > + >=20 > +# >=20 > +# SystemAgent >=20 > +# >=20 > + >=20 > +# >=20 > +# Cpu >=20 > +# >=20 > + >=20 > diff --git a/Silicon/Intel/TigerlakeSiliconPkg/SiPkgPeiLib.dsc > b/Silicon/Intel/TigerlakeSiliconPkg/SiPkgPeiLib.dsc > new file mode 100644 > index 0000000000..6f90ff02bb > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/SiPkgPeiLib.dsc > @@ -0,0 +1,20 @@ > +## @file >=20 > +# Component description file for the TigerLake silicon package PEI libr= aries. >=20 > +# >=20 > +# Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > +# SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +# >=20 > +## >=20 > + >=20 > +# >=20 > +# Silicon Init Pei Library >=20 > +# >=20 > + >=20 > +# >=20 > +# FRUs >=20 > +# >=20 > +!include $(PLATFORM_SI_PACKAGE)/Fru/TglCpu/PeiLib.dsc >=20 > + >=20 > +!include $(PLATFORM_SI_PACKAGE)/Fru/TglPch/PeiLib.dsc >=20 > + >=20 > + > SiConfigBlockLib|$(PLATFORM_SI_PACKAGE)/Library/BaseSiConfigBlockLib/B > aseSiConfigBlockLib.inf >=20 > diff --git a/Silicon/Intel/TigerlakeSiliconPkg/TigerlakeSiliconPkg.dsc > b/Silicon/Intel/TigerlakeSiliconPkg/TigerlakeSiliconPkg.dsc > new file mode 100644 > index 0000000000..73a2594887 > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/TigerlakeSiliconPkg.dsc > @@ -0,0 +1,229 @@ > +## @file >=20 > +# Component description file for the TigerLake silicon package DSC file= . >=20 > +# >=20 > +# Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > +# SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +# >=20 > +## >=20 > +[Packages] >=20 > +MdePkg/MdePkg.dec >=20 > +UefiCpuPkg/UefiCpuPkg.dec >=20 > +TigerlakeSiliconPkg/SiPkg.dec >=20 > + >=20 > +[PcdsFixedAtBuild] >=20 > +gSiPkgTokenSpaceGuid.PcdSmmVariableEnable |TRUE >=20 > +gSiPkgTokenSpaceGuid.PcdAtaEnable |FALSE >=20 > + >=20 > +gSiPkgTokenSpaceGuid.PcdAcpiEnable |TRUE >=20 > +gSiPkgTokenSpaceGuid.PcdSourceDebugEnable |FALSE >=20 > +gSiPkgTokenSpaceGuid.PcdPpmEnable |TRUE >=20 > +gSiPkgTokenSpaceGuid.PcdPttEnable |FALSE >=20 > +gSiPkgTokenSpaceGuid.PcdJhiEnable |FALSE >=20 > +gSiPkgTokenSpaceGuid.PcdSmbiosEnable |TRUE >=20 > +gSiPkgTokenSpaceGuid.PcdS3Enable |TRUE >=20 > +gSiPkgTokenSpaceGuid.PcdOverclockEnable |FALSE >=20 > +gSiPkgTokenSpaceGuid.PcdCpuPowerOnConfigEnable |FALSE >=20 > +gSiPkgTokenSpaceGuid.PcdBdatEnable |TRUE >=20 > +gSiPkgTokenSpaceGuid.PcdIgdEnable |TRUE >=20 > +gSiPkgTokenSpaceGuid.PcdPegEnable |TRUE >=20 > +gSiPkgTokenSpaceGuid.PcdSaDmiEnable |TRUE >=20 > +gSiPkgTokenSpaceGuid.PcdVtdEnable |TRUE >=20 > +gSiPkgTokenSpaceGuid.PcdBiosGuardEnable |FALSE > #BiosGuardModule.bin >=20 > +gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable |TRUE >=20 > +gSiPkgTokenSpaceGuid.PcdPeiDisplayEnable |TRUE >=20 > +gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable |FALSE >=20 > +gSiPkgTokenSpaceGuid.PcdMrcTraceMessageSupported |TRUE >=20 > +gSiPkgTokenSpaceGuid.PcdOcWdtEnable |TRUE >=20 > +gSiPkgTokenSpaceGuid.PcdSerialIoUartEnable |TRUE >=20 > + >=20 > +gSiPkgTokenSpaceGuid.PcdThcEnable |TRUE >=20 > +gSiPkgTokenSpaceGuid.PcdPpamEnable |TRUE >=20 > +gSiPkgTokenSpaceGuid.PcdEmbeddedEnable |0x0 >=20 > +gSiPkgTokenSpaceGuid.PcdCpuPcieEnable |TRUE >=20 > +gSiPkgTokenSpaceGuid.PcdHybridStorageSupport |TRUE >=20 > + >=20 > +!if gSiPkgTokenSpaceGuid.PcdPpamEnable =3D=3D TRUE >=20 > +# >=20 > +# PCD for State Save Support on DGR >=20 > +# TRUE - SMM State Save region access is protected >=20 > +# FALSE - SMM can have Read/Write access to SMM State Save region >=20 > +# >=20 > +gSiPkgTokenSpaceGuid.PcdSpsStateSaveEnable |FALSE >=20 > +# >=20 > +# PCD to enable SPA Support on DGR >=20 > +# Note: This PCD is mainly used for Debugging purpose. Not recommended > to set for End Product. >=20 > +# >=20 > +gSiPkgTokenSpaceGuid.PcdSpaEnable |FALSE >=20 > +!endif >=20 > + >=20 > +[PcdsFixedAtBuild.common] >=20 > +gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress |0xC0000000 >=20 > +gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress > |gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress >=20 > +gSiPkgTokenSpaceGuid.PcdTemporaryPciExpressRegionLength > |0x10000000 >=20 > + >=20 > +[PcdsDynamicDefault.common] >=20 > +gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength |0x10000000 >=20 > +## Specifies the AP wait loop state during POST phase. >=20 > +# The value is defined as below. >=20 > +# 1: Place AP in the Hlt-Loop state. >=20 > +# 2: Place AP in the Mwait-Loop state. >=20 > +# 3: Place AP in the Run-Loop state. >=20 > +# @Prompt The AP wait loop state. >=20 > +gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode|2 >=20 > +## Specifies the AP target C-state for Mwait during POST phase. >=20 > +# The default value 0 means C1 state. >=20 > +# The value is defined as below.

>=20 > +# @Prompt The specified AP target C-state for Mwait. >=20 > +gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate|0 >=20 > + >=20 > +[Defines] >=20 > + PLATFORM_NAME =3D TigerlakeSiliconPkg >=20 > + PLATFORM_GUID =3D CCD38CA7-61D3-4185-9CDA-A9FDF209CB31 >=20 > + PLATFORM_VERSION =3D 0.4 >=20 > + DSC_SPECIFICATION =3D 0x00010005 >=20 > + OUTPUT_DIRECTORY =3D Build/TigerlakeSiliconPkg >=20 > + SUPPORTED_ARCHITECTURES =3D IA32|X64 >=20 > + BUILD_TARGETS =3D DEBUG|RELEASE >=20 > + SKUID_IDENTIFIER =3D DEFAULT >=20 > + >=20 > + DEFINE PLATFORM_SI_PACKAGE =3D TigerlakeSiliconPkg >=20 > + # >=20 > + # Definition for Build Flag >=20 > + # >=20 > + !include $(PLATFORM_SI_PACKAGE)/SiPkgBuildOption.dsc >=20 > + >=20 > +[LibraryClasses.common] >=20 > + # >=20 > + # Entry point >=20 > + # >=20 > + > PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.in > f >=20 > + PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf >=20 > + > DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint > .inf >=20 > + > UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntry > Point.inf >=20 > + > UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiA > pplicationEntryPoint.inf >=20 > + > PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BaseP > eCoffExtraActionLibNull.inf >=20 > + >=20 > + # >=20 > + # Basic >=20 > + # >=20 > + BaseLib|MdePkg/Library/BaseLib/BaseLib.inf >=20 > + > BaseMemoryLib|MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibR > epStr.inf >=20 > + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf >=20 > + CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf >=20 > + IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf >=20 > + > PciSegmentLib|$(PLATFORM_SI_PACKAGE)/Library/BasePciSegmentMultiSe > gLibPci/BasePciSegmentMultiSegLibPci.inf >=20 > + PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf >=20 > + PciCf8Lib|MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf >=20 > + > CacheMaintenanceLib|MdePkg/Library/BaseCacheMaintenanceLib/BaseCac > heMaintenanceLib.inf >=20 > + PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf >=20 > + > PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/Base > PeCoffGetEntryPointLib.inf >=20 > + PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf >=20 > + > PostCodeLib|MdePkg/Library/BasePostCodeLibPort80/BasePostCodeLibPort > 80.inf >=20 > + >=20 > + # >=20 > + # UEFI & PI >=20 > + # >=20 > + > UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBo > otServicesTableLib.inf >=20 > + > UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib > /UefiRuntimeServicesTableLib.inf >=20 > + UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf >=20 > + UefiLib|MdePkg/Library/UefiLib/UefiLib.inf >=20 > + DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf >=20 > + > PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLibIdt/P > eiServicesTablePointerLibIdt.inf >=20 > + PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf >=20 > + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf >=20 > + > DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTabl > eLib.inf >=20 > + >=20 > + > S3BootScriptLib|MdePkg/Library/BaseS3BootScriptLibNull/BaseS3BootScriptL > ibNull.inf >=20 > + S3IoLib|MdePkg/Library/BaseS3IoLib/BaseS3IoLib.inf >=20 > + S3PciLib|MdePkg/Library/BaseS3PciLib/BaseS3PciLib.inf >=20 > + >=20 > + UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf >=20 > + UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf >=20 > + > SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchroniz > ationLib.inf >=20 > + >=20 > + > DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/Bas > eDebugPrintErrorLevelLib.inf >=20 > + >=20 > + # >=20 > + # Misc >=20 > + # >=20 > + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf >=20 > + > PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanc > eLibNull.inf >=20 > + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf >=20 > + > TimerLib|MdePkg/Library/BaseTimerLibNullTemplate/BaseTimerLibNullTem > plate.inf >=20 > + > ReportStatusCodeLib|MdePkg/Library/BaseReportStatusCodeLibNull/BaseR > eportStatusCodeLibNull.inf >=20 > + MtrrLib|UefiCpuPkg/Library/MtrrLib/MtrrLib.inf >=20 > + RngLib|MdePkg/Library/BaseRngLib/BaseRngLib.inf >=20 > + >=20 > +######################################################### > ############################################ >=20 > + >=20 > +# >=20 > +# Silicon Init Common Library >=20 > +# >=20 > +!include $(PLATFORM_SI_PACKAGE)/SiPkgCommonLib.dsc >=20 > +ConfigBlockLib|IntelSiliconPkg/Library/BaseConfigBlockLib/BaseConfigBloc= k > Lib.inf >=20 > + >=20 > +[LibraryClasses.IA32] >=20 > +# >=20 > +# PEI phase common >=20 > +# >=20 > + PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf >=20 > + HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf >=20 > + > MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemory > AllocationLib.inf >=20 > + > ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiEx > tractGuidedSectionLib.inf >=20 > + > PeiGetVtdPmrAlignmentLib|IntelSiliconPkg/Library/PeiGetVtdPmrAlignment > Lib/PeiGetVtdPmrAlignmentLib.inf >=20 > + >=20 > +######################################################### > ########################################################## > ################## >=20 > + >=20 > +# >=20 > +# Silicon Init Pei Library >=20 > +# >=20 > +!include $(PLATFORM_SI_PACKAGE)/SiPkgPeiLib.dsc >=20 > + >=20 > +[LibraryClasses.IA32.SEC] >=20 > + > GpioHelpersLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Gpio/LibraryPrivate/Ba > seGpioHelpersLibNull/BaseGpioHelpersLibNull.inf >=20 > + >=20 > +[LibraryClasses.X64] >=20 > + # >=20 > + # DXE phase common >=20 > + # >=20 > + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf >=20 > + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf >=20 > + > MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemo > ryAllocationLib.inf >=20 > + > ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeE > xtractGuidedSectionLib.inf >=20 > + >=20 > +# >=20 > +# Hsti >=20 > +# >=20 > + HstiLib|MdePkg/Library/DxeHstiLib/DxeHstiLib.inf >=20 > + >=20 > +######################################################### > ########################################## >=20 > +# >=20 > +# Silicon Init Dxe Library >=20 > +# >=20 > +!include $(PLATFORM_SI_PACKAGE)/SiPkgDxeLib.dsc >=20 > + >=20 > +[LibraryClasses.X64.PEIM] >=20 > + >=20 > +[LibraryClasses.X64.DXE_CORE] >=20 > + HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf >=20 > + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf >=20 > + >=20 > +[LibraryClasses.X64.DXE_SMM_DRIVER] >=20 > + > SmmServicesTableLib|MdePkg/Library/SmmServicesTableLib/SmmServicesT > ableLib.inf >=20 > + > MemoryAllocationLib|MdePkg/Library/SmmMemoryAllocationLib/SmmMe > moryAllocationLib.inf >=20 > + SmmIoLib|MdePkg/Library/SmmIoLib/SmmIoLib.inf >=20 > + SmmMemLib|MdePkg/Library/SmmMemLib/SmmMemLib.inf >=20 > + >=20 > +[LibraryClasses.X64.SMM_CORE] >=20 > + >=20 > +[LibraryClasses.X64.UEFI_DRIVER] >=20 > + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf >=20 > + >=20 > +[LibraryClasses.X64.UEFI_APPLICATION] >=20 > + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf >=20 > + >=20 > +[Components.IA32] >=20 > +!include $(PLATFORM_SI_PACKAGE)/SiPkgPei.dsc >=20 > + >=20 > +[Components.X64] >=20 > +!include $(PLATFORM_SI_PACKAGE)/SiPkgDxe.dsc >=20 > -- > 2.24.0.windows.2