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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Nate DeSimone > -----Original Message----- > From: Luo, Heng > Sent: Sunday, January 31, 2021 5:37 PM > To: devel@edk2.groups.io > Cc: Chaganty, Rangasai V ; Desimone, > Nathaniel L > Subject: [PATCH 25/40] TigerlakeSiliconPkg/IpBlock: Add Psf component >=20 > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3171 >=20 > Adds the following files: > * IpBlock/Psf/IncludePrivate > * IpBlock/Psf/LibraryPrivate >=20 > Cc: Sai Chaganty > Cc: Nate DeSimone > Signed-off-by: Heng Luo > --- > Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Psf/IncludePrivate/Library/Psf= Lib.h > | 520 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Psf/LibraryPrivate/PsfLib/PeiDx= eSm > mPsfLibVer2.inf | 40 ++++++++++++++++++++++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Psf/LibraryPrivate/PsfLib/PsfL= ib.c > | 203 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Psf/LibraryPrivate/PsfLib/PsfLi= bInte > rnal.h | 470 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Psf/LibraryPrivate/PsfLib/PsfLi= bVer > 2.c | 115 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > 5 files changed, 1348 insertions(+) >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Psf/IncludePrivate/Library/Ps= fLib. > h > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Psf/IncludePrivate/Library/Ps= fLib. > h > new file mode 100644 > index 0000000000..f333be48d2 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Psf/IncludePrivate/Library/Ps= fLib. > h > @@ -0,0 +1,520 @@ > +/** @file >=20 > + Header file for PchPsfPrivateLib. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _PCH_PSF_PRIVATE_LIB_H_ >=20 > +#define _PCH_PSF_PRIVATE_LIB_H_ >=20 > + >=20 > +#include >=20 > +#include >=20 > + >=20 > +typedef struct { >=20 > + UINT32 Id; >=20 > + PCH_SBI_PID SbPid; >=20 > +} PSF_SEGMENT; >=20 > + >=20 > +/** >=20 > + Get list of supported PSF segments. >=20 > + >=20 > + @param[out] PsfTable Array of supported PSF segments >=20 > + @param[out] PsfTableLength Length of PsfTable >=20 > +**/ >=20 > +VOID >=20 > +PsfSegments ( >=20 > + OUT PSF_SEGMENT **PsfTable, >=20 > + OUT UINT32 *PsfTableLength >=20 > + ); >=20 > + >=20 > +// >=20 > +// Structure for storing data on both PSF SideBand Port ID and >=20 > +// PSF port register offset for specific device >=20 > +// >=20 > +typedef struct { >=20 > + PCH_SBI_PID PsfPid; >=20 > + UINT16 RegBase; >=20 > +} PSF_PORT; >=20 > + >=20 > +/** >=20 > + Disable device at PSF level >=20 > + Method not for bridges (e.g. PCIe Root Port) >=20 > + >=20 > + @param[in] PsfPort PSF PORT data structure >=20 > +**/ >=20 > +VOID >=20 > +PsfDisableDevice ( >=20 > + IN PSF_PORT PsfPort >=20 > + ); >=20 > + >=20 > +/** >=20 > + Enable device at PSF level >=20 > + Method not for bridges (e.g. PCIe Root Port) >=20 > + >=20 > + @param[in] PsfPort PSF PORT data structure >=20 > +**/ >=20 > +VOID >=20 > +PsfEnableDevice ( >=20 > + IN PSF_PORT PsfPort >=20 > + ); >=20 > + >=20 > +/** >=20 > + Hide PciCfgSpace of device at PSF level >=20 > + Method not for bridges (e.g. PCIe Root Port) >=20 > + >=20 > + @param[in] PsfPort PSF PORT data structure >=20 > +**/ >=20 > +VOID >=20 > +PsfHideDevice ( >=20 > + IN PSF_PORT PsfPort >=20 > + ); >=20 > + >=20 > +/** >=20 > + Unhide PciCfgSpace of device at PSF level >=20 > + Method not for bridges (e.g. PCIe Root Port) >=20 > + >=20 > + @param[in] PsfPort PSF PORT data structure >=20 > +**/ >=20 > +VOID >=20 > +PsfUnhideDevice ( >=20 > + IN PSF_PORT PsfPort >=20 > + ); >=20 > + >=20 > +/** >=20 > + Disable device BARs at PSF level >=20 > + Method not for bridges (e.g. PCIe Root Port) >=20 > + >=20 > + @param[in] PsfPort PSF PORT data structure >=20 > + @param[in] BarDisMask BIT0-BAR0, BIT1-BAR1,... >=20 > + Mask corresponds to 32bit wide BARs >=20 > +**/ >=20 > +VOID >=20 > +PsfDisableDeviceBar ( >=20 > + IN PSF_PORT PsfPort, >=20 > + IN UINT32 BarDisMask >=20 > + ); >=20 > + >=20 > +/** >=20 > + Enable device BARs at PSF level >=20 > + Method not for bridges (e.g. PCIe Root Port) >=20 > + >=20 > + @param[in] PsfPort PSF PORT data structure >=20 > + @param[in] BarEnMask BIT0-BAR0, BIT1-BAR1,... >=20 > + Mask corresponds to 32bit wide BARs >=20 > +**/ >=20 > +VOID >=20 > +PsfEnableDeviceBar ( >=20 > + IN PSF_PORT PsfPort, >=20 > + IN UINT32 BarEnMask >=20 > + ); >=20 > + >=20 > +/** >=20 > + Disable IDER device at PSF level >=20 > +**/ >=20 > +VOID >=20 > +PsfDisableIderDevice ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Enable SOL device at PSF level >=20 > +**/ >=20 > +VOID >=20 > +PsfEnableSolDevice ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Disable SOL device at PSF level >=20 > +**/ >=20 > +VOID >=20 > +PsfDisableSolDevice ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Set PMC ABASE value in PSF >=20 > + >=20 > + @param[in] Address Address for ACPI base. >=20 > +**/ >=20 > +VOID >=20 > +PsfSetPmcAbase ( >=20 > + IN UINT16 Address >=20 > + ); >=20 > + >=20 > +/** >=20 > + Get PMC ABASE value from PSF >=20 > + >=20 > + @retval Address Address for ACPI base. >=20 > +**/ >=20 > +UINT16 >=20 > +PsfGetPmcAbase ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Get PMC PWRMBASE value from PSF >=20 > + >=20 > + @retval Address Address for PWRM base. >=20 > +**/ >=20 > +UINT32 >=20 > +PsfGetPmcPwrmBase ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Hide Cnvi WiFi device's PciCfgSpace at PSF level >=20 > +**/ >=20 > +VOID >=20 > +PsfHideCnviWifiDevice ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Disable Cnvi Wifi device at PSF level >=20 > +**/ >=20 > +VOID >=20 > +PsfDisableCnviWifiDevice ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Disable HDAudio device at PSF level >=20 > +**/ >=20 > +VOID >=20 > +PsfDisableHdaDevice ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Disable Dsp bar at PSF level >=20 > +**/ >=20 > +VOID >=20 > +PsfDisableDspBar ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Disable THC device at PSF level >=20 > + >=20 > + @param[in] ThcNumber Touch Host Controller Number THC0= or > THC1 >=20 > +**/ >=20 > +VOID >=20 > +PsfDisableThcDevice ( >=20 > + IN UINT32 ThcNumber >=20 > + ); >=20 > + >=20 > +/** >=20 > + Disable xDCI device at PSF level >=20 > +**/ >=20 > +VOID >=20 > +PsfDisableXdciDevice ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Disable xHCI device at PSF level >=20 > +**/ >=20 > +VOID >=20 > +PsfDisableXhciDevice ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Disable xHCI VTIO Phantom device at PSF level >=20 > +**/ >=20 > +VOID >=20 > +PsfDisableXhciVtioDevice ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Disable SATA device at PSF level >=20 > + >=20 > + @param[in] SataCtrlIndex SATA controller index >=20 > +**/ >=20 > +VOID >=20 > +PsfDisableSataDevice ( >=20 > + IN UINT32 SataCtrlIndex >=20 > + ); >=20 > + >=20 > +/** >=20 > + Return PSF_PORT for SCS eMMC device >=20 > + >=20 > + @retval PsfPort PSF PORT structure for SCS eMMC device >=20 > +**/ >=20 > +PSF_PORT >=20 > +PsfScsEmmcPort ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Return PSF_PORT for SCS SD Card device >=20 > + >=20 > + @retval PsfPort PSF PORT structure for SCS SD Card device >=20 > +**/ >=20 > +PSF_PORT >=20 > +PsfScsSdCardPort ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Return PSF_PORT for SCS UFS device >=20 > + >=20 > + @param[in] UfsNum UFS Device >=20 > + >=20 > + @retval PsfPort PSF PORT structure for SCS UFS device >=20 > +**/ >=20 > +PSF_PORT >=20 > +PsfScsUfsPort ( >=20 > + IN UINT32 UfsNum >=20 > + ); >=20 > + >=20 > +/** >=20 > + Disable ISH device at PSF level >=20 > +**/ >=20 > +VOID >=20 > +PsfDisableIshDevice ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Disable FPAK device at PSF level >=20 > +**/ >=20 > +VOID >=20 > +PsfDisableFpakDevice ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Disable ISH BAR1 at PSF level >=20 > +**/ >=20 > +VOID >=20 > +PsfDisableIshBar1 ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Disable GbE device at PSF level >=20 > +**/ >=20 > +VOID >=20 > +PsfDisableGbeDevice ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Disable SMBUS device at PSF level >=20 > +**/ >=20 > +VOID >=20 > +PsfDisableSmbusDevice ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Disable TraceHub ACPI devices at PSF level >=20 > +**/ >=20 > +VOID >=20 > +PsfDisableTraceHubAcpiDevice ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Hide TraceHub ACPI devices PciCfgSpace at PSF level >=20 > +**/ >=20 > +VOID >=20 > +PsfHideTraceHubAcpiDevice ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + This procedure will hide TraceHub PciCfgSpace at PSF level >=20 > +**/ >=20 > +VOID >=20 > +PsfHideTraceHubDevice ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + This procedure will unhide TraceHub PciCfgSpace at PSF level >=20 > +**/ >=20 > +VOID >=20 > +PsfUnhideTraceHubDevice ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + This procedure will disable TraceHub device at PSF level >=20 > +**/ >=20 > +VOID >=20 > +PsfDisableTraceHubDevice ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Configures rootspace 3 bus number for PCIe IMR use >=20 > + >=20 > + @param[in] Rs3Bus bus number >=20 > +**/ >=20 > +VOID >=20 > +PsfSetRs3Bus ( >=20 > + UINT8 Rs3Bus >=20 > + ); >=20 > + >=20 > +/** >=20 > + Disable PCIe Root Port at PSF level >=20 > + >=20 > + @param[in] RpIndex PCIe Root Port Index (0 based) >=20 > +**/ >=20 > +VOID >=20 > +PsfDisablePcieRootPort ( >=20 > + IN UINT32 RpIndex >=20 > + ); >=20 > + >=20 > +/** >=20 > + Program PSF grant counts for SATA >=20 > + Call this before SATA ports are accessed for enumeration >=20 > +**/ >=20 > +VOID >=20 > +PsfConfigureSataGrantCounts ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Specifies the root port configuration of the >=20 > + PCIe controller. The number on the left of x >=20 > + signifies the number of root ports in the controller >=20 > + while value on the right is link width. N stands for >=20 > + the number of PCIe lanes per root port instance. >=20 > +**/ >=20 > +typedef enum { >=20 > + PsfPcieCtrl4xn, >=20 > + PsfPcieCtrl1x2n_2xn, >=20 > + PsfPcieCtrl2xn_1x2n, >=20 > + PsfPcieCtrl2x2n, >=20 > + PsfPcieCtrl1x4n, >=20 > + PsfPcieCtrlUndefined >=20 > +} PSF_PCIE_CTRL_CONFIG; >=20 > + >=20 > +/** >=20 > + Program PSF grant counts for PCI express depending on controllers > configuration >=20 > + >=20 > + @param[in] PsfPcieCtrlConfigTable Table with PCIe controllers > configuration >=20 > + @param[in] NumberOfPcieControllers Number of PCIe controllers. This i= s > also the size of PsfPcieCtrlConfig table >=20 > +**/ >=20 > +VOID >=20 > +PsfConfigurePcieGrantCounts ( >=20 > + IN PSF_PCIE_CTRL_CONFIG *PsfPcieCtrlConfigTable, >=20 > + IN UINT32 NumberOfPcieControllers >=20 > + ); >=20 > + >=20 > + >=20 > +/** >=20 > + This function enables EOI message forwarding in PSF for PCIe ports >=20 > + for cases where IOAPIC is present behind this root port. >=20 > + >=20 > + @param[in] RpIndex Root port index (0 based) >=20 > + >=20 > + @retval Status >=20 > +**/ >=20 > +EFI_STATUS >=20 > +PsfConfigurEoiForPciePort ( >=20 > + IN UINT32 RpIndex >=20 > + ); >=20 > + >=20 > +// >=20 > +// Structure for PSF Port Destination ID >=20 > +// >=20 > +typedef union { >=20 > + UINT32 RegVal; >=20 > + struct { >=20 > + UINT32 ChannelId : 8; // Channel ID >=20 > + UINT32 PortId : 7; // Port ID >=20 > + UINT32 PortGroupId : 1; // Port Group ID >=20 > + UINT32 PsfId : 8; // PSF ID >=20 > + UINT32 Rsvd : 7; // Reserved >=20 > + UINT32 ChanMap : 1; // Channel map >=20 > + } Fields; >=20 > +} PSF_PORT_DEST_ID; >=20 > + >=20 > +/** >=20 > + PCIe PSF port destination ID (psf_id:port_group_id:port_id:channel_id) >=20 > + >=20 > + @param[in] RpIndex PCIe Root Port Index (0 based) >=20 > + >=20 > + @retval Destination ID >=20 > +**/ >=20 > +PSF_PORT_DEST_ID >=20 > +PsfPcieDestinationId ( >=20 > + IN UINT32 RpIndex >=20 > + ); >=20 > + >=20 > +/** >=20 > + PSF early initialization. >=20 > +**/ >=20 > +VOID >=20 > +PsfEarlyInit ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Assign new function number for PCIe Port Number. >=20 > + >=20 > + @param[in] RpIndex PCIe Root Port Index (0 based) >=20 > + @param[in] NewFunction New Function number >=20 > +**/ >=20 > +VOID >=20 > +PsfSetPcieFunction ( >=20 > + IN UINT32 RpIndex, >=20 > + IN UINT32 NewFunction >=20 > + ); >=20 > + >=20 > +/** >=20 > + This function enables PCIe Relaxed Order in PSF >=20 > +**/ >=20 > +VOID >=20 > +PsfEnablePcieRelaxedOrder ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > + >=20 > +/** >=20 > + Enable VTd support in PSF. >=20 > +**/ >=20 > +VOID >=20 > +PchPsfEnableVtd ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Disable PSF address-based peer-to-peer decoding. >=20 > +**/ >=20 > +VOID >=20 > +PchPsfDisableP2pDecoding ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + This procedure will hide PMC device at PSF level >=20 > +**/ >=20 > +VOID >=20 > +PsfHidePmcDevice ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + This procedure will disable D3:F0 device at PSF level for PCH-LP >=20 > +**/ >=20 > +VOID >=20 > +PsfDisableD3F0 ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + This procedure will disable PSF upstream completion tracking for HDAud= io > on PCH-LP >=20 > +**/ >=20 > +VOID >=20 > +PsfDisableUpstreamCompletionTrackingForHda ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +#endif // _PCH_PSF_PRIVATE_LIB_H_ >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Psf/LibraryPrivate/PsfLib/Pei= DxeS > mmPsfLibVer2.inf > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Psf/LibraryPrivate/PsfLib/Pei= DxeS > mmPsfLibVer2.inf > new file mode 100644 > index 0000000000..d8fc52444a > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Psf/LibraryPrivate/PsfLib/Pei= DxeS > mmPsfLibVer2.inf > @@ -0,0 +1,40 @@ > +## @file >=20 > +# PEI/DXE/SMM PCH PSF Private Lib for TigerLake PCH >=20 > +# >=20 > +# Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > +# SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +# >=20 > +## >=20 > + >=20 > +[Defines] >=20 > +INF_VERSION =3D 0x00010017 >=20 > +BASE_NAME =3D PeiDxeSmmPsfLibTgl >=20 > +FILE_GUID =3D 28B03D2C-6FD5-4061-96B8-39E3F0402DE5 >=20 > +VERSION_STRING =3D 1.0 >=20 > +MODULE_TYPE =3D BASE >=20 > +LIBRARY_CLASS =3D PsfLib >=20 > +# >=20 > +# The following information is for reference only and not required by th= e > build tools. >=20 > +# >=20 > +# VALID_ARCHITECTURES =3D IA32 X64 >=20 > +# >=20 > + >=20 > +[LibraryClasses] >=20 > + BaseLib >=20 > + IoLib >=20 > + DebugLib >=20 > + PciSegmentLib >=20 > + PchInfoLib >=20 > + PchPcrLib >=20 > + SataLib >=20 > + CpuPcieInfoFruLib >=20 > + PchPciBdfLib >=20 > + >=20 > +[Packages] >=20 > + MdePkg/MdePkg.dec >=20 > + TigerlakeSiliconPkg/SiPkg.dec >=20 > + >=20 > + >=20 > +[Sources] >=20 > + PsfLib.c >=20 > + PsfLibVer2.c >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Psf/LibraryPrivate/PsfLib/Psf= Lib.c > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Psf/LibraryPrivate/PsfLib/Psf= Lib.c > new file mode 100644 > index 0000000000..1f0b11c11a > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Psf/LibraryPrivate/PsfLib/Psf= Lib.c > @@ -0,0 +1,203 @@ > +/** @file >=20 > + This file contains PSF routines for RC usage >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include "PsfLibInternal.h" >=20 > +#include >=20 > + >=20 > +/** >=20 > + Get PSF SideBand Port ID from PSF ID (1 - PSF1, 2 - PSF2, ...) >=20 > + >=20 > + @param[in] PsfId PSF ID (1 - PSF1, 2 - PSF2, ...) >=20 > + >=20 > + @retval PSF SideBand Port ID >=20 > +**/ >=20 > +PCH_SBI_PID >=20 > +PsfSbPortId ( >=20 > + UINT32 PsfId >=20 > + ) >=20 > +{ >=20 > + UINT32 PsfTableIndex; >=20 > + PSF_SEGMENT *PsfTable; >=20 > + UINT32 PsfTableSize; >=20 > + >=20 > + PsfSegments (&PsfTable, &PsfTableSize); >=20 > + >=20 > + for (PsfTableIndex =3D 0; PsfTableIndex < PsfTableSize; PsfTableIndex+= +) { >=20 > + if (PsfTable[PsfTableIndex].Id =3D=3D PsfId) { >=20 > + return PsfTable[PsfTableIndex].SbPid; >=20 > + } >=20 > + } >=20 > + >=20 > + ASSERT (FALSE); >=20 > + return 0; >=20 > +} >=20 > + >=20 > + >=20 > +/** >=20 > + Get PCH Root PSF ID. This is the PSF segment to which OPDMI/DMI is > connected. >=20 > + >=20 > + @retval PsfId Root PSF ID >=20 > +**/ >=20 > +UINT32 >=20 > +PsfRootId ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + PSF_SEGMENT *PsfTable; >=20 > + UINT32 PsfTableSize; >=20 > + >=20 > + PsfSegments (&PsfTable, &PsfTableSize); >=20 > + >=20 > + return PsfTable[0].Id; >=20 > +} >=20 > + >=20 > +/** >=20 > + Add EOI Target in a given PSF >=20 > + >=20 > + @param[in] PsfId PSF ID (1 - PSF1, 2 - PSF2, ...) >=20 > + @param[in] TargetId EOI Target ID >=20 > +**/ >=20 > +STATIC >=20 > +VOID >=20 > +PsfAddEoiTarget ( >=20 > + UINT32 PsfId, >=20 > + PSF_PORT_DEST_ID TargetId >=20 > + ) >=20 > +{ >=20 > + UINT16 EoiTargetBase; >=20 > + UINT16 EoiControlBase; >=20 > + UINT8 NumOfEnabledTargets; >=20 > + UINT8 MaximalNumberOfTargets; >=20 > + PCH_SBI_PID PsfSbiPortId; >=20 > + UINT32 Data32; >=20 > + UINT8 TargetIndex; >=20 > + >=20 > + MaximalNumberOfTargets =3D PsfEoiRegData (PsfId, &EoiTargetBase, > &EoiControlBase); >=20 > + PsfSbiPortId =3D PsfSbPortId (PsfId); >=20 > + >=20 > + // >=20 > + // Get number of enabled agents from > PSF_x_PSF_MC_CONTROL_MCAST0_RS0_EOI register >=20 > + // >=20 > + Data32 =3D PchPcrRead32 (PsfSbiPortId, EoiControlBase); >=20 > + NumOfEnabledTargets =3D (UINT8) (Data32 >> > N_PCH_PSFX_PCR_MC_CONTROL_MCASTX_NUMMC); >=20 > + >=20 > + // >=20 > + // Check if target was not already enabled >=20 > + // Targets from a different PSF segment are aggregated into single > destination on >=20 > + // current PSF segment. >=20 > + // >=20 > + for (TargetIndex =3D 0; TargetIndex < NumOfEnabledTargets; > TargetIndex++) { >=20 > + Data32 =3D PchPcrRead32 (PsfSbiPortId, EoiTargetBase + TargetIndex *= 4); >=20 > + // >=20 > + // If target already added don't add it again >=20 > + // >=20 > + if (Data32 =3D=3D TargetId.RegVal) { >=20 > + ASSERT (FALSE); >=20 > + return; >=20 > + } >=20 > + // >=20 > + // If target is from different PSF segment than currently being anal= yzed >=20 > + // it is enough that its PsfID is matching >=20 > + // >=20 > + if ((Data32 & B_PCH_PSFX_PCR_TARGET_PSFID) >> > N_PCH_PSFX_PCR_TARGET_PSFID =3D=3D TargetId.Fields.PsfId) { >=20 > + return; >=20 > + } >=20 > + } >=20 > + >=20 > + // >=20 > + // Check if next one can be added >=20 > + // >=20 > + if (NumOfEnabledTargets >=3D MaximalNumberOfTargets) { >=20 > + ASSERT (FALSE); >=20 > + return; >=20 > + } >=20 > + >=20 > + // >=20 > + // Add next target >=20 > + // Configure Multicast Destination ID register with target device on P= SF. >=20 > + // Configuration must be done in next available > PSF_MC_AGENT_MCAST0_RS0_TGT_EOI register >=20 > + // so that other targets are not overridden. is known from the > number of multicast agents >=20 > + // in Multicast Control Register. Value programmed is based on >=20 > + // PsfID, PortGroupID, PortID and ChannelID of the target >=20 > + // >=20 > + PchPcrWrite32 (PsfSbiPortId, EoiTargetBase + NumOfEnabledTargets * 4, > TargetId.RegVal); >=20 > + >=20 > + // >=20 > + // Enable new target >=20 > + // Configure PSF_x_PSF_MC_CONTROL_MCAST0_RS0_EOI, increase > NumMc and set MultCEn >=20 > + // >=20 > + NumOfEnabledTargets++; >=20 > + Data32 =3D (NumOfEnabledTargets << > N_PCH_PSFX_PCR_MC_CONTROL_MCASTX_NUMMC) | > B_PCH_PSFX_PCR_MC_CONTROL_MCASTX_MULTCEN; >=20 > + PchPcrWrite32 (PsfSbiPortId, EoiControlBase, Data32); >=20 > +} >=20 > + >=20 > +/** >=20 > + Enable EOI Target >=20 > + >=20 > + @param[in] TargetId Target ID >=20 > +**/ >=20 > +STATIC >=20 > +VOID >=20 > +PsfEnableEoiTarget ( >=20 > + PSF_PORT_DEST_ID TargetId >=20 > + ) >=20 > +{ >=20 > + UINT32 RootLevelPsf; >=20 > + >=20 > + RootLevelPsf =3D PsfRootId (); >=20 > + >=20 > + // >=20 > + // Enable EOI target in root PSF >=20 > + // >=20 > + PsfAddEoiTarget (RootLevelPsf, TargetId); >=20 > + >=20 > + // >=20 > + // Enable EOI target on other PSF segment if target >=20 > + // is not located on root PSF >=20 > + // >=20 > + if (TargetId.Fields.PsfId !=3D RootLevelPsf) { >=20 > + PsfAddEoiTarget (TargetId.Fields.PsfId, TargetId); >=20 > + } >=20 > +} >=20 > + >=20 > +/** >=20 > + This function enables EOI message forwarding in PSF for PCIe ports >=20 > + for cases where IOAPIC is present behind this root port. >=20 > + >=20 > + @param[in] RpIndex Root port index (0 based) >=20 > + >=20 > + @retval Status >=20 > +**/ >=20 > +EFI_STATUS >=20 > +PsfConfigurEoiForPciePort ( >=20 > + IN UINT32 RpIndex >=20 > + ) >=20 > +{ >=20 > + ASSERT (RpIndex < GetPchMaxPciePortNum ()); >=20 > + >=20 > + // >=20 > + // If there is an IOAPIC discovered behind root port program PSF Multi= cast > registers >=20 > + // accordingly to CNL PCH BWG PSF EOI Multicast Configuration >=20 > + // Since there is a device behind RootPort to which EOI needs to be > forwarded >=20 > + // enable multicast (MULTCEN) and increase the number of multicast > agents (NUMMC) >=20 > + // in Multicast Control Register. >=20 > + // >=20 > + PsfEnableEoiTarget (PsfPcieDestinationId (RpIndex)); >=20 > + >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Psf/LibraryPrivate/PsfLib/Psf= LibIn > ternal.h > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Psf/LibraryPrivate/PsfLib/Psf= LibIn > ternal.h > new file mode 100644 > index 0000000000..9d636b5298 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Psf/LibraryPrivate/PsfLib/Psf= LibIn > ternal.h > @@ -0,0 +1,470 @@ > +/** @file >=20 > + This file contains internal header for PSF lib usage >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _PCH_PSF_PRIVATE_LIB_INTERNAL_H_ >=20 > +#define _PCH_PSF_PRIVATE_LIB_INTERNAL_H_ >=20 > + >=20 > +#include >=20 > +#include >=20 > + >=20 > +#define PSF_PORT_NULL ((PSF_PORT){0,0}) >=20 > +#define PSF_IS_PORT_NULL(PsfPort) ((PsfPort.PsfPid =3D=3D 0) && > (PsfPort.RegBase =3D=3D 0)) >=20 > + >=20 > +typedef struct { >=20 > + PCH_SBI_PID PsfPid; >=20 > + UINT32 RegisterAddress; >=20 > + UINT8 Fro; >=20 > +} PSF_PORT_RELAXED_ORDERING_CONFIG_REG; >=20 > +/** >=20 > + Disable bridge (e.g. PCIe Root Port) at PSF level >=20 > + >=20 > + @param[in] PsfPort PSF PORT data structure >=20 > +**/ >=20 > +VOID >=20 > +PsfDisableBridge ( >=20 > + IN PSF_PORT PsfPort >=20 > + ); >=20 > + >=20 > +/** >=20 > + Disable bridge (e.g. PCIe Root Port) at PSF level in RS3 >=20 > + >=20 > + @param[in] PsfPort PSF PORT data structure >=20 > +**/ >=20 > +VOID >=20 > +PsfRs3DisableBridge ( >=20 > + IN PSF_PORT PsfPort >=20 > + ); >=20 > + >=20 > +/** >=20 > + Check if bridge (e.g. PCIe Root Port) is enabled at PSF level >=20 > + >=20 > + @param[in] PsfPort PSF PORT data structure >=20 > + >=20 > + @retval TRUE Bridge behind PSF Port is enabled >=20 > + FALSE Bridge behind PSF Port is disabled >=20 > +**/ >=20 > +BOOLEAN >=20 > +PsfIsBridgeEnabled ( >=20 > + IN PSF_PORT PsfPort >=20 > + ); >=20 > + >=20 > +/** >=20 > + Disable device IOSpace at PSF level >=20 > + Method not for bridges (e.g. PCIe Root Port) >=20 > + >=20 > + @param[in] PsfPort PSF PORT data structure >=20 > +**/ >=20 > +VOID >=20 > +PsfDisableDeviceIoSpace ( >=20 > + IN PSF_PORT PsfPort >=20 > + ); >=20 > + >=20 > +/** >=20 > + Enable device IOSpace at PSF level >=20 > + Method not for bridges (e.g. PCIe Root Port) >=20 > + >=20 > + @param[in] PsfPort PSF PORT data structure >=20 > +**/ >=20 > +VOID >=20 > +PsfEnableDeviceIoSpace ( >=20 > + IN PSF_PORT PsfPort >=20 > + ); >=20 > + >=20 > +/** >=20 > + Disable device Memory Space at PSF level >=20 > + Method not for bridges (e.g. PCIe Root Port) >=20 > + >=20 > + @param[in] PsfPort PSF PORT data structure >=20 > +**/ >=20 > +VOID >=20 > +PsfDisableDeviceMemSpace ( >=20 > + IN PSF_PORT PsfPort >=20 > + ); >=20 > + >=20 > +/** >=20 > + Enable device Memory Space at PSF level >=20 > + Method not for bridges (e.g. PCIe Root Port) >=20 > + >=20 > + @param[in] PsfPort PSF PORT data structure >=20 > +**/ >=20 > +VOID >=20 > +PsfEnableDeviceMemSpace ( >=20 > + IN PSF_PORT PsfPort >=20 > + ); >=20 > + >=20 > +/** >=20 > + Set device BARx address at PSF level >=20 > + Method not for bridges (e.g. PCIe Root Port) >=20 > + >=20 > + @param[in] PsfPort PSF PORT data structure >=20 > + @param[in] BarNum BAR Number (0:BAR0, 1:BAR1, ...) >=20 > + @param[in] BarValue 32bit BAR value >=20 > +**/ >=20 > +VOID >=20 > +PsfSetDeviceBarValue ( >=20 > + IN PSF_PORT PsfPort, >=20 > + IN UINT8 BarNum, >=20 > + IN UINT32 BarValue >=20 > + ); >=20 > + >=20 > +/** >=20 > + Return PSF_PORT for TraceHub device >=20 > + >=20 > + @retval PsfPort PSF PORT structure for TraceHub device >=20 > +**/ >=20 > +PSF_PORT >=20 > +PsfTraceHubPort ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + This procedure will return PSF_PORT for TraceHub ACPI device >=20 > + >=20 > + @retval PsfPort PSF PORT structure for TraceHub ACPI device >=20 > +**/ >=20 > +PSF_PORT >=20 > +PsfTraceHubAcpiDevPort ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + This procedure will return PSF_PORT for SOL device >=20 > + >=20 > + @retval PsfPort PSF PORT structure for SOL device >=20 > +**/ >=20 > +PSF_PORT >=20 > +PsfSolPort ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Return PSF_PORT for ISH device >=20 > + >=20 > + @retval PsfPort PSF PORT structure for ISH device >=20 > +**/ >=20 > +PSF_PORT >=20 > +PsfIshPort ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Return PSF_PORT for FPAK device >=20 > + >=20 > + @retval PsfPort PSF PORT structure for FPAK device >=20 > +**/ >=20 > +PSF_PORT >=20 > +PsfFpakPort ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Return PSF_PORT for CNVi device >=20 > + >=20 > + @retval PsfPort PSF PORT structure for CNVi device >=20 > +**/ >=20 > +PSF_PORT >=20 > +PsfCnviPort ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Return PSF_PORT for PMC device >=20 > + >=20 > + @retval PsfPort PSF PORT structure for PMC device >=20 > +**/ >=20 > +PSF_PORT >=20 > +PsfPmcPort ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Return second level PSF_PORT to which PCIE Root Port device is connect= ed > (directly) >=20 > + >=20 > + @param[in] RpIndex PCIe Root Port Index (0 based) >=20 > + >=20 > + @retval PsfPort PSF PORT structure for PCIe >=20 > +**/ >=20 > +PSF_PORT >=20 > +PsfPcieSecondLevelPort ( >=20 > + IN UINT32 RpIndex >=20 > + ); >=20 > + >=20 > +/** >=20 > + Return PSF_PORT at root PSF level to which PCIe Root Port device is > connected >=20 > + >=20 > + @param[in] RpIndex PCIe Root Port Index (0 based) >=20 > + >=20 > + @retval PsfPort PSF PORT structure for PCIe >=20 > + >=20 > +**/ >=20 > +PSF_PORT >=20 > +PsfRootPciePort ( >=20 > + IN UINT32 RpIndex >=20 > + ); >=20 > + >=20 > +/** >=20 > + Return RS3 PSF_PORT at root PSF level to which PCIe Root Port device i= s > connected >=20 > + >=20 > + @param[in] RpIndex PCIe Root Port Index (0 based) >=20 > + >=20 > + @retval PsfPort PSF PORT structure for PCIe >=20 > +**/ >=20 > +PSF_PORT >=20 > +PsfRootRs3PciePort ( >=20 > + IN UINT32 RpIndex >=20 > + ); >=20 > + >=20 > +/** >=20 > + Check if PCIe Root Port is enabled >=20 > + >=20 > + @param[in] RpIndex PCIe Root Port Index (0 based) >=20 > + >=20 > + @retval TRUE PCIe Root Port is enabled >=20 > + FALSE PCIe Root Port is disabled >=20 > +**/ >=20 > +BOOLEAN >=20 > +PsfIsPcieRootPortEnabled ( >=20 > + IN UINT32 RpIndex >=20 > + ); >=20 > + >=20 > +// >=20 > +// Type of enpoint connected to PSF port. >=20 > +// PsfNullPort is used for ports which do not exist >=20 > +// >=20 > +typedef enum { >=20 > + PsfNullPort, >=20 > + PsfToPsfPort, >=20 > + PsfPcieCtrlPort >=20 > +} PSF_TOPO_PORT_TYPE; >=20 > + >=20 > +// >=20 > +// Structure for storing information on location in PSF topology >=20 > +// Every PSF node is identified by PsfID and PsfPortId >=20 > +// >=20 > +typedef struct { >=20 > + UINT8 PsfId; >=20 > + UINT8 PortId; >=20 > +} PSF_TOPO_PORT; >=20 > + >=20 > +#define PSF_TOPO_PORT_NULL ((PSF_TOPO_PORT){0, 0}) >=20 > +#define PSF_IS_TOPO_PORT_NULL(PsfTopoPort) (((PsfTopoPort).PsfId =3D=3D > 0) && ((PsfTopoPort).PortId =3D=3D 0)) >=20 > + >=20 > +// >=20 > +// This is optional field containing PSF port specific data >=20 > +// >=20 > +typedef union { >=20 > + UINT32 PcieCtrlIndex; >=20 > +} PSF_TOPO_PORT_DATA; >=20 > + >=20 > +// >=20 > +// Structure representing PSF port in PSF topology >=20 > +// If port is of PsfToPsfPort type Child will point to the first >=20 > +// port of sub PSF segment. >=20 > +// >=20 > +typedef struct PSF_TOPOLOGY { >=20 > + PSF_TOPO_PORT PsfPort; >=20 > + PSF_TOPO_PORT_TYPE PortType; >=20 > + CONST struct PSF_TOPOLOGY *Child; >=20 > + PSF_TOPO_PORT_DATA PortData; >=20 > +} PSF_TOPOLOGY; >=20 > + >=20 > +// >=20 > +// Tag for identifying last element of PSF_TOPOLOGY type array >=20 > +// >=20 > +#define PSF_TOPOLOGY_END {{0, 0}, PsfNullPort, NULL} >=20 > + >=20 > +/** >=20 > + Get PSF Pcie Tree topology >=20 > + >=20 > + @param[in] PsfTopology PSF Port from PSF PCIe tree topology >=20 > + >=20 > + @retval PsfTopology PSF PCIe tree topology >=20 > +**/ >=20 > +CONST PSF_TOPOLOGY* >=20 > +PsfGetRootPciePsfTopology ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +// >=20 > +// Structure for storing data on PCIe controller to PSF assignment and > GrantCount register offsets >=20 > +// >=20 > +typedef struct { >=20 > + PCH_SBI_PID PsfPid; >=20 > + UINT16 DevGntCnt0Base; >=20 > + UINT16 TargetGntCntPg1Tgt0Base; >=20 > +} PSF_GRANT_COUNT_REG; >=20 > + >=20 > +/** >=20 > + Grant count regs data for PSF that is directly connected to PCIe Root = Ports >=20 > + >=20 > + @param[in] Controller PCIe Root Port Controller index (0 based) >=20 > + @param[out] GrantCountReg Structure with PSF Grant Count register > data >=20 > +**/ >=20 > +VOID >=20 > +PsfPcieGrantCountBaseReg ( >=20 > + IN UINT8 Controller, >=20 > + OUT PSF_GRANT_COUNT_REG *GrantCountReg >=20 > + ); >=20 > + >=20 > +/** >=20 > + Get Grant Count number (Device Grant Count and Target Grant Count) >=20 > + for PSF that is directly connected to PCIe Root Ports >=20 > + >=20 > + @param[in] Controller PCIe Root Port Controller index >=20 > + @param[in] Channel PCIe Root Port Channel index >=20 > + @param[out] DgcrNo Device Grant Count number >=20 > + @param[out] PgTgtNo Target Grant Count number >=20 > +**/ >=20 > +VOID >=20 > +PsfPcieGrantCountNumber ( >=20 > + IN UINT8 Controller, >=20 > + IN UINT8 Channel, >=20 > + OUT UINT8 *DgcrNo, >=20 > + OUT UINT8 *PgTgtNo >=20 > + ); >=20 > + >=20 > +/** >=20 > + Grant count regs data for a given PSF-to-PSF port. >=20 > + >=20 > + @param[in] PsfTopoPort PSF-to-PSF port >=20 > + >=20 > + @param[out] GrantCountReg Structure with PSF Grant Count register > data >=20 > +**/ >=20 > +VOID >=20 > +PsfSegmentGrantCountBaseReg ( >=20 > + IN PSF_TOPO_PORT PsfTopoPort, >=20 > + OUT PSF_GRANT_COUNT_REG *GrantCountReg >=20 > + ); >=20 > + >=20 > +/** >=20 > + Grant Count number (Device Grant Count and Target Grant Count) for a > given PSF-to-PSF port. >=20 > + >=20 > + @param[in] PsfTopoPort PSF-to-PSF port >=20 > + @param[out] DgcrNo Device Grant Count number >=20 > + @param[out] PgTgtNo Target Grant Count number >=20 > +**/ >=20 > +VOID >=20 > +PsfSegmentGrantCountNumber ( >=20 > + IN PSF_TOPO_PORT PsfTopoPort, >=20 > + OUT UINT8 *DgcrNo, >=20 > + OUT UINT8 *PgTgtNo >=20 > + ); >=20 > + >=20 > +// >=20 > +// Do not override PSF Grant Count value and leave HW default setting >=20 > +// >=20 > +#define DEFAULT_PCIE_GRANT_COUNT 0xFF >=20 > + >=20 > +/** >=20 > + Get PSF SideBand Port ID from PSF ID (1 - PSF1, 2 - PSF2, ...) >=20 > + >=20 > + @param[in] PsfId PSF ID (1 - PSF1, 2 - PSF2, ...) >=20 > + >=20 > + @retval PSF SideBand Port ID >=20 > +**/ >=20 > +PCH_SBI_PID >=20 > +PsfSbPortId ( >=20 > + UINT32 PsfId >=20 > + ); >=20 > + >=20 > +/** >=20 > + Get EOI register data for given PSF ID >=20 > + >=20 > + @param[in] PsfId PSF ID (1 - PSF1, 2 - PSF2, ...) >=20 > + @param[out] EoiTargetBase EOI Target register >=20 > + @param[out] EoiControlBase EOI Control register >=20 > + >=20 > + @retval MaxTargets Number of supported targets >=20 > + >=20 > +**/ >=20 > +UINT8 >=20 > +PsfEoiRegData ( >=20 > + UINT32 PsfId, >=20 > + UINT16 *EoiTargetBase, >=20 > + UINT16 *EoiControlBase >=20 > + ); >=20 > + >=20 > +/** >=20 > + Get MCTP register data for given PSF ID >=20 > + >=20 > + @param[in] PsfId PSF ID (1 - PSF1, 2 - PSF2, ...) >=20 > + @param[out] MctpTargetBase MCTP Target register >=20 > + @param[out] MctpControlBase MCTP Control register >=20 > + >=20 > + @retval MaxTargets Number of supported targets >=20 > + >=20 > +**/ >=20 > +UINT8 >=20 > +PsfMctpRegData ( >=20 > + UINT32 PsfId, >=20 > + UINT16 *MctpTargetBase, >=20 > + UINT16 *MctpControlBase >=20 > + ); >=20 > + >=20 > +/** >=20 > + Check if MCTP is supported >=20 > + >=20 > + @retval TRUE MCTP is supported >=20 > + FALSE MCTP is not supported >=20 > +**/ >=20 > +BOOLEAN >=20 > +PsfIsMctpSupported ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Return the PSF (Root level) Function Config PSF_PORT for PCIe Root Por= t >=20 > + >=20 > + @param[in] RpIndex PCIe Root Port Index (0 based) >=20 > + >=20 > + @retval PsfPort PSF PORT structure for PCIe Function Config >=20 > +**/ >=20 > +PSF_PORT >=20 > +PsfRootPcieFunctionConfigPort ( >=20 > + IN UINT32 RpIndex >=20 > + ); >=20 > + >=20 > +/** >=20 > + Return the PSF (Root level) RS3 Function Config PSF_PORT for PCIe Root > Port >=20 > + >=20 > + @param[in] RpIndex PCIe Root Port Index (0 based) >=20 > + >=20 > + @retval PsfPort PSF PORT structure for PCIe Function Config >=20 > +**/ >=20 > +PSF_PORT >=20 > +PsfRootRs3PcieFunctionConfigPort ( >=20 > + IN UINT32 RpIndex >=20 > + ); >=20 > + >=20 > +/** >=20 > + Return the PSF Function Config Second Level PSF_PORT for PCIe Root Por= t >=20 > + >=20 > + @param[in] RpIndex PCIe Root Port Index (0 based) >=20 > + >=20 > + @retval PsfPort PSF PORT structure for PCIe Function Config >=20 > +**/ >=20 > +PSF_PORT >=20 > +PsfPcieFunctionConfigSecondLevelPort ( >=20 > + IN UINT32 RpIndex >=20 > + ); >=20 > + >=20 > +/** >=20 > + This function returns Psf Port Relaxed Ordering Configs >=20 > + >=20 > + @param[out] PsfPortRelaxedOrderingConfigRegs = PCH Series > specific table >=20 > + @param[out] PsfPortRelaxedOrderingConfigRegsTableSize = PCH > Series specific table size >=20 > + @param[out] PsfPortRelaxedOrderingConfigRegsPchTypeSpecific > PCH type specific table >=20 > + @param[out] > PsfPortRelaxedOrderingConfigRegsPchTypeSpecificTableSize PCH type > specific table size >=20 > +**/ >=20 > +VOID >=20 > +GetPsfPortRelaxedOrderingTables ( >=20 > + PSF_PORT_RELAXED_ORDERING_CONFIG_REG** > PsfPortRelaxedOrderingConfigRegs, >=20 > + UINT32* PsfPortRelaxedOrderingConfigReg= sTableSize, >=20 > + PSF_PORT_RELAXED_ORDERING_CONFIG_REG** > PsfPortRelaxedOrderingConfigRegsPchTypeSpecific, >=20 > + UINT32* > PsfPortRelaxedOrderingConfigRegsPchTypeSpecificTableSize >=20 > + ); >=20 > + >=20 > +#endif >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Psf/LibraryPrivate/PsfLib/Psf= LibV > er2.c > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Psf/LibraryPrivate/PsfLib/Psf= LibV > er2.c > new file mode 100644 > index 0000000000..fd21e5bed4 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Psf/LibraryPrivate/PsfLib/Psf= LibV > er2.c > @@ -0,0 +1,115 @@ > +/** @file >=20 > + This file contains internal PSF routines for PCH PSF VER2 lib usage >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include "PsfLibInternal.h" >=20 > +#include >=20 > + >=20 > + >=20 > +/** >=20 > + Get EOI register data for given PSF ID >=20 > + >=20 > + @param[in] PsfId PSF ID (1 - PSF1, 2 - PSF2, ...) >=20 > + @param[out] EoiTargetBase EOI Target register >=20 > + @param[out] EoiControlBase EOI Control register >=20 > + >=20 > + @retval MaxTargets Number of supported targets >=20 > + >=20 > +**/ >=20 > +UINT8 >=20 > +PsfEoiRegData ( >=20 > + UINT32 PsfId, >=20 > + UINT16 *EoiTargetBase, >=20 > + UINT16 *EoiControlBase >=20 > + ) >=20 > +{ >=20 > + UINT8 MaxTargets; >=20 > + >=20 > + MaxTargets =3D 0; >=20 > + *EoiTargetBase =3D 0; >=20 > + *EoiControlBase =3D 0; >=20 > + >=20 > + switch (PsfId) { >=20 > + case 1: >=20 > + break; >=20 > + >=20 > + case 3: >=20 > + break; >=20 > + >=20 > + case 7: >=20 > + break; >=20 > + >=20 > + case 8: >=20 > + break; >=20 > + >=20 > + case 9: >=20 > + break; >=20 > + >=20 > + default: >=20 > + break; >=20 > + >=20 > + } >=20 > + return MaxTargets; >=20 > +} >=20 > + >=20 > +GLOBAL_REMOVE_IF_UNREFERENCED PSF_PORT_DEST_ID > PchLpRpDestId[] =3D >=20 > +{ >=20 > + {0x18000}, {0x18001}, {0x18002}, {0x18003}, // SPA: PSF1, PortID =3D 0 >=20 > + {0x18100}, {0x18101}, {0x18102}, {0x18103}, // SPB: PSF1, PortID =3D 1 >=20 > + {0x18200}, {0x18201}, {0x18202}, {0x18203}, // SPC: PSF1, PortID =3D 2 >=20 > +}; >=20 > + >=20 > +/** >=20 > + PCIe PSF port destination ID (psf_id:port_group_id:port_id:channel_id) >=20 > + >=20 > + @param[in] RpIndex PCIe Root Port Index (0 based) >=20 > + >=20 > + @retval Destination ID >=20 > +**/ >=20 > +PSF_PORT_DEST_ID >=20 > +PsfPcieDestinationId ( >=20 > + IN UINT32 RpIndex >=20 > + ) >=20 > +{ >=20 > + if (RpIndex < ARRAY_SIZE (PchLpRpDestId)) { >=20 > + return PchLpRpDestId[RpIndex]; >=20 > + } >=20 > + ASSERT (FALSE); >=20 > + return (PSF_PORT_DEST_ID){0}; >=20 > +} >=20 > + >=20 > +GLOBAL_REMOVE_IF_UNREFERENCED PSF_SEGMENT mPchLpPsfTable[] =3D >=20 > +{ >=20 > + {1, PID_PSF1}, >=20 > + {2, PID_PSF2}, >=20 > + {3, PID_PSF3}, >=20 > + {4, PID_PSF4}, >=20 > + {5, PID_CSME_PSF}, >=20 > + {6, PID_PSF6} >=20 > +}; >=20 > + >=20 > +/** >=20 > + Get list of supported PSF segments. >=20 > + >=20 > + @param[out] PsfTable Array of supported PSF segments >=20 > + @param[out] PsfTableLength Length of PsfTable >=20 > +**/ >=20 > +VOID >=20 > +PsfSegments ( >=20 > + OUT PSF_SEGMENT **PsfTable, >=20 > + OUT UINT32 *PsfTableLength >=20 > + ) >=20 > +{ >=20 > +*PsfTable =3D mPchLpPsfTable; >=20 > + *PsfTableLength =3D ARRAY_SIZE (mPchLpPsfTable); >=20 > +} >=20 > -- > 2.24.0.windows.2