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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Nate DeSimone > -----Original Message----- > From: Luo, Heng > Sent: Sunday, January 31, 2021 5:37 PM > To: devel@edk2.groups.io > Cc: Chaganty, Rangasai V ; Desimone, > Nathaniel L > Subject: [PATCH 14/40] TigerlakeSiliconPkg/IpBlock: Add CpuPcieRp > component >=20 > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3171 >=20 > Adds the following files: > * IpBlock/CpuPcieRp/Include > * IpBlock/CpuPcieRp/IncludePrivate > * IpBlock/CpuPcieRp/Library > * IpBlock/CpuPcieRp/LibraryPrivate >=20 > Cc: Sai Chaganty > Cc: Nate DeSimone > Signed-off-by: Heng Luo > --- > Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Include/CpuPcieInfo.= h > | 31 +++++++++++++++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Include/Library/CpuPc= ie > InitCommon.h | 353 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Include/Library/CpuPc= ie > RpLib.h | 47 > +++++++++++++++++++++++++++++++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/IncludePrivate/Librar= y/D > xeCpuPcieRpLib.h | 18 ++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Library/PeiDxeSmmCpu > PcieInitCommonLib/CpuPcieInitCommon.c | 445 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Library/PeiDxeSmmCpu > PcieInitCommonLib/PeiDxeSmmCpuPcieInitCommonLib.inf | 33 > +++++++++++++++++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Library/PeiDxeSmmCpu > PcieRpLib/CpuPcieRpLib.c | 48 > ++++++++++++++++++++++++++++++++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Library/PeiDxeSmmCpu > PcieRpLib/PeiDxeSmmCpuPcieRpLib.inf | 32 > ++++++++++++++++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/LibraryPrivate/DxeCpu= P > cieRpLib/DxeCpuPcieRpLib.c | 62 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/LibraryPrivate/DxeCpu= P > cieRpLib/DxeCpuPcieRpLib.inf | 40 > ++++++++++++++++++++++++++++++++++++++++ > 10 files changed, 1109 insertions(+) >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Include/CpuPcieInfo= .h > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Include/CpuPcieInfo= . > h > new file mode 100644 > index 0000000000..15eeab0ecf > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Include/CpuPcieInfo= . > h > @@ -0,0 +1,31 @@ > +/** @file >=20 > + This file contains definitions of PCIe controller information >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _CPU_PCIE_INFO_H_ >=20 > +#define _CPU_PCIE_INFO_H_ >=20 > + >=20 > +#define PCIE_HWEQ_COEFFS_MAX 5 >=20 > + >=20 > +// >=20 > +// Device 1 Memory Mapped IO Register Offset Equates >=20 > +// >=20 > +#define SA_PEG_DEV_NUM 0x01 >=20 > +#define SA_PEG0_DEV_NUM SA_PEG_DEV_NUM >=20 > +#define SA_PEG3_DEV_NUM 0x06 >=20 > + >=20 > +// >=20 > +// SA PCI Express* Port configuration >=20 > +// >=20 > + >=20 > +#define CPU_PCIE_MAX_ROOT_PORTS 4 >=20 > + >=20 > +#define SA_PEG_MAX_FUN 0x04 >=20 > +#define SA_PEG_MAX_LANE 0x14 >=20 > +#define SA_PEG_MAX_FUN_GEN3 0x03 >=20 > +#define SA_PEG_MAX_LANE_GEN3 0x10 >=20 > +#define SA_PEG_MAX_BUNDLE_GEN3 0x08 >=20 > + >=20 > +#endif >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Include/Library/Cpu= Pc > ieInitCommon.h > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Include/Library/Cpu= Pc > ieInitCommon.h > new file mode 100644 > index 0000000000..79b255c273 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Include/Library/Cpu= Pc > ieInitCommon.h > @@ -0,0 +1,353 @@ > +/** @file >=20 > +Header file for CpuPcieInitCommonLib. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _CPU_PCIE_INIT_COMMON_H_ >=20 > +#define _CPU_PCIE_INIT_COMMON_H_ >=20 > + >=20 > +#include >=20 > + >=20 > +/** >=20 > + Print registers value >=20 > + >=20 > + @param[in] PrintMmioBase Mmio base address >=20 > + @param[in] PrintSize Number of registers >=20 > + @param[in] OffsetFromBase Offset from mmio base address >=20 > + >=20 > + @retval None >=20 > +**/ >=20 > +VOID >=20 > +SaPrintRegisters ( >=20 > + IN UINTN PrintMmioBase, >=20 > + IN UINT32 PrintSize, >=20 > + IN UINT32 OffsetFromBase >=20 > + ); >=20 > + >=20 > +/** >=20 > + Print registers value >=20 > + >=20 > + @param[in] PrintPciSegmentBase Pci segment base address >=20 > + @param[in] PrintSize Number of registers >=20 > + @param[in] OffsetFromBase Offset from mmio base address >=20 > + >=20 > + @retval None >=20 > +**/ >=20 > +VOID >=20 > +SaPrintPciRegisters ( >=20 > + IN UINT64 PrintPciSegmentBase, >=20 > + IN UINT32 PrintSize, >=20 > + IN UINT32 OffsetFromBase >=20 > + ); >=20 > + >=20 > +// >=20 > +// 2LM: PegPcie APIs for Sideband Access Mechanism in 2LM mode >=20 > +// >=20 > +/** >=20 > +Reads an 8-bit PCI configuration register. >=20 > + >=20 > +Its a wrapper library function. This function uses side band access for = PEG60 > when 2LM mode is enabled. >=20 > +Other calls to this function will be routed to core PciSegmentRead8 > function. >=20 > + >=20 > +@param Address Address that encodes the PCI Segment, Bus, Device, > Function, and Register. >=20 > + >=20 > +@return The 8-bit PCI configuration register specified by Address. >=20 > + >=20 > +**/ >=20 > +UINT8 >=20 > +EFIAPI >=20 > +PegPciSegmentRead8 ( >=20 > + IN UINT64 Address >=20 > + ); >=20 > + >=20 > +/** >=20 > +Writes an 8-bit PCI configuration register. >=20 > + >=20 > +Its a wrapper library function. This function uses side band access for = PEG60 > when 2LM mode is enabled. >=20 > +Other calls to this function will be routed to core PciSegmentWrite8 > function. >=20 > + >=20 > +@param Address Address that encodes the PCI Segment, Bus, Device, > Function, and Register. >=20 > +@param Value The value to write. >=20 > + >=20 > +@return The value written to the PCI configuration register. >=20 > + >=20 > +**/ >=20 > +UINT8 >=20 > +EFIAPI >=20 > +PegPciSegmentWrite8 ( >=20 > + IN UINT64 Address, >=20 > + IN UINT8 Value >=20 > + ); >=20 > + >=20 > +/** >=20 > +Reads a 16-bit PCI configuration register. >=20 > + >=20 > +Its a wrapper library function. This function uses side band access for = PEG60 > when 2LM mode is enabled. >=20 > +Other calls to this function will be routed to core PciSegmentRead16 > function. >=20 > + >=20 > +@param Address Address that encodes the PCI Segment, Bus, Device, > Function, and Register. >=20 > + >=20 > +@return The 16-bit PCI configuration register specified by Address. >=20 > + >=20 > +**/ >=20 > +UINT16 >=20 > +EFIAPI >=20 > +PegPciSegmentRead16 ( >=20 > + IN UINT64 Address >=20 > + ); >=20 > + >=20 > +/** >=20 > +Writes a 16-bit PCI configuration register. >=20 > + >=20 > +Its a wrapper library function. This function uses side band access for = PEG60 > when 2LM mode is enabled. >=20 > +Other calls to this function will be routed to core PciSegmentWrite16 > function. >=20 > + >=20 > +@param Address Address that encodes the PCI Segment, Bus, Device, > Function, and Register. >=20 > +@param Value The value to write. >=20 > + >=20 > +@return The parameter of Value. >=20 > + >=20 > +**/ >=20 > +UINT16 >=20 > +EFIAPI >=20 > +PegPciSegmentWrite16 ( >=20 > + IN UINT64 Address, >=20 > + IN UINT16 Value >=20 > + ); >=20 > + >=20 > +/** >=20 > +Reads a 32-bit PCI configuration register. >=20 > + >=20 > +Its a wrapper library function. This function uses side band access for = PEG60 > when 2LM mode is enabled. >=20 > +Other calls to this function will be routed to core PciSegmentRead32 > function. >=20 > + >=20 > +@param Address Address that encodes the PCI Segment, Bus, Device, > Function, and Register. >=20 > + >=20 > +@return The 32-bit PCI configuration register specified by Address. >=20 > + >=20 > +**/ >=20 > +UINT32 >=20 > +EFIAPI >=20 > +PegPciSegmentRead32 ( >=20 > + IN UINT64 Address >=20 > + ); >=20 > + >=20 > +/** >=20 > +Writes a 32-bit PCI configuration register. >=20 > + >=20 > +Its a wrapper library function. This function uses side band access for = PEG60 > when 2LM mode is enabled. >=20 > +Other calls to this function will be routed to core PciSegmentWrite32 > function. >=20 > + >=20 > +@param Address Address that encodes the PCI Segment, Bus, Device, > Function, and Register. >=20 > +@param Value The value to write. >=20 > + >=20 > +@return The parameter of Value. >=20 > + >=20 > +**/ >=20 > +UINT32 >=20 > +EFIAPI >=20 > +PegPciSegmentWrite32 ( >=20 > + IN UINT64 Address, >=20 > + IN UINT32 Value >=20 > + ); >=20 > + >=20 > +/** >=20 > +Performs a bitwise OR of a 16-bit PCI configuration register with a 16-b= it > value. >=20 > + >=20 > +Its a wrapper library function. This function uses side band access for = PEG60 > when 2LM mode is enabled. >=20 > +Other calls to this function will be routed to core PciSegmentOr16 funct= ion. >=20 > + >=20 > +@param Address Address that encodes the PCI Segment, Bus, Device, > Function, and Register. >=20 > +@param OrData The value to OR with the PCI configuration register. >=20 > + >=20 > +@return The value written to the PCI configuration register. >=20 > +**/ >=20 > +UINT16 >=20 > +EFIAPI >=20 > +PegPciSegmentOr16 ( >=20 > + IN UINT64 Address, >=20 > + IN UINT16 OrData >=20 > + ); >=20 > + >=20 > +/** >=20 > +Performs a bitwise AND of a 16-bit PCI configuration register with a 16-= bit > value. >=20 > + >=20 > +Its a wrapper library function. This function uses side band access for = PEG60 > when 2LM mode is enabled. >=20 > +Other calls to this function will be routed to core PciSegmentAnd32 > function. >=20 > + >=20 > +@param Address Address that encodes the PCI Segment, Bus, Device, > Function, and Register. >=20 > +@param AndData The value to AND with the PCI configuration register. >=20 > + >=20 > +@return The value written to the PCI configuration register. >=20 > + >=20 > +**/ >=20 > +UINT16 >=20 > +EFIAPI >=20 > +PegPciSegmentAnd16 ( >=20 > + IN UINT64 Address, >=20 > + IN UINT16 AndData >=20 > + ); >=20 > + >=20 > +/** >=20 > +Performs a bitwise AND of a 8-bit PCI configuration register with a 8-bi= t > value. >=20 > + >=20 > +Its a wrapper library function. This function uses side band access for = PEG60 > when 2LM mode is enabled. >=20 > +Other calls to this function will be routed to core PciSegmentAnd8 funct= ion. >=20 > + >=20 > +@param Address Address that encodes the PCI Segment, Bus, Device, > Function, and Register. >=20 > +@param AndData The value to AND with the PCI configuration register. >=20 > + >=20 > +@return The value written to the PCI configuration register. >=20 > + >=20 > +**/ >=20 > +UINT8 >=20 > +EFIAPI >=20 > +PegPciSegmentAnd8 ( >=20 > + IN UINT64 Address, >=20 > + IN UINT8 AndData >=20 > + ); >=20 > + >=20 > +/** >=20 > +Performs a bitwise OR of a 32-bit PCI configuration register with a 32-b= it > value. >=20 > + >=20 > +Its a wrapper library function. This function uses side band access for = PEG60 > when 2LM mode is enabled. >=20 > +Other calls to this function will be routed to core PciSegmentOr32 funct= ion. >=20 > + >=20 > +@param Address Address that encodes the PCI Segment, Bus, Device, > Function, and Register. >=20 > +@param OrData The value to OR with the PCI configuration register. >=20 > + >=20 > +@return The value written to the PCI configuration register. >=20 > + >=20 > +**/ >=20 > +UINT32 >=20 > +EFIAPI >=20 > +PegPciSegmentOr32 ( >=20 > + IN UINT64 Address, >=20 > + IN UINT32 OrData >=20 > + ); >=20 > + >=20 > +/** >=20 > +Performs a bitwise OR of a 8-bit PCI configuration register with a 8-bit= value. >=20 > + >=20 > +Its a wrapper library function. This function uses side band access for = PEG60 > when 2LM mode is enabled. >=20 > +Other calls to this function will be routed to core PciSegmentOr8 functi= on. >=20 > + >=20 > +@param Address Address that encodes the PCI Segment, Bus, Device, > Function, and Register. >=20 > +@param OrData The value to OR with the PCI configuration register. >=20 > + >=20 > +@return The value written to the PCI configuration register. >=20 > + >=20 > +**/ >=20 > +UINT8 >=20 > +EFIAPI >=20 > +PegPciSegmentOr8 ( >=20 > + IN UINT64 Address, >=20 > + IN UINT8 OrData >=20 > + ); >=20 > + >=20 > +/** >=20 > +Performs a bitwise AND of a 32-bit PCI configuration register with a 32-= bit > value. >=20 > + >=20 > +Its a wrapper library function. This function uses side band access for = PEG60 > when 2LM mode is enabled. >=20 > +Other calls to this function will be routed to core PciSegmentAnd32 > function. >=20 > + >=20 > +@param Address Address that encodes the PCI Segment, Bus, Device, > Function, and Register. >=20 > +@param AndData The value to AND with the PCI configuration register. >=20 > + >=20 > +@return The value written to the PCI configuration register. >=20 > + >=20 > +**/ >=20 > +UINT32 >=20 > +EFIAPI >=20 > +PegPciSegmentAnd32 ( >=20 > + IN UINT64 Address, >=20 > + IN UINT32 AndData >=20 > + ); >=20 > + >=20 > +/** >=20 > +Performs a bitwise AND of a 32-bit PCI configuration register with a 32-= bit > value, >=20 > +followed a bitwise OR with another 32-bit value. >=20 > + >=20 > +Its a wrapper library function. This function uses side band access for = PEG60 > when 2LM mode is enabled. >=20 > +Other calls to this function will be routed to core PciSegmentAndThenOr3= 2 > function. >=20 > + >=20 > +@param Address Address that encodes the PCI Segment, Bus, Device, > Function, and Register. >=20 > +@param AndData The value to AND with the PCI configuration register. >=20 > +@param OrData The value to OR with the PCI configuration register. >=20 > + >=20 > +@return The value written to the PCI configuration register. >=20 > + >=20 > +**/ >=20 > +UINT32 >=20 > +EFIAPI >=20 > +PegPciSegmentAndThenOr32 ( >=20 > + IN UINT64 Address, >=20 > + IN UINT32 AndData, >=20 > + IN UINT32 OrData >=20 > + ); >=20 > + >=20 > +/** >=20 > +Performs a bitwise AND of a 16-bit PCI configuration register with a 16-= bit > value, >=20 > +followed a bitwise OR with another 16-bit value. >=20 > + >=20 > +Its a wrapper library function. This function uses side band access for = PEG60 > when 2LM mode is enabled. >=20 > +Other calls to this function will be routed to core PciSegmentAndThenOr1= 6 > function. >=20 > + >=20 > +@param Address Address that encodes the PCI Segment, Bus, Device, > Function, and Register. >=20 > +@param AndData The value to AND with the PCI configuration register. >=20 > +@param OrData The value to OR with the PCI configuration register. >=20 > + >=20 > +@return The value written to the PCI configuration register. >=20 > + >=20 > +**/ >=20 > +UINT16 >=20 > +EFIAPI >=20 > +PegPciSegmentAndThenOr16 ( >=20 > + IN UINT64 Address, >=20 > + IN UINT16 AndData, >=20 > + IN UINT16 OrData >=20 > + ); >=20 > + >=20 > +/** >=20 > +Performs a bitwise AND of a 8-bit PCI configuration register with a 8-bi= t > value, >=20 > +followed a bitwise OR with another 8-bit value. >=20 > + >=20 > +Its a wrapper library function. This function uses side band access for = PEG60 > when 2LM mode is enabled. >=20 > +Other calls to this function will be routed to core PciSegmentAndThenOr8 > function. >=20 > + >=20 > +@param Address Address that encodes the PCI Segment, Bus, Device, > Function, and Register. >=20 > +@param AndData The value to AND with the PCI configuration register. >=20 > +@param OrData The value to OR with the PCI configuration register. >=20 > + >=20 > +@return The value written to the PCI configuration register. >=20 > + >=20 > +**/ >=20 > +UINT8 >=20 > +EFIAPI >=20 > +PegPciSegmentAndThenOr8 ( >=20 > + IN UINT64 Address, >=20 > + IN UINT8 AndData, >=20 > + IN UINT8 OrData >=20 > + ); >=20 > + >=20 > +/** >=20 > +Find the Offset to a Capabilities ID >=20 > +@param[in] Segment Pci Segment Number >=20 > +@param[in] Bus Pci Bus Number >=20 > +@param[in] Device Pci Device Number >=20 > +@param[in] Function Pci Function Number >=20 > +@param[in] CapId CAPID to search for >=20 > + >=20 > +@retval 0 CAPID not found >=20 > +@retval Other CAPID found, Offset of desired CAPID >=20 > +**/ >=20 > +UINT8 >=20 > +PegPcieFindCapId ( >=20 > + IN UINT8 Segment, >=20 > + IN UINT8 Bus, >=20 > + IN UINT8 Device, >=20 > + IN UINT8 Function, >=20 > + IN UINT8 CapId >=20 > + ); >=20 > +#endif // _CPU_PCIE_INIT_COMMON_H_ >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Include/Library/Cpu= Pc > ieRpLib.h > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Include/Library/Cpu= Pc > ieRpLib.h > new file mode 100644 > index 0000000000..ebb568193a > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Include/Library/Cpu= Pc > ieRpLib.h > @@ -0,0 +1,47 @@ > +/** @file >=20 > + Header file for CpuPcieRpLib. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _CPU_PCIERP_LIB_H_ >=20 > +#define _CPU_PCIERP_LIB_H_ >=20 > + >=20 > +#include >=20 > +#include >=20 > + >=20 > +#pragma pack(1) >=20 > + >=20 > +typedef struct { >=20 > + UINT8 Segment; >=20 > + UINT8 Bus; >=20 > + UINT8 Device; >=20 > + UINT8 Function; >=20 > + BOOLEAN Enable; >=20 > +} CPU_PCIE_RP_INFO; >=20 > + >=20 > +#pragma pack() >=20 > + >=20 > +/** >=20 > + Determines whether PCIe link is active >=20 > + >=20 > + @param[in] RpBase Root Port base address >=20 > + @retval Link Active state >=20 > +**/ >=20 > +BOOLEAN >=20 > +CpuPcieIsLinkActive ( >=20 > + UINT64 RpBase >=20 > + ); >=20 > + >=20 > +/** >=20 > + Get max PCIe link speed supported by the root port. >=20 > + >=20 > + @param[in] RpBase Root Port pci segment base address >=20 > + @return Max link speed >=20 > +**/ >=20 > +UINT32 >=20 > +CpuPcieGetMaxLinkSpeed ( >=20 > + UINT64 RpBase >=20 > + ); >=20 > + >=20 > +#endif // _CPU_PCIERP_LIB_H_ >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/IncludePrivate/Libr= ary > /DxeCpuPcieRpLib.h > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/IncludePrivate/Libr= ary > /DxeCpuPcieRpLib.h > new file mode 100644 > index 0000000000..593e1893bb > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/IncludePrivate/Libr= ary > /DxeCpuPcieRpLib.h > @@ -0,0 +1,18 @@ > +/** @file >=20 > + Header file for private DxeCpuPcieRpLib. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _DXE_PCIE_RP_INIT_LIB_H_ >=20 > +#define _DXE_PCIE_RP_INIT_LIB_H_ >=20 > + >=20 > +/** >=20 > + Update CPU PCIE RP NVS AREA tables >=20 > + >=20 > +**/ >=20 > +VOID >=20 > +UpdateCpuPcieNVS ( >=20 > + VOID >=20 > + ); >=20 > +#endif >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Library/PeiDxeSmmCp > uPcieInitCommonLib/CpuPcieInitCommon.c > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Library/PeiDxeSmmC > puPcieInitCommonLib/CpuPcieInitCommon.c > new file mode 100644 > index 0000000000..28032e5b24 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Library/PeiDxeSmmC > puPcieInitCommonLib/CpuPcieInitCommon.c > @@ -0,0 +1,445 @@ > +/** @file >=20 > + common library for CPU PCIe INIT PEI/DXE/SMM modules >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +/** >=20 > + Print registers value >=20 > + >=20 > + @param[in] PrintMmioBase Mmio base address >=20 > + @param[in] PrintSize Number of registers >=20 > + @param[in] OffsetFromBase Offset from mmio base address >=20 > + >=20 > + @retval None >=20 > +**/ >=20 > +VOID >=20 > +SaPrintRegisters ( >=20 > + IN UINTN PrintMmioBase, >=20 > + IN UINT32 PrintSize, >=20 > + IN UINT32 OffsetFromBase >=20 > + ) >=20 > +{ >=20 > + UINT32 Offset; >=20 > + DEBUG ((DEBUG_VERBOSE, " 00 01 02 03 04 05 06 07 08 09 0A 0B 0C = 0D > 0E 0F")); >=20 > + for (Offset =3D 0; Offset < PrintSize; Offset++) { >=20 > + if ((Offset % 16) =3D=3D 0) { >=20 > + DEBUG ((DEBUG_VERBOSE, "\n %04X: ", (Offset + OffsetFromBase) & > 0xFFF0)); >=20 > + } >=20 > + DEBUG ((DEBUG_VERBOSE, "%02X ", MmioRead8 (PrintMmioBase + > Offset))); >=20 > + } >=20 > + DEBUG ((DEBUG_VERBOSE, "\n")); >=20 > +} >=20 > + >=20 > +/** >=20 > + Print registers value >=20 > + >=20 > + @param[in] PrintPciSegmentBase Pci segment base address >=20 > + @param[in] PrintSize Number of registers >=20 > + @param[in] OffsetFromBase Offset from mmio base address >=20 > + >=20 > + @retval None >=20 > +**/ >=20 > +VOID >=20 > +SaPrintPciRegisters ( >=20 > + IN UINT64 PrintPciSegmentBase, >=20 > + IN UINT32 PrintSize, >=20 > + IN UINT32 OffsetFromBase >=20 > + ) >=20 > +{ >=20 > + UINT32 Offset; >=20 > + DEBUG ((DEBUG_VERBOSE, " 00 01 02 03 04 05 06 07 08 09 0A 0B 0C = 0D > 0E 0F")); >=20 > + for (Offset =3D 0; Offset < PrintSize; Offset++) { >=20 > + if ((Offset % 16) =3D=3D 0) { >=20 > + DEBUG ((DEBUG_VERBOSE, "\n %04X: ", (Offset + OffsetFromBase) & > 0xFFF0)); >=20 > + } >=20 > + DEBUG ((DEBUG_VERBOSE, "%02X ", PciSegmentRead8 > (PrintPciSegmentBase + Offset))); >=20 > + } >=20 > + DEBUG ((DEBUG_VERBOSE, "\n")); >=20 > +} >=20 > + >=20 > +// >=20 > +// 2LM: PegPcie APIs using the Sideband Access Mechanism >=20 > +// >=20 > +/** >=20 > + Reads an 8-bit PCI configuration register. >=20 > + >=20 > + Its a wrapper library function. This function uses side band access fo= r > PEG60 when 2LM mode is enabled. >=20 > + Other calls to this function will be routed to core PciSegmentRead8 > function. >=20 > + >=20 > + @param Address Address that encodes the PCI Segment, Bus, Device, > Function, and Register. >=20 > + >=20 > + @return The 8-bit PCI configuration register specified by Address. >=20 > +**/ >=20 > +UINT8 >=20 > +EFIAPI >=20 > +PegPciSegmentRead8 ( >=20 > + IN UINT64 Address >=20 > + ) >=20 > +{ >=20 > + return PciSegmentRead8 (Address); >=20 > +} >=20 > + >=20 > +/** >=20 > + Writes an 8-bit PCI configuration register. >=20 > + >=20 > + Its a wrapper library function. This function uses side band access fo= r > PEG60 when 2LM mode is enabled. >=20 > + Other calls to this function will be routed to core PciSegmentWrite8 > function. >=20 > + >=20 > + @param Address Address that encodes the PCI Segment, Bus, Device, > Function, and Register. >=20 > + @param Value The value to write. >=20 > + >=20 > + @return The value written to the PCI configuration register. >=20 > +**/ >=20 > +UINT8 >=20 > +EFIAPI >=20 > +PegPciSegmentWrite8 ( >=20 > + IN UINT64 Address, >=20 > + IN UINT8 Value >=20 > + ) >=20 > +{ >=20 > + return PciSegmentWrite8 (Address, Value); >=20 > +} >=20 > + >=20 > +/** >=20 > + Reads a 16-bit PCI configuration register. >=20 > + >=20 > + Its a wrapper library function. This function uses side band access fo= r > PEG60 when 2LM mode is enabled. >=20 > + Other calls to this function will be routed to core PciSegmentRead16 > function. >=20 > + >=20 > + @param Address Address that encodes the PCI Segment, Bus, Device, > Function, and Register. >=20 > + >=20 > + @return The 16-bit PCI configuration register specified by Address. >=20 > +**/ >=20 > +UINT16 >=20 > +EFIAPI >=20 > +PegPciSegmentRead16 ( >=20 > + IN UINT64 Address >=20 > + ) >=20 > +{ >=20 > + return PciSegmentRead16 (Address); >=20 > +} >=20 > + >=20 > +/** >=20 > + Writes a 16-bit PCI configuration register. >=20 > + >=20 > + Its a wrapper library function. This function uses side band access fo= r > PEG60 when 2LM mode is enabled. >=20 > + Other calls to this function will be routed to core PciSegmentWrite16 > function. >=20 > + >=20 > + @param Address Address that encodes the PCI Segment, Bus, Device, > Function, and Register. >=20 > + @param Value The value to write. >=20 > + >=20 > + @return The parameter of Value. >=20 > +**/ >=20 > +UINT16 >=20 > +EFIAPI >=20 > +PegPciSegmentWrite16 ( >=20 > + IN UINT64 Address, >=20 > + IN UINT16 Value >=20 > + ) >=20 > +{ >=20 > + return PciSegmentWrite16 (Address, Value); >=20 > +} >=20 > + >=20 > +/** >=20 > + Reads a 32-bit PCI configuration register. >=20 > + >=20 > + Its a wrapper library function. This function uses side band access fo= r > PEG60 when 2LM mode is enabled. >=20 > + Other calls to this function will be routed to core PciSegmentRead32 > function. >=20 > + >=20 > + @param Address Address that encodes the PCI Segment, Bus, Device, > Function, and Register. >=20 > + >=20 > + @return The 32-bit PCI configuration register specified by Address. >=20 > +**/ >=20 > +UINT32 >=20 > +EFIAPI >=20 > +PegPciSegmentRead32 ( >=20 > + IN UINT64 Address >=20 > + ) >=20 > +{ >=20 > + return PciSegmentRead32 (Address); >=20 > +} >=20 > + >=20 > +/** >=20 > + Writes a 32-bit PCI configuration register. >=20 > + >=20 > + Its a wrapper library function. This function uses side band access fo= r > PEG60 when 2LM mode is enabled. >=20 > + Other calls to this function will be routed to core PciSegmentWrite32 > function. >=20 > + >=20 > + @param Address Address that encodes the PCI Segment, Bus, Device, > Function, and Register. >=20 > + @param Value The value to write. >=20 > + >=20 > + @return The parameter of Value. >=20 > +**/ >=20 > +UINT32 >=20 > +EFIAPI >=20 > +PegPciSegmentWrite32 ( >=20 > + IN UINT64 Address, >=20 > + IN UINT32 Value >=20 > + ) >=20 > +{ >=20 > + return PciSegmentWrite32 (Address, Value); >=20 > +} >=20 > + >=20 > +/** >=20 > + Performs a bitwise OR of a 16-bit PCI configuration register with a 16= -bit > value. >=20 > + >=20 > + Its a wrapper library function. This function uses side band access fo= r > PEG60 when 2LM mode is enabled. >=20 > + Other calls to this function will be routed to core PciSegmentOr16 fun= ction. >=20 > + >=20 > + @param Address Address that encodes the PCI Segment, Bus, Device, > Function, and Register. >=20 > + @param OrData The value to OR with the PCI configuration register. >=20 > + >=20 > + @return The value written to the PCI configuration register. >=20 > +**/ >=20 > +UINT16 >=20 > +EFIAPI >=20 > +PegPciSegmentOr16 ( >=20 > + IN UINT64 Address, >=20 > + IN UINT16 OrData >=20 > + ) >=20 > +{ >=20 > + return PciSegmentOr16 (Address, OrData); >=20 > +} >=20 > + >=20 > +/** >=20 > + Performs a bitwise AND of a 16-bit PCI configuration register with a 1= 6-bit > value. >=20 > + >=20 > + Its a wrapper library function. This function uses side band access fo= r > PEG60 when 2LM mode is enabled. >=20 > + Other calls to this function will be routed to core PciSegmentAnd32 > function. >=20 > + >=20 > + @param Address Address that encodes the PCI Segment, Bus, Device, > Function, and Register. >=20 > + @param AndData The value to AND with the PCI configuration register= . >=20 > + >=20 > + @return The value written to the PCI configuration register. >=20 > + >=20 > +**/ >=20 > +UINT16 >=20 > +EFIAPI >=20 > +PegPciSegmentAnd16 ( >=20 > + IN UINT64 Address, >=20 > + IN UINT16 AndData >=20 > + ) >=20 > +{ >=20 > + return PciSegmentAnd16 (Address, AndData); >=20 > +} >=20 > + >=20 > +/** >=20 > + Performs a bitwise AND of a 8-bit PCI configuration register with a 8-= bit > value. >=20 > + >=20 > + Its a wrapper library function. This function uses side band access fo= r > PEG60 when 2LM mode is enabled. >=20 > + Other calls to this function will be routed to core PciSegmentAnd8 > function. >=20 > + >=20 > + @param Address Address that encodes the PCI Segment, Bus, Device, > Function, and Register. >=20 > + @param AndData The value to AND with the PCI configuration register= . >=20 > + >=20 > + @return The value written to the PCI configuration register. >=20 > + >=20 > +**/ >=20 > +UINT8 >=20 > +EFIAPI >=20 > +PegPciSegmentAnd8 ( >=20 > + IN UINT64 Address, >=20 > + IN UINT8 AndData >=20 > + ) >=20 > +{ >=20 > + return PciSegmentAnd8 (Address, AndData); >=20 > +} >=20 > + >=20 > +/** >=20 > + Performs a bitwise OR of a 32-bit PCI configuration register with a 32= -bit > value. >=20 > + >=20 > + Its a wrapper library function. This function uses side band access fo= r > PEG60 when 2LM mode is enabled. >=20 > + Other calls to this function will be routed to core PciSegmentOr32 fun= ction. >=20 > + >=20 > + @param Address Address that encodes the PCI Segment, Bus, Device, > Function, and Register. >=20 > + @param OrData The value to OR with the PCI configuration register. >=20 > + >=20 > + @return The value written to the PCI configuration register. >=20 > +**/ >=20 > +UINT32 >=20 > +EFIAPI >=20 > +PegPciSegmentOr32 ( >=20 > + IN UINT64 Address, >=20 > + IN UINT32 OrData >=20 > + ) >=20 > +{ >=20 > + return PciSegmentOr32 (Address, OrData); >=20 > +} >=20 > + >=20 > +/** >=20 > + Performs a bitwise OR of a 8-bit PCI configuration register with a 8-b= it > value. >=20 > + >=20 > + Its a wrapper library function. This function uses side band access fo= r > PEG60 when 2LM mode is enabled. >=20 > + Other calls to this function will be routed to core PciSegmentOr8 func= tion. >=20 > + >=20 > + @param Address Address that encodes the PCI Segment, Bus, Device, > Function, and Register. >=20 > + @param OrData The value to OR with the PCI configuration register. >=20 > + >=20 > + @return The value written to the PCI configuration register. >=20 > +**/ >=20 > +UINT8 >=20 > +EFIAPI >=20 > +PegPciSegmentOr8 ( >=20 > + IN UINT64 Address, >=20 > + IN UINT8 OrData >=20 > + ) >=20 > +{ >=20 > + return PciSegmentOr8 (Address, OrData); >=20 > +} >=20 > + >=20 > +/** >=20 > + Performs a bitwise AND of a 32-bit PCI configuration register with a 3= 2-bit > value. >=20 > + >=20 > + Its a wrapper library function. This function uses side band access fo= r > PEG60 when 2LM mode is enabled. >=20 > + Other calls to this function will be routed to core PciSegmentAnd32 > function. >=20 > + >=20 > + @param Address Address that encodes the PCI Segment, Bus, Device, > Function, and Register. >=20 > + @param AndData The value to AND with the PCI configuration register= . >=20 > + >=20 > + @return The value written to the PCI configuration register. >=20 > + >=20 > +**/ >=20 > +UINT32 >=20 > +EFIAPI >=20 > +PegPciSegmentAnd32 ( >=20 > + IN UINT64 Address, >=20 > + IN UINT32 AndData >=20 > + ) >=20 > +{ >=20 > + return PciSegmentAnd32 (Address, AndData); >=20 > +} >=20 > + >=20 > +/** >=20 > + Performs a bitwise AND of a 32-bit PCI configuration register with a 3= 2-bit > value, >=20 > + followed a bitwise OR with another 32-bit value. >=20 > + >=20 > + Its a wrapper library function. This function uses side band access fo= r > PEG60 when 2LM mode is enabled. >=20 > + Other calls to this function will be routed to core PciSegmentAndThenO= r32 > function. >=20 > + >=20 > + @param Address Address that encodes the PCI Segment, Bus, Device, > Function, and Register. >=20 > + @param AndData The value to AND with the PCI configuration register= . >=20 > + @param OrData The value to OR with the PCI configuration register. >=20 > + >=20 > + @return The value written to the PCI configuration register. >=20 > +**/ >=20 > +UINT32 >=20 > +EFIAPI >=20 > +PegPciSegmentAndThenOr32 ( >=20 > + IN UINT64 Address, >=20 > + IN UINT32 AndData, >=20 > + IN UINT32 OrData >=20 > + ) >=20 > +{ >=20 > + return PciSegmentAndThenOr32 (Address, AndData, OrData); >=20 > +} >=20 > + >=20 > + >=20 > +/** >=20 > + Performs a bitwise AND of a 16-bit PCI configuration register with a 1= 6-bit > value, >=20 > + followed a bitwise OR with another 16-bit value. >=20 > + >=20 > + Its a wrapper library function. This function uses side band access fo= r > PEG60 when 2LM mode is enabled. >=20 > + Other calls to this function will be routed to core PciSegmentAndThenO= r16 > function. >=20 > + >=20 > + @param Address Address that encodes the PCI Segment, Bus, Device, > Function, and Register. >=20 > + @param AndData The value to AND with the PCI configuration register= . >=20 > + @param OrData The value to OR with the PCI configuration register. >=20 > + >=20 > + @return The value written to the PCI configuration register. >=20 > +**/ >=20 > +UINT16 >=20 > +EFIAPI >=20 > +PegPciSegmentAndThenOr16 ( >=20 > + IN UINT64 Address, >=20 > + IN UINT16 AndData, >=20 > + IN UINT16 OrData >=20 > + ) >=20 > +{ >=20 > + return PciSegmentAndThenOr16 (Address, AndData, OrData); >=20 > +} >=20 > + >=20 > + >=20 > +/** >=20 > + Performs a bitwise AND of a 8-bit PCI configuration register with a 8-= bit > value, >=20 > + followed a bitwise OR with another 8-bit value. >=20 > + >=20 > + Its a wrapper library function. This function uses side band access fo= r > PEG60 when 2LM mode is enabled. >=20 > + Other calls to this function will be routed to core PciSegmentAndThenO= r8 > function. >=20 > + >=20 > + @param Address Address that encodes the PCI Segment, Bus, Device, > Function, and Register. >=20 > + @param AndData The value to AND with the PCI configuration register= . >=20 > + @param OrData The value to OR with the PCI configuration register. >=20 > + >=20 > + @return The value written to the PCI configuration register. >=20 > +**/ >=20 > +UINT8 >=20 > +EFIAPI >=20 > +PegPciSegmentAndThenOr8 ( >=20 > + IN UINT64 Address, >=20 > + IN UINT8 AndData, >=20 > + IN UINT8 OrData >=20 > + ) >=20 > +{ >=20 > + return PciSegmentAndThenOr8 (Address, AndData, OrData); >=20 > +} >=20 > + >=20 > + >=20 > +/** >=20 > + Find the Offset to a Capabilities ID >=20 > + @param[in] Segment Pci Segment Number >=20 > + @param[in] Bus Pci Bus Number >=20 > + @param[in] Device Pci Device Number >=20 > + @param[in] Function Pci Function Number >=20 > + @param[in] CapId CAPID to search for >=20 > + >=20 > + @retval 0 CAPID not found >=20 > + @retval Other CAPID found, Offset of desired CAPID >=20 > +**/ >=20 > +UINT8 >=20 > +PegPcieFindCapId ( >=20 > + IN UINT8 Segment, >=20 > + IN UINT8 Bus, >=20 > + IN UINT8 Device, >=20 > + IN UINT8 Function, >=20 > + IN UINT8 CapId >=20 > + ) >=20 > +{ >=20 > + return PcieFindCapId (Segment, Bus, Device, Function, CapId); >=20 > +} >=20 > + >=20 > + >=20 > +/** >=20 > + Search and return the offset of desired Pci Express extended Capabilit= y ID >=20 > + @param[in] Segment Pci Segment Number >=20 > + @param[in] Bus Pci Bus Number >=20 > + @param[in] Device Pci Device Number >=20 > + @param[in] Function Pci Function Number >=20 > + @param[in] CapId Extended CAPID to search for >=20 > + >=20 > + @retval 0 CAPID not found >=20 > + @retval Other CAPID found, Offset of desired CAPID >=20 > +**/ >=20 > +UINT16 >=20 > +PegPcieFindExtendedCapId ( >=20 > + IN UINT8 Segment, >=20 > + IN UINT8 Bus, >=20 > + IN UINT8 Device, >=20 > + IN UINT8 Function, >=20 > + IN UINT16 CapId >=20 > + ) >=20 > +{ >=20 > + return PcieFindExtendedCapId (Segment, Bus, Device, Function, CapId); >=20 > +} >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Library/PeiDxeSmmCp > uPcieInitCommonLib/PeiDxeSmmCpuPcieInitCommonLib.inf > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Library/PeiDxeSmmC > puPcieInitCommonLib/PeiDxeSmmCpuPcieInitCommonLib.inf > new file mode 100644 > index 0000000000..2ad30ab7c9 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Library/PeiDxeSmmC > puPcieInitCommonLib/PeiDxeSmmCpuPcieInitCommonLib.inf > @@ -0,0 +1,33 @@ > +## @file >=20 > +# Component description file for the CpuPcieInitCommonLib >=20 > +# >=20 > +# Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > +# SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +# >=20 > +## >=20 > + >=20 > +[Defines] >=20 > + INF_VERSION =3D 0x00010017 >=20 > + BASE_NAME =3D PeiDxeSmmCpuPcieInitCommonLib >=20 > + FILE_GUID =3D 68992CB0-A3A5-4f73-9370-93A3559F84C= 8 >=20 > + MODULE_TYPE =3D BASE >=20 > + VERSION_STRING =3D 1.0 >=20 > + LIBRARY_CLASS =3D CpuPcieInitCommonLib >=20 > + >=20 > +[Sources] >=20 > + CpuPcieInitCommon.c >=20 > + >=20 > +[Packages] >=20 > + MdePkg/MdePkg.dec >=20 > + TigerlakeSiliconPkg/SiPkg.dec >=20 > + >=20 > +[LibraryClasses] >=20 > + IoLib >=20 > + DebugLib >=20 > + PciSegmentLib >=20 > + CpuPcieRpLib >=20 > + CpuRegbarAccessLib >=20 > + BasePcieHelperLib >=20 > + >=20 > +[Pcd] >=20 > + gSiPkgTokenSpaceGuid.PcdCpuPcieEnable ## CONSUMES >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Library/PeiDxeSmmCp > uPcieRpLib/CpuPcieRpLib.c > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Library/PeiDxeSmmC > puPcieRpLib/CpuPcieRpLib.c > new file mode 100644 > index 0000000000..02cd482b55 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Library/PeiDxeSmmC > puPcieRpLib/CpuPcieRpLib.c > @@ -0,0 +1,48 @@ > +/** @file >=20 > + CPU PCIe root port library. >=20 > + All function in this library is available for PEI, DXE, and SMM, >=20 > + But do not support UEFI RUNTIME environment call. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include "CpuPcieInfo.h" >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +/** >=20 > + Determines whether PCIe link is active >=20 > + >=20 > + @param[in] RpBase Root Port base address >=20 > + @retval Link Active state >=20 > +**/ >=20 > +BOOLEAN >=20 > +CpuPcieIsLinkActive ( >=20 > + UINT64 RpBase >=20 > + ) >=20 > +{ >=20 > + return !! (PegPciSegmentRead16 (RpBase + R_PCIE_LSTS) & > B_PCIE_LSTS_LA); >=20 > +} >=20 > + >=20 > +/** >=20 > + Get max PCIe link speed supported by the root port. >=20 > + >=20 > + @param[in] RpBase Root Port base address >=20 > + @return Max link speed >=20 > +**/ >=20 > +UINT32 >=20 > +CpuPcieGetMaxLinkSpeed ( >=20 > + UINT64 RpBase >=20 > + ) >=20 > +{ >=20 > + return PegPciSegmentRead32 (RpBase + R_PCIE_LCAP) & > B_PCIE_LCAP_MLS; >=20 > +} >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Library/PeiDxeSmmCp > uPcieRpLib/PeiDxeSmmCpuPcieRpLib.inf > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Library/PeiDxeSmmC > puPcieRpLib/PeiDxeSmmCpuPcieRpLib.inf > new file mode 100644 > index 0000000000..cea8bcbecd > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Library/PeiDxeSmmC > puPcieRpLib/PeiDxeSmmCpuPcieRpLib.inf > @@ -0,0 +1,32 @@ > +## @file >=20 > +# CPU PCIE root port Library. >=20 > +# >=20 > +# All function in this library is available for PEI, DXE, and SMM, >=20 > +# But do not support UEFI RUNTIME environment call. >=20 > +# >=20 > +# Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > +# SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +# >=20 > +## >=20 > + >=20 > + >=20 > +[Defines] >=20 > +INF_VERSION =3D 0x00010017 >=20 > +BASE_NAME =3D PeiDxeSmmCpuPcieRpLib >=20 > +FILE_GUID =3D 00199A03-41F4-43c7-B6D5-5A3AA1EE78D0 >=20 > +VERSION_STRING =3D 1.0 >=20 > +MODULE_TYPE =3D BASE >=20 > +LIBRARY_CLASS =3D CpuPcieRpLib >=20 > + >=20 > +[LibraryClasses] >=20 > +BaseLib >=20 > +IoLib >=20 > +DebugLib >=20 > +PciLib >=20 > + >=20 > +[Packages] >=20 > +MdePkg/MdePkg.dec >=20 > +TigerlakeSiliconPkg/SiPkg.dec >=20 > + >=20 > +[Sources] >=20 > +CpuPcieRpLib.c >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/LibraryPrivate/DxeC= p > uPcieRpLib/DxeCpuPcieRpLib.c > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/LibraryPrivate/DxeC= p > uPcieRpLib/DxeCpuPcieRpLib.c > new file mode 100644 > index 0000000000..48ef8165de > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/LibraryPrivate/DxeC= p > uPcieRpLib/DxeCpuPcieRpLib.c > @@ -0,0 +1,62 @@ > +/** @file >=20 > + The DXE CPU PCIE RP Library Implements After Memory PEIM >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +/** >=20 > +Update CPU PCIE RP NVS AREA tables >=20 > + >=20 > +**/ >=20 > +VOID >=20 > +UpdateCpuPcieNVS ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + EFI_STATUS Status; >=20 > + PCIE_DXE_CONFIG *PcieDxeConfig; >=20 > + SA_POLICY_PROTOCOL *SaPolicy; >=20 > + SYSTEM_AGENT_NVS_AREA_PROTOCOL *SaNvsAreaProtocol; >=20 > + >=20 > + DEBUG ((DEBUG_INFO, "Update Cpu Pcie NVS Area.\n")); >=20 > + >=20 > + Status =3D gBS->LocateProtocol (&gSaPolicyProtocolGuid, NULL, (VOID **= ) > &SaPolicy); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + >=20 > + Status =3D GetConfigBlock ((VOID *)SaPolicy, &gPcieDxeConfigGuid, (VOI= D > *)&PcieDxeConfig); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + >=20 > + Status =3D gBS->LocateProtocol (&gSaNvsAreaProtocolGuid, NULL, (VOID *= *) > &SaNvsAreaProtocol); >=20 > + if (Status !=3D EFI_SUCCESS) { >=20 > + DEBUG ((DEBUG_ERROR, "Locate SA NVS Area failed.\n")); >=20 > + return; >=20 > + } >=20 > + >=20 > + SaNvsAreaProtocol->Area->Peg0LtrEnable =3D PcieDxeConfig- > >PegPwrOpt[0].LtrEnable; >=20 > + SaNvsAreaProtocol->Area->Peg0ObffEnable =3D PcieDxeConfig- > >PegPwrOpt[0].ObffEnable; >=20 > + SaNvsAreaProtocol->Area->Peg1LtrEnable =3D PcieDxeConfig- > >PegPwrOpt[1].LtrEnable; >=20 > + SaNvsAreaProtocol->Area->Peg1ObffEnable =3D PcieDxeConfig- > >PegPwrOpt[1].ObffEnable; >=20 > + SaNvsAreaProtocol->Area->Peg2LtrEnable =3D PcieDxeConfig- > >PegPwrOpt[2].LtrEnable; >=20 > + SaNvsAreaProtocol->Area->Peg2ObffEnable =3D PcieDxeConfig- > >PegPwrOpt[2].ObffEnable; >=20 > + SaNvsAreaProtocol->Area->Peg3LtrEnable =3D PcieDxeConfig- > >PegPwrOpt[3].LtrEnable; >=20 > + SaNvsAreaProtocol->Area->Peg3ObffEnable =3D PcieDxeConfig- > >PegPwrOpt[3].ObffEnable; >=20 > + SaNvsAreaProtocol->Area->PegLtrMaxSnoopLatency =3D > V_SA_LTR_MAX_SNOOP_LATENCY_VALUE; >=20 > + SaNvsAreaProtocol->Area->PegLtrMaxNoSnoopLatency =3D > V_SA_LTR_MAX_NON_SNOOP_LATENCY_VALUE; >=20 > +} >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/LibraryPrivate/DxeC= p > uPcieRpLib/DxeCpuPcieRpLib.inf > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/LibraryPrivate/DxeC= p > uPcieRpLib/DxeCpuPcieRpLib.inf > new file mode 100644 > index 0000000000..dc9b893be3 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/LibraryPrivate/DxeC= p > uPcieRpLib/DxeCpuPcieRpLib.inf > @@ -0,0 +1,40 @@ > +## @file >=20 > +# The DXE CPU PCIE RP Library Implements After Memory PEIM >=20 > +# >=20 > +# Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > +# SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +# >=20 > +## >=20 > + >=20 > + >=20 > +[Defines] >=20 > +INF_VERSION =3D 0x00010017 >=20 > +BASE_NAME =3D DxeCpuPcieRpLib >=20 > +FILE_GUID =3D D563A22E-6A01-4EF7-84D1-78B6717E3402 >=20 > +VERSION_STRING =3D 1.0 >=20 > +MODULE_TYPE =3D DXE_DRIVER >=20 > +UEFI_SPECIFICATION_VERSION =3D 2.00 >=20 > +LIBRARY_CLASS =3D DxeCpuPcieRpLib >=20 > + >=20 > +[LibraryClasses] >=20 > +IoLib >=20 > +BaseLib >=20 > +DebugLib >=20 > +BaseMemoryLib >=20 > +UefiBootServicesTableLib >=20 > +UefiLib >=20 > +HobLib >=20 > + >=20 > +[Packages] >=20 > +MdePkg/MdePkg.dec >=20 > +TigerlakeSiliconPkg/SiPkg.dec >=20 > + >=20 > +[Sources] >=20 > +DxeCpuPcieRpLib.c >=20 > + >=20 > +[Guids] >=20 > +gPcieDxeConfigGuid >=20 > + >=20 > +[Protocols] >=20 > +gSaPolicyProtocolGuid ## CONSUMES >=20 > +gSaNvsAreaProtocolGuid ## CONSUMES >=20 > -- > 2.24.0.windows.2