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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Nate DeSimone > -----Original Message----- > From: Luo, Heng > Sent: Sunday, January 31, 2021 5:37 PM > To: devel@edk2.groups.io > Cc: Chaganty, Rangasai V ; Desimone, > Nathaniel L > Subject: [PATCH 27/40] TigerlakeSiliconPkg/IpBlock: Add SerialIo componen= t >=20 > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3171 >=20 > Adds the following files: > * IpBlock/SerialIo/IncludePrivate > * IpBlock/SerialIo/Library > * IpBlock/SerialIo/LibraryPrivate >=20 > Cc: Sai Chaganty > Cc: Nate DeSimone >=20 > Signed-off-by: Heng Luo > --- >=20 > Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/IncludePrivate/Library= /Seri > alIoPrivateLib.h | 377 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/IncludePrivate/Registe= r/Ser > ialIoRegsVer2.h | 108 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/Library/PeiDxeSmmSeria= lIo > AccessLib/PeiDxeSmmSerialIoAccessLib.inf | 35 > +++++++++++++++++++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/Library/PeiDxeSmmSeria= lIo > AccessLib/SerialIoAccessLib.c | 266 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPrivate/PeiDxeS= mm > SerialIoPrivateLib/PeiDxeSmmSerialIoPrivateLibVer2.inf | 34 > ++++++++++++++++++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPrivate/PeiDxeS= mm > SerialIoPrivateLib/SerialIoPrivateLib.c | 156 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPrivate/PeiDxeS= mm > SerialIoPrivateLib/SerialIoPrivateLibI2c.c | 122 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPrivate/PeiDxeS= mm > SerialIoPrivateLib/SerialIoPrivateLibI2cVer2.c | 70 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPrivate/PeiDxeS= mm > SerialIoPrivateLib/SerialIoPrivateLibInternal.h | 20 > ++++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPrivate/PeiDxeS= mm > SerialIoPrivateLib/SerialIoPrivateLibSpi.c | 122 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPrivate/PeiDxeS= mm > SerialIoPrivateLib/SerialIoPrivateLibSpiVer2.c | 82 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPrivate/PeiDxeS= mm > SerialIoPrivateLib/SerialIoPrivateLibUart.c | 136 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPrivate/PeiDxeS= mm > SerialIoPrivateLib/SerialIoPrivateLibUartVer2.c | 82 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++ > 13 files changed, 1610 insertions(+) >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/IncludePrivate/Libra= ry/Se > rialIoPrivateLib.h > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/IncludePrivate/Libra= ry/Se > rialIoPrivateLib.h > new file mode 100644 > index 0000000000..47057cd2ef > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/IncludePrivate/Libra= ry/Se > rialIoPrivateLib.h > @@ -0,0 +1,377 @@ > +/** @file >=20 > + Header file for Serial IO Private Lib implementation. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _SERIAL_IO_PRIVATE_LIB_H_ >=20 > +#define _SERIAL_IO_PRIVATE_LIB_H_ >=20 > + >=20 > +#include >=20 > +#include >=20 > + >=20 > +/** >=20 > + Serial Io Pci Device State structure. >=20 > + Used to preserve current information about the device when it is > configured in Pci mode prior to Pch Initialization. >=20 > +**/ >=20 > +typedef struct { >=20 > + UINT64 PciCfgBar0; ///< Pci Config Space Base Address Register >=20 > + UINT8 PciCfgCommand; ///< Pci Config Space Command Register >=20 > + UINT8 PciCfgPmeCtrlSts; ///< Pci Config Space Pme Control Status >=20 > + UINT8 PprReset; ///< MMIO Proprietary Reset Register >=20 > +} SERIAL_IO_PCI_DEVICE_STATE; >=20 > + >=20 > +/** >=20 > + Checks if higher functions are enabled. >=20 > + Used for Function 0 Serial Io Device disabling >=20 > + >=20 > + @param[in] DeviceNum Device Number >=20 > + >=20 > + @retval TRUE At least one higher function device is enab= led >=20 > + FALSE Higher functions are disabled >=20 > +**/ >=20 > +BOOLEAN >=20 > +SerialIoHigherFunctionsEnabled ( >=20 > + IN UINT8 DeviceNum >=20 > + ); >=20 > + >=20 > +/** >=20 > + Places SerialIo device in D3 >=20 > + >=20 > + @param[in] PciCfgBase Pci Config Offset >=20 > + >=20 > +**/ >=20 > +VOID >=20 > +SerialIoSetD3 ( >=20 > + IN UINT64 PciCfgBase >=20 > + ); >=20 > + >=20 > +/** >=20 > + Places SerialIo device in D0 >=20 > + >=20 > + @param[in] PciCfgBase Pci Config Offset >=20 > + >=20 > +**/ >=20 > +VOID >=20 > +SerialIoSetD0 ( >=20 > + IN UINT64 PciCfgBase >=20 > + ); >=20 > + >=20 > +/** >=20 > + Allows Memory Access >=20 > + >=20 > + @param[in] PciCfgBase Pci Config Offset >=20 > + @param[in] Hidden Mode that determines access type >=20 > + >=20 > +**/ >=20 > +VOID >=20 > +SerialIoEnableMse ( >=20 > + IN UINT64 PciCfgBase, >=20 > + IN BOOLEAN Hidden >=20 > + ); >=20 > + >=20 > +/** >=20 > + Disable SerialIo memory access >=20 > + >=20 > + @param[in] PciCfgBase Pci Config Offset >=20 > + >=20 > +**/ >=20 > +VOID >=20 > +SerialIoDisableMse ( >=20 > + IN UINT64 PciCfgBase >=20 > + ); >=20 > + >=20 > +/** >=20 > + Disable SerialIo memory encoding >=20 > + Designated for Pci modes >=20 > + >=20 > + @param[in] PciCfgBase Pci Config Offset >=20 > + @param[in] RemoveTempBar Remove temporary mem base address or > not >=20 > + >=20 > +**/ >=20 > +VOID >=20 > +SerialIoMmioDisable ( >=20 > + IN UINT64 PciCfgBase, >=20 > + IN BOOLEAN RemoveBar >=20 > + ); >=20 > + >=20 > +/** >=20 > + Gets Fixed Base Address used for BAR0 >=20 > + >=20 > + @param[in] SpiNumber Serial IO device SPI number >=20 > + >=20 > + @retval Config control offset >=20 > +**/ >=20 > +UINT32 >=20 > +GetSerialIoSpiFixedMmioAddress ( >=20 > + IN UINT8 SpiNumber >=20 > + ); >=20 > + >=20 > +/** >=20 > + Gets Fixed Address used for Pci Config Space manipulation >=20 > + >=20 > + @param[in] SpiNumber Serial IO device SPI number >=20 > + >=20 > + @retval Pci Config Address >=20 > +**/ >=20 > +UINT32 >=20 > +GetSerialIoSpiFixedPciCfgAddress ( >=20 > + IN UINT8 SpiNumber >=20 > + ); >=20 > + >=20 > +/** >=20 > + Gets Spi Device Id >=20 > + >=20 > + @param[in] SpiNumber Serial IO device SPI number >=20 > + >=20 > + @retval Device Id >=20 > +**/ >=20 > +UINT16 >=20 > +GetSerialIoSpiDeviceId ( >=20 > + IN UINT8 SpiNumber >=20 > + ); >=20 > + >=20 > +/** >=20 > + Checks if SPI is Hidden, and it's Pci Config space available >=20 > + >=20 > + @param[in] SpiNumber Selects Serial IO SPI device >=20 > + >=20 > + @retval TRUE SPI is in hidden mode >=20 > + @retval FALSE SPI is not in hidden mode >=20 > +**/ >=20 > +BOOLEAN >=20 > +IsSerialIoSpiHidden ( >=20 > + IN UINT8 SpiNumber >=20 > + ); >=20 > + >=20 > +/** >=20 > + Configures Serial IO Controller before control is passd to the OS >=20 > + >=20 > + @param[in] SpiNumber SPI Number >=20 > + @param[in] SpiDeviceConfig SerialIo SPI Config >=20 > + >=20 > +**/ >=20 > +VOID >=20 > +SerialIoSpiBootHandler ( >=20 > + IN UINT8 SpiNumber, >=20 > + IN SERIAL_IO_SPI_CONFIG *SpiDeviceConfig >=20 > + ); >=20 > + >=20 > +/** >=20 > + Sets Pme Control Status and Command register values required for S3 Bo= ot > Script >=20 > + >=20 > + @param[in] SpiNumber SPI Number >=20 > + @param[in] SpiDeviceConfig SerialIo SPI Config >=20 > + @param[in/out] S3PciCfgBase S3 Boot Script Pci Config Base >=20 > + @param[in/out] Command Pci Command register data to save >=20 > + @param[in/out] Pme Pci Pme Control register data to save >=20 > + >=20 > +**/ >=20 > +VOID >=20 > +SerialIoSpiS3Handler ( >=20 > + IN UINT8 SpiNumber, >=20 > + IN SERIAL_IO_SPI_CONFIG *SpiDeviceConfig, >=20 > + IN OUT UINT64 *S3PciCfgBase, >=20 > + IN OUT UINT32 *Command, >=20 > + IN OUT UINT32 *Pme >=20 > + ); >=20 > + >=20 > +/** >=20 > + Gets Pci Config control offset >=20 > + >=20 > + @param[in] UartNumber Serial IO device UART number >=20 > + >=20 > + @retval Config control offset >=20 > +**/ >=20 > +UINT16 >=20 > +GetSerialIoUartConfigControlOffset ( >=20 > + IN UINT8 UartNumber >=20 > + ); >=20 > + >=20 > +/** >=20 > + Gets Fixed Base Address used for BAR0 >=20 > + >=20 > + @param[in] UartNumber Serial IO device UART number >=20 > + >=20 > + @retval Config control offset >=20 > +**/ >=20 > +UINT32 >=20 > +GetSerialIoUartFixedMmioAddress ( >=20 > + IN UINT8 UartNumber >=20 > + ); >=20 > + >=20 > +/** >=20 > + Gets Fixed Address used for Pci Config Space manipulation >=20 > + >=20 > + @param[in] UartNumber Serial IO device UART number >=20 > + >=20 > + @retval Pci Config Address >=20 > +**/ >=20 > +UINT32 >=20 > +GetSerialIoUartFixedPciCfgAddress ( >=20 > + IN UINT8 UartNumber >=20 > + ); >=20 > + >=20 > +/** >=20 > + Returns UART S3 boot script PCI address >=20 > + >=20 > + @param[in] UartNumber UART Number >=20 > + >=20 > + @retval UART S3 boot script PCI address >=20 > +**/ >=20 > +UINT64 >=20 > +GetSerialIoUartS3PciBase ( >=20 > + IN UINT8 UartNumber >=20 > + ); >=20 > + >=20 > +/** >=20 > + Returns SPI S3 boot script PCI address >=20 > + >=20 > + @param[in] UartNumber UART Number >=20 > + >=20 > + @retval SPI S3 boot script PCI address >=20 > +**/ >=20 > +UINT64 >=20 > +GetSerialIoSpiS3PciBase ( >=20 > + IN UINT8 SpiNumber >=20 > + ); >=20 > + >=20 > +/** >=20 > + Returns I2C S3 boot script PCI address >=20 > + >=20 > + @param[in] I2cNumber I2C Number >=20 > + >=20 > + @retval I2C S3 boot script PCI address >=20 > +**/ >=20 > +UINT64 >=20 > +GetSerialIoI2cS3PciBase ( >=20 > + IN UINT8 I2cNumber >=20 > + ); >=20 > + >=20 > +/** >=20 > + Gets Uarts Device Id >=20 > + >=20 > + @param[in] UartNumbe Serial IO device UART number >=20 > + >=20 > + @retval Device Id >=20 > +**/ >=20 > +UINT16 >=20 > +GetSerialIoUartDeviceId ( >=20 > + IN UINT8 UartNumber >=20 > + ); >=20 > + >=20 > +/** >=20 > + Checks if UART is Hidden, and it's Pci Config space available >=20 > + >=20 > + @param[in] UartNumber Selects Serial IO UART device >=20 > + >=20 > + @retval TRUE UART is in hidden mode >=20 > + @retval FALSE UART is not in hidden mode >=20 > +**/ >=20 > +BOOLEAN >=20 > +IsSerialIoUartHidden ( >=20 > + IN UINT8 UartNumber >=20 > + ); >=20 > + >=20 > +/** >=20 > + Configures Serial IO Controller before control is passd to the OS >=20 > + >=20 > + @param[in] UartNumber UART Number >=20 > + @param[in] UartDeviceConfig SerialIo UART Config >=20 > + >=20 > +**/ >=20 > +VOID >=20 > +SerialIoUartBootHandler ( >=20 > + IN UINT8 UartNumber, >=20 > + IN SERIAL_IO_UART_CONFIG *UartDeviceConfig >=20 > + ); >=20 > + >=20 > +/** >=20 > + Sets Pme Control Status and Command register values required for S3 Bo= ot > Script >=20 > + >=20 > + @param[in] UartNumber UART Number >=20 > + @param[in] UartDeviceConfig SerialIo UART Config >=20 > + @param[in/out] S3PciCfgBase S3 Boot Script Pci Config Base >=20 > + @param[in/out] Command Pci Command register data to save >=20 > + @param[in/out] Pme Pci Pme Control register data to sav= e >=20 > + >=20 > +**/ >=20 > +VOID >=20 > +SerialIoUartS3Handler ( >=20 > + IN UINT8 UartNumber, >=20 > + IN SERIAL_IO_UART_CONFIG *UartDeviceConfig, >=20 > + IN OUT UINT64 *S3PciCfgBase, >=20 > + IN OUT UINT32 *Command, >=20 > + IN OUT UINT32 *Pme >=20 > + ); >=20 > + >=20 > +/** >=20 > + Gets Fixed Address used for Pci Config Space manipulation >=20 > + >=20 > + @param[in] I2cNumber Serial IO device I2C number >=20 > + >=20 > + @retval Pci Config Address >=20 > +**/ >=20 > +UINT32 >=20 > +GetSerialIoI2cFixedPciCfgAddress ( >=20 > + IN UINT8 I2cNumber >=20 > + ); >=20 > + >=20 > +/** >=20 > + Gets I2C Device Id >=20 > + >=20 > + @param[in] I2cNumber Serial IO device I2C number >=20 > + >=20 > + @retval Device Id >=20 > +**/ >=20 > +UINT16 >=20 > +GetSerialIoI2cDeviceId ( >=20 > + IN UINT8 I2cNumber >=20 > + ); >=20 > + >=20 > +/** >=20 > + Checks if I2C is Hidden, and it's Pci Config space available >=20 > + >=20 > + @param[in] 2cNumber Selects Serial IO I2C device >=20 > + >=20 > + @retval TRUE I2C is in hidden mode >=20 > + @retval FALSE I2C is not in hidden mode >=20 > +**/ >=20 > +BOOLEAN >=20 > +IsSerialIoI2cHidden ( >=20 > + IN UINT8 I2cNumber >=20 > + ); >=20 > + >=20 > +/** >=20 > + Configures Serial IO Controller before control is passd to the OS >=20 > + >=20 > + @param[in] I2cNumber I2C Number >=20 > + @param[in] I2cDeviceConfig SerialIo I2C Config >=20 > + >=20 > +**/ >=20 > +VOID >=20 > +SerialIoI2cBootHandler ( >=20 > + IN UINT8 I2cNumber, >=20 > + IN SERIAL_IO_I2C_CONFIG *I2cDeviceConfig >=20 > + ); >=20 > + >=20 > +/** >=20 > + Sets Pme Control Status and Command register values required for S3 Bo= ot > Script >=20 > + >=20 > + @param[in] I2cNumber I2C Number >=20 > + @param[in] I2cDeviceConfig SerialIo I2C Config >=20 > + @param[in/out] S3PciCfgBase S3 Boot Script Pci Config Base >=20 > + @param[in/out] Command Pci Command register data to save >=20 > + @param[in/out] Pme Pci Pme Control register data to save >=20 > + >=20 > +**/ >=20 > +VOID >=20 > +SerialIoI2cS3Handler ( >=20 > + IN UINT8 I2cNumber, >=20 > + IN SERIAL_IO_I2C_CONFIG *I2cDeviceConfig, >=20 > + IN OUT UINT64 *S3PciCfgBase, >=20 > + IN OUT UINT32 *Command, >=20 > + IN OUT UINT32 *Pme >=20 > + ); >=20 > + >=20 > +#endif // _SERIAL_IO_PRIVATE_LIB_H_ >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/IncludePrivate/Regis= ter/S > erialIoRegsVer2.h > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/IncludePrivate/Regis= ter/ > SerialIoRegsVer2.h > new file mode 100644 > index 0000000000..01840b14c9 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/IncludePrivate/Regis= ter/ > SerialIoRegsVer2.h > @@ -0,0 +1,108 @@ > +/** @file >=20 > + Device IDs for Serial IO Controllers for TGL PCH >=20 > + >=20 > + Conventions: >=20 > + >=20 > + - Register definition format: >=20 > + > Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterS > pace_RegisterName >=20 > + - Prefix: >=20 > + Definitions beginning with "R_" are registers >=20 > + Definitions beginning with "B_" are bits within registers >=20 > + Definitions beginning with "V_" are meaningful values within the bit= s >=20 > + Definitions beginning with "S_" are register size >=20 > + Definitions beginning with "N_" are the bit position >=20 > + - [GenerationName]: >=20 > + Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc= .). >=20 > + Register name without GenerationName applies to all generations. >=20 > + - [ComponentName]: >=20 > + This field indicates the component name that the register belongs to= (e.g. > PCH, SA etc.) >=20 > + Register name without ComponentName applies to all components. >=20 > + >=20 > + Register that is specific to -LP denoted by "_PCH_LP_" in component > name. >=20 > + - SubsystemName: >=20 > + This field indicates the subsystem name of the component that the > register belongs to >=20 > + (e.g. PCIE, USB, SATA, GPIO, PMC etc.). >=20 > + - RegisterSpace: >=20 > + MEM - MMIO space register of subsystem. >=20 > + IO - IO space register of subsystem. >=20 > + PCR - Private configuration register of subsystem. >=20 > + CFG - PCI configuration space register of subsystem. >=20 > + - RegisterName: >=20 > + Full register name. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _SERIAL_IO_REGS_VER2_H_ >=20 > +#define _SERIAL_IO_REGS_VER2_H_ >=20 > +// >=20 > +// Serial IO I2C0 Controller Registers >=20 > +// >=20 > +#define V_VER2_PCH_LP_SERIAL_IO_CFG_I2C0_DEVICE_ID 0xA0E8 >=20 > + >=20 > +// >=20 > +// Serial IO I2C1 Controller Registers >=20 > +// >=20 > +#define V_VER2_PCH_LP_SERIAL_IO_CFG_I2C1_DEVICE_ID 0xA0E9 >=20 > + >=20 > +// >=20 > +// Serial IO I2C2 Controller Registers >=20 > +// >=20 > +#define V_VER2_PCH_LP_SERIAL_IO_CFG_I2C2_DEVICE_ID 0xA0EA >=20 > + >=20 > +// >=20 > +// Serial IO I2C3 Controller Registers >=20 > +// >=20 > +#define V_VER2_PCH_LP_SERIAL_IO_CFG_I2C3_DEVICE_ID 0xA0EB >=20 > + >=20 > +// >=20 > +// Serial IO I2C4 Controller Registers >=20 > +// >=20 > +#define V_VER2_PCH_LP_SERIAL_IO_CFG_I2C4_DEVICE_ID 0xA0C5 >=20 > + >=20 > +// >=20 > +// Serial IO I2C5 Controller Registers >=20 > +// >=20 > +#define V_VER2_PCH_LP_SERIAL_IO_CFG_I2C5_DEVICE_ID 0xA0C6 >=20 > + >=20 > +// >=20 > +// Serial IO SPI0 Controller Registers >=20 > +// >=20 > +#define V_VER2_PCH_LP_SERIAL_IO_CFG_SPI0_DEVICE_ID 0xA0AA >=20 > + >=20 > +// >=20 > +// Serial IO SPI1 Controller Registers >=20 > +// >=20 > +#define V_VER2_PCH_LP_SERIAL_IO_CFG_SPI1_DEVICE_ID 0xA0AB >=20 > + >=20 > +// >=20 > +// Serial IO SPI2 Controller Registers >=20 > +// >=20 > +#define V_VER2_PCH_LP_SERIAL_IO_CFG_SPI2_DEVICE_ID 0xA0FB >=20 > + >=20 > +// >=20 > +// Serial IO SPI3 Controller Registers >=20 > +// >=20 > +#define V_VER2_PCH_LP_SERIAL_IO_CFG_SPI3_DEVICE_ID 0xA0FD >=20 > + >=20 > +// >=20 > +// Serial IO UART0 Controller Registers >=20 > +// >=20 > +#define V_VER2_PCH_LP_SERIAL_IO_CFG_UART0_DEVICE_ID 0xA0A8 >=20 > + >=20 > +// >=20 > +// Serial IO UART1 Controller Registers >=20 > +// >=20 > +#define V_VER2_PCH_LP_SERIAL_IO_CFG_UART1_DEVICE_ID 0xA0A9 >=20 > + >=20 > +// >=20 > +// Serial IO UART2 Controller Registers >=20 > +// >=20 > +#define V_VER2_PCH_LP_SERIAL_IO_CFG_UART2_DEVICE_ID 0xA0C7 >=20 > + >=20 > +// >=20 > +// Serial IO UART3 Controller Registers >=20 > +// >=20 > +#define V_VER2_PCH_LP_SERIAL_IO_CFG_UART3_DEVICE_ID 0xA0DA >=20 > + >=20 > +#endif //_SERIAL_IO_REGS_VER2_H_ >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/Library/PeiDxeSmmSer= ial > IoAccessLib/PeiDxeSmmSerialIoAccessLib.inf > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/Library/PeiDxeSmmSer= ial > IoAccessLib/PeiDxeSmmSerialIoAccessLib.inf > new file mode 100644 > index 0000000000..9178840ca8 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/Library/PeiDxeSmmSer= ial > IoAccessLib/PeiDxeSmmSerialIoAccessLib.inf > @@ -0,0 +1,35 @@ > +## @file >=20 > +# Component description file for PEI/DXE/SMM Serial Io Access Lib. >=20 > +# >=20 > +# All function in this library is available for PEI, DXE, and SMM, >=20 > +# But do not support UEFI RUNTIME environment call. >=20 > +# >=20 > +# Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > +# SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +# >=20 > +## >=20 > + >=20 > + >=20 > +[Defines] >=20 > + INF_VERSION =3D 0x00010017 >=20 > + BASE_NAME =3D PeiDxeSmmSerialIoAccessLib >=20 > + FILE_GUID =3D F1A20692-26CA-4CA4-A775-695BBD6D3EC7 >=20 > + VERSION_STRING =3D 1.0 >=20 > + MODULE_TYPE =3D BASE >=20 > + LIBRARY_CLASS =3D SerialIoAccessLib >=20 > + >=20 > +[LibraryClasses] >=20 > + BaseLib >=20 > + IoLib >=20 > + DebugLib >=20 > + PcdLib >=20 > + PciSegmentLib >=20 > + PchPcrLib >=20 > + SerialIoPrivateLib >=20 > + >=20 > +[Packages] >=20 > + MdePkg/MdePkg.dec >=20 > + TigerlakeSiliconPkg/SiPkg.dec >=20 > + >=20 > +[Sources] >=20 > + SerialIoAccessLib.c >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/Library/PeiDxeSmmSer= ial > IoAccessLib/SerialIoAccessLib.c > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/Library/PeiDxeSmmSer= ial > IoAccessLib/SerialIoAccessLib.c > new file mode 100644 > index 0000000000..2b3a3dca5a > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/Library/PeiDxeSmmSer= ial > IoAccessLib/SerialIoAccessLib.c > @@ -0,0 +1,266 @@ > +/** @file >=20 > + Serial Io Common Lib implementation. >=20 > + All function in this library is available for PEI, DXE, and SMM, >=20 > + But do not support UEFI RUNTIME environment call. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +/** >=20 > + Returns BAR0 >=20 > + >=20 > + @param[in] PciCfgBase Pci Config Base >=20 > + >=20 > + @retval 64bit MMIO BAR Address >=20 > +**/ >=20 > +UINT64 >=20 > +GetSerialIoBar ( >=20 > + IN UINT64 PciCfgBase >=20 > + ) >=20 > +{ >=20 > + if (PciCfgBase < PCH_SERIAL_IO_BASE_ADDRESS) { >=20 > + return (UINT64) ((PciSegmentRead32 ((UINTN) (PciCfgBase + > PCI_BASE_ADDRESSREG_OFFSET)) & 0xFFFFF000) + LShiftU64 > (PciSegmentRead32 ((UINTN) (PciCfgBase + PCI_BASE_ADDRESSREG_OFFSET > + 4)), 32)); >=20 > + } >=20 > + return (UINT64) ((MmioRead32 ((UINTN) (PciCfgBase + > PCI_BASE_ADDRESSREG_OFFSET)) & 0xFFFFF000) + LShiftU64 (MmioRead32 > ((UINTN) (PciCfgBase + PCI_BASE_ADDRESSREG_OFFSET + 4)), 32)); >=20 > +} >=20 > + >=20 > +/** >=20 > + Returns I2C Pci Config Space >=20 > + >=20 > + @param[in] I2cNumber I2C Number >=20 > + >=20 > + @retval I2C Pci Config Space Address >=20 > +**/ >=20 > +UINT64 >=20 > +GetSerialIoI2cPciCfg ( >=20 > + IN UINT8 I2cNumber >=20 > + ) >=20 > +{ >=20 > + if (IsSerialIoI2cHidden (I2cNumber)) { >=20 > + return (UINTN) GetSerialIoI2cFixedPciCfgAddress (I2cNumber); >=20 > + } >=20 > + return SerialIoI2cPciCfgBase (I2cNumber); >=20 > +} >=20 > + >=20 > +/** >=20 > + Returns SPI Pci Config Space >=20 > + >=20 > + @param[in] SpiNumber SPI Number >=20 > + >=20 > + @retval SPI Pci Config Space Address >=20 > +**/ >=20 > +UINT64 >=20 > +GetSerialIoSpiPciCfg ( >=20 > + IN UINT8 SpiNumber >=20 > + ) >=20 > +{ >=20 > + if (IsSerialIoSpiHidden (SpiNumber)) { >=20 > + return (UINTN) GetSerialIoSpiFixedPciCfgAddress (SpiNumber); >=20 > + } >=20 > + return SerialIoSpiPciCfgBase (SpiNumber); >=20 > +} >=20 > + >=20 > +/** >=20 > + Returns UART Pci Config Space >=20 > + >=20 > + @param[in] UartNumber UART Number >=20 > + >=20 > + @retval UART Pci Config Space Address >=20 > +**/ >=20 > +UINT64 >=20 > +GetSerialIoUartPciCfg ( >=20 > + IN UINT8 UartNumber >=20 > + ) >=20 > +{ >=20 > + if (IsSerialIoUartHidden (UartNumber)) { >=20 > + return GetSerialIoUartFixedPciCfgAddress (UartNumber); >=20 > + } >=20 > + return SerialIoUartPciCfgBase (UartNumber); >=20 > +} >=20 > + >=20 > +/** >=20 > + Returns SPI S3 boot script PCI address >=20 > + >=20 > + @param[in] UartNumber UART Number >=20 > + >=20 > + @retval SPI S3 boot script PCI address >=20 > +**/ >=20 > +UINT64 >=20 > +GetSerialIoSpiS3PciBase ( >=20 > + IN UINT8 SpiNumber >=20 > + ) >=20 > +{ >=20 > + if (IsSerialIoSpiHidden (SpiNumber)) { >=20 > + // >=20 > + // It's not expected to return Spi S3 Boot Script PCI address for non = PCI > mode. >=20 > + // >=20 > + ASSERT (TRUE); >=20 > + } >=20 > + return S3_BOOT_SCRIPT_LIB_PCI_ADDRESS ( >=20 > + DEFAULT_PCI_BUS_NUMBER_PCH, >=20 > + SerialIoSpiDevNumber (SpiNumber), >=20 > + SerialIoSpiFuncNumber (SpiNumber), >=20 > + 0 >=20 > + ); >=20 > +} >=20 > + >=20 > +/** >=20 > + Returns UART S3 boot script PCI address >=20 > + >=20 > + @param[in] UartNumber UART Number >=20 > + >=20 > + @retval UART S3 boot script PCI address >=20 > +**/ >=20 > +UINT64 >=20 > +GetSerialIoUartS3PciBase ( >=20 > + IN UINT8 UartNumber >=20 > + ) >=20 > +{ >=20 > + if (IsSerialIoUartHidden (UartNumber)) { >=20 > + // >=20 > + // It's not expected to return Uart S3 Boot Script PCI address for non= PCI > mode. >=20 > + // >=20 > + ASSERT (TRUE); >=20 > + } >=20 > + return S3_BOOT_SCRIPT_LIB_PCI_ADDRESS ( >=20 > + DEFAULT_PCI_BUS_NUMBER_PCH, >=20 > + SerialIoUartDevNumber (UartNumber), >=20 > + SerialIoUartFuncNumber (UartNumber), >=20 > + 0 >=20 > + ); >=20 > +} >=20 > + >=20 > +/** >=20 > + Returns I2C S3 boot script PCI address >=20 > + >=20 > + @param[in] I2cNumber I2C Number >=20 > + >=20 > + @retval I2C S3 boot script PCI address >=20 > +**/ >=20 > +UINT64 >=20 > +GetSerialIoI2cS3PciBase ( >=20 > + IN UINT8 I2cNumber >=20 > + ) >=20 > +{ >=20 > + if (IsSerialIoI2cHidden (I2cNumber)) { >=20 > + // >=20 > + // It's not expected to return I2c S3 Boot Script PCI address for non = PCI > mode. >=20 > + // >=20 > + ASSERT (TRUE); >=20 > + } >=20 > + return S3_BOOT_SCRIPT_LIB_PCI_ADDRESS ( >=20 > + DEFAULT_PCI_BUS_NUMBER_PCH, >=20 > + SerialIoI2cDevNumber (I2cNumber), >=20 > + SerialIoI2cFuncNumber (I2cNumber), >=20 > + 0 >=20 > + ); >=20 > +} >=20 > + >=20 > +/** >=20 > + Checks if Device with given PciDeviceId is one of SerialIo I2C control= lers >=20 > + If yes, its number is returned through I2cIndex parameter, otherwise > I2cIndex is not updated >=20 > + >=20 > + @param[in] PciDevId Device ID >=20 > + @param[out] I2cNumber Number of SerialIo I2C controlle= r >=20 > + >=20 > + @retval TRUE yes it is a SerialIo I2C control= ler >=20 > + @retval FALSE no it isn't a SerialIo I2C contr= oller >=20 > +**/ >=20 > +BOOLEAN >=20 > +IsSerialIoI2cDeviceId ( >=20 > + IN UINT16 PciDevId, >=20 > + OUT UINT8 *I2cNumber >=20 > + ) >=20 > +{ >=20 > + UINT8 Index; >=20 > + >=20 > + for (Index =3D 0; Index < GetPchMaxSerialIoI2cControllersNum (); Index= ++) { >=20 > + if (PciDevId =3D=3D GetSerialIoI2cDeviceId (Index)) { >=20 > + *I2cNumber =3D Index; >=20 > + return TRUE; >=20 > + } >=20 > + } >=20 > + return FALSE; >=20 > +} >=20 > + >=20 > +/** >=20 > + Checks if I2c is Function 0 Enabled >=20 > + >=20 > + @param[in] I2cIndex Number of the SerialIo I2C contr= oller >=20 > + >=20 > + @retval TRUE Enabled >=20 > + @retval FALSE Disabled >=20 > +**/ >=20 > +BOOLEAN >=20 > +IsSerialIoI2cFunction0Enabled ( >=20 > + IN UINT8 I2cIndex >=20 > + ) >=20 > +{ >=20 > + if (SerialIoI2cFuncNumber (I2cIndex) =3D=3D 0) { >=20 > + if (SerialIoHigherFunctionsEnabled (SerialIoI2cDevNumber (I2cIndex))= ) { >=20 > + return TRUE; >=20 > + } >=20 > + } >=20 > + return FALSE; >=20 > +} >=20 > + >=20 > +/** >=20 > + Checks if Uart is Function 0 Enabled >=20 > + >=20 > + @param[in] UartIndex Number of the SerialIo Uart con= troller >=20 > + >=20 > + @retval TRUE Enabled >=20 > + @retval FALSE Disabled >=20 > +**/ >=20 > +BOOLEAN >=20 > +IsSerialIoUartFunction0Enabled ( >=20 > + IN UINT8 UartIndex >=20 > + ) >=20 > +{ >=20 > + if (SerialIoUartFuncNumber (UartIndex) =3D=3D 0) { >=20 > + if (SerialIoHigherFunctionsEnabled (SerialIoUartDevNumber (UartIndex= ))) > { >=20 > + return TRUE; >=20 > + } >=20 > + } >=20 > + return FALSE; >=20 > +} >=20 > + >=20 > +/** >=20 > + Checks if Spi is Function 0 Enabled >=20 > + >=20 > + @param[in] SpiIndex Number of the SerialIo Spi contr= oller >=20 > + >=20 > + @retval TRUE Enabled >=20 > + @retval FALSE Disabled >=20 > +**/ >=20 > +BOOLEAN >=20 > +IsSerialIoSpiFunction0Enabled ( >=20 > + IN UINT8 SpiIndex >=20 > + ) >=20 > +{ >=20 > + if (SerialIoSpiFuncNumber (SpiIndex) =3D=3D 0) { >=20 > + if (SerialIoHigherFunctionsEnabled (SerialIoSpiDevNumber (SpiIndex))= ) { >=20 > + return TRUE; >=20 > + } >=20 > + } >=20 > + return FALSE; >=20 > +} >=20 > + >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPrivate/PeiDx= eSm > mSerialIoPrivateLib/PeiDxeSmmSerialIoPrivateLibVer2.inf > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPrivate/PeiDx= eSm > mSerialIoPrivateLib/PeiDxeSmmSerialIoPrivateLibVer2.inf > new file mode 100644 > index 0000000000..8981be2496 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPrivate/PeiDx= eSm > mSerialIoPrivateLib/PeiDxeSmmSerialIoPrivateLibVer2.inf > @@ -0,0 +1,34 @@ > +## @file >=20 > +# Serial Io Private Lib Ver 2 >=20 > +# >=20 > +# Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > +# SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +# >=20 > +## >=20 > + >=20 > +[Defines] >=20 > + INF_VERSION =3D 0x00010017 >=20 > + BASE_NAME =3D PeiDxeSmmSerialIoLibVer2 >=20 > + FILE_GUID =3D 9D9F99CD-C072-48C2-BF78-ABA3D664C0FA >=20 > + VERSION_STRING =3D 1.0 >=20 > + MODULE_TYPE =3D BASE >=20 > + LIBRARY_CLASS =3D SerialIoPrivateLib >=20 > + >=20 > +[LibraryClasses] >=20 > + BaseLib >=20 > + IoLib >=20 > + PciSegmentLib >=20 > + SerialIoAccessLib >=20 > + >=20 > +[Packages] >=20 > + MdePkg/MdePkg.dec >=20 > + TigerlakeSiliconPkg/SiPkg.dec >=20 > + >=20 > +[Sources] >=20 > + SerialIoPrivateLib.c >=20 > + SerialIoPrivateLibI2c.c >=20 > + SerialIoPrivateLibI2cVer2.c >=20 > + SerialIoPrivateLibSpi.c >=20 > + SerialIoPrivateLibSpiVer2.c >=20 > + SerialIoPrivateLibUart.c >=20 > + SerialIoPrivateLibUartVer2.c >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPrivate/PeiDx= eSm > mSerialIoPrivateLib/SerialIoPrivateLib.c > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPrivate/PeiDx= eSm > mSerialIoPrivateLib/SerialIoPrivateLib.c > new file mode 100644 > index 0000000000..9b84c2dda6 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPrivate/PeiDx= eSm > mSerialIoPrivateLib/SerialIoPrivateLib.c > @@ -0,0 +1,156 @@ > +/** @file >=20 > + Serial IO Private Lib implementation. >=20 > + All function in this library is available for PEI, DXE, and SMM, >=20 > + But do not support UEFI RUNTIME environment call. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +/** >=20 > + Checks if higher functions are enabled. >=20 > + Used for Function 0 Serial Io Device disabling >=20 > + >=20 > + @param[in] DeviceNum Device Number >=20 > + >=20 > + @retval TRUE At least one higher function device is enab= led >=20 > + FALSE Higher functions are disabled >=20 > +**/ >=20 > +BOOLEAN >=20 > +SerialIoHigherFunctionsEnabled ( >=20 > + IN UINT8 DeviceNum >=20 > + ) >=20 > +{ >=20 > + UINT8 FuncNum; >=20 > + // >=20 > + // Check all other func devs(1 to 7) status except func 0. >=20 > + // >=20 > + for (FuncNum =3D 1; FuncNum <=3D PCI_MAX_FUNC; FuncNum++) { >=20 > + if (PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRESS > (DEFAULT_PCI_SEGMENT_NUMBER_PCH, >=20 > + DEFAULT_PCI_BUS_NUMBE= R_PCH, >=20 > + DeviceNum, >=20 > + FuncNum, >=20 > + PCI_DEVICE_ID_OFFSET) >=20 > + ) !=3D 0xFFFF) { >=20 > + return TRUE; >=20 > + } >=20 > + } >=20 > + return FALSE; >=20 > +} >=20 > + >=20 > +/** >=20 > + Places SerialIo device in D3 >=20 > + >=20 > + @param[in] PciCfgBase Pci Config Offset >=20 > + >=20 > +**/ >=20 > +VOID >=20 > +SerialIoSetD3 ( >=20 > + IN UINT64 PciCfgBase >=20 > + ) >=20 > +{ >=20 > + if (PciCfgBase < PCH_SERIAL_IO_BASE_ADDRESS) { >=20 > + PciSegmentOr32 (PciCfgBase + R_SERIAL_IO_CFG_PME_CTRL_STS, BIT1 | > BIT0); >=20 > + } else { >=20 > + MmioOr8 ((UINTN) PciCfgBase + R_SERIAL_IO_CFG_PME_CTRL_STS, BIT1 > | BIT0); >=20 > + // >=20 > + // Reading back value after write to ensure bridge observes the BAR1 > write access >=20 > + // >=20 > + MmioRead8 ((UINTN) PciCfgBase + R_SERIAL_IO_CFG_PME_CTRL_STS); >=20 > + } >=20 > +} >=20 > + >=20 > +/** >=20 > + Places SerialIo device in D0 >=20 > + >=20 > + @param[in] PciCfgBase Pci Config Offset >=20 > + >=20 > +**/ >=20 > +VOID >=20 > +SerialIoSetD0 ( >=20 > + IN UINT64 PciCfgBase >=20 > + ) >=20 > +{ >=20 > + if (PciCfgBase < PCH_SERIAL_IO_BASE_ADDRESS) { >=20 > + PciSegmentAnd32 ((UINTN) PciCfgBase + > R_SERIAL_IO_CFG_PME_CTRL_STS, (UINT32) ~(BIT1 | BIT0)); >=20 > + } else { >=20 > + MmioAnd32 ((UINTN) PciCfgBase + R_SERIAL_IO_CFG_PME_CTRL_STS, > (UINT32) ~(BIT1 | BIT0)); >=20 > + // >=20 > + // Reading back value after write to ensure bridge observes the BAR1 > write access >=20 > + // >=20 > + MmioRead32 ((UINTN) PciCfgBase + R_SERIAL_IO_CFG_PME_CTRL_STS); >=20 > + } >=20 > +} >=20 > + >=20 > +/** >=20 > + Allows memory access >=20 > + >=20 > + @param[in] PciCfgBase Pci Config Offset >=20 > + @param[in] Hidden Mode that determines access type >=20 > + >=20 > +**/ >=20 > +VOID >=20 > +SerialIoEnableMse ( >=20 > + IN UINT64 PciCfgBase, >=20 > + IN BOOLEAN Hidden >=20 > + ) >=20 > +{ >=20 > + if (Hidden) { >=20 > + MmioOr16 ((UINTN) PciCfgBase + PCI_COMMAND_OFFSET, > EFI_PCI_COMMAND_MEMORY_SPACE); >=20 > + // >=20 > + // Reading back value after write to ensure bridge observes the BAR1 > write access >=20 > + // >=20 > + MmioRead16 ((UINTN) PciCfgBase + PCI_COMMAND_OFFSET); >=20 > + } else { >=20 > + PciSegmentOr16 ((UINTN) PciCfgBase + PCI_COMMAND_OFFSET, > EFI_PCI_COMMAND_MEMORY_SPACE); >=20 > + } >=20 > +} >=20 > + >=20 > +/** >=20 > + Disable SerialIo memory access >=20 > + >=20 > + @param[in] PciCfgBase Pci Config Offset >=20 > + >=20 > +**/ >=20 > +VOID >=20 > +SerialIoDisableMse ( >=20 > + IN UINT64 PciCfgBase >=20 > + ) >=20 > +{ >=20 > + PciSegmentAnd16 ((UINTN) PciCfgBase + PCI_COMMAND_OFFSET, > (UINT16) ~EFI_PCI_COMMAND_MEMORY_SPACE); >=20 > +} >=20 > + >=20 > +/** >=20 > + Disable SerialIo memory encoding >=20 > + Designated for Pci modes >=20 > + >=20 > + @param[in] PciCfgBase Pci Config Offset >=20 > + @param[in] RemoveTempBar Remove temporary mem base address or > not >=20 > + >=20 > +**/ >=20 > +VOID >=20 > +SerialIoMmioDisable ( >=20 > + IN UINT64 PciCfgBase, >=20 > + IN BOOLEAN RemoveBar >=20 > + ) >=20 > +{ >=20 > + SerialIoDisableMse (PciCfgBase); >=20 > + >=20 > + if (RemoveBar =3D=3D TRUE) { >=20 > + PciSegmentWrite32 ((UINTN) PciCfgBase + > R_SERIAL_IO_CFG_BAR0_LOW, 0x0); >=20 > + PciSegmentWrite32 ((UINTN) PciCfgBase + > R_SERIAL_IO_CFG_BAR0_HIGH, 0x0); >=20 > + } >=20 > +} >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPrivate/PeiDx= eSm > mSerialIoPrivateLib/SerialIoPrivateLibI2c.c > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPrivate/PeiDx= eSm > mSerialIoPrivateLib/SerialIoPrivateLibI2c.c > new file mode 100644 > index 0000000000..7601081cfa > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPrivate/PeiDx= eSm > mSerialIoPrivateLib/SerialIoPrivateLibI2c.c > @@ -0,0 +1,122 @@ > +/** @file >=20 > + Common Serial IO Private Lib implementation - I2C part >=20 > + All function in this library is available for PEI, DXE, and SMM, >=20 > + But do not support UEFI RUNTIME environment call. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +/** >=20 > + Checks if I2C is Hidden, and it's Pci Config space available >=20 > + >=20 > + @param[in] I2cNumber Selects Serial IO I2C device >=20 > + >=20 > + @retval TRUE I2C is in hidden mode >=20 > + @retval FALSE I2C is not in hidden mode >=20 > +**/ >=20 > +BOOLEAN >=20 > +IsSerialIoI2cHidden ( >=20 > + IN UINT8 I2cNumber >=20 > + ) >=20 > +{ >=20 > + if (MmioRead16 (GetSerialIoI2cFixedPciCfgAddress (I2cNumber) + > PCI_DEVICE_ID_OFFSET) =3D=3D GetSerialIoI2cDeviceId (I2cNumber)) { >=20 > + return TRUE; >=20 > + } >=20 > + return FALSE; >=20 > +} >=20 > + >=20 > +/** >=20 > + Configures Serial IO Controller before control is passd to the OS >=20 > + >=20 > + @param[in] I2cNumber I2C Number >=20 > + @param[in] I2cDeviceConfig SerialIo I2C Config >=20 > + >=20 > +**/ >=20 > +VOID >=20 > +SerialIoI2cBootHandler ( >=20 > + IN UINT8 I2cNumber, >=20 > + IN SERIAL_IO_I2C_CONFIG *I2cDeviceConfig >=20 > + ) >=20 > +{ >=20 > + UINT64 PciCfgBase; >=20 > + BOOLEAN TurnOff; >=20 > + >=20 > + TurnOff =3D FALSE; >=20 > + >=20 > + if (I2cDeviceConfig->Mode =3D=3D SerialIoI2cPci) { >=20 > + TurnOff =3D TRUE; >=20 > + } >=20 > + >=20 > + if ((I2cDeviceConfig->Mode =3D=3D SerialIoI2cDisabled) && > (SerialIoI2cFuncNumber (I2cNumber) =3D=3D 0x0)) { >=20 > + if (SerialIoHigherFunctionsEnabled (SerialIoI2cDevNumber (I2cNumber)= )) > { >=20 > + TurnOff =3D TRUE; >=20 > + } >=20 > + } >=20 > + >=20 > + if (TurnOff) { >=20 > + PciCfgBase =3D GetSerialIoI2cPciCfg (I2cNumber); >=20 > + SerialIoSetD3 (PciCfgBase); >=20 > + SerialIoMmioDisable (PciCfgBase, TRUE); >=20 > + } >=20 > +} >=20 > + >=20 > +/** >=20 > + Sets Pme Control Status and Command register values required for S3 Bo= ot > Script >=20 > + >=20 > + @param[in] I2cNumber I2C Number >=20 > + @param[in] I2cDeviceConfig SerialIo I2C Config >=20 > + @param[in/out] S3PciCfgBase S3 Boot Script Pci Config Base >=20 > + @param[in/out] Command Pci Command register data to save >=20 > + @param[in/out] Pme Pci Pme Control register data to save >=20 > + >=20 > +**/ >=20 > +VOID >=20 > +SerialIoI2cS3Handler ( >=20 > + IN UINT8 I2cNumber, >=20 > + IN SERIAL_IO_I2C_CONFIG *I2cDeviceConfig, >=20 > + IN OUT UINT64 *S3PciCfgBase, >=20 > + IN OUT UINT32 *Command, >=20 > + IN OUT UINT32 *Pme >=20 > + ) >=20 > +{ >=20 > + BOOLEAN TurnOff; >=20 > + UINT64 PciCfgBase; >=20 > + >=20 > + *S3PciCfgBase =3D 0; >=20 > + TurnOff =3D FALSE; >=20 > + >=20 > + if (I2cDeviceConfig->Mode =3D=3D SerialIoI2cPci) { >=20 > + TurnOff =3D TRUE; >=20 > + } >=20 > + >=20 > + if ((I2cDeviceConfig->Mode =3D=3D SerialIoI2cDisabled) && > (SerialIoI2cFuncNumber (I2cNumber) =3D=3D 0x0)) { >=20 > + if (SerialIoHigherFunctionsEnabled (SerialIoI2cDevNumber (I2cNumber)= )) > { >=20 > + TurnOff =3D TRUE; >=20 > + } >=20 > + } >=20 > + >=20 > + if (TurnOff) { >=20 > + *S3PciCfgBase =3D GetSerialIoI2cS3PciBase (I2cNumber); >=20 > + PciCfgBase =3D GetSerialIoI2cPciCfg (I2cNumber); >=20 > + *Pme =3D PciSegmentRead32 ((UINTN) PciCfgBase + > R_SERIAL_IO_CFG_PME_CTRL_STS); >=20 > + *Pme =3D *Pme | BIT0 | BIT1; >=20 > + *Command =3D PciSegmentRead32 ((UINTN) PciCfgBase + > PCI_COMMAND_OFFSET); >=20 > + *Command =3D *Command & > (UINT32)~(EFI_PCI_COMMAND_MEMORY_SPACE | > EFI_PCI_COMMAND_BUS_MASTER); >=20 > + } >=20 > +} >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPrivate/PeiDx= eSm > mSerialIoPrivateLib/SerialIoPrivateLibI2cVer2.c > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPrivate/PeiDx= eSm > mSerialIoPrivateLib/SerialIoPrivateLibI2cVer2.c > new file mode 100644 > index 0000000000..fd684ca2a9 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPrivate/PeiDx= eSm > mSerialIoPrivateLib/SerialIoPrivateLibI2cVer2.c > @@ -0,0 +1,70 @@ > +/** @file >=20 > + Serial IO I2C Private Lib implementation TigerLake specific. >=20 > + All function in this library is available for PEI, DXE, and SMM, >=20 > + But do not support UEFI RUNTIME environment call. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +GLOBAL_REMOVE_IF_UNREFERENCED UINT16 mPchLpSerialIoI2cDevId [] =3D > { >=20 > + V_VER2_PCH_LP_SERIAL_IO_CFG_I2C0_DEVICE_ID, >=20 > + V_VER2_PCH_LP_SERIAL_IO_CFG_I2C1_DEVICE_ID, >=20 > + V_VER2_PCH_LP_SERIAL_IO_CFG_I2C2_DEVICE_ID, >=20 > + V_VER2_PCH_LP_SERIAL_IO_CFG_I2C3_DEVICE_ID, >=20 > + V_VER2_PCH_LP_SERIAL_IO_CFG_I2C4_DEVICE_ID, >=20 > + V_VER2_PCH_LP_SERIAL_IO_CFG_I2C5_DEVICE_ID >=20 > +}; >=20 > + >=20 > +GLOBAL_REMOVE_IF_UNREFERENCED > SERIAL_IO_CONTROLLER_DESCRIPTOR mSerialIoI2cFixedAddress [] =3D { >=20 > + {PCH_SERIAL_IO_BASE_ADDRESS + 0x0000, > PCH_SERIAL_IO_BASE_ADDRESS + 0x1000}, >=20 > + {PCH_SERIAL_IO_BASE_ADDRESS + 0x2000, > PCH_SERIAL_IO_BASE_ADDRESS + 0x3000}, >=20 > + {PCH_SERIAL_IO_BASE_ADDRESS + 0x4000, > PCH_SERIAL_IO_BASE_ADDRESS + 0x5000}, >=20 > + {PCH_SERIAL_IO_BASE_ADDRESS + 0x6000, > PCH_SERIAL_IO_BASE_ADDRESS + 0x7000}, >=20 > + {PCH_SERIAL_IO_BASE_ADDRESS + 0x8000, > PCH_SERIAL_IO_BASE_ADDRESS + 0x9000}, >=20 > + {PCH_SERIAL_IO_BASE_ADDRESS + 0xA000, > PCH_SERIAL_IO_BASE_ADDRESS + 0xB000}, >=20 > + {PCH_SERIAL_IO_BASE_ADDRESS + 0xC000, > PCH_SERIAL_IO_BASE_ADDRESS + 0xD000}, >=20 > + {PCH_SERIAL_IO_BASE_ADDRESS + 0xE000, > PCH_SERIAL_IO_BASE_ADDRESS + 0xF000} >=20 > +}; >=20 > + >=20 > +/** >=20 > + Gets Fixed Address used for Pci Config Space manipulation >=20 > + >=20 > + @param[in] I2cNumber Serial IO device I2C number >=20 > + >=20 > + @retval Pci Config Address >=20 > +**/ >=20 > +UINT32 >=20 > +GetSerialIoI2cFixedPciCfgAddress ( >=20 > + IN UINT8 I2cNumber >=20 > + ) >=20 > +{ >=20 > + return mSerialIoI2cFixedAddress[I2cNumber].Bar1; >=20 > +} >=20 > + >=20 > + >=20 > +/** >=20 > + Gets I2C Device Id >=20 > + >=20 > + @param[in] I2cNumber Serial IO device I2C number >=20 > + >=20 > + @retval Device Id >=20 > +**/ >=20 > +UINT16 >=20 > +GetSerialIoI2cDeviceId ( >=20 > + IN UINT8 I2cNumber >=20 > + ) >=20 > +{ >=20 > + return mPchLpSerialIoI2cDevId[I2cNumber]; >=20 > +} >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPrivate/PeiDx= eSm > mSerialIoPrivateLib/SerialIoPrivateLibInternal.h > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPrivate/PeiDx= eSm > mSerialIoPrivateLib/SerialIoPrivateLibInternal.h > new file mode 100644 > index 0000000000..b5e8aba9ac > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPrivate/PeiDx= eSm > mSerialIoPrivateLib/SerialIoPrivateLibInternal.h > @@ -0,0 +1,20 @@ > +/** @file >=20 > + Header file for SerialIoPrivateLibInternal. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _SERIAL_IO_PRIVATE_LIB_INTERNAL_H_ >=20 > +#define _SERIAL_IO_PRIVATE_LIB_INTERNAL_H_ >=20 > + >=20 > +typedef struct { >=20 > + UINT32 Bar0; >=20 > + UINT32 Bar1; >=20 > +} SERIAL_IO_CONTROLLER_DESCRIPTOR; >=20 > + >=20 > +typedef struct { >=20 > + UINT8 DevNum; >=20 > + UINT8 FuncNum; >=20 > +} SERIAL_IO_BDF_NUMBERS; >=20 > + >=20 > +#endif >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPrivate/PeiDx= eSm > mSerialIoPrivateLib/SerialIoPrivateLibSpi.c > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPrivate/PeiDx= eSm > mSerialIoPrivateLib/SerialIoPrivateLibSpi.c > new file mode 100644 > index 0000000000..a926941baf > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPrivate/PeiDx= eSm > mSerialIoPrivateLib/SerialIoPrivateLibSpi.c > @@ -0,0 +1,122 @@ > +/** @file >=20 > + Common Serial IO Private Lib implementation - SPI part >=20 > + All function in this library is available for PEI, DXE, and SMM, >=20 > + But do not support UEFI RUNTIME environment call. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +/** >=20 > + Checks if SPI is Hidden, and it's Pci Config space available >=20 > + >=20 > + @param[in] SpiNumber Selects Serial IO SPI device >=20 > + >=20 > + @retval TRUE SPI is in hidden mode >=20 > + @retval FALSE SPI is not in hidden mode >=20 > +**/ >=20 > +BOOLEAN >=20 > +IsSerialIoSpiHidden ( >=20 > + IN UINT8 SpiNumber >=20 > + ) >=20 > +{ >=20 > + if (MmioRead16 (GetSerialIoSpiFixedPciCfgAddress (SpiNumber) + > PCI_DEVICE_ID_OFFSET) =3D=3D GetSerialIoSpiDeviceId (SpiNumber)) { >=20 > + return TRUE; >=20 > + } >=20 > + return FALSE; >=20 > +} >=20 > + >=20 > +/** >=20 > + Configures Serial IO Controller before control is passd to the OS >=20 > + >=20 > + @param[in] SpiNumber SPI Number >=20 > + @param[in] SpiDeviceConfig SerialIo SPI Config >=20 > + >=20 > +**/ >=20 > +VOID >=20 > +SerialIoSpiBootHandler ( >=20 > + IN UINT8 SpiNumber, >=20 > + IN SERIAL_IO_SPI_CONFIG *SpiDeviceConfig >=20 > + ) >=20 > +{ >=20 > + UINT64 PciCfgBase; >=20 > + BOOLEAN TurnOff; >=20 > + >=20 > + TurnOff =3D FALSE; >=20 > + >=20 > + if (SpiDeviceConfig->Mode =3D=3D SerialIoSpiPci) { >=20 > + TurnOff =3D TRUE; >=20 > + } >=20 > + >=20 > + if ((SpiDeviceConfig->Mode =3D=3D SerialIoSpiDisabled) && > (SerialIoSpiFuncNumber (SpiNumber) =3D=3D 0x0)) { >=20 > + if (SerialIoHigherFunctionsEnabled (SerialIoSpiDevNumber (SpiNumber)= )) > { >=20 > + TurnOff =3D TRUE; >=20 > + } >=20 > + } >=20 > + >=20 > + if (TurnOff) { >=20 > + PciCfgBase =3D GetSerialIoSpiPciCfg (SpiNumber); >=20 > + SerialIoSetD3 (PciCfgBase); >=20 > + SerialIoMmioDisable (PciCfgBase, TRUE); >=20 > + } >=20 > +} >=20 > + >=20 > +/** >=20 > + Sets Pme Control Status and Command register values required for S3 Bo= ot > Script >=20 > + >=20 > + @param[in] SpiNumber SPI Number >=20 > + @param[in] SpiDeviceConfig SerialIo SPI Config >=20 > + @param[in/out] S3PciCfgBase S3 Boot Script Pci Config Base >=20 > + @param[in/out] Command Pci Command register data to save >=20 > + @param[in/out] Pme Pci Pme Control register data to save >=20 > + >=20 > +**/ >=20 > +VOID >=20 > +SerialIoSpiS3Handler ( >=20 > + IN UINT8 SpiNumber, >=20 > + IN SERIAL_IO_SPI_CONFIG *SpiDeviceConfig, >=20 > + IN OUT UINT64 *S3PciCfgBase, >=20 > + IN OUT UINT32 *Command, >=20 > + IN OUT UINT32 *Pme >=20 > + ) >=20 > +{ >=20 > + BOOLEAN TurnOff; >=20 > + UINT64 PciCfgBase; >=20 > + >=20 > + *S3PciCfgBase =3D 0; >=20 > + TurnOff =3D FALSE; >=20 > + >=20 > + if (SpiDeviceConfig->Mode =3D=3D SerialIoSpiPci) { >=20 > + TurnOff =3D TRUE; >=20 > + } >=20 > + >=20 > + if ((SpiDeviceConfig->Mode =3D=3D SerialIoSpiDisabled) && > (SerialIoSpiFuncNumber (SpiNumber) =3D=3D 0x0)) { >=20 > + if (SerialIoHigherFunctionsEnabled (SerialIoSpiDevNumber (SpiNumber)= )) > { >=20 > + TurnOff =3D TRUE; >=20 > + } >=20 > + } >=20 > + >=20 > + if (TurnOff) { >=20 > + *S3PciCfgBase =3D GetSerialIoSpiS3PciBase (SpiNumber); >=20 > + PciCfgBase =3D GetSerialIoSpiPciCfg (SpiNumber); >=20 > + *Pme =3D PciSegmentRead32 ((UINTN) PciCfgBase + > R_SERIAL_IO_CFG_PME_CTRL_STS); >=20 > + *Pme =3D *Pme | BIT0 | BIT1; >=20 > + *Command =3D PciSegmentRead32 ((UINTN) PciCfgBase + > PCI_COMMAND_OFFSET); >=20 > + *Command =3D *Command & > (UINT32)~(EFI_PCI_COMMAND_MEMORY_SPACE | > EFI_PCI_COMMAND_BUS_MASTER); >=20 > + } >=20 > +} >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPrivate/PeiDx= eSm > mSerialIoPrivateLib/SerialIoPrivateLibSpiVer2.c > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPrivate/PeiDx= eSm > mSerialIoPrivateLib/SerialIoPrivateLibSpiVer2.c > new file mode 100644 > index 0000000000..abda359202 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPrivate/PeiDx= eSm > mSerialIoPrivateLib/SerialIoPrivateLibSpiVer2.c > @@ -0,0 +1,82 @@ > +/** @file >=20 > + Serial IO Spi Private Lib implementation TigerLake specific. >=20 > + All function in this library is available for PEI, DXE, and SMM, >=20 > + But do not support UEFI RUNTIME environment call. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +GLOBAL_REMOVE_IF_UNREFERENCED UINT16 mPchLpSerialIoSpiDevId [] =3D > { >=20 > + V_VER2_PCH_LP_SERIAL_IO_CFG_SPI0_DEVICE_ID, >=20 > + V_VER2_PCH_LP_SERIAL_IO_CFG_SPI1_DEVICE_ID, >=20 > + V_VER2_PCH_LP_SERIAL_IO_CFG_SPI2_DEVICE_ID, >=20 > + V_VER2_PCH_LP_SERIAL_IO_CFG_SPI3_DEVICE_ID >=20 > +}; >=20 > + >=20 > +GLOBAL_REMOVE_IF_UNREFERENCED > SERIAL_IO_CONTROLLER_DESCRIPTOR mSerialIoSpiFixedAddress [] =3D { >=20 > + {PCH_SERIAL_IO_BASE_ADDRESS + 0x10000, > PCH_SERIAL_IO_BASE_ADDRESS + 0x11000}, >=20 > + {PCH_SERIAL_IO_BASE_ADDRESS + 0x12000, > PCH_SERIAL_IO_BASE_ADDRESS + 0x13000}, >=20 > + {PCH_SERIAL_IO_BASE_ADDRESS + 0x14000, > PCH_SERIAL_IO_BASE_ADDRESS + 0x15000}, >=20 > + {PCH_SERIAL_IO_BASE_ADDRESS + 0x16000, > PCH_SERIAL_IO_BASE_ADDRESS + 0x17000}, >=20 > + {PCH_SERIAL_IO_BASE_ADDRESS + 0x18000, > PCH_SERIAL_IO_BASE_ADDRESS + 0x19000}, >=20 > + {PCH_SERIAL_IO_BASE_ADDRESS + 0x1A000, > PCH_SERIAL_IO_BASE_ADDRESS + 0x1B000}, >=20 > + {PCH_SERIAL_IO_BASE_ADDRESS + 0x1C000, > PCH_SERIAL_IO_BASE_ADDRESS + 0x1D000} >=20 > +}; >=20 > + >=20 > +/** >=20 > + Gets Fixed Base Address used for BAR0 >=20 > + >=20 > + @param[in] SpiNumber Serial IO device SPI number >=20 > + >=20 > + @retval Config control offset >=20 > +**/ >=20 > +UINT32 >=20 > +GetSerialIoSpiFixedMmioAddress ( >=20 > + IN UINT8 SpiNumber >=20 > + ) >=20 > +{ >=20 > + return mSerialIoSpiFixedAddress[SpiNumber].Bar0; >=20 > +} >=20 > + >=20 > +/** >=20 > + Gets Fixed Address used for Pci Config Space manipulation >=20 > + >=20 > + @param[in] SpiNumber Serial IO device SPI number >=20 > + >=20 > + @retval Pci Config Address >=20 > +**/ >=20 > +UINT32 >=20 > +GetSerialIoSpiFixedPciCfgAddress ( >=20 > + IN UINT8 SpiNumber >=20 > + ) >=20 > +{ >=20 > + return mSerialIoSpiFixedAddress[SpiNumber].Bar1; >=20 > +} >=20 > + >=20 > +/** >=20 > + Gets Spi Device Id >=20 > + >=20 > + @param[in] SpiNumber Serial IO device SPI number >=20 > + >=20 > + @retval Device Id >=20 > +**/ >=20 > +UINT16 >=20 > +GetSerialIoSpiDeviceId ( >=20 > + IN UINT8 SpiNumber >=20 > + ) >=20 > +{ >=20 > + return mPchLpSerialIoSpiDevId[SpiNumber]; >=20 > +} >=20 > + >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPrivate/PeiDx= eSm > mSerialIoPrivateLib/SerialIoPrivateLibUart.c > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPrivate/PeiDx= eSm > mSerialIoPrivateLib/SerialIoPrivateLibUart.c > new file mode 100644 > index 0000000000..0f7d6513ce > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPrivate/PeiDx= eSm > mSerialIoPrivateLib/SerialIoPrivateLibUart.c > @@ -0,0 +1,136 @@ > +/** @file >=20 > + Serial IO Private Lib implementation - UART part >=20 > + All function in this library is available for PEI, DXE, and SMM, >=20 > + But do not support UEFI RUNTIME environment call. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +/** >=20 > + Checks if UART is Hidden, and it's Pci Config space available >=20 > + >=20 > + @param[in] UartNumber Selects Serial IO UART device >=20 > + >=20 > + @retval TRUE UART is in hidden mode >=20 > + @retval FALSE UART is not in hidden mode >=20 > +**/ >=20 > +BOOLEAN >=20 > +IsSerialIoUartHidden ( >=20 > + IN UINT8 UartNumber >=20 > + ) >=20 > +{ >=20 > + if (MmioRead16 (GetSerialIoUartFixedPciCfgAddress (UartNumber) + > PCI_DEVICE_ID_OFFSET) =3D=3D GetSerialIoUartDeviceId (UartNumber)) { >=20 > + return TRUE; >=20 > + } >=20 > + return FALSE; >=20 > +} >=20 > + >=20 > +/** >=20 > + Configures Serial IO Controller before control is passd to the OS >=20 > + >=20 > + @param[in] UartNumber UART Number >=20 > + @param[in] UartDeviceConfig SerialIo UART Config >=20 > + >=20 > +**/ >=20 > +VOID >=20 > +SerialIoUartBootHandler ( >=20 > + IN UINT8 UartNumber, >=20 > + IN SERIAL_IO_UART_CONFIG *UartDeviceConfig >=20 > + ) >=20 > +{ >=20 > + UINT64 PciCfgBase; >=20 > + BOOLEAN TurnOff; >=20 > + >=20 > + TurnOff =3D FALSE; >=20 > + >=20 > + // >=20 > + // Even if Uart is Hidden and in D3 SerialIoUartLib is capable of sett= ing D0 > during each write/read. >=20 > + // In case it is required for Os Debug DBG2 must be set to TRUE. >=20 > + // >=20 > + if (UartDeviceConfig->Mode =3D=3D SerialIoUartPci || UartDeviceConfig- > >Mode =3D=3D SerialIoUartHidden) { >=20 > + TurnOff =3D TRUE; >=20 > + } >=20 > + >=20 > + // >=20 > + // Uart in Com mode will be placed in D3 depending on PG configuration > through ACPI _PS3 >=20 > + // >=20 > + >=20 > + if ((UartDeviceConfig->Mode =3D=3D SerialIoUartDisabled) && > (SerialIoUartFuncNumber (UartNumber) =3D=3D 0x0)) { >=20 > + if (SerialIoHigherFunctionsEnabled (SerialIoUartDevNumber > (UartNumber))) { >=20 > + TurnOff =3D TRUE; >=20 > + } >=20 > + } >=20 > + >=20 > + if (UartDeviceConfig->DBG2 =3D=3D TRUE) { >=20 > + TurnOff =3D FALSE; >=20 > + } >=20 > + >=20 > + if (TurnOff) { >=20 > + PciCfgBase =3D GetSerialIoUartPciCfg (UartNumber); >=20 > + SerialIoSetD3 (PciCfgBase); >=20 > + if ((UartDeviceConfig->Mode =3D=3D SerialIoUartPci) || (UartDeviceCo= nfig- > >Mode =3D=3D SerialIoUartDisabled)) { >=20 > + SerialIoMmioDisable (PciCfgBase, TRUE); >=20 > + } >=20 > + } >=20 > +} >=20 > + >=20 > +/** >=20 > + Sets Pme Control Status and Command register values required for S3 Bo= ot > Script >=20 > + >=20 > + @param[in] UartNumber UART Number >=20 > + @param[in] UartDeviceConfig SerialIo UART Config >=20 > + @param[in/out] S3PciCfgBase S3 Boot Script Pci Config Base >=20 > + @param[in/out] Command Pci Command register data to save >=20 > + @param[in/out] Pme Pci Pme Control register data to sav= e >=20 > + >=20 > +**/ >=20 > +VOID >=20 > +SerialIoUartS3Handler ( >=20 > + IN UINT8 UartNumber, >=20 > + IN SERIAL_IO_UART_CONFIG *UartDeviceConfig, >=20 > + IN OUT UINT64 *S3PciCfgBase, >=20 > + IN OUT UINT32 *Command, >=20 > + IN OUT UINT32 *Pme >=20 > + ) >=20 > +{ >=20 > + BOOLEAN TurnOff; >=20 > + UINT64 PciCfgBase; >=20 > + >=20 > + *S3PciCfgBase =3D 0; >=20 > + TurnOff =3D FALSE; >=20 > + >=20 > + if (UartDeviceConfig->Mode =3D=3D SerialIoUartPci) { >=20 > + TurnOff =3D TRUE; >=20 > + } >=20 > + >=20 > + if ((UartDeviceConfig->Mode =3D=3D SerialIoUartDisabled) && > (SerialIoUartFuncNumber (UartNumber) =3D=3D 0x0)) { >=20 > + if (SerialIoHigherFunctionsEnabled (SerialIoUartDevNumber > (UartNumber))) { >=20 > + TurnOff =3D TRUE; >=20 > + } >=20 > + } >=20 > + >=20 > + if (TurnOff) { >=20 > + *S3PciCfgBase =3D GetSerialIoUartS3PciBase (UartNumber); >=20 > + PciCfgBase =3D GetSerialIoUartPciCfg (UartNumber); >=20 > + *Pme =3D PciSegmentRead32 ((UINTN) PciCfgBase + > R_SERIAL_IO_CFG_PME_CTRL_STS); >=20 > + *Pme =3D *Pme | BIT0 | BIT1; >=20 > + *Command =3D PciSegmentRead32 ((UINTN) PciCfgBase + > PCI_COMMAND_OFFSET); >=20 > + *Command =3D *Command & > (UINT32)~(EFI_PCI_COMMAND_MEMORY_SPACE | > EFI_PCI_COMMAND_BUS_MASTER); >=20 > + } >=20 > +} >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPrivate/PeiDx= eSm > mSerialIoPrivateLib/SerialIoPrivateLibUartVer2.c > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPrivate/PeiDx= eSm > mSerialIoPrivateLib/SerialIoPrivateLibUartVer2.c > new file mode 100644 > index 0000000000..91280f8e90 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPrivate/PeiDx= eSm > mSerialIoPrivateLib/SerialIoPrivateLibUartVer2.c > @@ -0,0 +1,82 @@ > +/** @file >=20 > + Serial IO Private Uart Lib implementation TigerLake specific. >=20 > + All function in this library is available for PEI, DXE, and SMM, >=20 > + But do not support UEFI RUNTIME environment call. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +GLOBAL_REMOVE_IF_UNREFERENCED UINT16 mPchLpSerialIoUartDevId [] > =3D { >=20 > + V_VER2_PCH_LP_SERIAL_IO_CFG_UART0_DEVICE_ID, >=20 > + V_VER2_PCH_LP_SERIAL_IO_CFG_UART1_DEVICE_ID, >=20 > + V_VER2_PCH_LP_SERIAL_IO_CFG_UART2_DEVICE_ID, >=20 > + V_VER2_PCH_LP_SERIAL_IO_CFG_UART3_DEVICE_ID >=20 > +}; >=20 > + >=20 > +GLOBAL_REMOVE_IF_UNREFERENCED > SERIAL_IO_CONTROLLER_DESCRIPTOR mSerialIoUartFixedAddress [] =3D { >=20 > + {PCH_SERIAL_IO_BASE_ADDRESS + 0x1E000, > PCH_SERIAL_IO_BASE_ADDRESS + 0x1F000}, >=20 > + {PCH_SERIAL_IO_BASE_ADDRESS + 0x20000, > PCH_SERIAL_IO_BASE_ADDRESS + 0x21000}, >=20 > + {PCH_SERIAL_IO_BASE_ADDRESS + 0x22000, > PCH_SERIAL_IO_BASE_ADDRESS + 0x23000}, >=20 > + {PCH_SERIAL_IO_BASE_ADDRESS + 0x24000, > PCH_SERIAL_IO_BASE_ADDRESS + 0x25000}, >=20 > + {PCH_SERIAL_IO_BASE_ADDRESS + 0x26000, > PCH_SERIAL_IO_BASE_ADDRESS + 0x27000}, >=20 > + {PCH_SERIAL_IO_BASE_ADDRESS + 0x28000, > PCH_SERIAL_IO_BASE_ADDRESS + 0x29000}, >=20 > + {PCH_SERIAL_IO_BASE_ADDRESS + 0x2A000, > PCH_SERIAL_IO_BASE_ADDRESS + 0x2B000} >=20 > +}; >=20 > + >=20 > +/** >=20 > + Gets Fixed Base Address used for BAR0 >=20 > + >=20 > + @param[in] UartNumber Serial IO device UART number >=20 > + >=20 > + @retval Config control offset >=20 > +**/ >=20 > +UINT32 >=20 > +GetSerialIoUartFixedMmioAddress ( >=20 > + IN UINT8 UartNumber >=20 > + ) >=20 > +{ >=20 > + return mSerialIoUartFixedAddress[UartNumber].Bar0; >=20 > +} >=20 > + >=20 > +/** >=20 > + Gets Fixed Address used for Pci Config Space manipulation >=20 > + >=20 > + @param[in] UartNumber Serial IO device UART number >=20 > + >=20 > + @retval Pci Config Address >=20 > +**/ >=20 > +UINT32 >=20 > +GetSerialIoUartFixedPciCfgAddress ( >=20 > + IN UINT8 UartNumber >=20 > + ) >=20 > +{ >=20 > + return mSerialIoUartFixedAddress[UartNumber].Bar1; >=20 > +} >=20 > + >=20 > +/** >=20 > + Gets Uarts Device Id >=20 > + >=20 > + @param[in] UartNumbe Serial IO device UART number >=20 > + >=20 > + @retval Device Id >=20 > +**/ >=20 > +UINT16 >=20 > +GetSerialIoUartDeviceId ( >=20 > + IN UINT8 UartNumber >=20 > + ) >=20 > +{ >=20 > + return mPchLpSerialIoUartDevId[UartNumber]; >=20 > +} >=20 > -- > 2.24.0.windows.2