From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by mx.groups.io with SMTP id smtpd.web11.2879.1612410847986405175 for ; Wed, 03 Feb 2021 19:54:08 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@intel.onmicrosoft.com header.s=selector2-intel-onmicrosoft-com header.b=AdDpKrdu; spf=pass (domain: intel.com, ip: 192.55.52.88, mailfrom: nathaniel.l.desimone@intel.com) IronPort-SDR: rjHxYM7a/8e0+GOip/a9j9f99yy0tR94JQOnemBpWb2AdXw5LtpW/m6zxrMSN/CHXffJLWKV8o 6NKdaC/HenCg== X-IronPort-AV: E=McAfee;i="6000,8403,9884"; a="200143066" X-IronPort-AV: E=Sophos;i="5.79,400,1602572400"; d="scan'208";a="200143066" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Feb 2021 19:54:06 -0800 IronPort-SDR: vfiXS7n6YLDglIRufb8ljEmVgxumw/zTKU+fEIbkWGm9m8EIBV+MKlPvgYKp1ABbBZbjxL1obS chqZ6D04+8bg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.79,400,1602572400"; d="scan'208";a="507992457" Received: from orsmsx606.amr.corp.intel.com ([10.22.229.19]) by orsmga004.jf.intel.com with ESMTP; 03 Feb 2021 19:54:05 -0800 Received: from orsmsx611.amr.corp.intel.com (10.22.229.24) by ORSMSX606.amr.corp.intel.com (10.22.229.19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2106.2; Wed, 3 Feb 2021 19:54:05 -0800 Received: from orsmsx603.amr.corp.intel.com (10.22.229.16) by ORSMSX611.amr.corp.intel.com (10.22.229.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2106.2; Wed, 3 Feb 2021 19:54:04 -0800 Received: from orsedg603.ED.cps.intel.com (10.7.248.4) by orsmsx603.amr.corp.intel.com (10.22.229.16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2106.2 via Frontend Transport; Wed, 3 Feb 2021 19:54:04 -0800 Received: from NAM04-BN3-obe.outbound.protection.outlook.com (104.47.46.59) by edgegateway.intel.com (134.134.137.100) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.1713.5; Wed, 3 Feb 2021 19:54:04 -0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Vo0gY/EBtr+Q1tJJ3jyu2btPGkyfRYr5c78V12IQuyFnaKxGXDtSbc72eH4S9UljGAooRXytsLEr6UGqePylAd3Wc9w6rGGuPGpbC/YvanCRMnJiWkpaQdBr62VzhSzw1J+t+VX+L2lEJTtc+lN1xlSe36NXB/YndAHrQ0IpfiMAuS8QMXmBLlbMRYj2ufe4CvVvc48H9c/N62tSB218g55M7lu9wtAWU5lQczRm+ItMN4g0ydnu8QnDsZl9XEJIodi4usj546ihrfHEvEJB9pvjgditcY/81rM8hAH4KPTXBqLT7NX8qy4MZEF1asJm2C6wys30l/dLFePgFW4w4Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=xdklxUeR4T1vPu5eJ9OnIHEHi85DcQWKBIcPgwkOHlw=; b=SMFZuPgyIuU/Xcv2iOxvL3hrDeqQ8sRLPnVq+zg8nGe9pgAiIAl1qhl4dEZWlC7oJ/VgqVywiJYSH+tqngknNC80yJONdT825Pz7XDL/ZogCg0Qt4GHroSHOnsRHFn0D3TbgCl8agm2CBcYda5Pk4holkKz1LNolVI87NSjitBijG7BROrMZ+294xX6HPs1ohmuK8jHyY/CrGkSRTJVibtZQD3J1+gHAh0i14XpQfkVS7fZKAr2ZjvOOJWWeYYruJd9sUd8UNl4Up1I6obFFRMm3ecwfLTDzOM/IYq7KrPJUeU1Uxz0NMVNoS20uDjIPck1wFFoDNVxb6x7KzEid0A== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=intel.onmicrosoft.com; s=selector2-intel-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=xdklxUeR4T1vPu5eJ9OnIHEHi85DcQWKBIcPgwkOHlw=; b=AdDpKrduV+f5D+UKXSNmnNlCIR2fxXhQAX8l+MiS9dmv3jBybfbqBXXhRWyFb79yiATrLQQR6j0qEvs4ssjcKWe09iyIAyJ/Ycc13sXUxA9Mp0S+iyPxePg77wuwKMhcHGcEnfI0YJPPYxMpVHaeWmIK+81xRnaYXbwyfiUGIfg= Received: from BN6PR1101MB2147.namprd11.prod.outlook.com (2603:10b6:405:57::23) by BN6PR11MB1329.namprd11.prod.outlook.com (2603:10b6:404:47::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3805.19; Thu, 4 Feb 2021 03:53:19 +0000 Received: from BN6PR1101MB2147.namprd11.prod.outlook.com ([fe80::203e:ed6b:a572:6453]) by BN6PR1101MB2147.namprd11.prod.outlook.com ([fe80::203e:ed6b:a572:6453%3]) with mapi id 15.20.3805.024; Thu, 4 Feb 2021 03:53:19 +0000 From: "Nate DeSimone" To: "Luo, Heng" , "devel@edk2.groups.io" CC: "Chaganty, Rangasai V" Subject: Re: [PATCH 05/40] TigerlakeSiliconPkg/Pch: Add include headers Thread-Topic: [PATCH 05/40] TigerlakeSiliconPkg/Pch: Add include headers Thread-Index: AQHW+DrJwnLklCvzP0WjVRMr4bIvQKpHYg/w Date: Thu, 4 Feb 2021 03:53:19 +0000 Message-ID: References: <20210201013657.1833-1-heng.luo@intel.com> <20210201013657.1833-5-heng.luo@intel.com> In-Reply-To: <20210201013657.1833-5-heng.luo@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-reaction: no-action dlp-version: 11.5.1.3 dlp-product: dlpe-windows authentication-results: intel.com; dkim=none (message not signed) header.d=none;intel.com; dmarc=none action=none header.from=intel.com; x-originating-ip: [50.53.190.176] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 4157f9f8-1a17-428b-eed3-08d8c8c06913 x-ms-traffictypediagnostic: BN6PR11MB1329: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:206; x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: 4QdCN6xktM3TsH50IFZlgRC+vsG30OYcafVKmiq4emEQ61uztSfGvHcJn8lJi3flCwNo6XE59/uJrNsqNx1B0xK4RiRV50O6gLf579blHxsgmYtLtmy8bEA/ITv253qNBEnkh2cfqx9fT2xGRs36QNW4P7HpLg+4pIXk6bUnMNiLqm2YlM1XsuowMw7XH0aTz5cJES8bjxD788iOUsR+U0iTJVy66Rq33fzsognKiBksnW/EaFzViF6LalVvKVQXFZCgxzR8ZE+rlqNZZVnxLGeKfhciIH6lwHMk8NxnLdNDJ9RUXQK96owJgwKUWEGZ8yvT4NPLbe6Mn7TmVGhTG0dcey6oX5NWvrDI1X0SZH3TMicy0/KN/sjkKe4ZSMqaCCjRGDs8yh7P+Lg63WMWyor/RjHQRV1kY755mTP70Pk7c3CMeW1OuAjwDxMiWeuvrM0No5D1HMXHeIwEEaQ5TW+Ri9beIyJ4M39bUUovpM1in0CXQHPaTM063Jxor7DXXECiAEVxvCL1ICuyEuqqQGoElyCTkNtC2Xd92YCUx2xlnp1ATVTpbFPL14hNo6qVtUXqc4PL0nGMm9geZy1/jCSoJTc/ewwPr3UvpgUYM6Eb8CRTlq6DyXX4cfiP2dYO1/zuPXGBz1oEDNqpWSpwsQ== x-forefront-antispam-report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:BN6PR1101MB2147.namprd11.prod.outlook.com;PTR:;CAT:NONE;SFS:(396003)(346002)(136003)(366004)(376002)(39860400002)(7696005)(966005)(66574015)(52536014)(86362001)(83380400001)(76116006)(66476007)(9686003)(66446008)(8936002)(26005)(107886003)(478600001)(19627235002)(5660300002)(64756008)(4326008)(186003)(110136005)(55016002)(71200400001)(66946007)(8676002)(53546011)(33656002)(2906002)(30864003)(66556008)(316002)(6506007)(569008);DIR:OUT;SFP:1102; x-ms-exchange-antispam-messagedata: =?us-ascii?Q?IPpjSJ6srJv2eKIIQEbR7RhUIDvpDhidmHd/qjrsP7SBhBy3E3PYl3o94Hrv?= =?us-ascii?Q?UMysqvYFlgGnIeicIg5On5Nhi2RRm8LqUcAgQmSaSoWu4YLKjjqSImqA6Gb/?= =?us-ascii?Q?3IV8w/ThMSz8ExEHny1kMCqUwh6anczjD5LzLF6tRVbVa0Cf6HLp90iDiCsR?= =?us-ascii?Q?TEFvm+R+p9DP5486QjwBV2k5dWpyQhJHQ2CT9cQ83gCwYqwqF6mJ6uGyq/m2?= =?us-ascii?Q?53AurVcrNdreI7/VDShzHpELACEVjfJ0oNfeMNH2aqVzXOEsnC+it0zSWUd0?= =?us-ascii?Q?EGnLPwJxXUcMa1Bx7Wt3BPA2WC149MVFw0/2XJ9C4CtbaVVjsP7vu25iVVNY?= =?us-ascii?Q?3OZhLAW6v1Ucxtbfxrs/SgmKJ1Rxk5HmPk8V4dZ61ivij4IWRDoDGwhG76Xn?= =?us-ascii?Q?qox/MaV5UmdtZO4mqUvlVAecm0v7zMAuljXig0qNRb4Efq+bXjKv32oa7hFj?= =?us-ascii?Q?qpvlwOozeVD1rIC0KxVjqbdBFjbw0h+R9WaYW7SUAcP/mYpvAFixyeZRJqKV?= =?us-ascii?Q?HeTFnbVfWlkzk/TIC3v1VdYt5rOozq6awaqi3FehWcXB8VglOLNXVkXceAwP?= =?us-ascii?Q?7Qk75qETb9IcCSEtJ6yAnD4NiypzVceVqh+OWBPyCpktSm/OHPdL7STZfr/0?= =?us-ascii?Q?8dPSrAO8by2KNOmA0fbaFQWFuWOGc44RJZXigtHlquZ54c8CEQkRvPOaYOaI?= =?us-ascii?Q?w9Kf6Qs1CI1qd36EVOZJhJ4/xKzKTzhjfFo9DG31SvGOz/pv6gaZr4JmhjOy?= =?us-ascii?Q?P/rNVA5KJ+L9DFyfCKQVKer06Z1E6/pSsFCXJqsGxOWZ019p3Ju8D9GqqurK?= =?us-ascii?Q?tsdUHrx4sqdwLLeQTdUw9xQeWxXwBuHgVrLfAJQOKWE+hnTk7L9lc/OZuNGV?= =?us-ascii?Q?KgRmenPQgW2J8ZWvjSkS6dWicbfypfUdgS/EXftkqoqbCXHgi38wE7jmFUSE?= =?us-ascii?Q?D/snpvgIL0ERW6IWmB58wxbvG5w9a/Q2nseozAS+WO5BjIlprDvMLLnskzXz?= =?us-ascii?Q?JPeftCpu4kjWZYt5DnbMWGpeSB/w0KxisiY5XqQWeBFeSsJSe7wFsOmFq2Wg?= =?us-ascii?Q?57ziyc2j7SfefK+aKgqc55lTHWIr+XwZ0P9EvifYssyHpT/RLCNZJERYz6Sk?= =?us-ascii?Q?W3kbxBHSR2794GX8oerUzEGLcyEe+yVtDMX/QR8moQSprr5re07AUexl7nht?= =?us-ascii?Q?mcwYAdrDUqc0rTRvEHhsGg6rdzBdz9GGGtxW2Jmt1MbTnuIGpaQjvT2g2eqM?= =?us-ascii?Q?v8Rccvtqir+SaiX7oYbSLseG0nunCTY0JLxqqA6b5PqIGsPDjN7xUoqeFus2?= =?us-ascii?Q?Rdh2Y1Tb44a88O0N7qz58PZU?= MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BN6PR1101MB2147.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 4157f9f8-1a17-428b-eed3-08d8c8c06913 X-MS-Exchange-CrossTenant-originalarrivaltime: 04 Feb 2021 03:53:19.2566 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: iAL4+CXjfB7+Nm+D316/ultYVt58fiL6ttrVoax8/zww5Zu/2kl9/ze+8QDFlUXzt9dBETTsGXnKMcUMFUyegCs5KjgETxhU3GtblFARKOA= X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR11MB1329 Return-Path: nathaniel.l.desimone@intel.com X-OriginatorOrg: intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Nate DeSimone > -----Original Message----- > From: Luo, Heng > Sent: Sunday, January 31, 2021 5:36 PM > To: devel@edk2.groups.io > Cc: Chaganty, Rangasai V ; Desimone, > Nathaniel L > Subject: [PATCH 05/40] TigerlakeSiliconPkg/Pch: Add include headers >=20 > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3171 >=20 > Adds the following header files: > * Pch/Include >=20 > Cc: Sai Chaganty > Cc: Nate DeSimone > Signed-off-by: Heng Luo > --- >=20 > Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/FlashProtection= Co > nfig.h | 55 > +++++++++++++++++++++++++++++++++++++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/HsioConfig.h > | 57 > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/HsioPcieConfig= .h > | 58 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/HsioSataConfig= .h > | 64 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/LockDownConfig.= h > | 61 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++ > Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/LpcConfig.h > | 38 ++++++++++++++++++++++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/PchGeneralConfi= g. > h | 72 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Library/PchCycleDecodingLi= b.h > | 258 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Library/PchInfoLib.h = | > 590 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Library/PchPciBdfLib.h > | 552 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/PchInfoHob.h = | 70 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/PchLimits.h = | 67 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/PchPolicyCommon.h > | 55 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/PchPreMemPolicyCommon.h > | 56 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/PchResetPlatformSpecific.h > | 21 +++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/IoTrapExDispatch.= h > | 184 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchAcpiSmiDispatch= .h > | 134 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchEspiSmiDispatc= h.h > | 144 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchPcieSmiDispatch= .h > | 166 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchPolicy.h = | > 40 ++++++++++++++++++++++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchSmiDispatch.h > | 132 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchSmmIoTrapContro > l.h | 65 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchSmmPeriodicTime > rControl.h | 65 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++ > Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchTcoSmiDispatch= .h > | 150 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Register/PchRegs.h = | > 16 ++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Register/PchRegsLpc.h > | 145 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Register/PchRegsPsf.h > | 50 ++++++++++++++++++++++++++++++++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Register/PchRegsPsth.h > | 66 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++ > 28 files changed, 3431 insertions(+) >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/FlashProtecti= on > Config.h > b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/FlashProtecti= on > Config.h > new file mode 100644 > index 0000000000..d1e10c3422 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/FlashProtecti= on > Config.h > @@ -0,0 +1,55 @@ > +/** @file >=20 > + FlashProtection policy >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _FLASH_PROTECTION_CONFIG_H_ >=20 > +#define _FLASH_PROTECTION_CONFIG_H_ >=20 > + >=20 > +#define FLASH_PROTECTION_CONFIG_REVISION 1 >=20 > +extern EFI_GUID gFlashProtectionConfigGuid; >=20 > + >=20 > +#pragma pack (push,1) >=20 > + >=20 > +// >=20 > +// Flash Protection Range Register >=20 > +// >=20 > +#define PCH_FLASH_PROTECTED_RANGES 5 >=20 > + >=20 > +/** >=20 > + Protected Flash Range >=20 > +**/ >=20 > +typedef struct { >=20 > + UINT32 WriteProtectionEnable : 1; ///< Write o= r erase is > blocked by hardware. 0: Disable; 1: Enable. >=20 > + UINT32 ReadProtectionEnable : 1; ///< Read is= blocked by > hardware. 0: Disable; 1: Enable. >=20 > + UINT32 RsvdBits : 30; ///< Reserve= d >=20 > + /** >=20 > + The address of the upper limit of protection >=20 > + This is a left shifted address by 12 bits with address bits 11:0 are= assumed > to be FFFh for limit comparison >=20 > + **/ >=20 > + UINT16 ProtectedRangeLimit; >=20 > + /** >=20 > + The address of the upper limit of protection >=20 > + This is a left shifted address by 12 bits with address bits 11:0 are= assumed > to be 0 >=20 > + **/ >=20 > + UINT16 ProtectedRangeBase; >=20 > +} PROTECTED_RANGE; >=20 > + >=20 > +/** >=20 > + The PCH provides a method for blocking writes and reads to specific ra= nges >=20 > + in the SPI flash when the Protected Ranges are enabled. >=20 > + PROTECTED_RANGE is used to specify if flash protection are enabled, >=20 > + the write protection enable bit and the read protection enable bit, >=20 > + and to specify the upper limit and lower base for each register >=20 > + Platform code is responsible to get the range base by > PchGetSpiRegionAddresses routine, >=20 > + and set the limit and base accordingly. >=20 > +**/ >=20 > +typedef struct { >=20 > + CONFIG_BLOCK_HEADER Header; ///<= Config Block > Header >=20 > + PROTECTED_RANGE ProtectRange[PCH_FLASH_PROTECTED_RANGES]; > ///< Protected Flash Ranges >=20 > +} PCH_FLASH_PROTECTION_CONFIG; >=20 > + >=20 > +#pragma pack (pop) >=20 > + >=20 > +#endif // _FLASH_PROTECTION_CONFIG_H_ >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/HsioConfig.h > b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/HsioConfig.h > new file mode 100644 > index 0000000000..ec27845a48 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/HsioConfig.h > @@ -0,0 +1,57 @@ > +/** @file >=20 > + HSIO policy >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _HSIO_CONFIG_H_ >=20 > +#define _HSIO_CONFIG_H_ >=20 > +#define HSIO_PREMEM_CONFIG_REVISION 1 //@deprecated >=20 > +extern EFI_GUID gHsioPreMemConfigGuid; //@deprecated >=20 > + >=20 > +#define HSIO_CONFIG_REVISION 1 >=20 > +extern EFI_GUID gHsioConfigGuid; >=20 > + >=20 > +#pragma pack (push,1) >=20 > + >=20 > +/** >=20 > + The PCH_HSIO_PREMEM_CONFIG block provides HSIO message related > settings. >=20 > +**/ >=20 > +typedef struct { >=20 > + CONFIG_BLOCK_HEADER Header; ///< Config Block Header >=20 > + >=20 > + /** >=20 > + (Test) >=20 > + 0- Disable, disable will prevent the HSIO version check and ChipsetIni= t HECI > message from being sent >=20 > + 1- Enable ChipsetInit HECI message >=20 > + **/ >=20 > + UINT8 ChipsetInitMessage; >=20 > + /** >=20 > + (Test) >=20 > + 0- Disable >=20 > + 1- Enable When enabled, this is used to bypass the reset after Chipset= Init > HECI message. >=20 > + **/ >=20 > + UINT8 BypassPhySyncReset; >=20 > + UINT8 RsvdBytes[2]; >=20 > + >=20 > +} PCH_HSIO_PREMEM_CONFIG; >=20 > + >=20 > + >=20 > +/** >=20 > + The PCH_HSIO_CONFIG block provides HSIO message related settings. >=20 > +**/ >=20 > +typedef struct { >=20 > + CONFIG_BLOCK_HEADER Header; ///< Config Block Header >=20 > + /** >=20 > + Policy used to point to the Base (+ OEM) ChipsetInit binary used to = sync > between BIOS and CSME >=20 > + **/ >=20 > + UINT32 ChipsetInitBinPtr; >=20 > + /** >=20 > + Policy used to indicate the size of the Base (+ OEM) ChipsetInit bin= ary > used to sync between BIOS and CSME >=20 > + **/ >=20 > + UINT32 ChipsetInitBinLen; >=20 > +} PCH_HSIO_CONFIG; >=20 > + >=20 > +#pragma pack (pop) >=20 > + >=20 > +#endif // _HSIO_CONFIG_H_ >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/HsioPcieConfi= g.h > b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/HsioPcieConfi= g. > h > new file mode 100644 > index 0000000000..bc23f3e1a6 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/HsioPcieConfi= g. > h > @@ -0,0 +1,58 @@ > +/** @file >=20 > + HSIO pcie policy >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _HSIO_PCIE_CONFIG_H_ >=20 > +#define _HSIO_PCIE_CONFIG_H_ >=20 > + >=20 > +#include >=20 > + >=20 > +#define HSIO_PCIE_PREMEM_CONFIG_REVISION 1 >=20 > +extern EFI_GUID gHsioPciePreMemConfigGuid; >=20 > + >=20 > +#pragma pack (push,1) >=20 > + >=20 > +/** >=20 > + The PCH_HSIO_PCIE_LANE_CONFIG describes HSIO settings for PCIe lane >=20 > +**/ >=20 > +typedef struct { >=20 > + // >=20 > + // HSIO Rx Eq >=20 > + // Refer to the EDS for recommended values. >=20 > + // Note that these setting are per-lane and not per-port >=20 > + // >=20 > + UINT32 HsioRxSetCtleEnable : 1; ///< 0: Disable= ; 1: Enable > PCH PCIe Gen 3 Set CTLE Value >=20 > + UINT32 HsioRxSetCtle : 6; ///< PCH PCIe Gen 3 Se= t CTLE Value >=20 > + UINT32 HsioTxGen1DownscaleAmpEnable : 1; ///< 0: Disable= ; > 1: Enable PCH PCIe Gen 1 TX Output Downscale Amplitude Adjustment value > override >=20 > + UINT32 HsioTxGen1DownscaleAmp : 6; ///< PCH PCIe Gen 1 TX > Output Downscale Amplitude Adjustment value >=20 > + UINT32 HsioTxGen2DownscaleAmpEnable : 1; ///< 0: Disable= ; > 1: Enable PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value > override >=20 > + UINT32 HsioTxGen2DownscaleAmp : 6; ///< PCH PCIe Gen 2 TX > Output Downscale Amplitude Adjustment value >=20 > + UINT32 HsioTxGen3DownscaleAmpEnable : 1; ///< 0: Disable= ; > 1: Enable PCH PCIe Gen 3 TX Output Downscale Amplitude Adjustment value > override >=20 > + UINT32 HsioTxGen3DownscaleAmp : 6; ///< PCH PCIe Gen 3 TX > Output Downscale Amplitude Adjustment value >=20 > + UINT32 RsvdBits0 : 4; ///< Reserved Bits >=20 > + >=20 > + UINT32 HsioTxGen1DeEmphEnable : 1; ///< 0: Disable= ; 1: > Enable PCH PCIe Gen 1 TX Output De-Emphasis Adjustment Setting value > override >=20 > + UINT32 HsioTxGen1DeEmph : 6; ///< PCH PCIe Gen 1 TX= Output > De-Emphasis Adjustment Setting >=20 > + UINT32 HsioTxGen2DeEmph3p5Enable : 1; ///< 0: Disable= ; 1: > Enable PCH PCIe Gen 2 TX Output -3.5dB Mode De-Emphasis Adjustment > Setting value override >=20 > + UINT32 HsioTxGen2DeEmph3p5 : 6; ///< PCH PCIe Gen 2 TX= Output > -3.5dB Mode De-Emphasis Adjustment Setting >=20 > + UINT32 HsioTxGen2DeEmph6p0Enable : 1; ///< 0: Disable= ; 1: > Enable PCH PCIe Gen 2 TX Output -6.0dB Mode De-Emphasis Adjustment > Setting value override >=20 > + UINT32 HsioTxGen2DeEmph6p0 : 6; ///< PCH PCIe Gen 2 TX= Output > -6.0dB Mode De-Emphasis Adjustment Setting >=20 > + UINT32 RsvdBits1 : 11; ///< Reserved Bits >=20 > +} PCH_HSIO_PCIE_LANE_CONFIG; >=20 > + >=20 > +/// >=20 > +/// The PCH_HSIO_PCIE_CONFIG block describes the configuration of the > HSIO for PCIe lanes >=20 > +/// >=20 > +typedef struct { >=20 > + CONFIG_BLOCK_HEADER Header; ///< Config Block Head= er >=20 > + /// >=20 > + /// These members describe the configuration of HSIO for PCIe lanes. >=20 > + /// >=20 > + PCH_HSIO_PCIE_LANE_CONFIG Lane[PCH_MAX_PCIE_ROOT_PORTS]; >=20 > +} PCH_HSIO_PCIE_PREMEM_CONFIG; >=20 > + >=20 > +#pragma pack (pop) >=20 > + >=20 > +#endif // _HSIO_PCIE_LANE_CONFIG_H_ >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/HsioSataConfi= g. > h > b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/HsioSataConfi= g. > h > new file mode 100644 > index 0000000000..21b0d7ff63 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/HsioSataConfi= g. > h > @@ -0,0 +1,64 @@ > +/** @file >=20 > + Hsio Sata policy >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _HSIO_SATA_CONFIG_H_ >=20 > +#define _HSIO_SATA_CONFIG_H_ >=20 > + >=20 > +#define HSIO_SATA_PREMEM_CONFIG_REVISION 1 >=20 > +extern EFI_GUID gHsioSataPreMemConfigGuid; >=20 > + >=20 > +#pragma pack (push,1) >=20 > + >=20 > +/** >=20 > + The PCH_HSIO_SATA_PORT_LANE describes HSIO settings for SATA Port > lane >=20 > +**/ >=20 > +typedef struct { >=20 > + // >=20 > + // HSIO Rx Eq >=20 > + // >=20 > + UINT32 HsioRxGen1EqBoostMagEnable : 1; ///< 0: Disable= ; 1: > Enable Receiver Equalization Boost Magnitude Adjustment Value override >=20 > + UINT32 HsioRxGen1EqBoostMag : 6; ///< SATA 1.5 Gb/sRece= iver > Equalization Boost Magnitude Adjustment value >=20 > + UINT32 HsioRxGen2EqBoostMagEnable : 1; ///< 0: Disable= ; 1: > Enable Receiver Equalization Boost Magnitude Adjustment Value override >=20 > + UINT32 HsioRxGen2EqBoostMag : 6; ///< SATA 3.0 Gb/sRece= iver > Equalization Boost Magnitude Adjustment value >=20 > + UINT32 HsioRxGen3EqBoostMagEnable : 1; ///< 0: Disable= ; 1: > Enable Receiver Equalization Boost Magnitude Adjustment Value override >=20 > + UINT32 HsioRxGen3EqBoostMag : 6; ///< SATA 6.0 Gb/sRece= iver > Equalization Boost Magnitude Adjustment value >=20 > + // >=20 > + // HSIO Tx Eq >=20 > + // >=20 > + UINT32 HsioTxGen1DownscaleAmpEnable : 1; ///< 0: Disable= ; > 1: Enable SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value > override >=20 > + UINT32 HsioTxGen1DownscaleAmp : 6; ///< SATA 1.5 Gb/s TX > Output Downscale Amplitude Adjustment value >=20 > + UINT32 RsvdBits0 : 4; ///< Reserved bits >=20 > + >=20 > + UINT32 HsioTxGen2DownscaleAmpEnable : 1; ///< 0: Disable= ; > 1: Enable SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value > override >=20 > + UINT32 HsioTxGen2DownscaleAmp : 6; ///< SATA 3.0 Gb/s TX > Output Downscale Amplitude Adjustment >=20 > + UINT32 HsioTxGen3DownscaleAmpEnable : 1; ///< 0: Disable= ; > 1: Enable SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value > override >=20 > + UINT32 HsioTxGen3DownscaleAmp : 6; ///< SATA 6.0 Gb/s TX > Output Downscale Amplitude Adjustment >=20 > + UINT32 HsioTxGen1DeEmphEnable : 1; ///< 0: Disable= ; 1: > Enable SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting value > override >=20 > + UINT32 HsioTxGen1DeEmph : 6; ///< SATA 1.5 Gb/s TX = Output > De-Emphasis Adjustment Setting >=20 > + >=20 > + UINT32 HsioTxGen2DeEmphEnable : 1; ///< 0: Disable= ; 1: > Enable SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting value > override >=20 > + UINT32 HsioTxGen2DeEmph : 6; ///< SATA 3.0 Gb/s TX = Output > De-Emphasis Adjustment Setting >=20 > + UINT32 RsvdBits1 : 4; ///< Reserved bits >=20 > + >=20 > + UINT32 HsioTxGen3DeEmphEnable : 1; ///< 0: Disable= ; 1: > Enable SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting value > override >=20 > + UINT32 HsioTxGen3DeEmph : 6; ///< SATA 6.0 Gb/s TX = Output > De-Emphasis Adjustment Setting value override >=20 > + UINT32 RsvdBits2 : 25; ///< Reserved bits >=20 > +} PCH_HSIO_SATA_PORT_LANE; >=20 > + >=20 > +/// >=20 > +/// The PCH_HSIO_SATA_CONFIG block describes the HSIO configuration of > the SATA controller. >=20 > +/// >=20 > +typedef struct { >=20 > + CONFIG_BLOCK_HEADER Header; ///< Config Block Head= er >=20 > + /// >=20 > + /// These members describe the configuration of HSIO for SATA lanes. >=20 > + /// >=20 > + PCH_HSIO_SATA_PORT_LANE PortLane[PCH_MAX_SATA_PORTS]; >=20 > +} PCH_HSIO_SATA_PREMEM_CONFIG; >=20 > + >=20 > +#pragma pack (pop) >=20 > + >=20 > +#endif // _HSIO_SATA_CONFIG_H_ >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/LockDownConfi= g > .h > b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/LockDownConfi > g.h > new file mode 100644 > index 0000000000..23f116cf3d > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/LockDownConfi > g.h > @@ -0,0 +1,61 @@ > +/** @file >=20 > + Lock down policy >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _LOCK_DOWN_CONFIG_H_ >=20 > +#define _LOCK_DOWN_CONFIG_H_ >=20 > + >=20 > +#define LOCK_DOWN_CONFIG_REVISION 1 >=20 > +extern EFI_GUID gLockDownConfigGuid; >=20 > + >=20 > +#pragma pack (push,1) >=20 > + >=20 > +/** >=20 > + The PCH_LOCK_DOWN_CONFIG block describes the expected > configuration of the PCH >=20 > + for security requirement. >=20 > +**/ >=20 > +typedef struct { >=20 > + CONFIG_BLOCK_HEADER Header; ///< Config Block Head= er >=20 > + /** >=20 > + (Test) Enable SMI_LOCK bit to prevent writes to the Global SM= I > Enable bit. 0: Disable; 1: Enable. >=20 > + **/ >=20 > + UINT32 GlobalSmi : 1; >=20 > + /** >=20 > + (Test) Enable BIOS Interface Lock Down bit to prevent writes = to > the Backup Control Register >=20 > + Top Swap bit and the General Control and Status Registers Boot BIOS > Straps. >=20 > + Intel strongly recommends that BIOS sets the BIOS Interface Lock Dow= n > bit. Enabling this bit >=20 > + will mitigate malicious software attempts to replace the system BIOS= with > its own code. >=20 > + 0: Disable; 1: Enable. >=20 > + **/ >=20 > + UINT32 BiosInterface : 1; >=20 > + /** >=20 > + Enable the BIOS Lock Enable (BLE) feature and set EISS bit > (D31:F5:RegDCh[5]) >=20 > + for the BIOS region protection. When it is enabled, the BIOS Region = can > only be >=20 > + modified from SMM. >=20 > + If this EISS bit is set, then WPD must be a '1' and InSMM.STS must b= e '1' > also >=20 > + in order to write to BIOS regions of SPI Flash. If this EISS bit is = clear, >=20 > + then the InSMM.STS is a don't care. >=20 > + The BIOS must set the EISS bit while BIOS Guard support is enabled. >=20 > + In recovery path, platform can temporary disable EISS for SPI > programming in >=20 > + PEI phase or early DXE phase. >=20 > + When PcdSmmVariableEnable is FALSE, to support BIOS regions update > outside of SMM, >=20 > + the BiosLock must be set to Disabled by platform. >=20 > + 0: Disable; 1: Enable. >=20 > + **/ >=20 > + UINT32 BiosLock : 1; >=20 > + /** >=20 > + (Test) This test option when set will force all GPIO pads to = be > unlocked >=20 > + before BIOS transitions to POSTBOOT_SAI. This option should not be > enabled in production >=20 > + configuration and used only for debug purpose when free runtime > reconfiguration of >=20 > + GPIO pads is needed. >=20 > + 0: Disable; 1: Enable. >=20 > + **/ >=20 > + UINT32 UnlockGpioPads : 1; >=20 > + UINT32 RsvdBits0 : 28; ///< Reserved bits >=20 > +} PCH_LOCK_DOWN_CONFIG; >=20 > + >=20 > +#pragma pack (pop) >=20 > + >=20 > +#endif // _LOCK_DOWN_CONFIG_H_ >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/LpcConfig.h > b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/LpcConfig.h > new file mode 100644 > index 0000000000..3fc64aa056 > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/LpcConfig= .h > @@ -0,0 +1,38 @@ > +/** @file >=20 > + Lpc policy >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _LPC_CONFIG_H_ >=20 > +#define _LPC_CONFIG_H_ >=20 > + >=20 > +#define LPC_PREMEM_CONFIG_REVISION 1 >=20 > +extern EFI_GUID gLpcPreMemConfigGuid; >=20 > + >=20 > +#pragma pack (push,1) >=20 > + >=20 > +/** >=20 > + This structure contains the policies which are related to LPC. >=20 > +**/ >=20 > +typedef struct { >=20 > + CONFIG_BLOCK_HEADER Header; ///< Config Block Head= er >=20 > + /** >=20 > + Enhance the port 8xh decoding. >=20 > + Original LPC only decodes one byte of port 80h, with this enhancemen= t > LPC can decode word or dword of port 80h-83h. >=20 > + @note: this will occupy one LPC generic IO range register. While thi= s is > enabled, read from port 80h always return 0x00. >=20 > + 0: Disable, 1: Enable >=20 > + **/ >=20 > + UINT32 EnhancePort8xhDecoding : 1; >=20 > + /** >=20 > + Hardware Autonomous Enable. >=20 > + When enabled, LPC will automatically engage power gating when it has > reached its idle condition. >=20 > + 0: Disable, 1: Enable >=20 > + **/ >=20 > + UINT32 LpcPmHAE : 1; >=20 > + UINT32 RsvdBits : 30; ///< Reserved bits >=20 > +} PCH_LPC_PREMEM_CONFIG; >=20 > + >=20 > +#pragma pack (pop) >=20 > + >=20 > +#endif // _LPC_CONFIG_H_ >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/PchGeneralCon= f > ig.h > b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/PchGeneralCon= f > ig.h > new file mode 100644 > index 0000000000..da77abc1b3 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/PchGeneralCon= f > ig.h > @@ -0,0 +1,72 @@ > +/** @file >=20 > + PCH General policy >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _PCH_GENERAL_CONFIG_H_ >=20 > +#define _PCH_GENERAL_CONFIG_H_ >=20 > + >=20 > +#define PCH_GENERAL_CONFIG_REVISION 1 >=20 > +#define PCH_GENERAL_PREMEM_CONFIG_REVISION 2 >=20 > + >=20 > +extern EFI_GUID gPchGeneralConfigGuid; >=20 > +extern EFI_GUID gPchGeneralPreMemConfigGuid; >=20 > + >=20 > +#pragma pack (push,1) >=20 > + >=20 > +enum PCH_RESERVED_PAGE_ROUTE { >=20 > + PchReservedPageToLpc, ///< Port 80h cycles are sent = to LPC. >=20 > + PchReservedPageToPcie ///< Port 80h cycles are sent = to PCIe. >=20 > +}; >=20 > + >=20 > +/** >=20 > + PCH General Configuration >=20 > + Revision 1: - Initial version. >=20 > +**/ >=20 > +typedef struct { >=20 > + CONFIG_BLOCK_HEADER Header; ///< Config Block Head= er >=20 > + /** >=20 > + This member describes whether or not the Compatibility Revision ID > (CRID) feature >=20 > + of PCH should be enabled. 0: Disable; 1: Enable >=20 > + **/ >=20 > + UINT32 Crid : 1; >=20 > + /** >=20 > + Set to enable low latency of legacy IO. >=20 > + Some systems require lower IO latency irrespective of power. >=20 > + This is a tradeoff between power and IO latency. >=20 > + @note: Once this is enabled, DmiAspm, Pcie DmiAspm in SystemAgent >=20 > + and ITSS Clock Gating are forced to disabled. >=20 > + 0: Disable, 1: Enable >=20 > + **/ >=20 > + UINT32 LegacyIoLowLatency : 1; >=20 > + UINT32 RsvdBits0 : 30; ///< Reserved bits >=20 > +} PCH_GENERAL_CONFIG; >=20 > + >=20 > +/** >=20 > + PCH General Pre-Memory Configuration >=20 > + Revision 1: - Initial version. >=20 > + Revision 2: - Added GpioOverride. >=20 > +**/ >=20 > +typedef struct { >=20 > + CONFIG_BLOCK_HEADER Header; ///< Config Block Head= er >=20 > + /** >=20 > + Control where the Port 80h cycles are sent, 0: LPC; 1: PCI. >=20 > + **/ >=20 > + UINT32 Port80Route : 1; >=20 > + UINT32 IotgPllSscEn : 1; ///< Need to disable CPU Side SS= C for A0 PO >=20 > + /** >=20 > + Gpio override Level >=20 > + -- 0: Disable; >=20 > + - 1: Override Level 1 - only skips GpioSetNativePadByFunction >=20 > + - 2: Override Level 2 - skips GpioSetNativePadByFunction and > GpioSetPadMode >=20 > + Additional policy that allows GPIO configuration to be done by exter= nal > means. >=20 > + If equal to 1 PCH will skip every Pad configuration. >=20 > + **/ >=20 > + UINT32 GpioOverride : 3; >=20 > + UINT32 RsvdBits0 : 27; ///< Reserved bits >=20 > +} PCH_GENERAL_PREMEM_CONFIG; >=20 > + >=20 > +#pragma pack (pop) >=20 > + >=20 > +#endif // _PCH_GENERAL_CONFIG_H_ >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Library/PchCycleDecodingL= ib. > h > b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Library/PchCycleDecodingL= ib > .h > new file mode 100644 > index 0000000000..94509a80fe > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Library/PchCycleDecodingL= ib > .h > @@ -0,0 +1,258 @@ > +/** @file >=20 > + Header file for PchCycleDecodingLib. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _PCH_CYCLE_DECODING_LIB_H_ >=20 > +#define _PCH_CYCLE_DECODING_LIB_H_ >=20 > + >=20 > + >=20 > +/** >=20 > + Get PCH TCO base address. >=20 > + >=20 > + @param[out] Address Address of TCO base address. >=20 > + >=20 > + @retval EFI_SUCCESS Successfully completed. >=20 > + @retval EFI_INVALID_PARAMETER Invalid pointer passed. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +PchTcoBaseGet ( >=20 > + OUT UINT16 *Address >=20 > + ); >=20 > + >=20 > +/// >=20 > +/// structure of LPC general IO range register >=20 > +/// It contains base address, address mask, and enable status. >=20 > +/// >=20 > +typedef struct { >=20 > + UINT32 BaseAddr :16; >=20 > + UINT32 Length :15; >=20 > + UINT32 Enable : 1; >=20 > +} PCH_LPC_GEN_IO_RANGE; >=20 > + >=20 > +#define PCH_LPC_GEN_IO_RANGE_MAX 4 >=20 > +#define ESPI_CS1_GEN_IO_RANGE_MAX 1 >=20 > + >=20 > +/// >=20 > +/// structure of LPC general IO range register list >=20 > +/// It lists all LPC general IO ran registers supported by PCH. >=20 > +/// >=20 > +typedef struct { >=20 > + PCH_LPC_GEN_IO_RANGE > Range[PCH_LPC_GEN_IO_RANGE_MAX]; >=20 > +} PCH_LPC_GEN_IO_RANGE_LIST; >=20 > + >=20 > +/** >=20 > + Set PCH LPC/eSPI generic IO range. >=20 > + For generic IO range, the base address must align to 4 and less than > 0xFFFF, and the length must be power of 2 >=20 > + and less than or equal to 256. Moreover, the address must be length > aligned. >=20 > + This function basically checks the address and length, which should no= t > overlap with all other generic ranges. >=20 > + If no more generic range register available, it returns out of resourc= e error. >=20 > + This cycle decoding is also required on DMI side. >=20 > + Some IO ranges below 0x100 have fixed target. The target might be > ITSS,RTC,LPC,PMC or terminated inside P2SB >=20 > + but all predefined and can't be changed. IO range below 0x100 will be > rejected in this function except below ranges: >=20 > + 0x00-0x1F, >=20 > + 0x44-0x4B, >=20 > + 0x54-0x5F, >=20 > + 0x68-0x6F, >=20 > + 0x80-0x8F, >=20 > + 0xC0-0xFF >=20 > + Steps of programming generic IO range: >=20 > + 1. Program LPC/eSPI PCI Offset 84h ~ 93h of Mask, Address, and Enable. >=20 > + 2. Program LPC/eSPI Generic IO Range in DMI >=20 > + >=20 > + @param[in] Address Address for generic IO range bas= e address. >=20 > + @param[in] Length Length of generic IO range. >=20 > + >=20 > + @retval EFI_SUCCESS Successfully completed. >=20 > + @retval EFI_INVALID_PARAMETER Invalid base address or length > passed. >=20 > + @retval EFI_OUT_OF_RESOURCES No more generic range available. >=20 > + @retval EFI_UNSUPPORTED DMIC.SRL is set. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +PchLpcGenIoRangeSet ( >=20 > + IN UINT16 Address, >=20 > + IN UINTN Length >=20 > + ); >=20 > + >=20 > +/** >=20 > + Set PCH LPC/eSPI memory range decoding. >=20 > + This cycle decoding is required to be set on DMI side >=20 > + Programming steps: >=20 > + 1. Program LPC PCI Offset 98h [0] to [0] to disable memory decoding fi= rst > before changing base address. >=20 > + 2. Program LPC PCI Offset 98h [31:16, 0] to [Address, 1]. >=20 > + 3. Program LPC Memory Range in DMI >=20 > + >=20 > + @param[in] Address Address for memory base address. >=20 > + >=20 > + @retval EFI_SUCCESS Successfully completed. >=20 > + @retval EFI_INVALID_PARAMETER Invalid base address or length > passed. >=20 > + @retval EFI_OUT_OF_RESOURCES No more generic range available. >=20 > + @retval EFI_UNSUPPORTED DMIC.SRL is set. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +PchLpcMemRangeSet ( >=20 > + IN UINT32 Address >=20 > + ); >=20 > + >=20 > +/** >=20 > + Set PCH eSPI CS1# memory range decoding. >=20 > + This cycle decoding is required to be set on DMI side >=20 > + Programming steps: >=20 > + 1. Program eSPI PCI Offset A8h (eSPI CS1#) [0] to [0] to disable memor= y > decoding first before changing base address. >=20 > + 2. Program eSPI PCI Offset A8h (eSPI CS1#) [31:16, 0] to [Address, 1]. >=20 > + 3. Program eSPI Memory Range in DMI >=20 > + >=20 > + @param[in] Address Address for memory for decoding. >=20 > + >=20 > + @retval EFI_SUCCESS Successfully completed. >=20 > + @retval EFI_INVALID_PARAMETER Invalid base address or length > passed. >=20 > + @retval EFI_UNSUPPORTED eSPI secondary slave not support= ed >=20 > +**/ >=20 > +EFI_STATUS >=20 > +PchEspiCs1MemRangeSet ( >=20 > + IN UINT32 Address >=20 > + ); >=20 > + >=20 > +/** >=20 > + Get PCH LPC/eSPI memory range decoding address. >=20 > + >=20 > + @param[out] Address Address of LPC/eSPI memory decod= ing > base address. >=20 > + >=20 > + @retval EFI_SUCCESS Successfully completed. >=20 > + @retval EFI_INVALID_PARAMETER Invalid base address passed. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +PchLpcMemRangeGet ( >=20 > + OUT UINT32 *Address >=20 > + ); >=20 > + >=20 > +/** >=20 > + Get PCH eSPI CS1# memory range decoding address. >=20 > + >=20 > + @param[out] Address Address of eSPI CS1# memory deco= ding > base address. >=20 > + >=20 > + @retval EFI_SUCCESS Successfully completed. >=20 > + @retval EFI_INVALID_PARAMETER Invalid base address passed. >=20 > + @retval EFI_UNSUPPORTED eSPI secondary slave not support= ed >=20 > +**/ >=20 > +EFI_STATUS >=20 > +PchEspiCs1MemRangeGet ( >=20 > + OUT UINT32 *Address >=20 > + ); >=20 > + >=20 > +/** >=20 > + Set PCH BIOS range deocding. >=20 > + This will check General Control and Status bit 10 (GCS.BBS) to identif= y SPI > or LPC/eSPI and program BDE register accordingly. >=20 > + Please check EDS for detail of BiosDecodeEnable bit definition. >=20 > + bit 15: F8-FF Enable >=20 > + bit 14: F0-F8 Enable >=20 > + bit 13: E8-EF Enable >=20 > + bit 12: E0-E8 Enable >=20 > + bit 11: D8-DF Enable >=20 > + bit 10: D0-D7 Enable >=20 > + bit 9: C8-CF Enable >=20 > + bit 8: C0-C7 Enable >=20 > + bit 7: Legacy F Segment Enable >=20 > + bit 6: Legacy E Segment Enable >=20 > + bit 5: Reserved >=20 > + bit 4: Reserved >=20 > + bit 3: 70-7F Enable >=20 > + bit 2: 60-6F Enable >=20 > + bit 1: 50-5F Enable >=20 > + bit 0: 40-4F Enable >=20 > + This cycle decoding is allowed to set when DMIC.SRL is 0. >=20 > + Programming steps: >=20 > + 1. if GCS.BBS is 0 (SPI), program SPI PCI offset D8h to BiosDecodeEnab= le. >=20 > + if GCS.BBS is 1 (LPC/eSPi), program LPC/eSPI PCI offset D8h to > BiosDecodeEnable. >=20 > + 2. program LPC/eSPI/SPI BIOS Decode Enable, PCR[DMI] + 2744h to the > same value programmed in LPC/eSPI or SPI PCI Offset D8h. >=20 > + >=20 > + @param[in] BiosDecodeEnable Bios decode enable setting. >=20 > + >=20 > + @retval EFI_SUCCESS Successfully completed. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +PchBiosDecodeEnableSet ( >=20 > + IN UINT16 BiosDecodeEnable >=20 > + ); >=20 > + >=20 > +/** >=20 > + Set PCH LPC IO decode ranges. >=20 > + Program LPC I/O Decode Ranges, PCR[DMI] + 2770h[15:0] to the same > value programmed in LPC offset 80h. >=20 > + Please check EDS for detail of Lpc IO decode ranges bit definition. >=20 > + Bit 12: FDD range >=20 > + Bit 9:8: LPT range >=20 > + Bit 6:4: ComB range >=20 > + Bit 2:0: ComA range >=20 > + >=20 > + @param[in] LpcIoDecodeRanges Lpc IO decode ranges bit setting= s. >=20 > + >=20 > + @retval EFI_SUCCESS Successfully completed. >=20 > + @retval EFI_UNSUPPORTED DMIC.SRL is set. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +PchLpcIoDecodeRangesSet ( >=20 > + IN UINT16 LpcIoDecodeRanges >=20 > + ); >=20 > + >=20 > +/** >=20 > + Set PCH LPC and eSPI CS0# IO enable decoding. >=20 > + Setup I/O Enables in DMI to the same value program in LPC/eSPI PCI off= set > 82h. >=20 > + Note: Bit[15:10] of the source decode register is Read-Only. The IO ra= nge > indicated by the Enables field >=20 > + in LPC/eSPI PCI offset 82h[13:10] is always forwarded by DMI to > subtractive agent for handling. >=20 > + Please check EDS for detail of LPC/eSPI IO decode ranges bit definitio= n. >=20 > + >=20 > + @param[in] LpcIoEnableDecoding LPC IO enable decoding bit setti= ngs. >=20 > + >=20 > + @retval EFI_SUCCESS Successfully completed. >=20 > + @retval EFI_UNSUPPORTED DMIC.SRL is set. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +PchLpcIoEnableDecodingSet ( >=20 > + IN UINT16 LpcIoEnableDecoding >=20 > + ); >=20 > + >=20 > +/** >=20 > + Set PCH eSPI CS1# IO enable decoding. >=20 > + Setup I/O Enables in DMI to the same value program in eSPI PCI offset = A0h > (eSPI CS1#). >=20 > + Note: Bit[15:10] of the source decode register is Read-Only. The IO ra= nge > indicated by the Enables field >=20 > + in eSPI PCI offset A0h[13:10] is always forwarded by DMI to subtractiv= e > agent for handling. >=20 > + Please check EDS for detail of eSPI IO decode ranges bit definition. >=20 > + >=20 > + @param[in] IoEnableDecoding eSPI IO enable decoding bit sett= ings. >=20 > + >=20 > + @retval EFI_SUCCESS Successfully completed. >=20 > + @retval EFI_UNSUPPORTED DMI configuration is locked >=20 > +**/ >=20 > +EFI_STATUS >=20 > +PchEspiCs1IoEnableDecodingSet ( >=20 > + IN UINT16 IoEnableDecoding >=20 > + ); >=20 > + >=20 > +/** >=20 > + Get IO APIC regsiters base address. >=20 > + >=20 > + @param[out] IoApicBase Buffer of IO APIC regsiter addre= ss >=20 > + >=20 > + @retval EFI_SUCCESS Successfully completed. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +PchIoApicBaseGet ( >=20 > + OUT UINT32 *IoApicBase >=20 > + ); >=20 > + >=20 > +/** >=20 > + Get HPET base address. >=20 > + This function will be unavailable after P2SB is hidden by PSF. >=20 > + >=20 > + @param[out] HpetBase Buffer of HPET base address >=20 > + >=20 > + @retval EFI_SUCCESS Successfully completed. >=20 > + @retval EFI_INVALID_PARAMETER Invalid offset passed. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +PchHpetBaseGet ( >=20 > + OUT UINT32 *HpetBase >=20 > + ); >=20 > + >=20 > +#endif // _PCH_CYCLE_DECODING_LIB_H_ >=20 > diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Library/PchInf= oLib.h > b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Library/PchInfoLib.h > new file mode 100644 > index 0000000000..c8aee81a8b > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Library/PchInfoLib.h > @@ -0,0 +1,590 @@ > +/** @file >=20 > + Header file for PchInfoLib. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _PCH_INFO_LIB_H_ >=20 > +#define _PCH_INFO_LIB_H_ >=20 > + >=20 > +#include >=20 > +#include >=20 > + >=20 > +typedef UINT8 PCH_STEPPING; >=20 > + >=20 > +typedef UINT8 PCH_SERIES; >=20 > +#define PCH_LP 2 >=20 > + >=20 > +typedef UINT8 PCH_GENERATION; >=20 > +#define TGL_PCH 5 >=20 > + >=20 > +typedef enum { >=20 > + RstUnsupported =3D 0, >=20 > + RstPremium, >=20 > + RstOptane, >=20 > + RstMaxMode >=20 > +} RST_MODE; >=20 > + >=20 > +/** >=20 > + Return Pch stepping type >=20 > + >=20 > + @retval PCH_STEPPING Pch stepping type >=20 > +**/ >=20 > +PCH_STEPPING >=20 > +PchStepping ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Return Pch Series >=20 > + >=20 > + @retval PCH_SERIES Pch Series >=20 > +**/ >=20 > +PCH_SERIES >=20 > +PchSeries ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Return Pch Generation >=20 > + >=20 > + @retval PCH_GENERATION Pch Generation >=20 > +**/ >=20 > +PCH_GENERATION >=20 > +PchGeneration ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Check if this is TGL PCH generation >=20 > + >=20 > + @retval TRUE It's TGL PCH >=20 > + @retval FALSE It's not TGL PCH >=20 > +**/ >=20 > +BOOLEAN >=20 > +IsTglPch ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Get Pch Maximum Pcie Root Port Number >=20 > + >=20 > + @retval PcieMaxRootPort Pch Maximum Pcie Root Port Number >=20 > +**/ >=20 > +UINT8 >=20 > +GetPchMaxPciePortNum ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Get Pch Maximum Pcie Controller Number >=20 > + >=20 > + @retval Pch Maximum Pcie Controller Number >=20 > +**/ >=20 > +UINT8 >=20 > +GetPchMaxPcieControllerNum ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Get Pch Maximum Pcie Clock Number >=20 > + >=20 > + @retval Pch Maximum Pcie Clock Number >=20 > +**/ >=20 > +UINT8 >=20 > +GetPchMaxPcieClockNum ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Get Pch Maximum Pcie ClockReq Number >=20 > + >=20 > + @retval Pch Maximum Pcie ClockReq Number >=20 > +**/ >=20 > +UINT8 >=20 > +GetPchMaxPcieClockReqNum ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Get Pch Usb2 Maximum Physical Port Number >=20 > + >=20 > + @retval Pch Usb2 Maximum Physical Port Number >=20 > +**/ >=20 > +UINT8 >=20 > +GetPchUsb2MaxPhysicalPortNum ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Get Pch Maximum Usb2 Port Number of XHCI Controller >=20 > + >=20 > + @retval Pch Maximum Usb2 Port Number of XHCI Controller >=20 > +**/ >=20 > +UINT8 >=20 > +GetPchXhciMaxUsb2PortNum ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Get Pch Usb3 Maximum Physical Port Number >=20 > + >=20 > + @retval Pch Usb3 Maximum Physical Port Number >=20 > +**/ >=20 > +UINT8 >=20 > +GetPchUsb3MaxPhysicalPortNum ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Get Pch Maximum Usb3 Port Number of XHCI Controller >=20 > + >=20 > + @retval Pch Maximum Usb3 Port Number of XHCI Controller >=20 > +**/ >=20 > +UINT8 >=20 > +GetPchXhciMaxUsb3PortNum ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Get Pch Maximum Serial IO I2C controllers number >=20 > + >=20 > + @retval Pch Maximum Serial IO I2C controllers number >=20 > +**/ >=20 > +UINT8 >=20 > +GetPchMaxSerialIoI2cControllersNum ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Get Pch Maximum Serial IO SPI controllers number >=20 > + >=20 > + @retval Pch Maximum Serial IO SPI controllers number >=20 > +**/ >=20 > +UINT8 >=20 > +GetPchMaxSerialIoSpiControllersNum ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Get Pch Maximum Serial IO UART controllers number >=20 > + >=20 > + @retval Pch Maximum Serial IO UART controllers number >=20 > +**/ >=20 > +UINT8 >=20 > +GetPchMaxSerialIoUartControllersNum ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Get Pch Maximum Serial IO SPI Chip Selects count >=20 > + >=20 > + @retval Pch Maximum Serial IO SPI Chip Selects nu,ber >=20 > +**/ >=20 > +UINT8 >=20 > +GetPchMaxSerialIoSpiChipSelectsNum ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Get Pch Maximum ISH UART Controller number >=20 > + >=20 > + @retval Pch Maximum ISH UART controllers number >=20 > +**/ >=20 > +UINT8 >=20 > +GetPchMaxIshUartControllersNum ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Get Pch Maximum ISH I2C Controller number >=20 > + >=20 > + @retval Pch Maximum ISH I2C controllers number >=20 > +**/ >=20 > +UINT8 >=20 > +GetPchMaxIshI2cControllersNum ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Get Pch Maximum ISH I3C Controller number >=20 > + >=20 > + @retval Pch Maximum ISH I3C controllers number >=20 > +**/ >=20 > +UINT8 >=20 > +GetPchMaxIshI3cControllersNum ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Get Pch Maximum ISH SPI Controller number >=20 > + >=20 > + @retval Pch Maximum ISH SPI controllers number >=20 > +**/ >=20 > +UINT8 >=20 > +GetPchMaxIshSpiControllersNum ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Get Pch Maximum ISH SPI Controller Cs pins number >=20 > + >=20 > + @retval Pch Maximum ISH SPI controller Cs pins number >=20 > +**/ >=20 > +UINT8 >=20 > +GetPchMaxIshSpiControllerCsPinsNum ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Get Pch Maximum ISH GP number >=20 > + >=20 > + @retval Pch Maximum ISH GP number >=20 > +**/ >=20 > +UINT8 >=20 > +GetPchMaxIshGpNum ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Get Pch Maximum ME Applet count >=20 > + >=20 > + @retval Pch Maximum ME Applet number >=20 > +**/ >=20 > +UINT8 >=20 > +GetPchMaxMeAppletCount ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > +Get Pch Maximum ME Session count >=20 > + >=20 > +@retval Pch Maximum ME Sesion number >=20 > +**/ >=20 > +UINT8 >=20 > +GetPchMaxMeSessionCount( >=20 > + VOID >=20 > +); >=20 > + >=20 > +/** >=20 > + Get Pch Maximum Type C Port Number >=20 > + >=20 > + @retval Pch Maximum Type C Port Number >=20 > +**/ >=20 > +UINT8 >=20 > +GetPchMaxTypeCPortNum ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +#define PCH_STEPPING_STR_LENGTH_MAX 3 >=20 > + >=20 > +/** >=20 > + Get PCH stepping ASCII string. >=20 > + Function determines major and minor stepping versions and writes them > into a buffer. >=20 > + The return string is zero terminated >=20 > + >=20 > + @param [out] Buffer Output buffer of string >=20 > + @param [in] BufferSize Buffer size. >=20 > + Must not be less then > PCH_STEPPING_STR_LENGTH_MAX >=20 > + >=20 > + @retval EFI_SUCCESS String copied successfully >=20 > + @retval EFI_INVALID_PARAMETER The stepping is not supported, o= r > parameters are NULL >=20 > + @retval EFI_BUFFER_TOO_SMALL Input buffer size is too small >=20 > +**/ >=20 > +EFI_STATUS >=20 > +PchGetSteppingStr ( >=20 > + OUT CHAR8 *Buffer, >=20 > + IN UINT32 BufferSize >=20 > + ); >=20 > + >=20 > +/** >=20 > + Get PCH series ASCII string. >=20 > + The return string is zero terminated. >=20 > + >=20 > + @retval Static ASCII string of PCH Series >=20 > +**/ >=20 > +CHAR8* >=20 > +PchGetSeriesStr ( >=20 > + ); >=20 > + >=20 > +/** >=20 > + Check if this chipset supports eMMC controller >=20 > + >=20 > + @retval BOOLEAN TRUE if supported, FALSE otherwise >=20 > +**/ >=20 > +BOOLEAN >=20 > +IsPchEmmcSupported ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Check if this chipset supports SD controller >=20 > + >=20 > + @retval BOOLEAN TRUE if supported, FALSE otherwise >=20 > +**/ >=20 > +BOOLEAN >=20 > +IsPchSdCardSupported ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Check if this chipset supports THC controller >=20 > + >=20 > + @retval BOOLEAN TRUE if supported, FALSE otherwise >=20 > +**/ >=20 > +BOOLEAN >=20 > +IsPchThcSupported ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Check if this chipset supports HSIO BIOS Sync >=20 > + >=20 > + @retval BOOLEAN TRUE if supported, FALSE otherwise >=20 > +**/ >=20 > +BOOLEAN >=20 > +IsPchChipsetInitSyncSupported ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Gets the maximum number of UFS controller supported by this chipset. >=20 > + >=20 > + @return Number of supported UFS controllers >=20 > +**/ >=20 > +UINT8 >=20 > +PchGetMaxUfsNum ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Check whether integrated LAN controller is supported. >=20 > + >=20 > + @retval TRUE GbE is supported in PCH >=20 > + @retval FALSE GbE is not supported by PCH >=20 > +**/ >=20 > +BOOLEAN >=20 > +PchIsGbeSupported ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Check whether integrated TSN is supported. >=20 > + >=20 > + @retval TRUE TSN is supported in current PCH >=20 > + @retval FALSE TSN is not supported on current PCH >=20 > +**/ >=20 > +BOOLEAN >=20 > +PchIsTsnSupported ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Check whether ISH is supported. >=20 > + >=20 > + @retval TRUE ISH is supported in PCH >=20 > + @retval FALSE ISH is not supported by PCH >=20 > +**/ >=20 > +BOOLEAN >=20 > +PchIsIshSupported ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Check whether ATX Shutdown (PS_ON) is supported. >=20 > + >=20 > + @retval TRUE ATX Shutdown (PS_ON) is supported in PCH >=20 > + @retval FALSE ATX Shutdown (PS_ON) is not supported by PCH >=20 > +**/ >=20 > +BOOLEAN >=20 > +IsPchPSOnSupported ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Get Pch Maximum Hda Sndw Link >=20 > + >=20 > + @retval Pch Maximum Hda Sndw Link >=20 > +**/ >=20 > +UINT8 >=20 > +GetPchHdaMaxSndwLinkNum ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Get Pch Maximum Hda Ssp Link >=20 > + >=20 > + @retval Pch Maximum Hda Ssp Link >=20 > +**/ >=20 > +UINT8 >=20 > +GetPchHdaMaxSspLinkNum ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Get Pch Maximum Hda Dmic Link >=20 > + >=20 > + @retval Pch Maximum Hda Dmic Link >=20 > +**/ >=20 > +UINT8 >=20 > +GetPchHdaMaxDmicLinkNum ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Check if given Audio Interface is supported >=20 > + >=20 > + @param[in] AudioLinkType Link type support to be checked >=20 > + @param[in] AudioLinkIndex Link number >=20 > + >=20 > + @retval TRUE Link supported >=20 > + @retval FALSE Link not supported >=20 > +**/ >=20 > +BOOLEAN >=20 > +IsAudioInterfaceSupported ( >=20 > + IN HDAUDIO_LINK_TYPE AudioLinkType, >=20 > + IN UINT32 AudioLinkIndex >=20 > + ); >=20 > + >=20 > +/** >=20 > + Check if given Display Audio Link T-Mode is supported >=20 > + >=20 > + @param[in] Tmode T-mode support to be checked >=20 > + >=20 > + @retval TRUE T-mode supported >=20 > + @retval FALSE T-mode not supported >=20 > +**/ >=20 > +BOOLEAN >=20 > +IsAudioIDispTmodeSupported ( >=20 > + IN HDAUDIO_IDISP_TMODE Tmode >=20 > + ); >=20 > + >=20 > +/** >=20 > + Check if link between PCH and CPU is an P-DMI >=20 > + >=20 > + @retval TRUE P-DMI link >=20 > + @retval FALSE Not an P-DMI link >=20 > +**/ >=20 > +BOOLEAN >=20 > +IsPchWithPdmi ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Check if link between PCH and CPU is an OP-DMI >=20 > + >=20 > + @retval TRUE OP-DMI link >=20 > + @retval FALSE Not an OP-DMI link >=20 > +**/ >=20 > +BOOLEAN >=20 > +IsPchWithOpdmi ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Check if link between PCH and CPU is an F-DMI >=20 > + >=20 > + @retval TRUE F-DMI link >=20 > + @retval FALSE Not an F-DMI link >=20 > +**/ >=20 > +BOOLEAN >=20 > +IsPchWithFdmi ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Get Pch Maximum THC count >=20 > + >=20 > + @retval Pch Maximum THC count number >=20 > +**/ >=20 > +UINT8 >=20 > +GetPchMaxThcCount ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +typedef enum { >=20 > + SataSosc125Mhz =3D 0, >=20 > + SataSosc120Mhz, >=20 > + SataSosc100Mhz, >=20 > + SataSosc25Mhz, >=20 > + SataSosc19p2Mhz, >=20 > + SataSoscUnsupported >=20 > +} SATA_SOSC_CLK_FREQ; >=20 > + >=20 > +/** >=20 > + Returns a frequency of the sosc_clk signal. >=20 > + All SATA controllers on the system are assumed to >=20 > + work on the same sosc_clk frequency. >=20 > + >=20 > + @retval Frequency of the sosc_clk signal. >=20 > +**/ >=20 > +SATA_SOSC_CLK_FREQ >=20 > +GetSataSoscClkFreq ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Check if SATA support should be awake after function disable >=20 > + >=20 > + @retval TRUE >=20 > + @retval FALSE >=20 > +**/ >=20 > +BOOLEAN >=20 > +IsSataSupportWakeAfterFunctionDisable ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > + >=20 > +// >=20 > +// USB2 PHY reference frequencies values (MHz) >=20 > +// >=20 > +typedef enum { >=20 > + FREQ_19_2 =3D 0u, >=20 > + FREQ_24_0, >=20 > + FREQ_96_0, >=20 > + FREQ_MAX >=20 > +} USB2_PHY_REF_FREQ; >=20 > + >=20 > +/** >=20 > + Returns USB2 PHY Reference Clock frequency value used by PCH >=20 > + This defines what electrical tuning parameters shall be used >=20 > + during USB2 PHY initialization programming >=20 > + >=20 > + @retval Frequency reference clock for USB2 PHY >=20 > +**/ >=20 > +USB2_PHY_REF_FREQ >=20 > +GetUsb2PhyRefFreq ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + return support status for P2SB PCR 20-bit addressing >=20 > + >=20 > + @retval TRUE >=20 > + @retval FALSE >=20 > +**/ >=20 > +BOOLEAN >=20 > +IsP2sb20bPcrSupported ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Check if SPI in a given PCH generation supports an Extended BIOS Range > Decode >=20 > + >=20 > + @retval TRUE or FALSE if PCH supports Extended BIOS Range Decode >=20 > +**/ >=20 > +BOOLEAN >=20 > +IsExtendedBiosRangeDecodeSupported ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Returns DMI target for current PCH SPI >=20 > + >=20 > + @retval PCH SPI DMI target >=20 > +**/ >=20 > +UINT16 >=20 > +GetPchSpiDmiTarget ( >=20 > + VOID >=20 > + ); >=20 > +#endif // _PCH_INFO_LIB_H_ >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Library/PchPciBdfLib.h > b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Library/PchPciBdfLib.h > new file mode 100644 > index 0000000000..85456653de > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Library/PchPciBdfLib.= h > @@ -0,0 +1,552 @@ > +/** @file >=20 > + Header file for PchPciBdfLib. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _PCH_PCI_BDF_LIB_H_ >=20 > +#define _PCH_PCI_BDF_LIB_H_ >=20 > + >=20 > + >=20 > +/** >=20 > + Get eSPI controller address that can be passed to the PCI Segment Libr= ary > functions. >=20 > + >=20 > + @retval eSPI controller address in PCI Segment Library representation >=20 > +**/ >=20 > +UINT64 >=20 > +EspiPciCfgBase ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Get GbE controller address that can be passed to the PCI Segment Libra= ry > functions. >=20 > + >=20 > + @retval GbE controller address in PCI Segment Library representation >=20 > +**/ >=20 > +UINT64 >=20 > +GbePciCfgBase ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Returns Gigabit Ethernet PCI Device Number >=20 > + >=20 > + @retval GbE device number >=20 > +**/ >=20 > +UINT8 >=20 > +GbeDevNumber ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Returns Gigabit Ethernet PCI Function Number >=20 > + >=20 > + @retval GbE function number >=20 > +**/ >=20 > +UINT8 >=20 > +GbeFuncNumber ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Get HDA controller address that can be passed to the PCI Segment Libra= ry > functions. >=20 > + >=20 > + @retval HDA controller address in PCI Segment Library representation >=20 > +**/ >=20 > +UINT64 >=20 > +HdaPciCfgBase ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Get HDA PCI device number >=20 > + >=20 > + @retval PCI dev number >=20 > +**/ >=20 > +UINT8 >=20 > +HdaDevNumber ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Get HDA PCI function number >=20 > + >=20 > + @retval PCI fun number >=20 > +**/ >=20 > +UINT8 >=20 > +HdaFuncNumber ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > + >=20 > +/** >=20 > + Get P2SB controller address that can be passed to the PCI Segment Libr= ary > functions. >=20 > + >=20 > + @retval P2SB controller address in PCI Segment Library representation >=20 > +**/ >=20 > +UINT64 >=20 > +P2sbPciCfgBase ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Get P2SB PCI device number >=20 > + >=20 > + @retval PCI dev number >=20 > +**/ >=20 > +UINT8 >=20 > +P2sbDevNumber ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Returns SPI PCI Config Space base address >=20 > + >=20 > + @retval UINT64 SPI Config Space base address >=20 > +**/ >=20 > +UINT64 >=20 > +SpiPciCfgBase ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Returns SPI Device number >=20 > + >=20 > + @retval UINT8 PCH SPI Device number >=20 > +**/ >=20 > +UINT8 >=20 > +SpiDevNumber ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Returns SPI Function number >=20 > + >=20 > + @retval UINT8 PCH SPI Function number >=20 > +**/ >=20 > +UINT8 >=20 > +SpiFuncNumber ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Get XHCI controller address that can be passed to the PCI Segment Libr= ary > functions. >=20 > + >=20 > + @retval XHCI controller address in PCI Segment Library representation >=20 > +**/ >=20 > +UINT64 >=20 > +PchXhciPciCfgBase ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Get XHCI controller PCIe Device Number >=20 > + >=20 > + @retval XHCI controller PCIe Device Number >=20 > +**/ >=20 > +UINT8 >=20 > +PchXhciDevNumber ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Get XHCI controller PCIe Function Number >=20 > + >=20 > + @retval XHCI controller PCIe Function Number >=20 > +**/ >=20 > +UINT8 >=20 > +PchXhciFuncNumber ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Get XDCI controller address that can be passed to the PCI Segment Libr= ary > functions. >=20 > + >=20 > + @retval XDCI controller address in PCI Segment Library representation >=20 > +**/ >=20 > +UINT64 >=20 > +PchXdciPciCfgBase ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Get XDCI controller PCIe Device Number >=20 > + >=20 > + @retval XDCI controller PCIe Device Number >=20 > +**/ >=20 > +UINT8 >=20 > +PchXdciDevNumber ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Get XDCI controller PCIe Function Number >=20 > + >=20 > + @retval XDCI controller PCIe Function Number >=20 > +**/ >=20 > +UINT8 >=20 > +PchXdciFuncNumber ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Get SMBUS controller address that can be passed to the PCI Segment > Library functions. >=20 > + >=20 > + @retval SMBUS controller address in PCI Segment Library representation >=20 > +**/ >=20 > +UINT64 >=20 > +SmbusPciCfgBase ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Return DMA Smbus Device Number >=20 > + >=20 > + @retval DMA Smbus Device Number >=20 > +**/ >=20 > +UINT8 >=20 > +SmbusDmaDevNumber ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Return DMA Smbus Function Number >=20 > + >=20 > + @retval DMA Smbus Function Number >=20 > +**/ >=20 > +UINT8 >=20 > +SmbusDmaFuncNumber ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Get DMA SMBUS controller address that can be passed to the PCI Segment > Library functions. >=20 > + >=20 > + @retval DMA SMBUS controller address in PCI Segment Library > representation >=20 > +**/ >=20 > +UINT64 >=20 > +SmbusDmaPciCfgBase ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Return Smbus Device Number >=20 > + >=20 > + @retval Smbus Device Number >=20 > +**/ >=20 > +UINT8 >=20 > +SmbusDevNumber ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Return Smbus Function Number >=20 > + >=20 > + @retval Smbus Function Number >=20 > +**/ >=20 > +UINT8 >=20 > +SmbusFuncNumber ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Gets SATA controller PCIe config space base address >=20 > + >=20 > + @param[in] SataCtrlIndex SATA controller index >=20 > + >=20 > + @retval SATA controller PCIe config space base address >=20 > +**/ >=20 > +UINT64 >=20 > +SataPciCfgBase ( >=20 > + IN UINT32 SataCtrlIndex >=20 > + ); >=20 > + >=20 > +/** >=20 > + Gets SATA controller PCIe Device Number >=20 > + >=20 > + @param[in] SataCtrlIndex SATA controller index >=20 > + >=20 > + @retval SATA controller PCIe Device Number >=20 > +**/ >=20 > +UINT8 >=20 > +SataDevNumber ( >=20 > + IN UINT32 SataCtrlIndex >=20 > + ); >=20 > + >=20 > +/** >=20 > + Gets SATA controller PCIe Function Number >=20 > + >=20 > + @param[in] SataCtrlIndex SATA controller index >=20 > + >=20 > + @retval SATA controller PCIe Function Number >=20 > +**/ >=20 > +UINT8 >=20 > +SataFuncNumber ( >=20 > + IN UINT32 SataCtrlIndex >=20 > + ); >=20 > + >=20 > +/** >=20 > + Returns PCH LPC device PCI base address. >=20 > + >=20 > + @retval PCH LPC PCI base address. >=20 > +**/ >=20 > +UINT64 >=20 > +LpcPciCfgBase ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Get LPC controller PCIe Device Number >=20 > + >=20 > + @retval LPC controller PCIe Device Number >=20 > +**/ >=20 > +UINT8 >=20 > +LpcDevNumber ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Get Thermal Device PCIe Device Number >=20 > + >=20 > + @retval Thermal Device PCIe Device Number >=20 > +**/ >=20 > +UINT8 >=20 > +ThermalDevNumber ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Get Thermal Device PCIe Function Number >=20 > + >=20 > + @retval Thermal Device PCIe Function Number >=20 > +**/ >=20 > +UINT8 >=20 > +ThermalFuncNumber ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Returns Thermal Device PCI base address. >=20 > + >=20 > + @retval Thermal Device PCI base address. >=20 > +**/ >=20 > +UINT64 >=20 > +ThermalPciCfgBase ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Get LPC controller PCIe Function Number >=20 > + >=20 > + @retval LPC controller PCIe Function Number >=20 > +**/ >=20 > +UINT8 >=20 > +LpcFuncNumber ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Get Serial IO I2C controller PCIe Device Number >=20 > + >=20 > + @param[in] I2cNumber Serial IO I2C controller index >=20 > + >=20 > + @retval Serial IO I2C controller PCIe Device Number >=20 > +**/ >=20 > +UINT8 >=20 > +SerialIoI2cDevNumber ( >=20 > + IN UINT8 I2cNumber >=20 > + ); >=20 > + >=20 > +/** >=20 > + Get Serial IO I2C controller PCIe Function Number >=20 > + >=20 > + @param[in] I2cNumber Serial IO I2C controller index >=20 > + >=20 > + @retval Serial IO I2C controller PCIe Function Number >=20 > +**/ >=20 > +UINT8 >=20 > +SerialIoI2cFuncNumber ( >=20 > + IN UINT8 I2cNumber >=20 > + ); >=20 > + >=20 > +/** >=20 > + Get Serial IO I2C controller address that can be passed to the PCI Seg= ment > Library functions. >=20 > + >=20 > + @param[in] I2cNumber Serial IO I2C controller index >=20 > + >=20 > + @retval Serial IO I2C controller address in PCI Segment Library > representation >=20 > +**/ >=20 > +UINT64 >=20 > +SerialIoI2cPciCfgBase ( >=20 > + IN UINT8 I2cNumber >=20 > + ); >=20 > + >=20 > +/** >=20 > + Get Serial IO SPI controller PCIe Device Number >=20 > + >=20 > + @param[in] I2cNumber Serial IO SPI controller index >=20 > + >=20 > + @retval Serial IO SPI controller PCIe Device Number >=20 > +**/ >=20 > +UINT8 >=20 > +SerialIoSpiDevNumber ( >=20 > + IN UINT8 SpiNumber >=20 > + ); >=20 > + >=20 > +/** >=20 > + Get Serial IO SPI controller PCIe Function Number >=20 > + >=20 > + @param[in] SpiNumber Serial IO SPI controller index >=20 > + >=20 > + @retval Serial IO SPI controller PCIe Function Number >=20 > +**/ >=20 > +UINT8 >=20 > +SerialIoSpiFuncNumber ( >=20 > + IN UINT8 SpiNumber >=20 > + ); >=20 > + >=20 > +/** >=20 > + Get Serial IO SPI controller address that can be passed to the PCI Seg= ment > Library functions. >=20 > + >=20 > + @param[in] SpiNumber Serial IO SPI controller index >=20 > + >=20 > + @retval Serial IO SPI controller address in PCI Segment Library > representation >=20 > +**/ >=20 > +UINT64 >=20 > +SerialIoSpiPciCfgBase ( >=20 > + IN UINT8 SpiNumber >=20 > + ); >=20 > + >=20 > +/** >=20 > + Get Serial IO UART controller PCIe Device Number >=20 > + >=20 > + @param[in] UartNumber Serial IO UART controller index >=20 > + >=20 > + @retval Serial IO UART controller PCIe Device Number >=20 > +**/ >=20 > +UINT8 >=20 > +SerialIoUartDevNumber ( >=20 > + IN UINT8 UartNumber >=20 > + ); >=20 > + >=20 > +/** >=20 > + Get Serial IO UART controller PCIe Function Number >=20 > + >=20 > + @param[in] UartNumber Serial IO UART controller index >=20 > + >=20 > + @retval Serial IO UART controller PCIe Function Number >=20 > +**/ >=20 > +UINT8 >=20 > +SerialIoUartFuncNumber ( >=20 > + IN UINT8 UartNumber >=20 > + ); >=20 > + >=20 > +/** >=20 > + Get Serial IO UART controller address that can be passed to the PCI > Segment Library functions. >=20 > + >=20 > + @param[in] UartNumber Serial IO UART controller index >=20 > + >=20 > + @retval Serial IO UART controller address in PCI Segment Library > representation >=20 > +**/ >=20 > +UINT64 >=20 > +SerialIoUartPciCfgBase ( >=20 > + IN UINT8 UartNumber >=20 > + ); >=20 > + >=20 > +/** >=20 > + Get PCH PCIe controller PCIe Device Number >=20 > + >=20 > + @param[in] RpIndex Root port physical number. (0-based) >=20 > + >=20 > + @retval PCH PCIe controller PCIe Device Number >=20 > +**/ >=20 > +UINT8 >=20 > +PchPcieRpDevNumber ( >=20 > + IN UINTN RpIndex >=20 > + ); >=20 > + >=20 > +/** >=20 > + Get PCH PCIe controller PCIe Function Number >=20 > + >=20 > + @param[in] RpIndex Root port physical number. (0-based) >=20 > + >=20 > + @retval PCH PCIe controller PCIe Function Number >=20 > +**/ >=20 > +UINT8 >=20 > +PchPcieRpFuncNumber ( >=20 > + IN UINTN RpIndex >=20 > + ); >=20 > + >=20 > +/** >=20 > + Get PCH PCIe controller address that can be passed to the PCI Segment > Library functions. >=20 > + >=20 > + @param[in] RpIndex PCH PCIe Root Port physical number. (0-based= ) >=20 > + >=20 > + @retval PCH PCIe controller address in PCI Segment Library representat= ion >=20 > +**/ >=20 > +UINT64 >=20 > +PchPcieRpPciCfgBase ( >=20 > + IN UINT32 RpIndex >=20 > + ); >=20 > + >=20 > +/** >=20 > + Get HECI1 PCI device number >=20 > + >=20 > + @retval PCI dev number >=20 > +**/ >=20 > +UINT8 >=20 > +PchHeci1DevNumber ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Get HECI1 PCI function number >=20 > + >=20 > + @retval PCI fun number >=20 > +**/ >=20 > +UINT8 >=20 > +PchHeci1FuncNumber ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Get HECI1 controller address that can be passed to the PCI Segment Lib= rary > functions. >=20 > + >=20 > + @retval HECI1 controller address in PCI Segment Library representation >=20 > +**/ >=20 > +UINT64 >=20 > +PchHeci1PciCfgBase ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Get HECI3 PCI device number >=20 > + >=20 > + @retval PCI dev number >=20 > +**/ >=20 > +UINT8 >=20 > +PchHeci3DevNumber ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Get HECI3 PCI function number >=20 > + >=20 > + @retval PCI fun number >=20 > +**/ >=20 > +UINT8 >=20 > +PchHeci3FuncNumber ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Get HECI3 controller address that can be passed to the PCI Segment Lib= rary > functions. >=20 > + >=20 > + @retval HECI3 controller address in PCI Segment Library representation >=20 > +**/ >=20 > +UINT64 >=20 > +PchHeci3PciCfgBase ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +#endif //_PCH_PCI_BDF_LIB_H_ >=20 > diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/PchInfoHob.h > b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/PchInfoHob.h > new file mode 100644 > index 0000000000..845bb19a65 > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/PchInfoHob.h > @@ -0,0 +1,70 @@ > +/** @file >=20 > + This file contains definitions of PCH Info HOB. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _PCH_INFO_HOB_H_ >=20 > +#define _PCH_INFO_HOB_H_ >=20 > + >=20 > +extern EFI_GUID gPchInfoHobGuid; >=20 > + >=20 > +#define PCH_INFO_HOB_REVISION 4 >=20 > + >=20 > +#pragma pack (push,1) >=20 > +/** >=20 > + This structure is used to provide the information of PCH controller. >=20 > + >=20 > + Revision 1: >=20 > + - Initial version. >=20 > + Revision 2: >=20 > + - Add CridSupport, CridOrgRid, and CridNewRid. >=20 > + Revision 3: >=20 > + - Add Thc0Strap. >=20 > + Revision 4 >=20 > + - Removed GbePciePortNumber >=20 > +**/ >=20 > +typedef struct { >=20 > + /** >=20 > + This member specifies the revision of the PCH Info HOB. This field i= s used >=20 > + to indicate backwards compatible changes to the protocol. Platform c= ode > that >=20 > + consumes this protocol must read the correct revision value to corre= ctly > interpret >=20 > + the content of the protocol fields. >=20 > + **/ >=20 > + UINT8 Revision; >=20 > + UINT8 PcieControllerCfg[6]; >=20 > + /** >=20 > + THC strap disable/enable status >=20 > + **/ >=20 > + UINT8 Thc0Strap; >=20 > + UINT32 PciePortFuses; >=20 > + /** >=20 > + Bit map for PCIe Root Port Lane setting. If bit is set it means that >=20 > + corresponding Root Port has its lane enabled. >=20 > + BIT0 - RP0, BIT1 - RP1, ... >=20 > + This information needs to be passed through HOB as FIA registers >=20 > + are not accessible with POSTBOOT_SAI >=20 > + **/ >=20 > + UINT32 PciePortLaneEnabled; >=20 > + /** >=20 > + Publish Hpet BDF and IoApic BDF information for VTD. >=20 > + **/ >=20 > + UINT32 HpetBusNum : 8; >=20 > + UINT32 HpetDevNum : 5; >=20 > + UINT32 HpetFuncNum : 3; >=20 > + UINT32 IoApicBusNum : 8; >=20 > + UINT32 IoApicDevNum : 5; >=20 > + UINT32 IoApicFuncNum : 3; >=20 > + /** >=20 > + Publish the CRID information. >=20 > + **/ >=20 > + UINT32 CridOrgRid : 8; >=20 > + UINT32 CridNewRid : 8; >=20 > + UINT32 CridSupport : 1; >=20 > + UINT32 Rsvdbits : 15; >=20 > +} PCH_INFO_HOB; >=20 > + >=20 > +#pragma pack (pop) >=20 > + >=20 > +#endif // _PCH_INFO_HOB_H_ >=20 > + >=20 > diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/PchLimits.h > b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/PchLimits.h > new file mode 100644 > index 0000000000..04ad17c8bd > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/PchLimits.h > @@ -0,0 +1,67 @@ > +/** @file >=20 > + Build time limits of PCH resources. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _PCH_LIMITS_H_ >=20 > +#define _PCH_LIMITS_H_ >=20 > +/* >=20 > + * Defines povided in this file are indended to be used only where stati= c > value >=20 > + * is needed. They are set to values which allow to accomodate multiple > projects >=20 > + * needs. Where runtime usage is possible please used dedicated function= s > from >=20 > + * PchInfoLib to retrieve accurate values >=20 > + */ >=20 > + >=20 > +// >=20 > +// PCIe limits >=20 > +// >=20 > +#define PCH_MAX_PCIE_ROOT_PORTS 24 >=20 > +#define PCH_MAX_PCIE_CONTROLLERS 6 >=20 > + >=20 > +// >=20 > +// PCIe clocks limits >=20 > +// >=20 > +#define PCH_MAX_PCIE_CLOCKS 16 >=20 > + >=20 > +// >=20 > +// RST PCIe Storage Cycle Router limits >=20 > +// >=20 > +#define PCH_MAX_RST_PCIE_STORAGE_CR 3 >=20 > + >=20 > +// >=20 > +// SATA limits >=20 > +// >=20 > +#define PCH_MAX_SATA_CONTROLLERS 3 >=20 > +#define PCH_MAX_SATA_PORTS 8 >=20 > + >=20 > +// >=20 > +// SerialIo limits >=20 > +// >=20 > +#define PCH_MAX_SERIALIO_I2C_CONTROLLERS 8 >=20 > +#define PCH_MAX_SERIALIO_SPI_CONTROLLERS 7 >=20 > +#define PCH_MAX_SERIALIO_SPI_CHIP_SELECTS 2 >=20 > +#define PCH_MAX_SERIALIO_UART_CONTROLLERS 7 >=20 > + >=20 > +// >=20 > +// ISH limits >=20 > +// >=20 > +#define PCH_MAX_ISH_GP_PINS 8 >=20 > +#define PCH_MAX_ISH_UART_CONTROLLERS 2 >=20 > +#define PCH_MAX_ISH_I2C_CONTROLLERS 3 >=20 > +#define PCH_MAX_ISH_SPI_CONTROLLERS 1 >=20 > +#define PCH_MAX_ISH_SPI_CS_PINS 1 >=20 > +// >=20 > +// HDA limits >=20 > +// >=20 > +#define PCH_MAX_HDA_SDI 2 >=20 > +#define PCH_MAX_HDA_SSP_LINK_NUM 6 >=20 > +#define PCH_MAX_HDA_SNDW_LINK_NUM 4 >=20 > + >=20 > +// >=20 > +// Number of eSPI slaves >=20 > +// >=20 > +#define PCH_MAX_ESPI_SLAVES 2 >=20 > + >=20 > +#endif // _PCH_LIMITS_H_ >=20 > + >=20 > diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/PchPolicyCommo= n.h > b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/PchPolicyCommon.h > new file mode 100644 > index 0000000000..7b749818fa > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/PchPolicyCommon.h > @@ -0,0 +1,55 @@ > +/** @file >=20 > + PCH configuration based on PCH policy >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _PCH_POLICY_COMMON_H_ >=20 > +#define _PCH_POLICY_COMMON_H_ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +#include "PchLimits.h" >=20 > +#include "ConfigBlock/PchGeneralConfig.h" >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include "ConfigBlock/FlashProtectionConfig.h" >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include "ConfigBlock/LockDownConfig.h" >=20 > +#include "P2sbConfig.h" >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +#ifndef FORCE_ENABLE >=20 > +#define FORCE_ENABLE 1 >=20 > +#endif >=20 > +#ifndef FORCE_DISABLE >=20 > +#define FORCE_DISABLE 2 >=20 > +#endif >=20 > +#ifndef PLATFORM_POR >=20 > +#define PLATFORM_POR 0 >=20 > +#endif >=20 > + >=20 > + >=20 > +#endif // _PCH_POLICY_COMMON_H_ >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/PchPreMemPolicyCommon.h > b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/PchPreMemPolicyCommon. > h > new file mode 100644 > index 0000000000..25e99d3a68 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/PchPreMemPolicyCommon. > h > @@ -0,0 +1,56 @@ > +/** @file >=20 > + PCH configuration based on PCH policy >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _PCH_PREMEM_POLICY_COMMON_H_ >=20 > +#define _PCH_PREMEM_POLICY_COMMON_H_ >=20 > + >=20 > +#include >=20 > + >=20 > +#include "PchLimits.h" >=20 > +#include "ConfigBlock/PchGeneralConfig.h" >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include "ConfigBlock/LpcConfig.h" >=20 > +#include "ConfigBlock/HsioPcieConfig.h" >=20 > +#include "ConfigBlock/HsioSataConfig.h" >=20 > +#include "ConfigBlock/HsioConfig.h" >=20 > + >=20 > +#pragma pack (push,1) >=20 > + >=20 > +#ifndef FORCE_ENABLE >=20 > +#define FORCE_ENABLE 1 >=20 > +#endif >=20 > +#ifndef FORCE_DISABLE >=20 > +#define FORCE_DISABLE 2 >=20 > +#endif >=20 > +#ifndef PLATFORM_POR >=20 > +#define PLATFORM_POR 0 >=20 > +#endif >=20 > + >=20 > +/** >=20 > + PCH Policy revision number >=20 > + Any backwards compatible changes to this structure will result in an u= pdate > in the revision number >=20 > +**/ >=20 > +#define PCH_PREMEM_POLICY_REVISION 1 >=20 > + >=20 > +/** >=20 > + PCH Policy PPI\n >=20 > + All PCH config block change history will be listed here\n\n >=20 > + >=20 > + - Revision 1: >=20 > + - Initial version.\n >=20 > +**/ >=20 > +typedef struct _PCH_PREMEM_POLICY { >=20 > + CONFIG_BLOCK_TABLE_HEADER TableHeader; >=20 > +/* >=20 > + Individual Config Block Structures are added here in memory as part of > AddConfigBlock() >=20 > +*/ >=20 > +} PCH_PREMEM_POLICY; >=20 > + >=20 > +#pragma pack (pop) >=20 > + >=20 > +#endif // _PCH_PREMEM_POLICY_COMMON_H_ >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/PchResetPlatformSpecific.= h > b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/PchResetPlatformSpecific.= h > new file mode 100644 > index 0000000000..4573a11520 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/PchResetPlatformSpecific.= h > @@ -0,0 +1,21 @@ > +/** @file >=20 > + PCH Reset Platform Specific definitions. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _PCH_RESET_PLATFORM_SPECIFIC_H_ >=20 > +#define _PCH_RESET_PLATFORM_SPECIFIC_H_ >=20 > + >=20 > +#define PCH_PLATFORM_SPECIFIC_RESET_STRING L"PCH_RESET" >=20 > +#define PCH_RESET_DATA_STRING_MAX_LENGTH (sizeof > (PCH_PLATFORM_SPECIFIC_RESET_STRING) / sizeof (UINT16)) >=20 > + >=20 > +extern EFI_GUID gPchGlobalResetGuid; >=20 > + >=20 > +typedef struct _RESET_DATA { >=20 > + CHAR16 Description[PCH_RESET_DATA_STRING_MAX_LENGTH]; >=20 > + EFI_GUID Guid; >=20 > +} PCH_RESET_DATA; >=20 > + >=20 > +#endif // _PCH_RESET_PLATFORM_SPECIFIC_H_ >=20 > + >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/IoTrapExDispatch= .h > b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/IoTrapExDispatch= .h > new file mode 100644 > index 0000000000..4d6241c32b > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/IoTrapExDispatch= .h > @@ -0,0 +1,184 @@ > +/** @file >=20 > + PCH IO TrapEx Dispatch Protocol >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _IO_TRAP_EX_DISPATCH_H_ >=20 > +#define _IO_TRAP_EX_DISPATCH_H_ >=20 > + >=20 > +// >=20 > +// Extern the GUID for protocol users. >=20 > +// >=20 > +extern EFI_GUID gIoTrapExDispatchP= rotocolGuid; >=20 > + >=20 > +typedef struct _IO_TRAP_EX_DISPATCH_PROTOCOL > IO_TRAP_EX_DISPATCH_PROTOCOL; >=20 > + >=20 > +/** >=20 > + IO Trap Ex valid types >=20 > +**/ >=20 > +typedef enum { >=20 > + IoTrapExTypeWrite, >=20 > + IoTrapExTypeRead, >=20 > + IoTrapExTypeReadWrite, >=20 > + IoTrapExTypeMaximum >=20 > +} IO_TRAP_EX_DISPATCH_TYPE; >=20 > + >=20 > +/** >=20 > + IO Trap Ex context structure containing information about the >=20 > + IO trap Ex event that should invoke the handler. >=20 > + ByteEnableMask bitwise to ignore the ByteEnable setting. E.g. 1111b fo= r > any byte access. >=20 > + >=20 > + Here are some examples for the usage. >=20 > + 1. To trigger the TRAP for the IO address from 0x2000 to 0x20FF with > BYTE/WORD/DWORD read/write access: >=20 > + Address =3D 0x2000 >=20 > + Length =3D 0x100 >=20 > + Type =3D IoTrapExTypeReadWrite >=20 > + ByteEnable =3D 0x00 (BE is not matter) >=20 > + ByteEnableMask =3D 0x0F (BEM 0xF for any BYTE/WORD/DWORD access) >=20 > + 2. To trigger the TRAP for port 0x61 with BYTE read access: >=20 > + Address =3D 0x60 >=20 > + Length =3D 4 >=20 > + Type =3D IoTrapExTypeRead >=20 > + ByteEnable =3D 0x02 (BE is 0010b to trap only second byte of e= very > DWORD) >=20 > + ByteEnableMask =3D 0x00 (BEM doesn't mask any BE bit) >=20 > + 3. To trigger the TRAP for port 0x60 and 0x64 with BYTE write access: >=20 > + Address =3D 0x60 >=20 > + Length =3D 8 >=20 > + Type =3D IoTrapExTypeWrite >=20 > + ByteEnable =3D 0x01 (BE is 0001b to trap only first byte of ev= ery DWORD) >=20 > + ByteEnableMask =3D 0x00 (BEM doesn't mask any BE bit) >=20 > +**/ >=20 > +typedef struct { >=20 > + /** >=20 > + The Address must be dword alignment. >=20 > + **/ >=20 > + UINT16 Address; >=20 > + UINT16 Length; >=20 > + IO_TRAP_EX_DISPATCH_TYPE Type; >=20 > + /** >=20 > + Bitmap to enable trap for each byte of every dword alignment address= . >=20 > + The Io Trap Address must be dword alignment for ByteEnable. >=20 > + E.g. 0001b for first byte, 0010b for second byte, 1100b for third an= d fourth > byte. >=20 > + **/ >=20 > + UINT8 ByteEnable; >=20 > + /** >=20 > + ByteEnableMask bitwise to ignore the ByteEnable setting. E.g. 1111b = for > any byte access. >=20 > + The Io Trap Address must be dword alignment for ByteEnableMask. >=20 > + **/ >=20 > + UINT8 ByteEnableMask; >=20 > +} IO_TRAP_EX_REGISTER_CONTEXT; >=20 > + >=20 > +/** >=20 > + Callback function for an PCH IO TRAP EX handler dispatch. >=20 > + >=20 > + @param[in] Address DWord-aligned address of the tra= pped > cycle. >=20 > + @param[in] ByteEnable This is the DWord-aligned byte e= nables > associated with the trapped cycle. >=20 > + A 1 in any bit location indicate= s that the corresponding > byte is enabled in the cycle. >=20 > + @param[in] WriteCycle TRUE =3D Write cycle; FALSE =3D = Read cycle >=20 > + @param[in] WriteData DWord of I/O write data. This fi= eld is > undefined after trapping a read cycle. >=20 > + The byte of WriteData is only va= lid if the corresponding > bits in ByteEnable is 1. >=20 > + E.g. >=20 > + If ByteEnable is 0001b, then onl= y first byte of WriteData > is valid. >=20 > + If ByteEnable is 0010b, then onl= y second byte of > WriteData is valid. >=20 > +**/ >=20 > +typedef >=20 > +VOID >=20 > +(EFIAPI *IO_TRAP_EX_DISPATCH_CALLBACK) ( >=20 > + IN UINT16 Address, >=20 > + IN UINT8 ByteEnable, >=20 > + IN BOOLEAN WriteCycle, >=20 > + IN UINT32 WriteData >=20 > + ); >=20 > + >=20 > +/** >=20 > + Register a new IO Trap Ex SMI dispatch function. >=20 > + The caller will provide information of IO trap setting via the context= . >=20 > + Please consider to use EfiSmmIoTrapDispatch2Protocol as possible. >=20 > + This is the function to extend the IoTrap capability, and it's expecte= d >=20 > + to handle the special ByteEnable and ByteEnableMask setting. >=20 > + This register function will occupy one IoTrap register if possible. >=20 > + And it only support one handler for one IoTrap event. >=20 > + The Address of context MUST NOT be 0, and MUST be dword alignment. >=20 > + The Length of context MUST not less than 4, and MUST be power of 2. >=20 > + The ByteEnable and ByteEnableMask MUST not be zero at the same time. >=20 > + if the IO Trap handler is not used. It also enable the IO Trap Range t= o > generate >=20 > + SMI. >=20 > + Caller must take care of reserving the IO addresses in ACPI. >=20 > + >=20 > + @param[in] This Pointer to the > IO_TRAP_EX_DISPATCH_PROTOCOL instance. >=20 > + @param[in] DispatchFunction Pointer to dispatch function to be inv= oked > for >=20 > + this SMI source. >=20 > + @param[in] RegisterContext Pointer to the dispatch function's con= text. >=20 > + The caller fills this context in befor= e calling >=20 > + the register function to indicate to t= he register >=20 > + function the IO trap Ex SMI source for= which the dispatch >=20 > + function should be invoked. This MUST= not be NULL. >=20 > + @param[out] DispatchHandle Handle of dispatch function. >=20 > + >=20 > + @retval EFI_SUCCESS The dispatch function has been success= fully >=20 > + registered and the SMI source has been= enabled. >=20 > + @retval EFI_OUT_OF_RESOURCES Insufficient resources are available >=20 > + @retval EFI_INVALID_PARAMETER Address requested is already in use. >=20 > + @retval EFI_ACCESS_DENIED Return access denied if the > SmmReadyToLock event has been triggered >=20 > +**/ >=20 > +typedef >=20 > +EFI_STATUS >=20 > +(EFIAPI *IO_TRAP_EX_DISPATCH_REGISTER) ( >=20 > + IN IO_TRAP_EX_DISPATCH_PROTOCOL *This, >=20 > + IN IO_TRAP_EX_DISPATCH_CALLBACK DispatchFunction, >=20 > + IN IO_TRAP_EX_REGISTER_CONTEXT *RegisterContext, >=20 > + OUT EFI_HANDLE *DispatchHandle >=20 > + ); >=20 > + >=20 > +/** >=20 > + Unregister a SMI source dispatch function. >=20 > + This function is unsupported. >=20 > + >=20 > + @param[in] This Pointer to the > IO_TRAP_EX_DISPATCH_PROTOCOL instance. >=20 > + @param[in] DispatchHandle Handle of dispatch function to deregis= ter. >=20 > + >=20 > + @retval EFI_UNSUPPORTED The function is unsupported. >=20 > +**/ >=20 > +typedef >=20 > +EFI_STATUS >=20 > +(EFIAPI *IO_TRAP_EX_DISPATCH_UNREGISTER) ( >=20 > + IN IO_TRAP_EX_DISPATCH_PROTOCOL *This, >=20 > + IN EFI_HANDLE DispatchHandle >=20 > + ); >=20 > + >=20 > +/** >=20 > + Interface structure for the IO trap Extention protocol. >=20 > + This protocol exposes full IO TRAP capability for ByteEnable and > ByteEnableMask setting. >=20 > + Platform code should fully control the ByteEnable and ByteEnableMake > while using this protocol. >=20 > + >=20 > + Please consider to use EfiSmmIoTrapDispatch2Protocol as possible. >=20 > + This is the function to extend the IoTrap capability, and it's expecte= d >=20 > + to handle the special ByteEnable and ByteEnableMask setting. >=20 > + >=20 > + The protocol is low level, It returns PSTH trapped cycle. This might n= ot be > safe for multithread >=20 > + if more than one thread triggers the same IOTRAP at the same time. >=20 > +**/ >=20 > +struct _IO_TRAP_EX_DISPATCH_PROTOCOL { >=20 > + /** >=20 > + Register function for PCH IO TRAP EX DISPATCH PROTOCOL. >=20 > + The caller will provide information of IO trap setting via the conte= xt. >=20 > + Please consider to use EfiSmmIoTrapDispatch2Protocol as possible. >=20 > + This is the function to extend the IoTrap capability, and it's expec= ted >=20 > + to handle the special ByteEnable and ByteEnableMask setting. >=20 > + This register function will occupy one IoTrap register if possible. >=20 > + And it only support one handler for one IoTrap event. >=20 > + The Address of context MUST NOT be 0, and MUST be dword alignment. >=20 > + The Length of context MUST not less than 4, and MUST be power of 2. >=20 > + The ByteEnable and ByteEnableMask MUST not be zero at the same time. >=20 > + if the IO Trap handler is not used. It also enable the IO Trap Range= to >=20 > + generate SMI. >=20 > + **/ >=20 > + IO_TRAP_EX_DISPATCH_REGISTER Register; >=20 > + /** >=20 > + Unregister function for PCH IO TRAP EX DISPATCH PROTOCOL. >=20 > + **/ >=20 > + IO_TRAP_EX_DISPATCH_UNREGISTER UnRegister; >=20 > +}; >=20 > + >=20 > +#endif >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchAcpiSmiDispat= ch > .h > b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchAcpiSmiDispat= c > h.h > new file mode 100644 > index 0000000000..136734d9ff > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchAcpiSmiDispat= c > h.h > @@ -0,0 +1,134 @@ > +/** @file >=20 > + APIs of PCH ACPI SMI Dispatch Protocol. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _PCH_ACPI_SMI_DISPATCH_PROTOCOL_H_ >=20 > +#define _PCH_ACPI_SMI_DISPATCH_PROTOCOL_H_ >=20 > + >=20 > +// >=20 > +// Extern the GUID for protocol users. >=20 > +// >=20 > +extern EFI_GUID gPchAcpiSmiDispatchProtocolGuid; >=20 > + >=20 > +// >=20 > +// Forward reference for ANSI C compatibility >=20 > +// >=20 > +typedef struct _PCH_ACPI_SMI_DISPATCH_PROTOCOL > PCH_ACPI_SMI_DISPATCH_PROTOCOL; >=20 > + >=20 > +// >=20 > +// Member functions >=20 > +// >=20 > + >=20 > +/** >=20 > + Callback function for an PCH ACPI SMI handler dispatch. >=20 > + >=20 > + @param[in] DispatchHandle The unique handle assigned to th= is > handler by register function. >=20 > + >=20 > +**/ >=20 > +typedef >=20 > +VOID >=20 > +(EFIAPI *PCH_ACPI_SMI_DISPATCH_CALLBACK) ( >=20 > + IN EFI_HANDLE DispatchHandle >=20 > + ); >=20 > + >=20 > +/** >=20 > + Register a child SMI source dispatch function for PCH ACPI SMI events. >=20 > + >=20 > + @param[in] This Protocol instance pointer. >=20 > + @param[in] DispatchFunction Pointer to dispatch function to = be > invoked for >=20 > + this SMI source >=20 > + @param[out] DispatchHandle Handle of dispatch function, for= when > interfacing >=20 > + with the parent SMM driver. >=20 > + >=20 > + @retval EFI_SUCCESS The dispatch function has been s= uccessfully >=20 > + registered and the SMI source ha= s been enabled. >=20 > + @retval EFI_DEVICE_ERROR The driver was unable to enable = the > SMI source. >=20 > + @retval EFI_OUT_OF_RESOURCES Not enough memory (system or > SMM) to manage this child. >=20 > + @retval EFI_ACCESS_DENIED Return access denied if the EndO= fDxe > event has been triggered >=20 > +**/ >=20 > +typedef >=20 > +EFI_STATUS >=20 > +(EFIAPI *PCH_ACPI_SMI_DISPATCH_REGISTER) ( >=20 > + IN PCH_ACPI_SMI_DISPATCH_PROTOCOL *This, >=20 > + IN PCH_ACPI_SMI_DISPATCH_CALLBACK DispatchFunction, >=20 > + OUT EFI_HANDLE *DispatchHandle >=20 > + ); >=20 > + >=20 > +/** >=20 > + Unregister a child SMI source dispatch function with a parent ACPI SMM > driver >=20 > + >=20 > + @param[in] This Protocol instance pointer. >=20 > + @param[in] DispatchHandle Handle of dispatch function to > deregister. >=20 > + >=20 > + @retval EFI_SUCCESS The dispatch function has been s= uccessfully >=20 > + unregistered and the SMI source = has been disabled >=20 > + if there are no other registered= child dispatch >=20 > + functions for this SMI source. >=20 > + @retval EFI_INVALID_PARAMETER Handle is invalid. >=20 > + @retval EFI_ACCESS_DENIED Return access denied if the EndO= fDxe > event has been triggered >=20 > +**/ >=20 > +typedef >=20 > +EFI_STATUS >=20 > +(EFIAPI *PCH_ACPI_SMI_DISPATCH_UNREGISTER) ( >=20 > + IN PCH_ACPI_SMI_DISPATCH_PROTOCOL *This, >=20 > + IN EFI_HANDLE DispatchHandle >=20 > + ); >=20 > + >=20 > +/** >=20 > + Interface structure for PCH ACPI SMIs Dispatch Protocol >=20 > + The PCH ACPI SMI DISPATCH PROTOCOL provides the ability to dispatch > function for PCH ACPI related SMIs. >=20 > + It contains SMI types of Pme, RtcAlarm, PmeB0, and Time overflow. >=20 > +**/ >=20 > +struct _PCH_ACPI_SMI_DISPATCH_PROTOCOL { >=20 > + /** >=20 > + This member specifies the revision of this structure. This field is = used to >=20 > + indicate backwards compatible changes to the protocol. >=20 > + **/ >=20 > + UINT8 Revision; >=20 > + /** >=20 > + Smi unregister function for PCH ACPI SMI DISPATCH PROTOCOL. >=20 > + **/ >=20 > + PCH_ACPI_SMI_DISPATCH_UNREGISTER UnRegister; >=20 > + /** >=20 > + Pme >=20 > + The event is triggered by hardware when the PME# signal goes active. >=20 > + Additionally, the event is only triggered when SCI_EN is not set. >=20 > + **/ >=20 > + PCH_ACPI_SMI_DISPATCH_REGISTER PmeRegister; >=20 > + /** >=20 > + PmeB0 >=20 > + The event is triggered PCH when any internal device with PCI Power > Management >=20 > + capabilities on bus 0 asserts the equivalent of the PME# signal. >=20 > + Additionally, the event is only triggered when SCI_EN is not set. >=20 > + The following are internal devices which can set this bit: >=20 > + Intel HD Audio, Intel Management Engine "maskable" wake events, > Integrated LAN, >=20 > + SATA, xHCI, Intel SST >=20 > + **/ >=20 > + PCH_ACPI_SMI_DISPATCH_REGISTER PmeB0Register; >=20 > + /** >=20 > + RtcAlarm >=20 > + The event is triggered by hardware when the RTC generates an alarm >=20 > + (assertion of the IRQ8# signal). >=20 > + **/ >=20 > + PCH_ACPI_SMI_DISPATCH_REGISTER RtcAlarmRegister; >=20 > + /** >=20 > + TmrOverflow >=20 > + The event is triggered any time bit 22 of the 24-bit timer goes high >=20 > + (bits are numbered from 0 to 23). >=20 > + This will occur every 2.3435 seconds. When the TMROF_EN bit (ABASE + > 02h, bit 0) is set, >=20 > + then the setting of the TMROF_STS bit will additionally generate an = SMI# >=20 > + Additionally, the event is only triggered when SCI_EN is not set. >=20 > + **/ >=20 > + PCH_ACPI_SMI_DISPATCH_REGISTER TmrOverflowRegister; >=20 > +}; >=20 > + >=20 > +/** >=20 > + PCH ACPI SMI dispatch revision number >=20 > + >=20 > + Revision 1: Initial version >=20 > +**/ >=20 > +#define PCH_ACPI_SMI_DISPATCH_REVISION 1 >=20 > + >=20 > +#endif >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchEspiSmiDispat= ch > .h > b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchEspiSmiDispat= ch > .h > new file mode 100644 > index 0000000000..4ea48c3fcd > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchEspiSmiDispat= ch > .h > @@ -0,0 +1,144 @@ > +/** @file >=20 > + SmmEspiDispatch Protocol >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _PCH_ESPI_SMI_DISPATCH_PROTOCOL_H_ >=20 > +#define _PCH_ESPI_SMI_DISPATCH_PROTOCOL_H_ >=20 > + >=20 > +// >=20 > +// Extern the GUID for protocol users. >=20 > +// >=20 > +extern EFI_GUID gPchEspiSmiDispatchProtocolGuid; >=20 > + >=20 > +// >=20 > +// Forward reference for ANSI C compatibility >=20 > +// >=20 > +typedef struct _PCH_ESPI_SMI_DISPATCH_PROTOCOL > PCH_ESPI_SMI_DISPATCH_PROTOCOL; >=20 > + >=20 > +// >=20 > +// Member functions >=20 > +// >=20 > + >=20 > +/** >=20 > + Callback function for an PCH eSPI SMI handler dispatch. >=20 > + >=20 > + @param[in] DispatchHandle The unique handle assigned to th= is > handler by register function. >=20 > +**/ >=20 > +typedef >=20 > +VOID >=20 > +(EFIAPI *PCH_ESPI_SMI_DISPATCH_CALLBACK) ( >=20 > + IN EFI_HANDLE DispatchHandle >=20 > + ); >=20 > + >=20 > +/** >=20 > + Generic function to register different types of eSPI SMI types >=20 > + >=20 > + @param[in] This Not used >=20 > + @param[in] DispatchFunction The callback to execute >=20 > + @param[out] DispatchHandle The handle for this callback registratio= n >=20 > + >=20 > + @retval EFI_SUCCESS Registration successful >=20 > + @retval EFI_ACCESS_DENIED Return access denied if the EndOfDxe > event has been triggered >=20 > + @retval others Registration failed >=20 > +**/ >=20 > +typedef >=20 > +EFI_STATUS >=20 > +(EFIAPI *PCH_ESPI_SMI_REGISTER) ( >=20 > + IN PCH_ESPI_SMI_DISPATCH_PROTOCOL *This, >=20 > + IN PCH_ESPI_SMI_DISPATCH_CALLBACK DispatchFunction, >=20 > + OUT EFI_HANDLE *DispatchHandle >=20 > + ); >=20 > + >=20 > +/** >=20 > + eSPI SMI Dispatch Protocol instance to unregister a callback based on > handle >=20 > + >=20 > + @param[in] This Not used >=20 > + @param[in] DispatchHandle Handle acquired during registratio= n >=20 > + >=20 > + @retval EFI_SUCCESS Unregister successful >=20 > + @retval EFI_INVALID_PARAMETER DispatchHandle is null >=20 > + @retval EFI_INVALID_PARAMETER DispatchHandle's forward link has > bad pointer >=20 > + @retval EFI_INVALID_PARAMETER DispatchHandle does not exist in > database >=20 > + @retval EFI_ACCESS_DENIED Unregistration is done after end o= f DXE >=20 > +**/ >=20 > + >=20 > +typedef >=20 > +EFI_STATUS >=20 > +(EFIAPI *PCH_ESPI_SMI_UNREGISTER) ( >=20 > + IN PCH_ESPI_SMI_DISPATCH_PROTOCOL *This, >=20 > + IN EFI_HANDLE DispatchHandle >=20 > + ); >=20 > + >=20 > +/** >=20 > + Interface structure for PCH eSPI SMIs Dispatch Protocol >=20 > + The PCH ESPI SMI DISPATCH PROTOCOL provides the ability to dispatch > function for PCH eSPI related SMIs. >=20 > + It contains SMI types of BiosWr, EcAssertedVw, and eSPI Master asserte= d > SMIs >=20 > +**/ >=20 > +struct _PCH_ESPI_SMI_DISPATCH_PROTOCOL { >=20 > + /** >=20 > + This member specifies the revision of this structure. This field is = used to >=20 > + indicate backwards compatible changes to the protocol. >=20 > + **/ >=20 > + UINT8 Revision; >=20 > + /** >=20 > + Unregister eSPI SMI events >=20 > + **/ >=20 > + PCH_ESPI_SMI_UNREGISTER UnRegister; >=20 > + /** >=20 > + Register a BIOS Write Protect event >=20 > + **/ >=20 > + PCH_ESPI_SMI_REGISTER BiosWrProtectRegister; >=20 > + /** >=20 > + Register a BIOS Write Report event >=20 > + **/ >=20 > + PCH_ESPI_SMI_REGISTER BiosWrReportRegister; >=20 > + /** >=20 > + Register a Peripheral Channel Non Fatal Error event >=20 > + **/ >=20 > + PCH_ESPI_SMI_REGISTER PcErrNonFatalRegister; >=20 > + /** >=20 > + Register a Peripheral Channel Fatal Error event >=20 > + **/ >=20 > + PCH_ESPI_SMI_REGISTER PcErrFatalRegister; >=20 > + /** >=20 > + Register a Virtual Wire Non Fatal Error event >=20 > + **/ >=20 > + PCH_ESPI_SMI_REGISTER VwErrNonFatalRegister; >=20 > + /** >=20 > + Register a Virtual Wire Fatal Error event >=20 > + **/ >=20 > + PCH_ESPI_SMI_REGISTER VwErrFatalRegister; >=20 > + /** >=20 > + Register a Flash Channel Non Fatal Error event >=20 > + **/ >=20 > + PCH_ESPI_SMI_REGISTER FlashErrNonFatalRegister; >=20 > + /** >=20 > + Register a Flash Channel Fatal Error event >=20 > + **/ >=20 > + PCH_ESPI_SMI_REGISTER FlashErrFatalRegister; >=20 > + /** >=20 > + Register a Link Error event >=20 > + **/ >=20 > + PCH_ESPI_SMI_REGISTER LnkErrType1Register; >=20 > + /** >=20 > + Register a SMI handler for Espi slaver >=20 > + This routine will also lock down ESPI_SMI_LOCK bit after registratio= n and > prevent >=20 > + this handler from unregistration. >=20 > + On platform that supports more than 1 device through another chip se= lect > (SPT-H), >=20 > + the SMI handler itself needs to inspect both the eSPI devices' inter= rupt > status registers >=20 > + (implementation specific for each Slave) in order to identify and se= rvice > the cause. >=20 > + After servicing it, it has to clear the Slaves' internal SMI# status= registers >=20 > + **/ >=20 > + PCH_ESPI_SMI_REGISTER EspiSlaveSmiRegister; >=20 > +}; >=20 > + >=20 > +/** >=20 > + PCH ESPI SMI dispatch revision number >=20 > + >=20 > + Revision 1: Initial version >=20 > +**/ >=20 > +#define PCH_ESPI_SMI_DISPATCH_REVISION 1 >=20 > + >=20 > +#endif >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchPcieSmiDispat= ch > .h > b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchPcieSmiDispat= ch > .h > new file mode 100644 > index 0000000000..b75b9ab45d > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchPcieSmiDispat= ch > .h > @@ -0,0 +1,166 @@ > +/** @file >=20 > + APIs of PCH PCIE SMI Dispatch Protocol. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _PCH_PCIE_SMI_DISPATCH_PROTOCOL_H_ >=20 > +#define _PCH_PCIE_SMI_DISPATCH_PROTOCOL_H_ >=20 > + >=20 > +// >=20 > +// Extern the GUID for protocol users. >=20 > +// >=20 > +extern EFI_GUID gPchPcieSmiDispatchProtocolGuid; >=20 > + >=20 > +// >=20 > +// Forward reference for ANSI C compatibility >=20 > +// >=20 > +typedef struct _PCH_PCIE_SMI_DISPATCH_PROTOCOL > PCH_PCIE_SMI_DISPATCH_PROTOCOL; >=20 > + >=20 > +typedef enum { >=20 > + PchRpIndex0 =3D 0, >=20 > + PchRpIndex1 =3D 1, >=20 > + PchRpIndex2 =3D 2, >=20 > + PchRpIndex3 =3D 3, >=20 > + PchRpIndex4 =3D 4, >=20 > + PchRpIndex5 =3D 5, >=20 > + PchRpIndex6 =3D 6, >=20 > + PchRpIndex7 =3D 7, >=20 > + PchRpIndex8 =3D 8, >=20 > + PchRpIndex9 =3D 9, >=20 > + PchRpIndex10 =3D 10, >=20 > + PchRpIndex11 =3D 11, >=20 > + PchRpIndex12 =3D 12, >=20 > + PchRpIndex13 =3D 13, >=20 > + PchRpIndex14 =3D 14, >=20 > + PchRpIndex15 =3D 15, >=20 > + PchRpIndex16 =3D 16, >=20 > + PchRpIndex17 =3D 17, >=20 > + PchRpIndex18 =3D 18, >=20 > + PchRpIndex19 =3D 19, >=20 > + PchRpIndex20 =3D 20, >=20 > + PchRpIndex21 =3D 21, >=20 > + PchRpIndex22 =3D 22, >=20 > + PchRpIndex23 =3D 23, >=20 > + /** >=20 > + Quantity of PCH and CPU PCIe ports, as well as their encoding in thi= s > enum, may change between >=20 > + silicon generations and series. Do not assume that PCH port 0 will b= e > always encoded by 0. >=20 > + Instead, it is recommended to use (PchRpIndex0 + PchPortIndex) style= to > be forward-compatible >=20 > + **/ >=20 > + CpuRpIndex0 =3D 0x40, >=20 > + CpuRpIndex1 =3D 0x41, >=20 > + CpuRpIndex2 =3D 0x42, >=20 > + CpuRpIndex3 =3D 0x43 >=20 > +} PCIE_COMBINED_RPINDEX; >=20 > + >=20 > +// >=20 > +// Member functions >=20 > +// >=20 > + >=20 > +typedef struct { >=20 > + UINT8 RpIndex; ///< Root port index (0= -based), 0: RP1, 1: > RP2, n: RP(N+1) >=20 > + UINT8 BusNum; ///< Root port pci bus = number >=20 > + UINT8 DevNum; ///< Root port pci devi= ce number >=20 > + UINT8 FuncNum; ///< Root port pci func= tion number >=20 > +} PCH_PCIE_SMI_RP_CONTEXT; >=20 > + >=20 > +/** >=20 > + Callback function for an PCH PCIE RP SMI handler dispatch. >=20 > + >=20 > + @param[in] DispatchHandle The unique handle assigned to th= is > handler by register function. >=20 > + @param[in] RpContext Pointer of PCH PCIE Root Port co= ntext. >=20 > + >=20 > +**/ >=20 > +typedef >=20 > +VOID >=20 > +(EFIAPI *PCH_PCIE_SMI_RP_DISPATCH_CALLBACK) ( >=20 > + IN EFI_HANDLE DispatchHandle, >=20 > + IN PCH_PCIE_SMI_RP_CONTEXT *RpContext >=20 > + ); >=20 > + >=20 > +/** >=20 > + Register a child SMI source dispatch function for PCH PCIERP SMI event= s. >=20 > + >=20 > + @param[in] This Protocol instance pointer. >=20 > + @param[in] DispatchFunction Pointer to dispatch function to = be > invoked for >=20 > + this SMI source >=20 > + @param[in] RpIndex Refer PCIE_COMBINED_RPINDEX for = PCH > RP index and CPU RP index. >=20 > + 0: RP1, 1: RP2, n: RP(N+1) >=20 > + @param[out] DispatchHandle Handle of dispatch function, for= when > interfacing >=20 > + with the parent SMM driver. >=20 > + >=20 > + @retval EFI_SUCCESS The dispatch function has been s= uccessfully >=20 > + registered and the SMI source ha= s been enabled. >=20 > + @retval EFI_DEVICE_ERROR The driver was unable to enable = the > SMI source. >=20 > + @retval EFI_OUT_OF_RESOURCES Not enough memory (system or > SMM) to manage this child. >=20 > + @retval EFI_ACCESS_DENIED Return access denied if the EndO= fDxe > event has been triggered >=20 > +**/ >=20 > +typedef >=20 > +EFI_STATUS >=20 > +(EFIAPI *PCH_PCIE_SMI_RP_DISPATCH_REGISTER) ( >=20 > + IN PCH_PCIE_SMI_DISPATCH_PROTOCOL *This, >=20 > + IN PCH_PCIE_SMI_RP_DISPATCH_CALLBACK DispatchFunction, >=20 > + IN UINTN RpIndex, >=20 > + OUT EFI_HANDLE *DispatchHandle >=20 > + ); >=20 > + >=20 > +/** >=20 > + Unregister a child SMI source dispatch function with a parent PCIE SMM > driver >=20 > + >=20 > + @param[in] This Protocol instance pointer. >=20 > + @param[in] DispatchHandle Handle of dispatch function to > deregister. >=20 > + >=20 > + @retval EFI_SUCCESS The dispatch function has been s= uccessfully >=20 > + unregistered and the SMI source = has been disabled >=20 > + if there are no other registered= child dispatch >=20 > + functions for this SMI source. >=20 > + @retval EFI_INVALID_PARAMETER Handle is invalid. >=20 > + @retval EFI_ACCESS_DENIED Return access denied if the EndO= fDxe > event has been triggered >=20 > +**/ >=20 > +typedef >=20 > +EFI_STATUS >=20 > +(EFIAPI *PCH_PCIE_SMI_DISPATCH_UNREGISTER) ( >=20 > + IN PCH_PCIE_SMI_DISPATCH_PROTOCOL *This, >=20 > + IN EFI_HANDLE DispatchHandle >=20 > + ); >=20 > + >=20 > +/** >=20 > + Interface structure for PCH PCIE SMIs Dispatch Protocol >=20 > + The PCH PCIE SMI DISPATCH PROTOCOL provides the ability to dispatch > function for PCH PCIE related SMIs. >=20 > + It contains SMI types of HotPlug, LinkActive, and Link EQ. >=20 > +**/ >=20 > +struct _PCH_PCIE_SMI_DISPATCH_PROTOCOL { >=20 > + /** >=20 > + This member specifies the revision of this structure. This field is = used to >=20 > + indicate backwards compatible changes to the protocol. >=20 > + **/ >=20 > + UINT8 Revision; >=20 > + /** >=20 > + Smi unregister function for PCH PCIE SMI DISPATCH PROTOCOL. >=20 > + **/ >=20 > + PCH_PCIE_SMI_DISPATCH_UNREGISTER UnRegister; >=20 > + /** >=20 > + PcieRpXHotPlug >=20 > + The event is triggered when PCIE root port Hot-Plug Presence Detect. >=20 > + **/ >=20 > + PCH_PCIE_SMI_RP_DISPATCH_REGISTER HotPlugRegister; >=20 > + /** >=20 > + PcieRpXLinkActive >=20 > + The event is triggered when Hot-Plug Link Active State Changed. >=20 > + **/ >=20 > + PCH_PCIE_SMI_RP_DISPATCH_REGISTER LinkActiveRegister; >=20 > + /** >=20 > + PcieRpXLinkEq >=20 > + The event is triggered when Device Requests Software Link Equalizati= on. >=20 > + **/ >=20 > + PCH_PCIE_SMI_RP_DISPATCH_REGISTER LinkEqRegister; >=20 > +}; >=20 > + >=20 > +/** >=20 > + PCH PCIE SMI dispatch revision number >=20 > + >=20 > + Revision 1: Initial version >=20 > +**/ >=20 > +#define PCH_PCIE_SMI_DISPATCH_REVISION 1 >=20 > + >=20 > +#endif >=20 > diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchPo= licy.h > b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchPolicy.h > new file mode 100644 > index 0000000000..ba7cbdb23e > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchPolicy.h > @@ -0,0 +1,40 @@ > +/** @file >=20 > + Interface definition details between Pch and platform drivers during D= XE > phase. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _PCH_POLICY_H_ >=20 > +#define _PCH_POLICY_H_ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include "../IncludePrivate/PchConfigHob.h" // To Be corrected >=20 > +#include >=20 > + >=20 > +extern EFI_GUID gPchPolicyProtocolGuid; >=20 > + >=20 > +#define PCH_POLICY_PROTOCOL_REVISION 1 >=20 > + >=20 > + >=20 > +/** >=20 > + PCH DXE Policy >=20 > + >=20 > + The PCH_POLICY_PROTOCOL producer drvier is recommended to >=20 > + set all the PCH_POLICY_PROTOCOL size buffer zero before init any > member parameter, >=20 > + this clear step can make sure no random value for those unknown new > version parameters. >=20 > + >=20 > + Make sure to update the Revision if any change to the protocol, includ= ing > the existing >=20 > + internal structure definations.\n >=20 > + Note: Here revision will be bumped up when adding/removing any config > block under this structure.\n >=20 > + Revision 1: >=20 > + - Initial version. >=20 > +**/ >=20 > +typedef struct { >=20 > + CONFIG_BLOCK_TABLE_HEADER TableHeader; >=20 > +/* >=20 > + Individual Config Block Structures are added here in memory as part of > AddConfigBlock() >=20 > +*/ >=20 > +} PCH_POLICY_PROTOCOL; >=20 > + >=20 > +#endif >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchSmiDispatch.h > b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchSmiDispatch.h > new file mode 100644 > index 0000000000..12b5f8117b > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchSmiDispatch.h > @@ -0,0 +1,132 @@ > +/** @file >=20 > + APIs of PCH SMI Dispatch Protocol. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _PCH_SMI_DISPATCH_PROTOCOL_H_ >=20 > +#define _PCH_SMI_DISPATCH_PROTOCOL_H_ >=20 > + >=20 > +// >=20 > +// Extern the GUID for protocol users. >=20 > +// >=20 > +extern EFI_GUID gPchSmiDispatchProtocolGuid; >=20 > + >=20 > +// >=20 > +// Forward reference for ANSI C compatibility >=20 > +// >=20 > +typedef struct _PCH_SMI_DISPATCH_PROTOCOL > PCH_SMI_DISPATCH_PROTOCOL; >=20 > + >=20 > +// >=20 > +// Member functions >=20 > +// >=20 > + >=20 > +/** >=20 > + Callback function for an PCH SMI handler dispatch. >=20 > + >=20 > + @param[in] DispatchHandle The unique handle assigned to th= is > handler by register function. >=20 > + >=20 > +**/ >=20 > +typedef >=20 > +VOID >=20 > +(EFIAPI *PCH_SMI_DISPATCH_CALLBACK) ( >=20 > + IN EFI_HANDLE DispatchHandle >=20 > + ); >=20 > + >=20 > +/** >=20 > + Register a child SMI source dispatch function for specific PCH SMI dis= patch > event. >=20 > + >=20 > + @param[in] This Protocol instance pointer. >=20 > + @param[in] DispatchFunction Pointer to dispatch function to = be > invoked for >=20 > + this SMI source >=20 > + @param[out] DispatchHandle Handle of dispatch function, for= when > interfacing >=20 > + with the parent SMM driver. >=20 > + >=20 > + @retval EFI_SUCCESS The dispatch function has been s= uccessfully >=20 > + registered and the SMI source ha= s been enabled. >=20 > + @retval EFI_DEVICE_ERROR The driver was unable to enable = the > SMI source. >=20 > + @retval EFI_OUT_OF_RESOURCES Not enough memory (system or > SMM) to manage this child. >=20 > + @retval EFI_ACCESS_DENIED Return access denied if the EndO= fDxe > event has been triggered >=20 > +**/ >=20 > +typedef >=20 > +EFI_STATUS >=20 > +(EFIAPI *PCH_SMI_DISPATCH_REGISTER) ( >=20 > + IN PCH_SMI_DISPATCH_PROTOCOL *This, >=20 > + IN PCH_SMI_DISPATCH_CALLBACK DispatchFunction, >=20 > + OUT EFI_HANDLE *DispatchHandle >=20 > + ); >=20 > + >=20 > +/** >=20 > + Unregister a child SMI source dispatch function with a parent SMM driv= er >=20 > + >=20 > + @param[in] This Protocol instance pointer. >=20 > + @param[in] DispatchHandle Handle of dispatch function to > deregister. >=20 > + >=20 > + @retval EFI_SUCCESS The dispatch function has been s= uccessfully >=20 > + unregistered and the SMI source = has been disabled >=20 > + if there are no other registered= child dispatch >=20 > + functions for this SMI source. >=20 > + @retval EFI_INVALID_PARAMETER Handle is invalid. >=20 > + @retval EFI_ACCESS_DENIED Return access denied if the EndO= fDxe > event has been triggered >=20 > +**/ >=20 > +typedef >=20 > +EFI_STATUS >=20 > +(EFIAPI *PCH_SMI_DISPATCH_UNREGISTER) ( >=20 > + IN PCH_SMI_DISPATCH_PROTOCOL *This, >=20 > + IN EFI_HANDLE DispatchHandle >=20 > + ); >=20 > + >=20 > +/** >=20 > + Interface structure for PCH specific SMIs Dispatch Protocol >=20 > + The PCH SMI DISPATCH PROTOCOL provides the ability to dispatch functio= n > for PCH misc SMIs. >=20 > + It contains legacy SMIs and new PCH SMI types like: >=20 > + SerialIrq, McSmi, Smbus, ... >=20 > +**/ >=20 > +struct _PCH_SMI_DISPATCH_PROTOCOL { >=20 > + /** >=20 > + This member specifies the revision of this structure. This field is = used to >=20 > + indicate backwards compatible changes to the protocol. >=20 > + **/ >=20 > + UINT8 Revision; >=20 > + /** >=20 > + Smi unregister function for PCH SMI DISPATCH PROTOCOL. >=20 > + **/ >=20 > + PCH_SMI_DISPATCH_UNREGISTER UnRegister; >=20 > + /** >=20 > + SerialIrq >=20 > + The event is triggered while the SMI# was caused by the SERIRQ decod= er. >=20 > + **/ >=20 > + PCH_SMI_DISPATCH_REGISTER SerialIrqRegister; >=20 > + /** >=20 > + McSmi >=20 > + The event is triggered if there has been an access to the power > management >=20 > + microcontroller range (62h or 66h) and the Microcontroller Decode En= able > #1 bit >=20 > + in the LPC Bridge I/O Enables configuration register is 1 . >=20 > + **/ >=20 > + PCH_SMI_DISPATCH_REGISTER McSmiRegister; >=20 > + /** >=20 > + SmBus >=20 > + The event is triggered while the SMI# was caused by: >=20 > + 1. The SMBus Slave receiving a message that an SMI# should be caused= , > or >=20 > + 2. The SMBALERT# signal goes active and the SMB_SMI_EN bit is set an= d > the >=20 > + SMBALERT_DIS bit is cleared, or >=20 > + 3. The SMBus Slave receiving a Host Notify message and the > HOST_NOTIFY_INTREN and >=20 > + the SMB_SMI_EN bits are set, or >=20 > + 4. The PCH detecting the SMLINK_SLAVE_SMI command while in the S0 > state. >=20 > + **/ >=20 > + PCH_SMI_DISPATCH_REGISTER SmbusRegister; >=20 > + /** >=20 > + SPI Asynchronous >=20 > + When registered, the flash controller will generate an SMI when it b= locks > a BIOS write or erase. >=20 > + **/ >=20 > + PCH_SMI_DISPATCH_REGISTER SpiAsyncRegister; >=20 > +}; >=20 > + >=20 > +/** >=20 > + PCH SMI dispatch revision number >=20 > + >=20 > + Revision 1: Initial version >=20 > +**/ >=20 > +#define PCH_SMI_DISPATCH_REVISION 1 >=20 > + >=20 > +#endif >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchSmmIoTrapCont > rol.h > b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchSmmIoTrapCont > rol.h > new file mode 100644 > index 0000000000..9f2793634e > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchSmmIoTrapCont > rol.h > @@ -0,0 +1,65 @@ > +/** @file >=20 > + PCH SMM IO Trap Control Protocol >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _PCH_SMM_IO_TRAP_CONTROL_H_ >=20 > +#define _PCH_SMM_IO_TRAP_CONTROL_H_ >=20 > + >=20 > + >=20 > +// >=20 > +// Extern the GUID for protocol users. >=20 > +// >=20 > +extern EFI_GUID gPchSmmIoTrapControlGu= id; >=20 > + >=20 > +// >=20 > +// Forward reference for ANSI C compatibility >=20 > +// >=20 > +typedef struct _PCH_SMM_IO_TRAP_CONTROL_PROTOCOL > PCH_SMM_IO_TRAP_CONTROL_PROTOCOL; >=20 > + >=20 > +// >=20 > +// Related Definitions >=20 > +// >=20 > + >=20 > +// >=20 > +// Member functions >=20 > +// >=20 > + >=20 > +/** >=20 > + The Prototype of Pause and Resume IoTrap callback function. >=20 > + >=20 > + @param[in] This Pointer to the > PCH_SMM_IO_TRAP_CONTROL_PROTOCOL instance. >=20 > + @param[in] DispatchHandle Handle of the child service to change = state. >=20 > + >=20 > + @retval EFI_SUCCESS This operation is complete. >=20 > + @retval EFI_INVALID_PARAMETER The DispatchHandle is invalid. >=20 > + @retval EFI_ACCESS_DENIED The SMI status is alrady > PAUSED/RESUMED. >=20 > +**/ >=20 > +typedef >=20 > +EFI_STATUS >=20 > +(EFIAPI *PCH_SMM_IO_TRAP_CONTROL_FUNCTION) ( >=20 > + IN PCH_SMM_IO_TRAP_CONTROL_PROTOCOL * This, >=20 > + IN EFI_HANDLE DispatchHandle >=20 > + ); >=20 > + >=20 > +/** >=20 > + Interface structure for the SMM IO trap pause and resume protocol >=20 > + This protocol provides the functions to runtime control the IoTrap SMI > enabled/disable. >=20 > + This applys the capability to the DispatchHandle which returned by IoT= rap > callback >=20 > + registration, and the DispatchHandle which must be MergeDisable =3D TR= UE > and Address !=3D 0. >=20 > + Besides, when S3 resuem, it only restores the state of IoTrap callback > registration. >=20 > + The Paused/Resume state won't be restored after S3 resume. >=20 > +**/ >=20 > +struct _PCH_SMM_IO_TRAP_CONTROL_PROTOCOL { >=20 > + /** >=20 > + This runtime pauses a registered IoTrap handler. >=20 > + **/ >=20 > + PCH_SMM_IO_TRAP_CONTROL_FUNCTION Pause; >=20 > + /** >=20 > + This runtime resumes a registered IoTrap handler. >=20 > + **/ >=20 > + PCH_SMM_IO_TRAP_CONTROL_FUNCTION Resume; >=20 > +}; >=20 > + >=20 > +#endif >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchSmmPeriodicTi > merControl.h > b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchSmmPeriodicTi > merControl.h > new file mode 100644 > index 0000000000..a7b44c5f7e > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchSmmPeriodicTi > merControl.h > @@ -0,0 +1,65 @@ > +/** @file >=20 > + PCH SMM Periodic Timer Control Protocol >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _PCH_SMM_PERIODIC_TIMER_CONTROL_H_ >=20 > +#define _PCH_SMM_PERIODIC_TIMER_CONTROL_H_ >=20 > + >=20 > + >=20 > +// >=20 > +// Extern the GUID for protocol users. >=20 > +// >=20 > +extern EFI_GUID gPchSmmPerio= dicTimerControlGuid; >=20 > + >=20 > +// >=20 > +// Forward reference for ANSI C compatibility >=20 > +// >=20 > +typedef struct _PCH_SMM_PERIODIC_TIMER_CONTROL_PROTOCOL > PCH_SMM_PERIODIC_TIMER_CONTROL_PROTOCOL; >=20 > + >=20 > +// >=20 > +// Related Definitions >=20 > +// >=20 > + >=20 > +// >=20 > +// Member functions >=20 > +// >=20 > + >=20 > +/** >=20 > + The Prototype of Pause and Resume SMM PERIODIC TIMER function. >=20 > + >=20 > + @param[in] This Pointer to the > PCH_SMM_PERIODIC_TIMER_CONTROL_PROTOCOL instance. >=20 > + @param[in] DispatchHandle Handle of the child service to c= hange > state. >=20 > + >=20 > + @retval EFI_SUCCESS This operation is complete. >=20 > + @retval EFI_INVALID_PARAMETER The DispatchHandle is invalid. >=20 > + @retval EFI_ACCESS_DENIED The SMI status is alrady > PAUSED/RESUMED. >=20 > +**/ >=20 > +typedef >=20 > +EFI_STATUS >=20 > +(EFIAPI *PCH_SMM_PERIODIC_TIMER_CONTROL_FUNCTION) ( >=20 > + IN PCH_SMM_PERIODIC_TIMER_CONTROL_PROTOCOL *This, >=20 > + IN EFI_HANDLE DispatchHandle >=20 > + ); >=20 > + >=20 > +/** >=20 > + Interface structure for the SMM PERIODIC TIMER pause and resume > protocol >=20 > + This protocol provides the functions to runtime control the SM periodi= c > timer enabled/disable. >=20 > + This applies the capability to the DispatchHandle which returned by SM= M > periodic timer callback >=20 > + registration. >=20 > + Besides, when S3 resume, it only restores the state of callback regist= ration. >=20 > + The Paused/Resume state won't be restored after S3 resume. >=20 > +**/ >=20 > +struct _PCH_SMM_PERIODIC_TIMER_CONTROL_PROTOCOL { >=20 > + /** >=20 > + This runtime pauses the registered periodic timer handler. >=20 > + **/ >=20 > + PCH_SMM_PERIODIC_TIMER_CONTROL_FUNCTION Pause; >=20 > + /** >=20 > + This runtime resumes the registered periodic timer handler. >=20 > + **/ >=20 > + PCH_SMM_PERIODIC_TIMER_CONTROL_FUNCTION Resume; >=20 > +}; >=20 > + >=20 > +#endif // _PCH_SMM_PERIODIC_TIMER_CONTROL_H_ >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchTcoSmiDispatc= h. > h > b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchTcoSmiDispatc= h. > h > new file mode 100644 > index 0000000000..b443484f39 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchTcoSmiDispatc= h. > h > @@ -0,0 +1,150 @@ > +/** @file >=20 > + APIs of PCH TCO SMI Dispatch Protocol. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _PCH_TCO_SMI_DISPATCH_PROTOCOL_H_ >=20 > +#define _PCH_TCO_SMI_DISPATCH_PROTOCOL_H_ >=20 > + >=20 > +// >=20 > +// Extern the GUID for protocol users. >=20 > +// >=20 > +extern EFI_GUID gPchTcoSmiDispatchProtocolGuid; >=20 > + >=20 > +// >=20 > +// Forward reference for ANSI C compatibility >=20 > +// >=20 > +typedef struct _PCH_TCO_SMI_DISPATCH_PROTOCOL > PCH_TCO_SMI_DISPATCH_PROTOCOL; >=20 > + >=20 > +// >=20 > +// Member functions >=20 > +// >=20 > + >=20 > +/** >=20 > + Callback function for an PCH TCO SMI handler dispatch. >=20 > + >=20 > + @param[in] DispatchHandle The unique handle assigned to th= is > handler by register function. >=20 > + >=20 > +**/ >=20 > +typedef >=20 > +VOID >=20 > +(EFIAPI *PCH_TCO_SMI_DISPATCH_CALLBACK) ( >=20 > + IN EFI_HANDLE DispatchHandle >=20 > + ); >=20 > + >=20 > +/** >=20 > + Register a child SMI source dispatch function for PCH TCO SMI events. >=20 > + >=20 > + @param[in] This Protocol instance pointer. >=20 > + @param[in] DispatchFunction Pointer to dispatch function to = be > invoked for >=20 > + this SMI source >=20 > + @param[out] DispatchHandle Handle of dispatch function, for= when > interfacing >=20 > + with the parent SMM driver. >=20 > + >=20 > + @retval EFI_SUCCESS The dispatch function has been s= uccessfully >=20 > + registered and the SMI source ha= s been enabled. >=20 > + @retval EFI_DEVICE_ERROR The driver was unable to enable = the > SMI source. >=20 > + @retval EFI_OUT_OF_RESOURCES Not enough memory (system or > SMM) to manage this child. >=20 > + @retval EFI_ACCESS_DENIED Return access denied if the EndO= fDxe > event has been triggered >=20 > +**/ >=20 > +typedef >=20 > +EFI_STATUS >=20 > +(EFIAPI *PCH_TCO_SMI_DISPATCH_REGISTER) ( >=20 > + IN PCH_TCO_SMI_DISPATCH_PROTOCOL *This, >=20 > + IN PCH_TCO_SMI_DISPATCH_CALLBACK DispatchFunction, >=20 > + OUT EFI_HANDLE *DispatchHandle >=20 > + ); >=20 > + >=20 > +/** >=20 > + Unregister a child SMI source dispatch function with a parent TCO SMM > driver >=20 > + >=20 > + @param[in] This Protocol instance pointer. >=20 > + @param[in] DispatchHandle Handle of dispatch function to > deregister. >=20 > + >=20 > + @retval EFI_SUCCESS The dispatch function has been s= uccessfully >=20 > + unregistered and the SMI source = has been disabled >=20 > + if there are no other registered= child dispatch >=20 > + functions for this SMI source. >=20 > + @retval EFI_INVALID_PARAMETER Handle is invalid. >=20 > + @retval EFI_ACCESS_DENIED Return access denied if the EndO= fDxe > event has been triggered >=20 > +**/ >=20 > +typedef >=20 > +EFI_STATUS >=20 > +(EFIAPI *PCH_TCO_SMI_DISPATCH_UNREGISTER) ( >=20 > + IN PCH_TCO_SMI_DISPATCH_PROTOCOL *This, >=20 > + IN EFI_HANDLE DispatchHandle >=20 > + ); >=20 > + >=20 > +/** >=20 > + Interface structure for PCH TCO SMIs Dispatch Protocol >=20 > + The PCH TCO SMI DISPATCH PROTOCOL provides the ability to dispatch > function for PCH TCO related SMIs. >=20 > + It contains SMI types of Mch, TcoTimeout, OsTco, Nmi, IntruderDectect, > and BiowWp. >=20 > +**/ >=20 > +struct _PCH_TCO_SMI_DISPATCH_PROTOCOL { >=20 > + /** >=20 > + This member specifies the revision of this structure. This field is = used to >=20 > + indicate backwards compatible changes to the protocol. >=20 > + **/ >=20 > + UINT8 Revision; >=20 > + /** >=20 > + Smi unregister function for PCH TCO SMI DISPATCH PROTOCOL. >=20 > + **/ >=20 > + PCH_TCO_SMI_DISPATCH_UNREGISTER UnRegister; >=20 > + /** >=20 > + Mch >=20 > + The event is triggered when PCH received a DMI special cycle message > using DMI indicating that >=20 > + it wants to cause an SMI. >=20 > + The software must read the processor to determine the reason for the > SMI. >=20 > + **/ >=20 > + PCH_TCO_SMI_DISPATCH_REGISTER MchRegister; >=20 > + /** >=20 > + TcoTimeout >=20 > + The event is triggered by PCH to indicate that the SMI was caused by= the > TCO timer reaching 0. >=20 > + **/ >=20 > + PCH_TCO_SMI_DISPATCH_REGISTER TcoTimeoutRegister; >=20 > + /** >=20 > + OsTco >=20 > + The event is triggered when software caused an SMI# by writing to th= e > TCO_DAT_IN register (TCOBASE + 02h). >=20 > + **/ >=20 > + PCH_TCO_SMI_DISPATCH_REGISTER OsTcoRegister; >=20 > + /** >=20 > + Nmi >=20 > + The event is triggered by the PCH when an SMI# occurs because an eve= nt > occurred that would otherwise have >=20 > + caused an NMI (because NMI2SMI_EN is set) >=20 > + **/ >=20 > + PCH_TCO_SMI_DISPATCH_REGISTER NmiRegister; >=20 > + /** >=20 > + IntruderDectect >=20 > + The event is triggered by PCH to indicate that an intrusion was dete= cted. >=20 > + **/ >=20 > + PCH_TCO_SMI_DISPATCH_REGISTER IntruderDetRegister; >=20 > + /** >=20 > + SpiBiosWp >=20 > + This event is triggered when SMI# was caused by the TCO logic and >=20 > + SPI flash controller asserted Synchronous SMI by BIOS lock enable se= t. >=20 > + **/ >=20 > + PCH_TCO_SMI_DISPATCH_REGISTER SpiBiosWpRegister; >=20 > + /** >=20 > + LpcBiosWp >=20 > + This event is triggered when SMI# was caused by the TCO logic and >=20 > + LPC/eSPI BIOS lock enable set. >=20 > + **/ >=20 > + PCH_TCO_SMI_DISPATCH_REGISTER LpcBiosWpRegister; >=20 > + /** >=20 > + NewCentury >=20 > + This event is triggered when SMI# was caused by the TCO logic and >=20 > + year of RTC date rolls over a century (99 to 00). >=20 > + **/ >=20 > + PCH_TCO_SMI_DISPATCH_REGISTER NewCenturyRegister; >=20 > +}; >=20 > + >=20 > +/** >=20 > + PCH TCO SMI dispatch revision number >=20 > + >=20 > + Revision 1: Initial version >=20 > + Revision 2: Add NEWCENTURY support >=20 > +**/ >=20 > +#define PCH_TCO_SMI_DISPATCH_REVISION 2 >=20 > + >=20 > +#endif >=20 > diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Register/PchRe= gs.h > b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Register/PchRegs.h > new file mode 100644 > index 0000000000..679cb17f6c > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Register/PchRegs.h > @@ -0,0 +1,16 @@ > +/** @file >=20 > + Generic register definitions for PCH. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _PCH_REGS_H_ >=20 > +#define _PCH_REGS_H_ >=20 > + >=20 > +/// >=20 > +/// The default PCH PCI segment and bus number >=20 > +/// >=20 > +#define DEFAULT_PCI_SEGMENT_NUMBER_PCH 0 >=20 > +#define DEFAULT_PCI_BUS_NUMBER_PCH 0 >=20 > + >=20 > +#endif //_PCH_REGS_H_ >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Register/PchRegsLpc.h > b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Register/PchRegsLpc.h > new file mode 100644 > index 0000000000..32dd88be0e > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Register/PchRegsLpc.h > @@ -0,0 +1,145 @@ > +/** @file >=20 > + Register names for PCH LPC/eSPI device >=20 > + >=20 > +Conventions: >=20 > + >=20 > + - Register definition format: >=20 > + > Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterS > pace_RegisterName >=20 > + - Prefix: >=20 > + Definitions beginning with "R_" are registers >=20 > + Definitions beginning with "B_" are bits within registers >=20 > + Definitions beginning with "V_" are meaningful values within the bit= s >=20 > + Definitions beginning with "S_" are register size >=20 > + Definitions beginning with "N_" are the bit position >=20 > + - [GenerationName]: >=20 > + Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc= .). >=20 > + Register name without GenerationName applies to all generations. >=20 > + - [ComponentName]: >=20 > + This field indicates the component name that the register belongs to= (e.g. > PCH, SA etc.) >=20 > + Register name without ComponentName applies to all components. >=20 > + Register that is specific to -LP denoted by "_PCH_LP_" in component > name. >=20 > + - SubsystemName: >=20 > + This field indicates the subsystem name of the component that the > register belongs to >=20 > + (e.g. PCIE, USB, SATA, GPIO, PMC etc.). >=20 > + - RegisterSpace: >=20 > + MEM - MMIO space register of subsystem. >=20 > + IO - IO space register of subsystem. >=20 > + PCR - Private configuration register of subsystem. >=20 > + CFG - PCI configuration space register of subsystem. >=20 > + - RegisterName: >=20 > + Full register name. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _PCH_REGS_LPC_H_ >=20 > +#define _PCH_REGS_LPC_H_ >=20 > + >=20 > +#define B_LPC_CFG_DID 0xFFE0 >=20 > + >=20 > +// >=20 > +// PCI to LPC Bridge Registers >=20 > +// >=20 > + >=20 > +#define R_LPC_CFG_IOD 0x80 >=20 > +#define V_LPC_CFG_IOD_COMB_2F8 1 >=20 > +#define V_LPC_CFG_IOD_COMA_3F8 0 >=20 > +#define V_LPC_CFG_IOD_COMA_2F8 1 >=20 > +#define R_LPC_CFG_IOE 0x82 >=20 > +#define B_LPC_CFG_IOE_SE BIT12 ///< S= uper I/O Enable, > Enables decoding of I/O locations 2Eh and 2Fh to LPC. >=20 > +#define B_LPC_CFG_IOE_KE BIT10 ///< K= eyboard Enable, > Enables decoding of the keyboard I/O locations 60h and 64h to LPC. >=20 > +#define B_LPC_CFG_IOE_PPE BIT2 ///< P= arallel Port > Enable, Enables decoding of the LPT range to LPC. Range is selected by > LIOD.LPT. >=20 > +#define B_LPC_CFG_IOE_CBE BIT1 ///< C= om Port B > Enable, Enables decoding of the COMB range to LPC. Range is selected > LIOD.CB. >=20 > +#define B_LPC_CFG_IOE_CAE BIT0 ///< C= om Port A > Enable, Enables decoding of the COMA range to LPC. Range is selected > LIOD.CA. >=20 > +#define R_LPC_CFG_ULKMC 0x94 >=20 > +#define B_LPC_CFG_ULKMC_A20PASSEN BIT5 >=20 > +#define B_LPC_CFG_ULKMC_64WEN BIT3 >=20 > +#define B_LPC_CFG_ULKMC_64REN BIT2 >=20 > +#define B_LPC_CFG_ULKMC_60WEN BIT1 >=20 > +#define B_LPC_CFG_ULKMC_60REN BIT0 >=20 > +#define R_LPC_CFG_LGMR 0x98 >=20 > +#define B_LPC_CFG_LGMR_MA 0xFFFF0000 >=20 > +#define B_LPC_CFG_LGMR_LMRD_EN BIT0 >=20 > +#define R_ESPI_CFG_CS1IORE 0xA0 >=20 > +#define R_ESPI_CFG_CS1GMR1 0xA8 >=20 > + >=20 > +#define R_LPC_CFG_BDE 0xD8 = ///< BIOS decode > enable >=20 > + >=20 > +// >=20 > +// APM Registers >=20 > +// >=20 > +#define R_PCH_IO_APM_CNT 0xB2 >=20 > +#define R_PCH_IO_APM_STS 0xB3 >=20 > + >=20 > +#define R_LPC_CFG_BC 0xDC ///< B= ios Control >=20 > +#define S_LPC_CFG_BC 1 >=20 > +#define N_LPC_CFG_BC_LE 1 >=20 > +#define B_LPC_CFG_BC_WPD BIT0 ///< W= rite Protect > Disable >=20 > + >=20 > +#define R_ESPI_CFG_PCBC 0xDC ///< P= eripheral Channel > BIOS Control >=20 > +#define S_ESPI_CFG_PCBC 4 ///< P= eripheral Channel > BIOS Control register size >=20 > +#define B_ESPI_CFG_PCBC_BWRE BIT11 ///< B= IOS Write > Report Enable >=20 > +#define B_ESPI_CFG_PCBC_BWRS BIT10 ///< B= IOS Write > Report Status >=20 > +#define B_ESPI_CFG_PCBC_BWPDS BIT8 ///< B= IOS Write > Protect Disable Status >=20 > +#define N_ESPI_CFG_PCBC_BWPDS 8 ///< B= IOS Write > Protect Disable Status bit position >=20 > +#define B_ESPI_CFG_PCBC_ESPI_EN BIT2 ///< e= SPI Enable > Pin Strap >=20 > +#define B_ESPI_CFG_PCBC_LE BIT1 ///< L= ock Enable >=20 > +#define N_ESPI_CFG_PCBC_LE 1 >=20 > + >=20 > +// >=20 > +// eSPI slave registers >=20 > +// >=20 > +#define B_ESPI_SLAVE_BME BIT2 ///< B= us Master Enable >=20 > + >=20 > +// >=20 > +// Reset Generator I/O Port >=20 > +// >=20 > +#define R_PCH_IO_RST_CNT 0xCF9 >=20 > +#define V_PCH_IO_RST_CNT_FULLRESET 0x0E >=20 > +#define V_PCH_IO_RST_CNT_HARDRESET 0x06 >=20 > + >=20 > +// >=20 > +// eSPI PCR Registers >=20 > +// >=20 > +#define R_ESPI_PCR_SLV_CFG_REG_CTL 0x4000 //= /< Slave > Configuration Register and Link Control >=20 > +#define B_ESPI_PCR_SLV_CFG_REG_CTL_SCRE BIT31 //= /< Slave > Configuration Register Access Enable >=20 > +#define B_ESPI_PCR_SLV_CFG_REG_CTL_SCRS (BIT30 | BIT29 | BIT28) > ///< Slave Configuration Register Access Status >=20 > +#define N_ESPI_PCR_SLV_CFG_REG_CTL_SCRS 28 //= /< Slave > Configuration Register Access Status bit position >=20 > +#define B_ESPI_PCR_SLV_CFG_REG_CTL_SBLCL BIT27 //= /< > IOSF-SB eSPI Link Configuration Lock >=20 > +#define V_ESPI_PCR_SLV_CFG_REG_CTL_SCRS_NOERR 7 //= /< > No errors (transaction completed successfully) >=20 > +#define B_ESPI_PCR_SLV_CFG_REG_CTL_SID (BIT20 | BIT19) //= /< > Slave ID >=20 > +#define N_ESPI_PCR_SLV_CFG_REG_CTL_SID 19 //= /< Slave ID > bit position >=20 > +#define B_ESPI_PCR_SLV_CFG_REG_CTL_SCRT (BIT17 | BIT16) //= /< > Slave Configuration Register Access Type >=20 > +#define N_ESPI_PCR_SLV_CFG_REG_CTL_SCRT 16 //= /< Slave > Configuration Register Access Type bit position >=20 > +#define B_ESPI_PCR_SLV_CFG_REG_CTL_SCRA 0x00000FFF //= /< > Slave Configuration Register Address >=20 > +#define R_ESPI_PCR_SLV_CFG_REG_DATA 0x4004 //= /< Slave > Configuration Register Data >=20 > + >=20 > +#define R_ESPI_PCR_PCERR_SLV0 0x4020 ///< Perip= heral > Channel Error for Slave 0 >=20 > +#define B_ESPI_PCR_PCERR_PCURD BIT24 ///< Perip= heral > Channel Unsupported Request Detected >=20 > +#define R_ESPI_PCR_VWERR_SLV0 0x4030 ///< Virtu= al Wire > Channel Error for Slave 0 >=20 > +#define R_ESPI_PCR_FCERR_SLV0 0x4040 ///< Flash= Access > Channel Error for Slave 0 >=20 > +#define B_ESPI_PCR_FCERR_SAFBLK BIT17 ///< SAF B= locked > (SAFBLK) >=20 > +#define B_ESPI_PCR_XERR_XNFEE (BIT14 | BIT13) ///< Non-F= atal > Error Reporting Enable bits >=20 > +#define N_ESPI_PCR_XERR_XNFEE 13 ///< Non-F= atal Error > Reporting Enable bit position >=20 > +#define V_ESPI_PCR_XERR_XNFEE_SMI 3 ///< Enabl= e Non- > Fatal Error Reporting as SMI >=20 > +#define B_ESPI_PCR_XERR_XNFES BIT12 ///< Fatal= Error Status >=20 > +#define B_ESPI_PCR_XERR_XFEE (BIT6 | BIT5) ///< Fatal= Error > Reporting Enable bits >=20 > +#define N_ESPI_PCR_XERR_XFEE 5 ///< Fatal= Error > Reporting Enable bit position >=20 > +#define V_ESPI_PCR_XERR_XFEE_SMI 3 ///< Enabl= e Fatal > Error Reporting as SMI >=20 > +#define B_ESPI_PCR_XERR_XFES BIT4 ///< Fatal= Error Status >=20 > +#define S_ESPI_PCR_XERR 4 ///< Chann= el register sizes >=20 > +#define B_ESPI_PCR_PCERR_SLV0_PCURD BIT24 ///< Perip= heral > Channel Unsupported Request Detected >=20 > +#define R_ESPI_PCR_LNKERR_SLV0 0x4050 ///< Link = Error for > Slave 0 >=20 > +#define S_ESPI_PCR_LNKERR_SLV0 4 ///< Link = Error for Slave > 0 register size >=20 > +#define B_ESPI_PCR_LNKERR_SLV0_SLCRR BIT31 ///< eSPI = Link > and Slave Channel Recovery Required >=20 > +#define B_ESPI_PCR_LNKERR_SLV0_LFET1E (BIT22 | BIT21) ///< Fatal > Error Type 1 Reporting Enable >=20 > +#define N_ESPI_PCR_LNKERR_SLV0_LFET1E 21 ///< Fatal= Error > Type 1 Reporting Enable bit position >=20 > +#define V_ESPI_PCR_LNKERR_SLV0_LFET1E_SMI 3 ///< Enabl= e > Fatal Error Type 1 Reporting as SMI >=20 > +#define B_ESPI_PCR_LNKERR_SLV0_LFET1S BIT20 ///< Link = Fatal > Error Type 1 Status >=20 > +#define R_ESPI_PCR_LNKERR_SLV1 0x4054 ///< Link = Error for > Slave 1 >=20 > +#define R_ESPI_PCR_CFG_VAL 0xC00C ///< ESPI = Enabled > Strap >=20 > +#define B_ESPI_PCR_CFG_VAL_ESPI_EN BIT0 ///< ESPI = Enabled > Strap bit position >=20 > +#define R_ESPI_PCR_SOFTSTRAPS 0xC210 ///< eSPI = Sofstraps > Register 0 >=20 > +#define B_ESPI_PCR_SOFTSTRAPS_CS1_EN BIT12 ///< CS1# > Enable >=20 > + >=20 > +#endif >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Register/PchRegsPsf.h > b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Register/PchRegsPsf.h > new file mode 100644 > index 0000000000..dc32f1e5b3 > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Register/PchRegsPsf.h > @@ -0,0 +1,50 @@ > +/** @file >=20 > + Register definition for PSF component >=20 > + >=20 > + Conventions: >=20 > + >=20 > + - Register definition format: >=20 > + > Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterS > pace_RegisterName >=20 > + - Prefix: >=20 > + Definitions beginning with "R_" are registers >=20 > + Definitions beginning with "B_" are bits within registers >=20 > + Definitions beginning with "V_" are meaningful values within the bit= s >=20 > + Definitions beginning with "S_" are register size >=20 > + Definitions beginning with "N_" are the bit position >=20 > + - [GenerationName]: >=20 > + Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc= .). >=20 > + Register name without GenerationName applies to all generations. >=20 > + - [ComponentName]: >=20 > + This field indicates the component name that the register belongs to= (e.g. > PCH, SA etc.) >=20 > + Register name without ComponentName applies to all components. >=20 > + Register that is specific to -LP denoted by "_PCH_LP_" in component > name. >=20 > + - SubsystemName: >=20 > + This field indicates the subsystem name of the component that the > register belongs to >=20 > + (e.g. PCIE, USB, SATA, GPIO, PMC etc.). >=20 > + - RegisterSpace: >=20 > + MEM - MMIO space register of subsystem. >=20 > + IO - IO space register of subsystem. >=20 > + PCR - Private configuration register of subsystem. >=20 > + CFG - PCI configuration space register of subsystem. >=20 > + - RegisterName: >=20 > + Full register name. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _PCH_REGS_PSF_H_ >=20 > +#define _PCH_REGS_PSF_H_ >=20 > +// >=20 > +// PSFx segment registers >=20 > +// >=20 > + >=20 > +#define N_PCH_PSFX_PCR_MC_CONTROL_MCASTX_NUMMC 1 >=20 > +#define B_PCH_PSFX_PCR_MC_CONTROL_MCASTX_MULTCEN BIT0 >=20 > + >=20 > +// >=20 > +// PSFx PCRs definitions >=20 > +// >=20 > +#define B_PCH_PSFX_PCR_TARGET_PSFID 0xFF0000 >=20 > +#define N_PCH_PSFX_PCR_TARGET_PSFID 16 >=20 > + >=20 > +#endif >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Register/PchRegsPsth.h > b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Register/PchRegsPsth.h > new file mode 100644 > index 0000000000..2007eae44f > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Register/PchRegsPsth.= h > @@ -0,0 +1,66 @@ > +/** @file >=20 > + Register definition for PSTH component >=20 > + >=20 > + Conventions: >=20 > + >=20 > + - Register definition format: >=20 > + > Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterS > pace_RegisterName >=20 > + - Prefix: >=20 > + Definitions beginning with "R_" are registers >=20 > + Definitions beginning with "B_" are bits within registers >=20 > + Definitions beginning with "V_" are meaningful values within the bit= s >=20 > + Definitions beginning with "S_" are register size >=20 > + Definitions beginning with "N_" are the bit position >=20 > + - [GenerationName]: >=20 > + Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc= .). >=20 > + Register name without GenerationName applies to all generations. >=20 > + - [ComponentName]: >=20 > + This field indicates the component name that the register belongs to= (e.g. > PCH, SA etc.) >=20 > + Register name without ComponentName applies to all components. >=20 > + Register that is specific to -LP denoted by "_PCH_LP_" in component > name. >=20 > + - SubsystemName: >=20 > + This field indicates the subsystem name of the component that the > register belongs to >=20 > + (e.g. PCIE, USB, SATA, GPIO, PMC etc.). >=20 > + - RegisterSpace: >=20 > + MEM - MMIO space register of subsystem. >=20 > + IO - IO space register of subsystem. >=20 > + PCR - Private configuration register of subsystem. >=20 > + CFG - PCI configuration space register of subsystem. >=20 > + - RegisterName: >=20 > + Full register name. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _PCH_REGS_PSTH_H_ >=20 > +#define _PCH_REGS_PSTH_H_ >=20 > + >=20 > +// >=20 > +// Private chipset regsiter (Memory space) offset definition >=20 > +// The PCR register defines is used for PCR MMIO programming and PCH SBI > programming as well. >=20 > +// >=20 > + >=20 > +// >=20 > +// PSTH and IO Trap PCRs (PID:PSTH) >=20 > +// >=20 > +#define R_PSTH_PCR_PSTHCTL 0x1D00 ///< PSTH cont= rol > register >=20 > +#define B_PSTH_PCR_PSTHIOSFPTCGE BIT2 ///< PSTH IOSF > primary trunk clock gating enable >=20 > +#define R_PSTH_PCR_TRPST 0x1E00 ///< Trap stat= us regsiter >=20 > +#define R_PSTH_PCR_TRPC 0x1E10 ///< Trapped c= ycle >=20 > +#define B_PSTH_PCR_TRPC_RW BIT24 ///< Read/Writ= e#: > 1=3DRead, 0=3DWrite >=20 > +#define B_PSTH_PCR_TRPC_AHBE 0x00000000000F0000 ///< Active > high byte enables >=20 > +#define B_PSTH_PCR_TRPC_IOA 0x000000000000FFFC ///< Trap cycl= e > I/O address >=20 > +#define R_PSTH_PCR_TRPD 0x1E18 ///< Trapped w= rite data >=20 > +#define R_PSTH_PCR_TRPREG0 0x1E80 ///< IO Tarp 0= register >=20 > +#define R_PSTH_PCR_TRPREG1 0x1E88 ///< IO Tarp 1= register >=20 > +#define R_PSTH_PCR_TRPREG2 0x1E90 ///< IO Tarp 2= register >=20 > +#define R_PSTH_PCR_TRPREG3 0x1E98 ///< IO Tarp 3= register >=20 > +#define B_PSTH_PCR_TRPREG_RWM BIT17 ///< 49 - 32 f= or 32 bit > access, Read/Write mask >=20 > +#define B_PSTH_PCR_TRPREG_RWIO BIT16 ///< 48 - 32 f= or 32 bit > access, Read/Write#, 1=3DRead, 0=3DWrite >=20 > +#define N_PSTH_PCR_TRPREG_RWIO 16 ///< 48 - 32 f= or 32 bit > access, 16bit shift for Read/Write field >=20 > +#define N_PSTH_PCR_TRPREG_BEM 36 >=20 > +#define N_PSTH_PCR_TRPREG_BE 32 >=20 > +#define B_PSTH_PCR_TRPREG_AD 0x000000000000FFFC ///< IO > Address >=20 > +#define B_PSTH_PCR_TRPREG_TSE BIT0 ///< Trap and = SMI# > Enable >=20 > + >=20 > +#endif >=20 > -- > 2.24.0.windows.2