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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Nate DeSimone > -----Original Message----- > From: Luo, Heng > Sent: Sunday, January 31, 2021 5:36 PM > To: devel@edk2.groups.io > Cc: Chaganty, Rangasai V ; Desimone, > Nathaniel L > Subject: [PATCH 08/40] TigerlakeSiliconPkg/SystemAgent: Add IncludePrivat= e > headers >=20 > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3171 >=20 > Adds the following header files: > * SystemAgent/IncludePrivate >=20 > Cc: Sai Chaganty > Cc: Nate DeSimone > Signed-off-by: Heng Luo > --- >=20 > Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/IncludePrivate/Protocol/SaI= ot > rapSmi.h | 42 ++++++++++++++++++++++++++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/IncludePrivate/Protocol/SaN= v > sArea.h | 30 ++++++++++++++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/IncludePrivate/SaConfigHob. > h | 50 ++++++++++++++++++++++++++++++++++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/IncludePrivate/SaNvsAreaDef > .h | 222 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++ > 4 files changed, 344 insertions(+) >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/IncludePrivate/Protocol/S= aI > otrapSmi.h > b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/IncludePrivate/Protocol/S= aI > otrapSmi.h > new file mode 100644 > index 0000000000..2e86d497f9 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/IncludePrivate/Protocol/S= aI > otrapSmi.h > @@ -0,0 +1,42 @@ > +/** @file >=20 > + This file defines the SA Iotrap SMI Protocol to provide the >=20 > + I/O address for registered Iotrap SMI. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _SA_IOTRAP_SMI_PROTOCOL_H_ >=20 > +#define _SA_IOTRAP_SMI_PROTOCOL_H_ >=20 > + >=20 > +// >=20 > +// Extern the GUID for protocol users. >=20 > +// >=20 > +extern EFI_GUID gSaIotrapSmiProtocolGuid; >=20 > + >=20 > +#define SA_IOTRAP_SMI_PROTOCOL_REVISION_1 1 >=20 > + >=20 > +// >=20 > +// SA IO Trap SMI Protocol definition (Private protocol for RC internal = use > only) >=20 > +// >=20 > +typedef struct { >=20 > +/* >=20 > + Protocol revision number >=20 > + Any backwards compatible changes to this protocol will result in an upd= ate > in the revision number >=20 > + Major changes will require publication of a new protocol >=20 > + >=20 > + Revision 1: >=20 > + - First version >=20 > +*/ >=20 > + UINT8 Revision; >=20 > + UINT16 SaIotrapSmiAddress; >=20 > +} SA_IOTRAP_SMI_PROTOCOL; >=20 > + >=20 > +/// >=20 > +/// Pcie Trap valid types >=20 > +/// >=20 > +typedef enum { >=20 > + CpuPciePmTrap, >=20 > + CpuPcieTrapTypeMaximum >=20 > +} CPU_PCIE_TRAP_TYPE; >=20 > + >=20 > +#endif >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/IncludePrivate/Protocol/S= a > NvsArea.h > b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/IncludePrivate/Protocol/S= a > NvsArea.h > new file mode 100644 > index 0000000000..785a808cf4 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/IncludePrivate/Protocol/S= a > NvsArea.h > @@ -0,0 +1,30 @@ > +/** @file >=20 > + Definition of the System Agent global NVS area protocol. >=20 > + This protocol publishes the address and format of a global ACPI NVS bu= ffer >=20 > + used as a communications buffer between SMM/DXE/PEI code and ASL > code. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +#ifndef _SYSTEM_AGENT_NVS_AREA_H_ >=20 > +#define _SYSTEM_AGENT_NVS_AREA_H_ >=20 > + >=20 > +// >=20 > +// SA NVS Area definition >=20 > +// >=20 > +#include >=20 > + >=20 > +// >=20 > +// Extern the GUID for protocol users. >=20 > +// >=20 > +extern EFI_GUID gSaNvsAreaProtocolGuid; >=20 > + >=20 > +/// >=20 > +/// System Agent Global NVS Area Protocol >=20 > +/// >=20 > +typedef struct { >=20 > + SYSTEM_AGENT_NVS_AREA *Area; ///< System Agent Global NVS > Area Structure >=20 > +} SYSTEM_AGENT_NVS_AREA_PROTOCOL; >=20 > + >=20 > +#endif // _SYSTEM_AGENT_NVS_AREA_H_ >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/IncludePrivate/SaConfigHo > b.h > b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/IncludePrivate/SaConfigHo > b.h > new file mode 100644 > index 0000000000..65622069e6 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/IncludePrivate/SaConfigHo > b.h > @@ -0,0 +1,50 @@ > +/** @file >=20 > + The GUID definition for SaConfigHob >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _SA_CONFIG_HOB_H_ >=20 > +#define _SA_CONFIG_HOB_H_ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include "CpuPcieInfo.h" >=20 > +#include >=20 > + >=20 > +extern EFI_GUID gSaConfigHobGuid; >=20 > +#define SA_VTD_ENGINE_NUMBER 3 >=20 > + >=20 > +#pragma pack (push,1) >=20 > +/// >=20 > +/// DPR Directory Types >=20 > +/// >=20 > +typedef enum { >=20 > + EnumDprDirectoryTxt =3D 0, >=20 > +} DPR_DIRECTORY_ELEMENT; >=20 > + >=20 > +#define DPR_DIRECTORY_TYPE_TXT 0x01 ///< DPR directory typ= e - > TXT >=20 > +#define DPR_DIRECTORY_TYPE_BIOSGUARD 0x02 ///< DPR directory > type - BIOS Guard >=20 > +#define DPR_DIRECTORY_MAX 1 ///< DPR Maximum Size >=20 > + >=20 > +/// >=20 > +/// DPR directory entry definition >=20 > +/// >=20 > +typedef struct { >=20 > + UINT8 Type; ///< DPR Directory Type >=20 > + UINT8 Size; ///< DPR Size in MB >=20 > + UINT32 PhysBase; ///< Must be 4K aligned (bits 11..0 must be cle= ar) >=20 > + UINT16 Reserved; ///< Must be 0 >=20 > +} DPR_DIRECTORY_ENTRY; >=20 > + >=20 > +/// >=20 > +/// System Agent Config Hob >=20 > +/// >=20 > +typedef struct { >=20 > + EFI_HOB_GUID_TYPE EfiHobGuidType; ///= < GUID Hob > type structure for gSaConfigHobGuid >=20 > + DPR_DIRECTORY_ENTRY DprDirectory[DPR_DIRECTORY_MAX]; ///= < > DPR directory entry definition >=20 > + UINT8 ApertureSize; ///= < Aperture size value >=20 > + BOOLEAN CridEnable; ///= < This field inidicates if > CRID is enabled or disabled (to support Intel(R) SIPP) >=20 > +} SA_CONFIG_HOB; >=20 > +#pragma pack (pop) >=20 > +#endif >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/IncludePrivate/SaNvsAreaD > ef.h > b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/IncludePrivate/SaNvsAreaD > ef.h > new file mode 100644 > index 0000000000..6ee2343363 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/IncludePrivate/SaNvsAreaD > ef.h > @@ -0,0 +1,222 @@ > +// >=20 > +// Automatically generated by GenNvs ver 2.4.6 >=20 > +// Please DO NOT modify !!! >=20 > +// >=20 > + >=20 > +/** @file >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > + // >=20 > + // Define SA NVS Area operation region. >=20 > + // >=20 > +#ifndef _SA_NVS_AREA_DEF_H_ >=20 > +#define _SA_NVS_AREA_DEF_H_ >=20 > + >=20 > +#pragma pack (push,1) >=20 > +typedef struct { >=20 > + UINT32 IgdOpRegionAddress; ///< Offset 0 = IGD OpRegion > base address >=20 > + UINT8 GfxTurboIMON; ///< Offset 4 = IMON Current > Value >=20 > + UINT8 IgdState; ///< Offset 5 = IGD State (Primary > Display =3D 1) >=20 > + UINT8 IgdBootType; ///< Offset 6 = IGD Boot Display > Device >=20 > + UINT8 IgdPanelType; ///< Offset 7 = IGD Panel Type CMOS > option >=20 > + UINT8 IgdPanelScaling; ///< Offset 8 = IGD Panel Scaling >=20 > + UINT8 IgdBiaConfig; ///< Offset 9 = IGD BIA Configuration >=20 > + UINT8 IgdSscConfig; ///< Offset 10 = IGD SSC Configuration >=20 > + UINT8 IgdDvmtMemSize; ///< Offset 11 = IGD DVMT > Memory Size >=20 > + UINT8 IgdFunc1Enable; ///< Offset 12 = IGD Function 1 > Enable >=20 > + UINT8 IgdHpllVco; ///< Offset 13 = HPLL VCO >=20 > + UINT8 IgdSciSmiMode; ///< Offset 14 = GMCH SMI/SCI > mode (0=3DSCI) >=20 > + UINT8 IgdPAVP; ///< Offset 15 = IGD PAVP data >=20 > + UINT8 CurrentDeviceList; ///< Offset 16 = Current Attached > Device List >=20 > + UINT16 CurrentDisplayState; ///< Offset 17 = Current Display > State >=20 > + UINT16 NextDisplayState; ///< Offset 19 = Next Display State >=20 > + UINT8 NumberOfValidDeviceId; ///< Offset 21 = Number of > Valid Device IDs >=20 > + UINT32 DeviceId1; ///< Offset 22 = Device ID 1 >=20 > + UINT32 DeviceId2; ///< Offset 26 = Device ID 2 >=20 > + UINT32 DeviceId3; ///< Offset 30 = Device ID 3 >=20 > + UINT32 DeviceId4; ///< Offset 34 = Device ID 4 >=20 > + UINT32 DeviceId5; ///< Offset 38 = Device ID 5 >=20 > + UINT32 DeviceId6; ///< Offset 42 = Device ID 6 >=20 > + UINT32 DeviceId7; ///< Offset 46 = Device ID 7 >=20 > + UINT32 DeviceId8; ///< Offset 50 = Device ID 8 >=20 > + UINT32 DeviceId9; ///< Offset 54 = Device ID 9 >=20 > + UINT32 DeviceId10; ///< Offset 58 = Device ID 10 >=20 > + UINT32 DeviceId11; ///< Offset 62 = Device ID 11 >=20 > + UINT32 DeviceId12; ///< Offset 66 = Device ID 12 >=20 > + UINT32 DeviceId13; ///< Offset 70 = Device ID 13 >=20 > + UINT32 DeviceId14; ///< Offset 74 = Device ID 14 >=20 > + UINT32 DeviceId15; ///< Offset 78 = Device ID 15 >=20 > + UINT32 DeviceIdX; ///< Offset 82 = Device ID for eDP > device >=20 > + UINT32 NextStateDid1; ///< Offset 86 = Next state DID1 for > _DGS >=20 > + UINT32 NextStateDid2; ///< Offset 90 = Next state DID2 for > _DGS >=20 > + UINT32 NextStateDid3; ///< Offset 94 = Next state DID3 for > _DGS >=20 > + UINT32 NextStateDid4; ///< Offset 98 = Next state DID4 for > _DGS >=20 > + UINT32 NextStateDid5; ///< Offset 102 = Next state DID5 for > _DGS >=20 > + UINT32 NextStateDid6; ///< Offset 106 = Next state DID6 for > _DGS >=20 > + UINT32 NextStateDid7; ///< Offset 110 = Next state DID7 for > _DGS >=20 > + UINT32 NextStateDid8; ///< Offset 114 = Next state DID8 for > _DGS >=20 > + UINT32 NextStateDidEdp; ///< Offset 118 = Next state DID for > eDP >=20 > + UINT8 LidState; ///< Offset 122 = Lid State (Lid Open =3D 1) >=20 > + UINT32 AKsv0; ///< Offset 123 = First four bytes of AKSV > (manufacturing mode) >=20 > + UINT8 AKsv1; ///< Offset 127 = Fifth byte of AKSV > (manufacturing mode) >=20 > + UINT8 BrightnessPercentage; ///< Offset 128 = Brightness Level > Percentage >=20 > + UINT8 AlsEnable; ///< Offset 129 = Ambient Light Sensor > Enable >=20 > + UINT8 AlsAdjustmentFactor; ///< Offset 130 = Ambient Light > Adjusment Factor >=20 > + UINT8 LuxLowValue; ///< Offset 131 = LUX Low Value >=20 > + UINT8 LuxHighValue; ///< Offset 132 = LUX High Value >=20 > + UINT8 ActiveLFP; ///< Offset 133 = Active LFP >=20 > + UINT8 IpuAcpiMode; ///< Offset 134 = IPU ACPI device > type (0=3DDisabled, 1=3DAVStream virtual device as child of GFX) >=20 > + UINT8 EdpValid; ///< Offset 135 = Check for eDP display > device >=20 > + UINT8 HgMode; ///< Offset 136 = SG Mode (0=3DDisabled, > 1=3DHG Muxed, 2=3DHG Muxless, 3=3DDGPU Only) >=20 > + UINT8 HgFeatureList; ///< Offset 137 = HG Feature List >=20 > + UINT8 Pcie0GpioSupport; ///< Offset 138 = PCIe0 GPIO > Support (0=3DDisabled, 1=3DPCH Based, 2=3DI2C Based) >=20 > + UINT8 Pcie0HoldRstExpanderNo; ///< Offset 139 = PCIe0 HLD > RST IO Expander Number >=20 > + UINT32 Pcie0HoldRstGpioNo; ///< Offset 140 = PCIe0 HLD RST > GPIO Number >=20 > + UINT8 Pcie0HoldRstActiveInfo; ///< Offset 144 = PCIe0 HLD RST > GPIO Active Information >=20 > + UINT8 Pcie0PwrEnExpanderNo; ///< Offset 145 = PCIe0 PWR > Enable IO Expander Number >=20 > + UINT32 Pcie0PwrEnGpioNo; ///< Offset 146 = PCIe0 PWR > Enable GPIO Number >=20 > + UINT8 Pcie0PwrEnActiveInfo; ///< Offset 150 = PCIe0 PWR > Enable GPIO Active Information >=20 > + UINT8 Pcie1GpioSupport; ///< Offset 151 = PCIe1 GPIO > Support (0=3DDisabled, 1=3DPCH Based, 2=3DI2C Based) >=20 > + UINT8 Pcie1HoldRstExpanderNo; ///< Offset 152 = PCIe1 HLD > RST IO Expander Number >=20 > + UINT32 Pcie1HoldRstGpioNo; ///< Offset 153 = PCIe1 HLD RST > GPIO Number >=20 > + UINT8 Pcie1HoldRstActiveInfo; ///< Offset 157 = PCIe1 HLD RST > GPIO Active Information >=20 > + UINT8 Pcie1PwrEnExpanderNo; ///< Offset 158 = PCIe1 PWR > Enable IO Expander Number >=20 > + UINT32 Pcie1PwrEnGpioNo; ///< Offset 159 = PCIe1 PWR > Enable GPIO Number >=20 > + UINT8 Pcie1PwrEnActiveInfo; ///< Offset 163 = PCIe1 PWR > Enable GPIO Active Information >=20 > + UINT8 Pcie2GpioSupport; ///< Offset 164 = PCIe2 GPIO > Support (0=3DDisabled, 1=3DPCH Based, 2=3DI2C Based) >=20 > + UINT8 Pcie2HoldRstExpanderNo; ///< Offset 165 = PCIe2 HLD > RST IO Expander Number >=20 > + UINT32 Pcie2HoldRstGpioNo; ///< Offset 166 = PCIe2 HLD RST > GPIO Number >=20 > + UINT8 Pcie2HoldRstActiveInfo; ///< Offset 170 = PCIe2 HLD RST > GPIO Active Information >=20 > + UINT8 Pcie2PwrEnExpanderNo; ///< Offset 171 = PCIe2 PWR > Enable IO Expander Number >=20 > + UINT32 Pcie2PwrEnGpioNo; ///< Offset 172 = PCIe2 PWR > Enable GPIO Number >=20 > + UINT8 Pcie2PwrEnActiveInfo; ///< Offset 176 = PCIe2 PWR > Enable GPIO Active Information >=20 > + UINT8 Pcie3GpioSupport; ///< Offset 177 = PCIe3 GPIO > Support (0=3DDisabled, 1=3DPCH Based, 2=3DI2C Based) >=20 > + UINT8 Pcie3HoldRstExpanderNo; ///< Offset 178 = PCIe3 HLD > RST IO Expander Number >=20 > + UINT32 Pcie3HoldRstGpioNo; ///< Offset 179 = PCIe3 HLD RST > GPIO Number >=20 > + UINT8 Pcie3HoldRstActiveInfo; ///< Offset 183 = PCIe3 HLD RST > GPIO Active Information >=20 > + UINT8 Pcie3PwrEnExpanderNo; ///< Offset 184 = PCIe3 PWR > Enable IO Expander Number >=20 > + UINT32 Pcie3PwrEnGpioNo; ///< Offset 185 = PCIe3 PWR > Enable GPIO Number >=20 > + UINT8 Pcie3PwrEnActiveInfo; ///< Offset 189 = PCIe3 PWR > Enable GPIO Active Information >=20 > + UINT32 Pcie3WakeGpioNo; ///< Offset 190 = PCIe3 RTD3 > Device Wake GPIO Number >=20 > + UINT16 DelayAfterPwrEn; ///< Offset 194 = Delay after power > enable for PCIe >=20 > + UINT16 DelayAfterHoldReset; ///< Offset 196 = Delay after Hold > Reset for PCIe >=20 > + UINT8 Pcie0EpCapOffset; ///< Offset 198 = PCIe0 Endpoint > Capability Structure Offset >=20 > + UINT32 XPcieCfgBaseAddress; ///< Offset 199 = Any Device's > PCIe Config Space Base Address >=20 > + UINT16 GpioBaseAddress; ///< Offset 203 = GPIO Base > Address >=20 > + UINT32 NvIgOpRegionAddress; ///< Offset 205 = NVIG > opregion address >=20 > + UINT32 NvHmOpRegionAddress; ///< Offset 209 = NVHM > opregion address >=20 > + UINT32 ApXmOpRegionAddress; ///< Offset 213 = AMDA > opregion address >=20 > + UINT8 Peg0LtrEnable; ///< Offset 217 = Latency Tolerance > Reporting Enable >=20 > + UINT8 Peg0ObffEnable; ///< Offset 218 = Optimized Buffer > Flush and Fill >=20 > + UINT8 Peg1LtrEnable; ///< Offset 219 = Latency Tolerance > Reporting Enable >=20 > + UINT8 Peg1ObffEnable; ///< Offset 220 = Optimized Buffer > Flush and Fill >=20 > + UINT8 Peg2LtrEnable; ///< Offset 221 = Latency Tolerance > Reporting Enable >=20 > + UINT8 Peg2ObffEnable; ///< Offset 222 = Optimized Buffer > Flush and Fill >=20 > + UINT8 Peg3LtrEnable; ///< Offset 223 = Latency Tolerance > Reporting Enable >=20 > + UINT8 Peg3ObffEnable; ///< Offset 224 = Optimized Buffer > Flush and Fill >=20 > + UINT16 PegLtrMaxSnoopLatency; ///< Offset 225 = SA Peg > Latency Tolerance Reporting Max Snoop Latency >=20 > + UINT16 PegLtrMaxNoSnoopLatency; ///< Offset 227 = SA Peg > Latency Tolerance Reporting Max No Snoop Latency >=20 > + UINT64 Mmio64Base; ///< Offset 229 = Base of above 4GB > MMIO resource >=20 > + UINT64 Mmio64Length; ///< Offset 237 = Length of above > 4GB MMIO resource >=20 > + UINT32 CpuIdInfo; ///< Offset 245 = CPU ID info to get > Family Id or Stepping >=20 > + UINT32 Mmio32Base; ///< Offset 249 = Base of below 4GB > MMIO resource >=20 > + UINT32 Mmio32Length; ///< Offset 253 = Length of below > 4GB MMIO resource >=20 > + UINT32 Pcie0WakeGpioNo; ///< Offset 257 = PCIe0 RTD3 > Device Wake GPIO Number >=20 > + UINT32 Pcie1WakeGpioNo; ///< Offset 261 = PCIe1 RTD3 > Device Wake GPIO Number >=20 > + UINT32 Pcie2WakeGpioNo; ///< Offset 265 = PCIe2 RTD3 > Device Wake GPIO Number >=20 > + UINT8 VtdDisable; ///< Offset 269 = VT-d Enable/Disable >=20 > + UINT32 VtdBaseAddress[7]; ///< Offset 270 = VT-d Base > Address 1 >=20 > + ///< Offset 274 = VT-d Base Address 2 >=20 > + ///< Offset 278 = VT-d Base Address 3 >=20 > + ///< Offset 282 = VT-d Base Address 4 (iTBT PCIE0) >=20 > + ///< Offset 286 = VT-d Base Address 5 (iTBT PCIE1) >=20 > + ///< Offset 290 = VT-d Base Address 6 (iTBT PCIE2) >=20 > + ///< Offset 294 = VT-d Base Address 7 (iTBT PCIE3) >=20 > + UINT16 VtdEngine1Vid; ///< Offset 298 = VT-d Engine#1 > Vendor ID >=20 > + UINT16 VtdEngine2Vid; ///< Offset 300 = VT-d Engine#2 > Vendor ID >=20 > + UINT8 RootPortIndex; ///< Offset 302 = RootPort Number >=20 > + UINT32 RootPortAddress; ///< Offset 303 = RootPortAddress >=20 > + UINT8 CpuTraceHubMode; ///< Offset 307 = CPU Trace Hub > Mode >=20 > + UINT8 SimicsEnvironment; ///< Offset 308 = Simics > Environment information >=20 > + UINT8 ItbtXhciEn; ///< Offset 309 = TCSS XHCI Device > Enable >=20 > + UINT8 ItbtXdciEn; ///< Offset 310 = TCSS XDCI Device > Enable >=20 > + UINT8 ItbtDmaEn[2]; ///< Offset 311 = TCSS DMA 0 Device > Enable >=20 > + ///< Offset 312 = TCSS DMA 1 Device Enable >=20 > + UINT8 ItbtPcieRpEn[4]; ///< Offset 313 = TCSS ItbtPcieRp PCIE > RP 0 Device Enable >=20 > + ///< Offset 314 = TCSS ItbtPcieRp PCIE RP 1 Device > Enable >=20 > + ///< Offset 315 = TCSS ItbtPcieRp PCIE RP 2 Device > Enable >=20 > + ///< Offset 316 = TCSS ItbtPcieRp PCIE RP 3 Device > Enable >=20 > + UINT32 ItbtPcieRpAddress[4]; ///< Offset 317 = TCSS ItbtPcie > Root Port address 0 >=20 > + ///< Offset 321 = TCSS ItbtPcie Root Port address > 1 >=20 > + ///< Offset 325 = TCSS ItbtPcie Root Port address > 2 >=20 > + ///< Offset 329 = TCSS ItbtPcie Root Port address > 3 >=20 > + UINT32 TcssxDCIPwrDnScale; ///< Offset 333 = TCSS xDCI > Power Down Scale Value, DWC_USB3_GCTL_INIT[31:19] >=20 > + UINT8 TcssxDCIInt; ///< Offset 337 = TCSS xDCI Int Pin >=20 > + UINT8 TcssxDCIIrq; ///< Offset 338 = TCSS xDCI Irq Number >=20 > + UINT8 TcssRtd3; ///< Offset 339 = TCSS RTD3 >=20 > + UINT32 TcssDma0RmrrAddr; ///< Offset 340 = TCSS DMA0 > RMRR address >=20 > + UINT32 TcssDma1RmrrAddr; ///< Offset 344 = TCSS DMA1 > RMRR address >=20 > + UINT8 LtrEnable[4]; ///< Offset 348 = Latency Tolerance > Reporting Mechanism. 0: Disable; 1: Enable. >=20 > + ///< Offset 349 = Latency Tolerance Reporting > Mechanism. 0: Disable; 1: Enable. >=20 > + ///< Offset 350 = Latency Tolerance Reporting > Mechanism. 0: Disable; 1: Enable. >=20 > + ///< Offset 351 = Latency Tolerance Reporting > Mechanism. 0: Disable; 1: Enable. >=20 > + UINT16 PcieLtrMaxSnoopLatency[4]; ///< Offset 352 = PCIE LTR > max snoop Latency 0 >=20 > + ///< Offset 354 = PCIE LTR max snoop Latency 1 >=20 > + ///< Offset 356 = PCIE LTR max snoop Latency 2 >=20 > + ///< Offset 358 = PCIE LTR max snoop Latency 3 >=20 > + UINT16 PcieLtrMaxNoSnoopLatency[4]; ///< Offset 360 = PCIE LTR > max no snoop Latency 0 >=20 > + ///< Offset 362 = PCIE LTR max no snoop Latency > 1 >=20 > + ///< Offset 364 = PCIE LTR max no snoop Latency > 2 >=20 > + ///< Offset 366 = PCIE LTR max no snoop Latency > 3 >=20 > + UINT8 IomReady; ///< Offset 368 = IOM Ready >=20 > + UINT8 TcssIomVccSt; ///< Offset 369 = TCSS IOM VccSt >=20 > + UINT8 CpuPcieRp0Enable; ///< Offset 370 = <0:Disabled, > 1:Enabled> >=20 > + UINT8 CpuPcieRp1Enable; ///< Offset 371 = <0:Disabled, > 1:Enabled> >=20 > + UINT8 CpuPcieRp2Enable; ///< Offset 372 = <0:Disabled, > 1:Enabled> >=20 > + UINT8 CpuPcieRp3Enable; ///< Offset 373 = <0:Disabled, > 1:Enabled> >=20 > + UINT8 VmdEnable; ///< Offset 374 = VMD Device Enable >=20 > + UINT32 DeviceIdY; ///< Offset 375 = Device ID for second > LFP device >=20 > + UINT32 NextStateDidEdp2; ///< Offset 379 = Next state DID > for Second Display >=20 > + UINT8 SlotSelection; ///< Offset 383 = PCIe slot selection >=20 > + UINT8 VmdRp1to8; ///< Offset 384 = VMD PCH RP 1 to 8 > <0:Disabled, 1:Enabled> >=20 > + UINT8 VmdRp9to16; ///< Offset 385 = VMD PCH RP 9 to 16 > <0:Disabled, 1:Enabled> >=20 > + UINT8 VmdRp17to24; ///< Offset 386 = VMD PCH RP 17 to > 24 <0:Disabled, 1:Enabled> >=20 > + UINT8 VmdSataPort[8]; ///< Offset 387 = VMD SATA PORT 0 > <0:Disabled, 1:Enabled> >=20 > + ///< Offset 388 = VMD SATA PORT 1 <0:Disabled, > 1:Enabled> >=20 > + ///< Offset 389 = VMD SATA PORT 2 <0:Disabled, > 1:Enabled> >=20 > + ///< Offset 390 = VMD SATA PORT 3 <0:Disabled, > 1:Enabled> >=20 > + ///< Offset 391 = VMD SATA PORT 4 <0:Disabled, > 1:Enabled> >=20 > + ///< Offset 392 = VMD SATA PORT 5 <0:Disabled, > 1:Enabled> >=20 > + ///< Offset 393 = VMD SATA PORT 6 <0:Disabled, > 1:Enabled> >=20 > + ///< Offset 394 = VMD SATA PORT 7 <0:Disabled, > 1:Enabled> >=20 > + UINT8 VmdCpuRp; ///< Offset 395 = VMD CPU RP > <0:Disabled, 1:Enabled> >=20 > + UINT8 CpuPcieRtd3; ///< Offset 396 = RTD3 Support for > CPU PCIE. >=20 > + UINT32 LaneUsed; ///< Offset 397 = Lane Used of each CSI > Port <0:Not Configured, 1:x1, 2:x2, 3:x3 4:x4> >=20 > + UINT32 CsiSpeed; ///< Offset 401 = Speed of each CSI Port > <0:Not configured, 1:<416GMbps, 2:<1.5Gbps, 3:<2.0Gbps, 4:<2.5Gbps, > 5:<4Gbps, 6:>4Gbps> >=20 > + UINT8 MaxPegPortNumber; ///< Offset 405 = Max PEG port > number >=20 > + UINT8 MemBootMode; ///< Offset 406 = Current Memory > Boot Mode <0: BOOT_MODE_1LM(Default), 1: BOOT_MODE_2LM, 2: > BOOT_MODE_PROVISION> >=20 > + UINT8 DpmemSupport; ///< Offset 407 = Dynamic PMem > Support <0: Disabled, 1:Enabled> >=20 > + UINT64 PmemStartingAddress; ///< Offset 408 = Private Pmem > Starting address >=20 > + UINT64 PmemRangeLength; ///< Offset 416 = Private Pmem > Range Length >=20 > + UINT8 Pcie3EpCapOffset; ///< Offset 424 = PCIe3 Endpoint > Capability Structure Offset >=20 > + UINT8 Pcie0SrcClkNo; ///< Offset 425 = PCIe0 RTD3 Device > Source Clock Number >=20 > + UINT8 Pcie1SrcClkNo; ///< Offset 426 = PCIe1 RTD3 Device > Source Clock Number >=20 > + UINT8 Pcie2SrcClkNo; ///< Offset 427 = PCIe2 RTD3 Device > Source Clock Number >=20 > + UINT8 Pcie3SrcClkNo; ///< Offset 428 = PCIe2 RTD3 Device > Source Clock Number >=20 > + UINT8 Pcie0SecBusNum; ///< Offset 429 = PCIe0 Secondary > Bus Number (PCIe0 Endpoint Bus Number) >=20 > + UINT8 Pcie1SecBusNum; ///< Offset 430 = PCIe1 Secondary > Bus Number (PCIe0 Endpoint Bus Number) >=20 > + UINT8 Pcie2SecBusNum; ///< Offset 431 = PCIe2 Secondary > Bus Number (PCIe0 Endpoint Bus Number) >=20 > + UINT8 Pcie3SecBusNum; ///< Offset 432 = PCIe2 Secondary > Bus Number (PCIe0 Endpoint Bus Number) >=20 > + UINT8 Pcie1EpCapOffset; ///< Offset 433 = PCIe1 Endpoint > Capability Structure Offset >=20 > + UINT8 Pcie2EpCapOffset; ///< Offset 434 = PCIe2 Endpoint > Capability Structure Offset >=20 > + UINT8 IsBridgeDeviceBehindPeg1; ///< Offset 435 = Is bridge > device behind PEG1 >=20 > + UINT8 IsBridgeDeviceBehindPeg2; ///< Offset 436 = Is bridge > device behind PEG2 >=20 > + UINT8 IsBridgeDeviceBehindPeg3; ///< Offset 437 = Is bridge > device behind PEG3 >=20 > + UINT8 HgSlot; ///< Offset 438 = Slot selection between > PCH/PEG >=20 > +} SYSTEM_AGENT_NVS_AREA; >=20 > + >=20 > +#pragma pack(pop) >=20 > +#endif >=20 > -- > 2.24.0.windows.2