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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Nate DeSimone > -----Original Message----- > From: Luo, Heng > Sent: Sunday, January 31, 2021 5:37 PM > To: devel@edk2.groups.io > Cc: Chaganty, Rangasai V ; Desimone, > Nathaniel L > Subject: [PATCH 37/40] TigerlakeSiliconPkg/SystemAgent: Add SystemAgent > modules >=20 > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3171 >=20 > Adds the following files: > * SystemAgent/SaInit/Dxe > * SystemAgent/SaInit/Smm >=20 > Cc: Sai Chaganty > Cc: Nate DeSimone > Signed-off-by: Heng Luo > --- > Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/SaInit/Dxe/SaAcpi.c = | > 431 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInit.c = | 120 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++ > Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInit.h = | 58 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInitDxe.c = | > 181 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++ > Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInitDxe.h = | > 136 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInitDxe.inf = | > 117 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > + > Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/SaInit/Smm/CpuPcieSmm.c > | 454 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/SaInit/Smm/SaLateInitSmm.c > | 112 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/SaInit/Smm/SaLateInitSmm.h > | 122 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/SaInit/Smm/SaLateInitSmm.in > f | 72 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++ > 10 files changed, 1803 insertions(+) >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/SaInit/Dxe/SaAcpi.c > b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/SaInit/Dxe/SaAcpi.c > new file mode 100644 > index 0000000000..d84a0c1fa4 > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/SaInit/Dxe/SaAcpi.c > @@ -0,0 +1,431 @@ > +/** @file >=20 > + This is the driver that initializes the Intel System Agent. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#include "SaInitDxe.h" >=20 > +#include "SaInit.h" >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +/// >=20 > +/// Global Variables >=20 > +/// >=20 > +GLOBAL_REMOVE_IF_UNREFERENCED > SYSTEM_AGENT_NVS_AREA_PROTOCOL mSaNvsAreaProtocol; >=20 > +GLOBAL_REMOVE_IF_UNREFERENCED SA_POLICY_PROTOCOL > *mSaPolicy; >=20 > +extern SA_CONFIG_HOB *mSaConfig= Hob; >=20 > + >=20 > +/** >=20 > + A protocol callback which updates 64bits MMIO Base and Length in SA > GNVS area >=20 > +**/ >=20 > +VOID >=20 > +UpdateSaGnvsForMmioResourceBaseLength ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + EFI_PHYSICAL_ADDRESS PciBaseAddress; >=20 > + UINT32 Tolud; >=20 > + UINT64 Length; >=20 > + UINT64 McD0BaseAddress; >=20 > + UINTN ResMemLimit1; >=20 > + UINT8 EnableAbove4GBMmioBiosAssignemnt; >=20 > + HOST_BRIDGE_DATA_HOB *HostBridgeDataHob; >=20 > + >=20 > + PciBaseAddress =3D 0; >=20 > + Tolud =3D 0; >=20 > + Length =3D 0; >=20 > + ResMemLimit1 =3D 0; >=20 > + EnableAbove4GBMmioBiosAssignemnt =3D 0; >=20 > + HostBridgeDataHob =3D NULL; >=20 > + // >=20 > + // Read memory map registers >=20 > + // >=20 > + McD0BaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, > SA_MC_BUS, 0, 0, 0); >=20 > + Tolud =3D PciSegmentRead32 (McD0BaseAddress + R_SA_TO= LUD) & > B_SA_TOLUD_TOLUD_MASK; >=20 > + PciBaseAddress =3D Tolud; >=20 > + >=20 > + ResMemLimit1 =3D (UINTN) PcdGet64 (PcdSiPciExpressBaseAddress); >=20 > + >=20 > + Length =3D ResMemLimit1 - PciBaseAddress; >=20 > + >=20 > + // >=20 > + // Get HostBridgeData HOB and see if above 4GB MMIO BIOS assignment > enabled >=20 > + // >=20 > + HostBridgeDataHob =3D (HOST_BRIDGE_DATA_HOB *) GetFirstGuidHob > (&gHostBridgeDataHobGuid); >=20 > + if ((HostBridgeDataHob !=3D NULL) && (HostBridgeDataHob- > >EnableAbove4GBMmio =3D=3D 1)) { >=20 > + EnableAbove4GBMmioBiosAssignemnt =3D 1; >=20 > + } >=20 > + >=20 > + // >=20 > + // Enable Above 4GB MMIO when Aperture Size is 2GB or higher >=20 > + // >=20 > + if ((mSaConfigHob !=3D NULL) && (mSaConfigHob->ApertureSize >=3D 15)) = { >=20 > + EnableAbove4GBMmioBiosAssignemnt =3D 1; >=20 > + } >=20 > + >=20 > + // >=20 > + // Check Enable Above 4GB MMIO or not >=20 > + // >=20 > + >=20 > + DEBUG ((DEBUG_INFO, "Update SA GNVS Area.\n")); >=20 > + mSaNvsAreaProtocol.Area->Mmio32Base =3D (UINT32) PciBaseAddress; >=20 > + mSaNvsAreaProtocol.Area->Mmio32Length =3D (UINT32) Length; >=20 > + if (EnableAbove4GBMmioBiosAssignemnt =3D=3D 1) { >=20 > + mSaNvsAreaProtocol.Area->Mmio64Base =3D BASE_256GB; >=20 > + mSaNvsAreaProtocol.Area->Mmio64Length =3D SIZE_256GB; >=20 > + } >=20 > + DEBUG ((DEBUG_INFO, "SaNvsAreaProtocol.Area->Mmio64Base =3D %lx\n", > mSaNvsAreaProtocol.Area->Mmio64Base)); >=20 > + DEBUG ((DEBUG_INFO, "SaNvsAreaProtocol.Area->Mmio64Length =3D > %lx\n", mSaNvsAreaProtocol.Area->Mmio64Length)); >=20 > + DEBUG ((DEBUG_INFO, "SaNvsAreaProtocol.Area->Mmio32Base =3D %lx\n", > mSaNvsAreaProtocol.Area->Mmio32Base)); >=20 > + DEBUG ((DEBUG_INFO, "SaNvsAreaProtocol.Area->Mmio32Length =3D > %lx\n", mSaNvsAreaProtocol.Area->Mmio32Length)); >=20 > +} >=20 > + >=20 > +/** >=20 > + Install SSDT Table >=20 > + >=20 > + @retval EFI_SUCCESS - SSDT Table load successful. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +InstallSsdtAcpiTable ( >=20 > + IN GUID SsdtTableGuid, >=20 > + IN UINT64 Signature >=20 > + ) >=20 > +{ >=20 > + EFI_STATUS Status; >=20 > + EFI_HANDLE *HandleBuffer; >=20 > + BOOLEAN LoadTable; >=20 > + UINTN NumberOfHandles; >=20 > + UINTN Index; >=20 > + INTN Instance; >=20 > + UINTN Size; >=20 > + UINT32 FvStatus; >=20 > + UINTN TableHandle; >=20 > + EFI_FV_FILETYPE FileType; >=20 > + EFI_FV_FILE_ATTRIBUTES Attributes; >=20 > + EFI_FIRMWARE_VOLUME2_PROTOCOL *FwVol; >=20 > + EFI_ACPI_TABLE_PROTOCOL *AcpiTable; >=20 > + EFI_ACPI_DESCRIPTION_HEADER *TableHeader; >=20 > + EFI_ACPI_COMMON_HEADER *Table; >=20 > + >=20 > + FwVol =3D NULL; >=20 > + Table =3D NULL; >=20 > + >=20 > + DEBUG ((DEBUG_INFO, "Loading SSDT Table GUID: %g\n", > SsdtTableGuid)); >=20 > + >=20 > + /// >=20 > + /// Locate FV protocol. >=20 > + /// >=20 > + Status =3D gBS->LocateHandleBuffer ( >=20 > + ByProtocol, >=20 > + &gEfiFirmwareVolume2ProtocolGuid, >=20 > + NULL, >=20 > + &NumberOfHandles, >=20 > + &HandleBuffer >=20 > + ); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + >=20 > + /// >=20 > + /// Look for FV with ACPI storage file >=20 > + /// >=20 > + for (Index =3D 0; Index < NumberOfHandles; Index++) { >=20 > + /// >=20 > + /// Get the protocol on this handle >=20 > + /// This should not fail because of LocateHandleBuffer >=20 > + /// >=20 > + Status =3D gBS->HandleProtocol ( >=20 > + HandleBuffer[Index], >=20 > + &gEfiFirmwareVolume2ProtocolGuid, >=20 > + (VOID **) &FwVol >=20 > + ); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + if (FwVol =3D=3D NULL) { >=20 > + return EFI_NOT_FOUND; >=20 > + } >=20 > + /// >=20 > + /// See if it has the ACPI storage file >=20 > + /// >=20 > + Size =3D 0; >=20 > + FvStatus =3D 0; >=20 > + Status =3D FwVol->ReadFile ( >=20 > + FwVol, >=20 > + &SsdtTableGuid, >=20 > + NULL, >=20 > + &Size, >=20 > + &FileType, >=20 > + &Attributes, >=20 > + &FvStatus >=20 > + ); >=20 > + >=20 > + /// >=20 > + /// If we found it, then we are done >=20 > + /// >=20 > + if (!EFI_ERROR (Status)) { >=20 > + break; >=20 > + } >=20 > + } >=20 > + /// >=20 > + /// Our exit status is determined by the success of the previous opera= tions >=20 > + /// If the protocol was found, Instance already points to it. >=20 > + /// >=20 > + /// >=20 > + /// Free any allocated buffers >=20 > + /// >=20 > + FreePool (HandleBuffer); >=20 > + >=20 > + /// >=20 > + /// Sanity check that we found our data file >=20 > + /// >=20 > + ASSERT (FwVol); >=20 > + >=20 > + /// >=20 > + /// Locate ACPI tables >=20 > + /// >=20 > + Status =3D gBS->LocateProtocol (&gEfiAcpiTableProtocolGuid, NULL, (VOI= D > **) &AcpiTable); >=20 > + >=20 > + /// >=20 > + /// Read tables from the storage file. >=20 > + /// >=20 > + if (FwVol =3D=3D NULL) { >=20 > + ASSERT_EFI_ERROR (EFI_NOT_FOUND); >=20 > + return EFI_NOT_FOUND; >=20 > + } >=20 > + Instance =3D 0; >=20 > + >=20 > + while (Status =3D=3D EFI_SUCCESS) { >=20 > + /// >=20 > + /// Read the ACPI tables >=20 > + /// >=20 > + Status =3D FwVol->ReadSection ( >=20 > + FwVol, >=20 > + &SsdtTableGuid, >=20 > + EFI_SECTION_RAW, >=20 > + Instance, >=20 > + (VOID **) &Table, >=20 > + &Size, >=20 > + &FvStatus >=20 > + ); >=20 > + if (!EFI_ERROR (Status)) { >=20 > + /// >=20 > + /// check and load HybridGraphics SSDT table >=20 > + /// >=20 > + LoadTable =3D FALSE; >=20 > + TableHeader =3D (EFI_ACPI_DESCRIPTION_HEADER *) Table; >=20 > + >=20 > + if (((EFI_ACPI_DESCRIPTION_HEADER *) TableHeader)->OemTableId =3D= =3D > Signature) { >=20 > + /// >=20 > + /// This is the SSDT table that match the Signature >=20 > + /// >=20 > + DEBUG ((DEBUG_INFO, "Found out SSDT Table GUID: %g\n", > SsdtTableGuid)); >=20 > + LoadTable =3D TRUE; >=20 > + } >=20 > + >=20 > + /// >=20 > + /// Add the table >=20 > + /// >=20 > + if (LoadTable) { >=20 > + TableHandle =3D 0; >=20 > + Status =3D AcpiTable->InstallAcpiTable ( >=20 > + AcpiTable, >=20 > + TableHeader, >=20 > + TableHeader->Length, >=20 > + &TableHandle >=20 > + ); >=20 > + } >=20 > + /// >=20 > + /// Increment the instance >=20 > + /// >=20 > + Instance++; >=20 > + Table =3D NULL; >=20 > + } >=20 > + } >=20 > + >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > +/** >=20 > + This function gets registered as a callback to perform Dmar Igd >=20 > + >=20 > + @param[in] Event - A pointer to the Event that triggered the callb= ack. >=20 > + @param[in] Context - A pointer to private data registered with the > callback function. >=20 > +**/ >=20 > +VOID >=20 > +EFIAPI >=20 > +SaAcpiEndOfDxeCallback ( >=20 > + IN EFI_EVENT Event, >=20 > + IN VOID *Context >=20 > + ) >=20 > +{ >=20 > + EFI_STATUS Status; >=20 > + >=20 > + if (PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, > IGD_BUS_NUM, IGD_DEV_NUM, IGD_FUN_NUM, > PCI_VENDOR_ID_OFFSET)) !=3D 0xFFFF) { >=20 > + Status =3D PostPmInitEndOfDxe (); >=20 > + if (EFI_SUCCESS !=3D Status) { >=20 > + DEBUG ((DEBUG_WARN, "[SA] EndOfDxe GraphicsInit Error, Status =3D = %r > \n", Status)); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + } >=20 > + } >=20 > + >=20 > + if (PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, > IGD_BUS_NUM, IGD_DEV_NUM, IGD_FUN_NUM, > PCI_VENDOR_ID_OFFSET)) !=3D 0xFFFF) { >=20 > + Status =3D GetVBiosVbtEndOfDxe (); >=20 > + if (EFI_SUCCESS !=3D Status) { >=20 > + DEBUG ((DEBUG_WARN, "[SA] EndOfDxe Op Region Error, Status =3D %r > \n", Status)); >=20 > + } >=20 > + >=20 > + Status =3D UpdateIgdOpRegionEndOfDxe (); >=20 > + if (EFI_SUCCESS !=3D Status) { >=20 > + DEBUG ((DEBUG_WARN, "[SA] EndOfDxe Update Op Region Error, > Status =3D %r \n", Status)); >=20 > + } >=20 > + } >=20 > + >=20 > + return; >=20 > +} >=20 > + >=20 > +/** >=20 > + SystemAgent Acpi Initialization. >=20 > + >=20 > + @param[in] ImageHandle Handle for the image of this driver >=20 > + >=20 > + @retval EFI_SUCCESS The function completed successfully >=20 > + @retval EFI_OUT_OF_RESOURCES No enough buffer to allocate >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +SaAcpiInit ( >=20 > + IN EFI_HANDLE ImageHandle >=20 > + ) >=20 > +{ >=20 > + EFI_STATUS Status; >=20 > + EFI_CPUID_REGISTER CpuidRegs; >=20 > + EFI_EVENT EndOfDxeEvent; >=20 > + >=20 > + CPU_PCIE_HOB *CpuPcieHob; >=20 > + >=20 > + AsmCpuid (1, &CpuidRegs.RegEax, 0, 0, 0); >=20 > + /// >=20 > + /// Get the platform setup policy. >=20 > + /// >=20 > + Status =3D gBS->LocateProtocol (&gSaPolicyProtocolGuid, NULL, (VOID **= ) > &mSaPolicy); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + >=20 > + /// >=20 > + /// Install System Agent Global NVS protocol >=20 > + /// >=20 > + DEBUG ((DEBUG_INFO, "Install SA GNVS protocol\n")); >=20 > + Status =3D (gBS->AllocatePool) (EfiACPIMemoryNVS, sizeof > (SYSTEM_AGENT_NVS_AREA), (VOID **) &mSaNvsAreaProtocol.Area); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + ZeroMem ((VOID *) mSaNvsAreaProtocol.Area, sizeof > (SYSTEM_AGENT_NVS_AREA)); >=20 > + mSaNvsAreaProtocol.Area->XPcieCfgBaseAddress =3D (UINT32) (PcdGet64 > (PcdSiPciExpressBaseAddress)); >=20 > + mSaNvsAreaProtocol.Area->CpuIdInfo =3D CpuidRegs.RegEax; >=20 > + >=20 > + /// >=20 > + /// Get CpuPcieHob HOB >=20 > + /// >=20 > + CpuPcieHob =3D NULL; >=20 > + CpuPcieHob =3D (CPU_PCIE_HOB *) GetFirstGuidHob (&gCpuPcieHobGuid); >=20 > + if (CpuPcieHob =3D=3D NULL) { >=20 > + DEBUG((DEBUG_ERROR, "CpuPcieHob not found\n")); >=20 > + // @todo: Will add it back once it will get add into NVS library sin= ce > currently it is failing for JSL >=20 > + //ASSERT(CpuPcieHob !=3D NULL); >=20 > + //return EFI_NOT_FOUND; >=20 > + } else { >=20 > + mSaNvsAreaProtocol.Area->SlotSelection =3D CpuPcieHob->SlotSelection= ; >=20 > + DEBUG((DEBUG_INFO, "RpEnabledMask =3D=3D %x\n", CpuPcieHob- > >RpEnabledMask)); >=20 > + if (CpuPcieHob->RpEnabledMask =3D=3D 0) { >=20 > + DEBUG ((DEBUG_ERROR, "All CPU PCIe root ports are disabled!!\n")); >=20 > + } else { >=20 > + if (CpuPcieHob->RpEnabledMask & BIT0) { >=20 > + mSaNvsAreaProtocol.Area->CpuPcieRp0Enable =3D 1; >=20 > + } >=20 > + if (CpuPcieHob->RpEnabledMask & BIT1) { >=20 > + mSaNvsAreaProtocol.Area->CpuPcieRp1Enable =3D 1; >=20 > + } >=20 > + if (CpuPcieHob->RpEnabledMask & BIT2) { >=20 > + mSaNvsAreaProtocol.Area->CpuPcieRp2Enable =3D 1; >=20 > + } >=20 > + if (CpuPcieHob->RpEnabledMask & BIT3) { >=20 > + mSaNvsAreaProtocol.Area->CpuPcieRp3Enable =3D 1; >=20 > + } >=20 > + } >=20 > + mSaNvsAreaProtocol.Area->MaxPegPortNumber =3D > GetMaxCpuPciePortNum (); >=20 > + } >=20 > + >=20 > + mSaNvsAreaProtocol.Area->SimicsEnvironment =3D 0; >=20 > + >=20 > + Status =3D gBS->InstallMultipleProtocolInterfaces ( >=20 > + &ImageHandle, >=20 > + &gSaNvsAreaProtocolGuid, >=20 > + &mSaNvsAreaProtocol, >=20 > + NULL >=20 > + ); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + >=20 > + /// >=20 > + /// GtPostInit Initialization >=20 > + /// >=20 > + DEBUG ((DEBUG_INFO, "Initializing GT ACPI tables\n")); >=20 > + GraphicsInit (ImageHandle, mSaPolicy); >=20 > + >=20 > + /// >=20 > + /// Audio (dHDA) Initialization >=20 > + /// >=20 > + /// >=20 > + /// Vtd Initialization >=20 > + /// >=20 > + DEBUG ((DEBUG_INFO, "Initializing VT-d ACPI tables\n")); >=20 > + VtdInit (mSaPolicy); >=20 > + >=20 > + /// >=20 > + /// IgdOpRegion Install Initialization >=20 > + /// >=20 > + DEBUG ((DEBUG_INFO, "Initializing IGD OpRegion\n")); >=20 > + IgdOpRegionInit (); >=20 > + >=20 > + /// >=20 > + /// Register an end of DXE event for SA ACPI to do tasks before invoki= ng > any UEFI drivers, >=20 > + /// applications, or connecting consoles,... >=20 > + /// >=20 > + Status =3D gBS->CreateEventEx ( >=20 > + EVT_NOTIFY_SIGNAL, >=20 > + TPL_CALLBACK, >=20 > + SaAcpiEndOfDxeCallback, >=20 > + NULL, >=20 > + &gEfiEndOfDxeEventGroupGuid, >=20 > + &EndOfDxeEvent >=20 > + ); >=20 > + >=20 > + /// >=20 > + /// Install System Agent Global NVS ACPI table >=20 > + /// >=20 > + Status =3D InstallSsdtAcpiTable (gSaSsdtAcpiTableStorageGuid, > SIGNATURE_64 ('S', 'a', 'S', 's', 'd', 't', ' ', 0)); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + >=20 > + /// >=20 > + /// Update CPU PCIE RP NVS AREA >=20 > + /// >=20 > + UpdateCpuPcieNVS(); >=20 > + /// >=20 > + /// Install Intel Graphics SSDT >=20 > + /// >=20 > + Status =3D InstallSsdtAcpiTable (gGraphicsAcpiTableStorageGuid, > SIGNATURE_64 ('I','g','f','x','S','s','d','t')); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + >=20 > + /// >=20 > + /// Install IPU SSDT if IPU is present. >=20 > + /// >=20 > + if (PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, > IPU_BUS_NUM, IPU_DEV_NUM, IPU_FUN_NUM, 0)) !=3D > V_SA_DEVICE_ID_INVALID) { >=20 > + Status =3D InstallSsdtAcpiTable (gIpuAcpiTableStorageGuid, SIGNATU= RE_64 > ('I','p','u','S','s','d','t',0)); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + >=20 > + } >=20 > + >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > diff --git a/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/SaInit/Dxe/SaI= nit.c > b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInit.c > new file mode 100644 > index 0000000000..5c0fea422b > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInit.c > @@ -0,0 +1,120 @@ > +/** @file >=20 > + This is the Common driver that initializes the Intel System Agent. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#include "SaInit.h" >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +/// >=20 > +/// Global Variables >=20 > +/// >=20 > +GLOBAL_REMOVE_IF_UNREFERENCED SA_CONFIG_HOB > *mSaConfigHob; >=20 > +BOOLEAN mSk= ipPamLock =3D FALSE; >=20 > + >=20 > +/* >=20 > + Intel(R) Core Processor Skylake BWG version 0.4.0 >=20 > + >=20 > + 18.6 System Agent Configuration Locking >=20 > + For reliable operation and security, System BIOS must set the followi= ng > bits: >=20 > + 1. For all modern Intel processors, Intel strongly recommends that BI= OS > should set >=20 > + the D_LCK bit. Set B0:D0:F0.R088h [4] =3D 1b to lock down SMRAM s= pace. >=20 > + BaseAddr values for mSaSecurityRegisters that uses > PciExpressBaseAddress will be initialized at >=20 > + Runtime inside function CpuPcieInitPolicy(). >=20 > +*/ >=20 > +GLOBAL_REMOVE_IF_UNREFERENCED BOOT_SCRIPT_REGISTER_SETTING > mSaSecurityRegisters[] =3D { >=20 > + {0, R_SA_SMRAMC, 0xFFFFFFFF, BIT4} >=20 > +}; >=20 > + >=20 > +/** >=20 > + SystemAgent Initialization Common Function. >=20 > + >=20 > + @retval EFI_SUCCESS - Always. >=20 > +**/ >=20 > + >=20 > +VOID >=20 > +SaInitEntryPoint ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + HOST_BRIDGE_DATA_HOB *HostBridgeDataHob; >=20 > + >=20 > + /// >=20 > + /// Get Host Bridge Data HOB >=20 > + /// >=20 > + HostBridgeDataHob =3D NULL; >=20 > + HostBridgeDataHob =3D (HOST_BRIDGE_DATA_HOB *) GetFirstGuidHob > (&gHostBridgeDataHobGuid); >=20 > + if (HostBridgeDataHob !=3D NULL) { >=20 > + mSkipPamLock =3D HostBridgeDataHob->SkipPamLock; >=20 > + } >=20 > + return; >=20 > +} >=20 > + >=20 > +/** >=20 > + This function does SA security lock >=20 > +**/ >=20 > +VOID >=20 > +SaSecurityLock ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + UINT8 Index; >=20 > + UINT64 BaseAddress; >=20 > + UINT32 RegOffset; >=20 > + UINT32 Data32And; >=20 > + UINT32 Data32Or; >=20 > + >=20 > + /// >=20 > + /// 17.2 System Agent Security Lock configuration >=20 > + /// >=20 > + DEBUG ((DEBUG_INFO, "DXE SaSecurityLock\n")); >=20 > + for (Index =3D 0; Index < (sizeof (mSaSecurityRegisters) / sizeof > (BOOT_SCRIPT_REGISTER_SETTING)); Index++) { >=20 > + BaseAddress =3D mSaSecurityRegisters[Index].BaseAddr; >=20 > + RegOffset =3D mSaSecurityRegisters[Index].Offset; >=20 > + Data32And =3D mSaSecurityRegisters[Index].AndMask; >=20 > + Data32Or =3D mSaSecurityRegisters[Index].OrMask; >=20 > + >=20 > + if (RegOffset =3D=3D R_SA_SMRAMC) { >=20 > + /// >=20 > + /// SMRAMC LOCK must use CF8/CFC access >=20 > + /// >=20 > + PciCf8Or8 (PCI_CF8_LIB_ADDRESS (SA_MC_BUS, SA_MC_DEV, > SA_MC_FUN, R_SA_SMRAMC), (UINT8) Data32Or); >=20 > + BaseAddress =3D S3_BOOT_SCRIPT_LIB_PCI_ADDRESS (SA_MC_BUS, > SA_MC_DEV, SA_MC_FUN, R_SA_SMRAMC); >=20 > + S3BootScriptSavePciCfgReadWrite ( >=20 > + S3BootScriptWidthUint8, >=20 > + (UINTN) BaseAddress, >=20 > + &Data32Or, >=20 > + &Data32And >=20 > + ); >=20 > + } >=20 > + } >=20 > + >=20 > +} >=20 > + >=20 > +/** >=20 > + This function performs SA Security locking in EndOfDxe callback >=20 > + >=20 > + @retval EFI_SUCCESS - Security lock has done >=20 > + @retval EFI_UNSUPPORTED - Security lock not done successfully >=20 > +**/ >=20 > +EFI_STATUS >=20 > +SaSecurityInit ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + >=20 > + UINT8 Index; >=20 > + >=20 > + for (Index =3D 0; Index < (sizeof (mSaSecurityRegisters) / sizeof > (BOOT_SCRIPT_REGISTER_SETTING)); Index++) { >=20 > + if (mSaSecurityRegisters[Index].BaseAddr !=3D PcdGet64 > (PcdMchBaseAddress)) { >=20 > + mSaSecurityRegisters[Index].BaseAddr =3D PcdGet64 > (PcdSiPciExpressBaseAddress); >=20 > + } >=20 > + } >=20 > + SaSecurityLock (); >=20 > + >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > diff --git a/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/SaInit/Dxe/SaI= nit.h > b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInit.h > new file mode 100644 > index 0000000000..5c8f7dfd5f > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInit.h > @@ -0,0 +1,58 @@ > +/** @file >=20 > + Header file for SA Common Initialization Driver. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _SA_INITIALIZATION_DRIVER_H_ >=20 > +#define _SA_INITIALIZATION_DRIVER_H_ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +extern SA_POLICY_PROTOCOL *mSaPolicy; >=20 > +extern SA_CONFIG_HOB *SaConfigHob; >=20 > + >=20 > +typedef struct { >=20 > + UINT64 BaseAddr; >=20 > + UINT32 Offset; >=20 > + UINT32 AndMask; >=20 > + UINT32 OrMask; >=20 > +} BOOT_SCRIPT_REGISTER_SETTING; >=20 > + >=20 > +/** >=20 > + SystemAgent Initialization Common Function. >=20 > + >=20 > + @retval EFI_SUCCESS - Always. >=20 > +**/ >=20 > +VOID >=20 > +SaInitEntryPoint ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + This function performs SA Security locking in EndOfDxe callback >=20 > + >=20 > + @retval EFI_SUCCESS - Security lock has done >=20 > + @retval EFI_UNSUPPORTED - Security lock not done successfully >=20 > +**/ >=20 > +EFI_STATUS >=20 > +SaSecurityInit ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +#endif >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInitDxe.c > b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInitDxe.c > new file mode 100644 > index 0000000000..2a0e0accf5 > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInitDxe.= c > @@ -0,0 +1,181 @@ > +/** @file >=20 > + This is the driver that initializes the Intel System Agent. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#include "SaInitDxe.h" >=20 > +#include "SaInit.h" >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +GLOBAL_REMOVE_IF_UNREFERENCED UINT16 > mPcieIoTrapAddress; >=20 > + >=20 > +/// >=20 > +/// Global Variables >=20 > +/// >=20 > +extern SA_CONFIG_HOB *mSaConfigHob; >=20 > + >=20 > + >=20 > +/** >=20 > + SystemAgent Dxe Initialization. >=20 > + >=20 > + @param[in] ImageHandle Handle for the image of this driver >=20 > + @param[in] SystemTable Pointer to the EFI System Table >=20 > + >=20 > + @retval EFI_SUCCESS The function completed successfully >=20 > + @retval EFI_OUT_OF_RESOURCES No enough buffer to allocate >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +SaInitEntryPointDxe ( >=20 > + IN EFI_HANDLE ImageHandle, >=20 > + IN EFI_SYSTEM_TABLE *SystemTable >=20 > + ) >=20 > +{ >=20 > + EFI_STATUS Status; >=20 > + VOID *Registration; >=20 > + EFI_EVENT ReadyToBoot; >=20 > + >=20 > + >=20 > + DEBUG ((DEBUG_INFO, "SaInitDxe Start\n")); >=20 > + >=20 > + SaInitEntryPoint (); >=20 > + >=20 > + Status =3D SaAcpiInit (ImageHandle); >=20 > + /// >=20 > + /// Create PCI Enumeration Completed callback for CPU PCIe >=20 > + /// >=20 > + EfiCreateProtocolNotifyEvent ( >=20 > + &gEfiPciEnumerationCompleteProtocolGuid, >=20 > + TPL_CALLBACK, >=20 > + CpuPciEnumCompleteCallback, >=20 > + NULL, >=20 > + &Registration >=20 > + ); >=20 > + >=20 > + // >=20 > + // Register a Ready to boot event to config PCIE power management > setting after OPROM executed >=20 > + // >=20 > + Status =3D EfiCreateEventReadyToBootEx ( >=20 > + TPL_CALLBACK, >=20 > + SaOnReadyToBoot, >=20 > + NULL, >=20 > + &ReadyToBoot >=20 > + ); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + >=20 > + DEBUG ((DEBUG_INFO, "SaInitDxe End\n")); >=20 > + >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > +/** >=20 > + Do PCIE power management while resume from S3 >=20 > +**/ >=20 > +VOID >=20 > +ReconfigureCpuPciePowerManagementForS3 ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + EFI_STATUS Status; >=20 > + UINT32 Data32; >=20 > + SA_IOTRAP_SMI_PROTOCOL *CpuPcieIoTrapProtocol; >=20 > + >=20 > + Status =3D gBS->LocateProtocol (&gCpuPcieIoTrapProtocolGuid, NULL, (VO= ID > **) &CpuPcieIoTrapProtocol); >=20 > + if (EFI_ERROR (Status)) { >=20 > + return; >=20 > + } >=20 > + mPcieIoTrapAddress =3D CpuPcieIoTrapProtocol->SaIotrapSmiAddress; >=20 > + DEBUG ((DEBUG_INFO, "PcieIoTrapAddress: %0x\n", > mPcieIoTrapAddress)); >=20 > + >=20 > + if (mPcieIoTrapAddress !=3D 0) { >=20 > + // >=20 > + // Save PCH PCIE IoTrap address to re-config PCIE power management > setting after resume from S3 >=20 > + // >=20 > + Data32 =3D CpuPciePmTrap; >=20 > + S3BootScriptSaveIoWrite ( >=20 > + S3BootScriptWidthUint32, >=20 > + (UINTN) (mPcieIoTrapAddress), >=20 > + 1, >=20 > + &Data32 >=20 > + ); >=20 > + } else { >=20 > + ASSERT (FALSE); >=20 > + } >=20 > +} >=20 > + >=20 > + >=20 > +/** >=20 > + SA initialization before boot to OS >=20 > + >=20 > + @param[in] Event A pointer to the Event that triggered = the > callback. >=20 > + @param[in] Context A pointer to private data registered w= ith the > callback function. >=20 > +**/ >=20 > +VOID >=20 > +EFIAPI >=20 > +SaOnReadyToBoot ( >=20 > + IN EFI_EVENT Event, >=20 > + IN VOID *Context >=20 > + ) >=20 > +{ >=20 > + DEBUG ((DEBUG_INFO, "Uefi SaOnReadyToBoot() Start\n")); >=20 > + >=20 > + if (Event !=3D NULL) { >=20 > + gBS->CloseEvent (Event); >=20 > + } >=20 > + >=20 > + // >=20 > + // Trigger an Iotrap SMI to config PCIE power management setting after > PCI enumrate is done >=20 > + // >=20 > +#if FixedPcdGetBool(PcdCpuPcieEnable) =3D=3D 1 >=20 > + if (mPcieIoTrapAddress !=3D 0) { >=20 > + IoWrite32 ((UINTN) mPcieIoTrapAddress, CpuPciePmTrap); >=20 > + } else { >=20 > + ASSERT (FALSE); >=20 > + } >=20 > +#endif >=20 > + DEBUG ((DEBUG_INFO, "Uefi SaOnReadyToBoot() End\n")); >=20 > +} >=20 > + >=20 > + >=20 > +/** >=20 > + This function gets registered as a callback to perform CPU PCIe initia= lization > before EndOfDxe >=20 > + >=20 > + @param[in] Event - A pointer to the Event that triggered the callb= ack. >=20 > + @param[in] Context - A pointer to private data registered with the > callback function. >=20 > +**/ >=20 > +VOID >=20 > +EFIAPI >=20 > +CpuPciEnumCompleteCallback ( >=20 > + IN EFI_EVENT Event, >=20 > + IN VOID *Context >=20 > + ) >=20 > +{ >=20 > + EFI_STATUS Status; >=20 > + VOID *ProtocolPointer; >=20 > + >=20 > + DEBUG ((DEBUG_INFO, "CpuPciEnumCompleteCallback Start\n")); >=20 > + /// >=20 > + /// Check if this is first time called by EfiCreateProtocolNotifyEvent= () or > not, >=20 > + /// if it is, we will skip it until real event is triggered >=20 > + /// >=20 > + Status =3D gBS->LocateProtocol > (&gEfiPciEnumerationCompleteProtocolGuid, NULL, (VOID **) > &ProtocolPointer); >=20 > + if (EFI_SUCCESS !=3D Status) { >=20 > + return; >=20 > + } >=20 > + >=20 > + gBS->CloseEvent (Event); >=20 > + >=20 > + ReconfigureCpuPciePowerManagementForS3(); >=20 > + // >=20 > + // Routine for update DMAR >=20 > + // >=20 > + UpdateDmarEndOfPcieEnum (); >=20 > + >=20 > + UpdateSaGnvsForMmioResourceBaseLength (); >=20 > + DEBUG ((DEBUG_INFO, "CpuPciEnumCompleteCallback End\n")); >=20 > + return; >=20 > +} >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInitDxe.h > b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInitDxe.h > new file mode 100644 > index 0000000000..7110d049a8 > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInitDxe.= h > @@ -0,0 +1,136 @@ > +/** @file >=20 > + Header file for SA Initialization Driver. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _SA_INIT_DXE_DRIVER_H_ >=20 > +#define _SA_INIT_DXE_DRIVER_H_ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +/// >=20 > +/// Driver Consumed Protocol Prototypes >=20 > +/// >=20 > +#include >=20 > + >=20 > +extern EFI_GUID gSaAcpiTableStorageGuid; >=20 > +extern EFI_GUID gSaSsdtAcpiTableStorageGuid; >=20 > + >=20 > +typedef struct { >=20 > + UINT64 Address; >=20 > + EFI_BOOT_SCRIPT_WIDTH Width; >=20 > + UINT32 Value; >=20 > +} BOOT_SCRIPT_PCI_REGISTER_SAVE; >=20 > + >=20 > +/// >=20 > +/// Function Prototype >=20 > +/// >=20 > +/** >=20 > + This function gets registered as a callback to perform CPU PCIe initia= lization > before ExitPmAuth >=20 > + >=20 > + @param[in] Event - A pointer to the Event that triggered the callb= ack. >=20 > + @param[in] Context - A pointer to private data registered with the > callback function. >=20 > + >=20 > +**/ >=20 > +VOID >=20 > +EFIAPI >=20 > +CpuPciEnumCompleteCallback ( >=20 > + IN EFI_EVENT Event, >=20 > + IN VOID *Context >=20 > + ); >=20 > + >=20 > +/** >=20 > + System Agent Initialization DXE Driver Entry Point >=20 > + - Introduction \n >=20 > + Based on the information/data in SA_POLICY_PROTOCOL, this module > performs further SA initialization in DXE phase, >=20 > + e.g. internal devices enable/disable, SSVID/SID programming, graphic > power-management, VT-d, IGD OpRegion initialization. >=20 > + From the perspective of a PCI Express hierarchy, the Broadwell Syste= m > Agent and PCH together appear as a Root Complex with root ports the > number of which depends on how the 8 PCH ports and 4 System Agent PCIe > ports are configured [4x1, 2x8, 1x16]. >=20 > + There is an internal link (DMI or OPI) that connects the System Agen= t to > the PCH component. This driver includes initialization of SA DMI, PCI Exp= ress, > SA & PCH Root Complex Topology. >=20 > + For iGFX, this module implements the initialization of the Graphics > Technology Power Management from the Broadwell System Agent BIOS > Specification and the initialization of the IGD OpRegion/Software SCI - B= IOS > Specification. >=20 > + The ASL files that go along with the driver define the IGD OpRegion > mailboxes in ACPI space and implement the software SCI interrupt > mechanism. >=20 > + The IGD OpRegion/Software SCI code serves as a communication > interface between system BIOS, ASL, and Intel graphics driver including > making a block of customizable data (VBT) from the Intel video BIOS > available. >=20 > + Reference Code for the SCI service functions "Get BIOS Data" and > "System BIOS Callback" can be found in the ASL files, those functions can= be > platform specific, the sample provided in the reference code are > implemented for Intel CRB. >=20 > + This module implements the VT-d functionality described in the Broad= well > System Agent BIOS Specification. >=20 > + This module publishes the LegacyRegion protocol to control the read = and > write accesses to the Legacy BIOS ranges. >=20 > + E000 and F000 segments are the legacy BIOS ranges and contain pointe= rs > to the ACPI regions, SMBIOS tables and so on. This is a private protocol = used > by Intel Framework. >=20 > + This module registers CallBack function that performs SA security re= gisters > lockdown at end of post as required from Broadwell Bios Spec. >=20 > + In addition, this module publishes the SaInfo Protocol with informat= ion > such as current System Agent reference code version#. >=20 > + >=20 > + - @pre >=20 > + - EFI_FIRMWARE_VOLUME_PROTOCOL: Documented in Firmware > Volume Specification, available at the URL: > http://www.intel.com/technology/framework/spec.htm >=20 > + - SA_POLICY_PROTOCOL: A protocol published by a platform DXE module > executed earlier; this is documented in this document as well. >=20 > + - EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL: Documented in the Unified > Extensible Firmware Interface Specification, version 2.0, available at th= e URL: > http://www.uefi.org/specs/ >=20 > + - EFI_BOOT_SCRIPT_SAVE_PROTOCOL: A protocol published by a > platform DXE module executed earlier; refer to the Sample Code section of > the Framework PCH Reference Code. >=20 > + - EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL: > Documented in the Unified Extensible Firmware Interface Specification, > version 2.0, available at the URL: http://www.uefi.org/specs/ >=20 > + - EFI_ACPI_TABLE_PROTOCOL : Documented in PI Specification 1.2 >=20 > + - EFI_CPU_IO_PROTOCOL: Documented in CPU I/O Protocol Specification, > available at the URL: > http://www.intel.com/technology/framework/spec.htm >=20 > + - EFI_DATA_HUB_PROTOCOL: Documented in EFI Data Hub Infrastructure > Specification, available at the URL: > http://www.intel.com/technology/framework/spec.htm >=20 > + - EFI_HII_PROTOCOL (or EFI_HII_DATABASE_PROTOCOL for UEFI 2.1): > Documented in Human Interface Infrastructure Specification, available at = the > URL: http://www.intel.com/technology/framework/spec.htm >=20 > + (For EFI_HII_DATABASE_PROTOCOL, refer to UEFI Specification Version > 2.1 available at the URL: http://www.uefi.org/) >=20 > + >=20 > + - @result >=20 > + IGD power-management functionality is initialized; VT-d is initiali= zed > (meanwhile, the DMAR table is updated); IGD OpRegion is initialized - > IGD_OPREGION_PROTOCOL installed, IGD OpRegion allocated and mailboxes > initialized, chipset initialized and ready to generate Software SCI for I= nternal > graphics events. Publishes the SA_INFO_PROTOCOL with current SA > reference code version #. Publishes the EFI_LEGACY_REGION_PROTOCOL > documented in the Compatibility Support Module Specification, version 0.9= , > available at the URL: > http://www.intel.com/technology/framework/spec.htm >=20 > + >=20 > + - References \n >=20 > + IGD OpRegion/Software SCI for Broadwell >=20 > + Advanced Configuration and Power Interface Specification Revision 4.= 0a. >=20 > + >=20 > + - Porting Recommendations \n >=20 > + No modification of the DXE driver should be typically necessary. >=20 > + This driver should be executed after all related devices (audio, vid= eo, ME, > etc.) are initialized to ensure correct data in DMAR table and DMA-remapp= ing > registers. >=20 > + >=20 > + @param[in] ImageHandle Handle for the image of this driver >=20 > + @param[in] SystemTable Pointer to the EFI System Table >=20 > + >=20 > + @retval EFI_SUCCESS The function completed successfully >=20 > + @retval EFI_OUT_OF_RESOURCES No enough buffer to allocate >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +SaInitEntryPointDxe ( >=20 > + IN EFI_HANDLE ImageHandle, >=20 > + IN EFI_SYSTEM_TABLE *SystemTable >=20 > + ); >=20 > + >=20 > +/** >=20 > + SystemAgent Acpi Initialization. >=20 > + >=20 > + @param[in] ImageHandle Handle for the image of this driver >=20 > + >=20 > + @retval EFI_SUCCESS The function completed successfully >=20 > + @retval EFI_OUT_OF_RESOURCES No enough buffer to allocate >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +SaAcpiInit ( >=20 > + IN EFI_HANDLE ImageHandle >=20 > + ); >=20 > + >=20 > +/** >=20 > + A protocol callback which updates 64bits MMIO Base and Length in SA > GNVS area >=20 > +**/ >=20 > +VOID >=20 > +UpdateSaGnvsForMmioResourceBaseLength ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + SA initialization before boot to OS >=20 > + >=20 > + @param[in] Event A pointer to the Event that triggered = the > callback. >=20 > + @param[in] Context A pointer to private data registered w= ith the > callback function. >=20 > +**/ >=20 > +VOID >=20 > +EFIAPI >=20 > +SaOnReadyToBoot ( >=20 > + IN EFI_EVENT Event, >=20 > + IN VOID *Context >=20 > + ); >=20 > + >=20 > +#endif >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInitDxe.inf > b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInitDxe.inf > new file mode 100644 > index 0000000000..d23ba0fa3b > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInitDxe.inf > @@ -0,0 +1,117 @@ > +## @file >=20 > +# Component description file for SystemAgent Initialization driver >=20 > +# >=20 > +# Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > +# SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +# >=20 > +## >=20 > + >=20 > + >=20 > +[Defines] >=20 > +INF_VERSION =3D 0x00010017 >=20 > +BASE_NAME =3D SaInitDxe >=20 > +FILE_GUID =3D DE23ACEE-CF55-4fb6-AA77-984AB53DE811 >=20 > +VERSION_STRING =3D 1.0 >=20 > +MODULE_TYPE =3D DXE_DRIVER >=20 > +ENTRY_POINT =3D SaInitEntryPointDxe >=20 > +# >=20 > +# The following information is for reference only and not required by th= e > build tools. >=20 > +# >=20 > +# VALID_ARCHITECTURES =3D IA32 X64 EBC >=20 > +# >=20 > + >=20 > + >=20 > + >=20 > +[LibraryClasses] >=20 > +UefiDriverEntryPoint >=20 > +UefiLib >=20 > +UefiBootServicesTableLib >=20 > +DxeServicesTableLib >=20 > +DebugLib >=20 > +PciCf8Lib >=20 > +PciSegmentLib >=20 > +BaseMemoryLib >=20 > +MemoryAllocationLib >=20 > +IoLib >=20 > +S3BootScriptLib >=20 > +PmcLib >=20 > +PchInfoLib >=20 > +GpioLib >=20 > +ConfigBlockLib >=20 > +SaPlatformLib >=20 > +PchPcieRpLib >=20 > +DxeGraphicsInitLib >=20 > +DxeIgdOpRegionInitLib >=20 > +DxeVtdInitLib >=20 > +PciExpressHelpersLib >=20 > +DxeCpuPcieRpLib >=20 > +SataLib >=20 > + >=20 > +[Packages] >=20 > +TigerlakeSiliconPkg/SiPkg.dec >=20 > +MdePkg/MdePkg.dec >=20 > +UefiCpuPkg/UefiCpuPkg.dec >=20 > +IntelSiliconPkg/IntelSiliconPkg.dec >=20 > + >=20 > +[Pcd] >=20 > +gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress >=20 > +gSiPkgTokenSpaceGuid.PcdMchBaseAddress >=20 > +gSiPkgTokenSpaceGuid.PcdSiIoApicBaseAddress >=20 > +gSiPkgTokenSpaceGuid.PcdCpuPcieEnable ## CONSUMES >=20 > + >=20 > +[FixedPcd] >=20 > + >=20 > +[Sources] >=20 > +SaInitDxe.h >=20 > +SaInitDxe.c >=20 > +SaInit.h >=20 > +SaInit.c >=20 > +SaAcpi.c >=20 > + >=20 > + >=20 > +[Protocols] >=20 > +gEfiAcpiTableProtocolGuid ## CONSUMES >=20 > +gSaNvsAreaProtocolGuid ## PRODUCES >=20 > +gSaPolicyProtocolGuid ## CONSUMES >=20 > +gEfiCpuArchProtocolGuid ## CONSUMES >=20 > +gEfiPciEnumerationCompleteProtocolGuid ## CONSUMES >=20 > +gEfiPciRootBridgeIoProtocolGuid ## CONSUMES >=20 > +gIgdOpRegionProtocolGuid ## PRODUCES >=20 > +gEfiFirmwareVolume2ProtocolGuid ## CONSUMES >=20 > +gGopComponentName2ProtocolGuid ## CONSUMES >=20 > +gSaIotrapSmiProtocolGuid ## CONSUMES >=20 > +gCpuPcieIoTrapProtocolGuid ## CONSUMES >=20 > + >=20 > +[Guids] >=20 > +gSaConfigHobGuid >=20 > +gHgAcpiTablePchStorageGuid >=20 > +gSaAcpiTableStorageGuid >=20 > +gHgAcpiTableStorageGuid >=20 > +gSaSsdtAcpiTableStorageGuid >=20 > +gSegSsdtAcpiTableStorageGuid >=20 > +gTcssSsdtAcpiTableStorageGuid >=20 > +gGraphicsAcpiTableStorageGuid >=20 > +gIpuAcpiTableStorageGuid >=20 > +gEfiEndOfDxeEventGroupGuid >=20 > +gSiConfigHobGuid ## CONSUMES >=20 > +gGraphicsDxeConfigGuid >=20 > +gMemoryDxeConfigGuid >=20 > +gPcieDxeConfigGuid >=20 > +gPchInfoHobGuid >=20 > +gTcssHobGuid >=20 > +gSaConfigHobGuid >=20 > +gSaDataHobGuid >=20 > +gCpuPcieHobGuid >=20 > +gHostBridgeDataHobGuid >=20 > +gVmdInfoHobGuid ## CONSUMES >=20 > + >=20 > +[FixedPcd] >=20 > + >=20 > +[Depex] >=20 > +gEfiAcpiTableProtocolGuid AND >=20 > +gEfiFirmwareVolume2ProtocolGuid AND >=20 > +gSaPolicyProtocolGuid AND >=20 > +gEfiPciRootBridgeIoProtocolGuid AND >=20 > +gEfiPciHostBridgeResourceAllocationProtocolGuid AND # This is to ensure > that PCI MMIO resource has been prepared and available for this driver to > allocate. >=20 > +gEfiHiiDatabaseProtocolGuid >=20 > + >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/SaInit/Smm/CpuPcieSmm.c > b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/SaInit/Smm/CpuPcieSmm.c > new file mode 100644 > index 0000000000..70d47e787f > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/SaInit/Smm/CpuPcieSmm.c > @@ -0,0 +1,454 @@ > +/** @file >=20 > + CPU PCIe SMM Driver Entry >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#include "SaLateInitSmm.h" >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mSaBusNumber; >=20 > +// >=20 > +// @note: >=20 > +// These temp bus numbers cannot be used in runtime (hot-plug). >=20 > +// These can be used only during boot. >=20 > +// >=20 > +GLOBAL_REMOVE_IF_UNREFERENCED UINT8 > mTempRootPortBusNumMin; >=20 > +GLOBAL_REMOVE_IF_UNREFERENCED UINT8 > mTempRootPortBusNumMax; >=20 > +GLOBAL_REMOVE_IF_UNREFERENCED CPU_PCIE_ROOT_PORT_CONFIG > mCpuPcieRootPortConfig[CPU_PCIE_MAX_ROOT_PORTS]; >=20 > +GLOBAL_REMOVE_IF_UNREFERENCED BOOLEAN > mCpuPciePmTrapExecuted =3D FALSE; >=20 > +GLOBAL_REMOVE_IF_UNREFERENCED PCH_PCIE_DEVICE_OVERRIDE > *mDevAspmOverride; >=20 > +GLOBAL_REMOVE_IF_UNREFERENCED UINT32 > mNumOfDevAspmOverride; >=20 > + >=20 > +/** >=20 > + An IoTrap callback to config PCIE power management settings >=20 > +**/ >=20 > +VOID >=20 > +CpuPciePmIoTrapSmiCallback ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + UINT32 PortIndex; >=20 > + UINT64 RpBase; >=20 > + UINT8 MaxPciePortNum; >=20 > + UINTN RpDevice; >=20 > + UINTN RpFunction; >=20 > + >=20 > + MaxPciePortNum =3D GetMaxCpuPciePortNum (); >=20 > + >=20 > + for (PortIndex =3D 0; PortIndex < MaxPciePortNum; PortIndex++) { >=20 > + GetCpuPcieRpDevFun (PortIndex, &RpDevice, &RpFunction); >=20 > + RpBase =3D PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, SA_MC_BUS, > (UINT32) RpDevice, (UINT32) RpFunction, 0); >=20 > + >=20 > + if (PciSegmentRead16 (RpBase) !=3D 0xFFFF) { >=20 > + mDevAspmOverride =3D NULL; >=20 > + mNumOfDevAspmOverride =3D 0; >=20 > + RootportDownstreamPmConfiguration ( >=20 > + SA_SEG_NUM, >=20 > + SA_MC_BUS, >=20 > + (UINT8)RpDevice, >=20 > + (UINT8)RpFunction, >=20 > + mTempRootPortBusNumMin, >=20 > + mTempRootPortBusNumMax, >=20 > + &mCpuPcieRootPortConfig[PortIndex].PcieRpCommonConfig, >=20 > + mNumOfDevAspmOverride, >=20 > + mDevAspmOverride >=20 > + ); >=20 > + >=20 > + } >=20 > + } >=20 > +} >=20 > + >=20 > +/** >=20 > + Program Common Clock and ASPM of Downstream Devices >=20 > + >=20 > + @param[in] PortIndex Pcie Root Port Number >=20 > + @param[in] RpDevice Pcie Root Pci Device Number >=20 > + @param[in] RpFunction Pcie Root Pci Function Number >=20 > + >=20 > + @retval EFI_SUCCESS Root port complete successfully >=20 > + @retval EFI_UNSUPPORTED PMC has invalid vendor ID >=20 > +**/ >=20 > +EFI_STATUS >=20 > +CpuPcieSmi ( >=20 > + IN UINT8 PortIndex, >=20 > + IN UINT8 RpDevice, >=20 > + IN UINT8 RpFunction >=20 > + ) >=20 > +{ >=20 > + UINT8 SecBus; >=20 > + UINT8 SubBus; >=20 > + UINT64 RpBase; >=20 > + UINT64 EpBase; >=20 > + UINT8 EpPcieCapPtr; >=20 > + UINT8 EpMaxSpeed; >=20 > + BOOLEAN DownstreamDevicePresent; >=20 > + UINT32 Timeout; >=20 > + UINT32 MaxLinkSpeed; >=20 > + >=20 > + RpBase =3D PCI_SEGMENT_LIB_ADDRESS ( >=20 > + SA_SEG_NUM, >=20 > + SA_MC_BUS, >=20 > + (UINT32) RpDevice, >=20 > + (UINT32) RpFunction, >=20 > + 0 >=20 > + ); >=20 > + >=20 > + if (PciSegmentRead16 (RpBase + PCI_VENDOR_ID_OFFSET) =3D=3D 0xFFFF) { >=20 > + DEBUG((DEBUG_INFO, "PCIe controller is disabled, return!!\n")); >=20 > + return EFI_SUCCESS; >=20 > + } >=20 > + // >=20 > + // Check presence detect state. Here the endpoint must be detected usi= ng > PDS rather than >=20 > + // the usual LinkActive check, because PDS changes immediately and LA > takes a few milliseconds to stabilize >=20 > + // >=20 > + DownstreamDevicePresent =3D !!(PciSegmentRead16 (RpBase + > R_PCIE_SLSTS) & B_PCIE_SLSTS_PDS); >=20 > + >=20 > + if (DownstreamDevicePresent) { >=20 > + /// >=20 > + /// Make sure the link is active before trying to talk to device beh= ind it >=20 > + /// Wait up to 100ms, according to PCIE spec chapter 6.7.3.3 >=20 > + /// >=20 > + Timeout =3D 100 * 1000; >=20 > + while (CpuPcieIsLinkActive(RpBase) =3D=3D 0) { >=20 > + MicroSecondDelay (10); >=20 > + Timeout-=3D10; >=20 > + if (Timeout =3D=3D 0) { >=20 > + DEBUG((DEBUG_INFO, "PDS set but timeout while waiting for LA bit= to > get set!!!\n")); >=20 > + return EFI_NOT_FOUND; >=20 > + } >=20 > + } >=20 > + SecBus =3D PciSegmentRead8 (RpBase + > PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET); >=20 > + SubBus =3D PciSegmentRead8 (RpBase + > PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET); >=20 > + ASSERT (SecBus !=3D 0 && SubBus !=3D 0); >=20 > + if (SecBus =3D=3D 0) { >=20 > + DEBUG((DEBUG_INFO, "Secondary Bus is 0, return!!!\n")); >=20 > + return EFI_NOT_FOUND; >=20 > + } >=20 > + RootportDownstreamConfiguration ( >=20 > + SA_SEG_NUM, >=20 > + SA_MC_BUS, >=20 > + RpDevice, >=20 > + RpFunction, >=20 > + mTempRootPortBusNumMin, >=20 > + mTempRootPortBusNumMax, >=20 > + EnumCpuPcie >=20 > + ); >=20 > + RootportDownstreamPmConfiguration ( >=20 > + SA_SEG_NUM, >=20 > + SA_MC_BUS, >=20 > + RpDevice, >=20 > + RpFunction, >=20 > + mTempRootPortBusNumMin, >=20 > + mTempRootPortBusNumMax, >=20 > + &mCpuPcieRootPortConfig[PortIndex].PcieRpCommonConfig, >=20 > + mNumOfDevAspmOverride, >=20 > + mDevAspmOverride >=20 > + ); >=20 > + // >=20 > + // Perform Equalization >=20 > + // >=20 > + EpBase =3D PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, SecBus, 0, 0, 0); >=20 > + EpPcieCapPtr =3D PcieFindCapId (SA_SEG_NUM, SecBus, 0, 0, > EFI_PCI_CAPABILITY_ID_PCIEXP); >=20 > + EpMaxSpeed =3D PciSegmentRead8 (EpBase + EpPcieCapPtr + > R_PCIE_LCAP_OFFSET) & B_PCIE_LCAP_MLS; >=20 > + MaxLinkSpeed =3D CpuPcieGetMaxLinkSpeed (RpBase); >=20 > + if (EpMaxSpeed < MaxLinkSpeed) { >=20 > + MaxLinkSpeed =3D EpMaxSpeed; >=20 > + } >=20 > + if (EpMaxSpeed >=3D V_PCIE_LCAP_MLS_GEN3 && EpMaxSpeed <=3D > V_PCIE_LCAP_MLS_GEN4) { >=20 > + PciSegmentAndThenOr16 (RpBase + R_PCIE_LCTL2, > (UINT16)~B_PCIE_LCTL2_TLS, (UINT16)MaxLinkSpeed); >=20 > + PciSegmentOr32 (RpBase + R_PCIE_LCTL3, B_PCIE_LCTL3_PE); >=20 > + PciSegmentOr32 (RpBase + R_PCIE_LCTL, B_PCIE_LCTL_RL); >=20 > + } >=20 > + } >=20 > + >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > +/** >=20 > + PCIE Hotplug SMI call back function for each Root port >=20 > + >=20 > + @param[in] DispatchHandle Handle of this dispatch function >=20 > + @param[in] RpContext Rootport context, which contains= RootPort > Index, >=20 > + and RootPort PCI BDF. >=20 > +**/ >=20 > +VOID >=20 > +EFIAPI >=20 > +CpuPcieSmiRpHandlerFunction ( >=20 > + IN EFI_HANDLE DispatchHandle, >=20 > + IN PCH_PCIE_SMI_RP_CONTEXT *RpContext >=20 > + ) >=20 > +{ >=20 > + CpuPcieSmi (RpContext->RpIndex, RpContext->DevNum, RpContext- > >FuncNum); >=20 > +} >=20 > + >=20 > +/** >=20 > + PCIE Link Active State Change Hotplug SMI call back function for all R= oot > ports >=20 > + >=20 > + @param[in] DispatchHandle Handle of this dispatch function >=20 > + @param[in] RpContext Rootport context, which contains= RootPort > Index, >=20 > + and RootPort PCI BDF. >=20 > +**/ >=20 > +VOID >=20 > +EFIAPI >=20 > +CpuPcieLinkActiveStateChange ( >=20 > + IN EFI_HANDLE DispatchHandle, >=20 > + IN PCH_PCIE_SMI_RP_CONTEXT *RpContext >=20 > + ) >=20 > +{ >=20 > + return; >=20 > +} >=20 > + >=20 > +/** >=20 > + PCIE Link Equalization Request SMI call back function for all Root por= ts >=20 > + >=20 > + @param[in] DispatchHandle Handle of this dispatch function >=20 > + @param[in] RpContext Rootport context, which contains= RootPort > Index, >=20 > + and RootPort PCI BDF. >=20 > +**/ >=20 > +VOID >=20 > +EFIAPI >=20 > +CpuPcieLinkEqHandlerFunction ( >=20 > + IN EFI_HANDLE DispatchHandle, >=20 > + IN PCH_PCIE_SMI_RP_CONTEXT *RpContext >=20 > + ) >=20 > +{ >=20 > + /// >=20 > + /// From PCI Express specification, the PCIe device can request for Li= nk > Equalization. When the >=20 > + /// Link Equalization is requested by the device, an SMI will be gener= ated > by PCIe RP when >=20 > + /// enabled and the SMI subroutine would invoke the Software > Preset/Coefficient Search >=20 > + /// software to re-equalize the link. >=20 > + /// >=20 > + >=20 > + return; >=20 > + >=20 > +} >=20 > +/** >=20 > + An IoTrap callback to config PCIE power management settings >=20 > + >=20 > + @param[in] DispatchHandle - The handle of this callback, obtained whe= n > registering >=20 > + @param[in] DispatchContext - Pointer to the > EFI_SMM_IO_TRAP_DISPATCH_CALLBACK_CONTEXT >=20 > + >=20 > +**/ >=20 > +VOID >=20 > +EFIAPI >=20 > +CpuPcieIoTrapSmiCallback ( >=20 > + IN EFI_HANDLE DispatchHandle, >=20 > + IN EFI_SMM_IO_TRAP_CONTEXT *CallbackContext, >=20 > + IN OUT VOID *CommBuffer, >=20 > + IN OUT UINTN *CommBufferSize >=20 > + ) >=20 > +{ >=20 > + if (CallbackContext->WriteData =3D=3D CpuPciePmTrap) { >=20 > + if (mCpuPciePmTrapExecuted =3D=3D FALSE) { >=20 > + CpuPciePmIoTrapSmiCallback (); >=20 > + mCpuPciePmTrapExecuted =3D TRUE; >=20 > + } >=20 > + } else { >=20 > + ASSERT_EFI_ERROR (EFI_INVALID_PARAMETER); >=20 > + } >=20 > +} >=20 > + >=20 > +/** >=20 > + This function clear the Io trap executed flag before enter S3 >=20 > + >=20 > + @param[in] Handle Handle of the callback >=20 > + @param[in] Context The dispatch context >=20 > + >=20 > + @retval EFI_SUCCESS SA register saved >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +CpuPcieS3EntryCallBack ( >=20 > + IN EFI_HANDLE Handle, >=20 > + IN CONST VOID *Context OPTIONAL, >=20 > + IN OUT VOID *CommBuffer OPTIONAL, >=20 > + IN OUT UINTN *CommBufferSize OPTIONAL >=20 > + ) >=20 > +{ >=20 > + mCpuPciePmTrapExecuted =3D FALSE; >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > +/** >=20 > + Register PCIE Hotplug SMI dispatch function to handle Hotplug enabling >=20 > + >=20 > + @param[in] ImageHandle The image handle of this module >=20 > + @param[in] SystemTable The EFI System Table >=20 > + >=20 > + @retval EFI_SUCCESS The function completes successfully >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +InitializeCpuPcieSmm ( >=20 > + IN EFI_HANDLE ImageHandle, >=20 > + IN EFI_SYSTEM_TABLE *SystemTable >=20 > + ) >=20 > +{ >=20 > + EFI_STATUS Status; >=20 > + UINT8 PortIndex; >=20 > + UINT8 Data8; >=20 > + UINT32 Data32Or; >=20 > + UINT32 Data32And; >=20 > + UINT64 RpBase; >=20 > + UINTN RpDevice; >=20 > + UINTN RpFunction; >=20 > + EFI_HANDLE PcieHandle; >=20 > + EFI_HANDLE PchIoTrapHandle; >=20 > + PCH_PCIE_SMI_DISPATCH_PROTOCOL *PchPcieSmiDispatchProtocol; >=20 > + EFI_SMM_IO_TRAP_REGISTER_CONTEXT PchIoTrapContext; >=20 > + EFI_SMM_SX_REGISTER_CONTEXT SxDispatchContext; >=20 > + SA_IOTRAP_SMI_PROTOCOL *CpuPcieIoTrapProtocol; >=20 > + EFI_HANDLE SxDispatchHandle; >=20 > + UINT8 MaxPciePortNum; >=20 > + CPU_PCIE_HOB *CpuPcieHob; >=20 > + >=20 > + DEBUG ((DEBUG_INFO, "InitializeCpuPcieSmm () Start\n")); >=20 > + >=20 > + MaxPciePortNum =3D GetMaxCpuPciePortNum (); >=20 > + >=20 > + // >=20 > + // Locate Pch Pcie Smi Dispatch Protocol >=20 > + // >=20 > + Status =3D gSmst->SmmLocateProtocol (&gPchPcieSmiDispatchProtocolGuid, > NULL, (VOID**) &PchPcieSmiDispatchProtocol); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + >=20 > + mTempRootPortBusNumMin =3D PcdGet8 (PcdSiliconInitTempPciBusMin); >=20 > + mTempRootPortBusNumMax =3D PcdGet8 (PcdSiliconInitTempPciBusMax); >=20 > + >=20 > + /// >=20 > + /// Locate HOB for CPU PCIe >=20 > + /// >=20 > + CpuPcieHob =3D GetFirstGuidHob(&gCpuPcieHobGuid); >=20 > + if (CpuPcieHob !=3D NULL) { >=20 > + ASSERT (sizeof mCpuPcieRootPortConfig =3D=3D sizeof CpuPcieHob- > >RootPort); >=20 > + CopyMem ( >=20 > + mCpuPcieRootPortConfig, >=20 > + &(CpuPcieHob->RootPort), >=20 > + sizeof (mCpuPcieRootPortConfig) >=20 > + ); >=20 > + } >=20 > + >=20 > + // >=20 > + // Throught all PCIE root port function and register the SMI Handler f= or > enabled ports. >=20 > + // >=20 > + for (PortIndex =3D 0; PortIndex < MaxPciePortNum; PortIndex++) { >=20 > + GetCpuPcieRpDevFun (PortIndex, &RpDevice, &RpFunction); >=20 > + RpBase =3D PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, SA_MC_BUS, > (UINT32) RpDevice, (UINT32) RpFunction, 0); >=20 > + // >=20 > + // Skip the root port function which is not enabled >=20 > + // >=20 > + if (PciSegmentRead32 (RpBase) =3D=3D 0xFFFFFFFF) { >=20 > + continue; >=20 > + } >=20 > + >=20 > + // >=20 > + // Register SMI Handlers for Hot Plug and Link Active State Change >=20 > + // >=20 > + Data8 =3D PciSegmentRead8 (RpBase + R_PCIE_SLCAP); >=20 > + if (Data8 & B_PCIE_SLCAP_HPC) { >=20 > + PcieHandle =3D NULL; >=20 > + Status =3D PchPcieSmiDispatchProtocol->HotPlugRegister ( >=20 > + PchPcieSmiDispatchProtocol, >=20 > + CpuPcieSmiRpHandlerFunction= , >=20 > + (PortIndex + CpuRpIndex0), >=20 > + &PcieHandle >=20 > + ); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + >=20 > + Status =3D PchPcieSmiDispatchProtocol->LinkActiveRegister ( >=20 > + PchPcieSmiDispatchProtocol, >=20 > + CpuPcieLinkActiveStateChang= e, >=20 > + (PortIndex + CpuRpIndex0), >=20 > + &PcieHandle >=20 > + ); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + >=20 > + Data32Or =3D B_PCIE_MPC_HPME; >=20 > + Data32And =3D (UINT32) ~B_PCIE_MPC_HPME; >=20 > + S3BootScriptSaveMemReadWrite ( >=20 > + S3BootScriptWidthUint32, >=20 > + PcdGet64 (PcdSiPciExpressBaseAddress) + RpBase + R_PCIE_MPC, >=20 > + &Data32Or, /// Data to be ORed >=20 > + &Data32And /// Data to be ANDed >=20 > + ); >=20 > + } >=20 > + >=20 > + // >=20 > + // Register SMI Handler for Link Equalization Request from Gen 3 Dev= ices. >=20 > + // >=20 > + Data8 =3D PciSegmentRead8 (RpBase + R_PCIE_LCAP); >=20 > + if ((Data8 & B_PCIE_LCAP_MLS) =3D=3D V_PCIE_LCAP_MLS_GEN3) { >=20 > + Status =3D PchPcieSmiDispatchProtocol->LinkEqRegister ( >=20 > + PchPcieSmiDispatchProtocol, >=20 > + CpuPcieLinkEqHandlerFunctio= n, >=20 > + (PortIndex + CpuRpIndex0), >=20 > + &PcieHandle >=20 > + ); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + } >=20 > + } >=20 > + >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + PchIoTrapContext.Type =3D WriteTrap; >=20 > + PchIoTrapContext.Length =3D 4; >=20 > + PchIoTrapContext.Address =3D 0; >=20 > + Status =3D mPchIoTrap->Register ( >=20 > + mPchIoTrap, >=20 > + (EFI_SMM_HANDLER_ENTRY_POINT2) > CpuPcieIoTrapSmiCallback, >=20 > + &PchIoTrapContext, >=20 > + &PchIoTrapHandle >=20 > + ); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + >=20 > + // >=20 > + // Install the SA Pcie IoTrap protocol >=20 > + // >=20 > + (gBS->AllocatePool) (EfiBootServicesData, sizeof > (SA_IOTRAP_SMI_PROTOCOL), (VOID **)&CpuPcieIoTrapProtocol); >=20 > + CpuPcieIoTrapProtocol->SaIotrapSmiAddress =3D > PchIoTrapContext.Address; >=20 > + >=20 > + Status =3D gBS->InstallMultipleProtocolInterfaces ( >=20 > + &ImageHandle, >=20 > + &gCpuPcieIoTrapProtocolGuid, >=20 > + CpuPcieIoTrapProtocol, >=20 > + NULL >=20 > + ); >=20 > + >=20 > + // >=20 > + // Register the callback for S3 entry >=20 > + // >=20 > + SxDispatchContext.Type =3D SxS3; >=20 > + SxDispatchContext.Phase =3D SxEntry; >=20 > + Status =3D mSxDispatch->Register ( >=20 > + mSxDispatch, >=20 > + CpuPcieS3EntryCallBack, >=20 > + &SxDispatchContext, >=20 > + &SxDispatchHandle >=20 > + ); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + >=20 > + DEBUG ((DEBUG_INFO, "InitializeCpuPcieSmm, IoTrap @ %x () End\n", > PchIoTrapContext.Address)); >=20 > + >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/SaInit/Smm/SaLateInitSmm > .c > b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/SaInit/Smm/SaLateInitSmm > .c > new file mode 100644 > index 0000000000..0e9ba41f1b > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/SaInit/Smm/SaLateInitSmm > .c > @@ -0,0 +1,112 @@ > +/** @file >=20 > + This SMM driver will handle SA relevant late initialization >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include "SaLateInitSmm.h" >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include "CpuPcieInfo.h" >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +typedef enum { >=20 > + EnumSaSmiCallbackForMaxPayLoad, >=20 > + EnumSaSmiCallbackForSaSaveRestore, >=20 > + EnumSaSmiCallbackForLateInit, >=20 > + EnumSaSmiCallbackForS3resume, >=20 > + EnumSaSmiCallbackMax >=20 > +} SMI_OPERATION; >=20 > + >=20 > +GLOBAL_REMOVE_IF_UNREFERENCED UINT8 > mSaSmiCallbackPhase =3D EnumSaSmiCallbackForMaxPayLoad; >=20 > +GLOBAL_REMOVE_IF_UNREFERENCED > EFI_SMM_IO_TRAP_DISPATCH2_PROTOCOL *mPchIoTrap; >=20 > +GLOBAL_REMOVE_IF_UNREFERENCED > EFI_SMM_SX_DISPATCH2_PROTOCOL *mSxDispatch; >=20 > + >=20 > + >=20 > +typedef struct { >=20 > + UINT64 BaseAddr; >=20 > + UINT32 Offset; >=20 > + UINT32 AndMask; >=20 > + UINT32 OrMask; >=20 > +} BOOT_SCRIPT_REGISTER_SETTING; >=20 > + >=20 > +/** >=20 > + Initializes the SA SMM handler >=20 > + >=20 > + @param[in] ImageHandle - The image handle of Wake On Lan driver >=20 > + @param[in] SystemTable - The standard EFI system table >=20 > + >=20 > + @retval EFI_SUCCESS - SA SMM handler was installed or not necessary >=20 > + @retval EFI_NOT_FOUND - Fail to register SMI callback or required > protocol/hob missing. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +SaLateInitSmmEntryPoint ( >=20 > + IN EFI_HANDLE ImageHandle, >=20 > + IN EFI_SYSTEM_TABLE *SystemTable >=20 > + ) >=20 > +{ >=20 > +#if FixedPcdGetBool(PcdCpuPcieEnable) =3D=3D 1 >=20 > + CPU_PCIE_HOB *CpuPcieHob =3D NULL; >=20 > + EFI_STATUS Status; >=20 > +#endif >=20 > + >=20 > + DEBUG ((DEBUG_INFO, "SaLateInitSmmEntryPoint()\n")); >=20 > + >=20 > +#if FixedPcdGetBool(PcdCpuPcieEnable) =3D=3D 1 >=20 > + CpuPcieHob =3D (CPU_PCIE_HOB *) GetFirstGuidHob (&gCpuPcieHobGuid); >=20 > + Status =3D EFI_NOT_FOUND; >=20 > + if (CpuPcieHob =3D=3D NULL) { >=20 > + DEBUG ((DEBUG_INFO, "CPU PCIE HOB Not found\n")); >=20 > + ASSERT (CpuPcieHob !=3D NULL); >=20 > + return Status; >=20 > + } >=20 > + >=20 > + /// >=20 > + /// Locate the PCH Trap dispatch protocol >=20 > + /// >=20 > + Status =3D gSmst->SmmLocateProtocol > (&gEfiSmmIoTrapDispatch2ProtocolGuid, NULL, (VOID **) &mPchIoTrap); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + Status =3D gSmst->SmmLocateProtocol (&gEfiSmmSxDispatch2ProtocolGuid, > NULL, (VOID**) &mSxDispatch); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + if (Status =3D=3D EFI_SUCCESS) { >=20 > + /// >=20 > + /// If ASPM policy is set to "Before OPROM", this SMI callback is no= t > necessary >=20 > + /// Ensure the SMI callback handler will directly return and continu= e the > POST. >=20 > + /// >=20 > + mSaSmiCallbackPhase =3D EnumSaSmiCallbackMax; >=20 > + Status =3D EFI_SUCCESS; >=20 > + } >=20 > + >=20 > + Status =3D InitializeCpuPcieSmm (ImageHandle, SystemTable); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + >=20 > + if (Status !=3D EFI_SUCCESS) { >=20 > + DEBUG ((DEBUG_ERROR, "Failed to register SaIotrapSmiCallback!\n")); >=20 > + /// >=20 > + /// System will halt when failing to register required SMI handler >=20 > + /// >=20 > + CpuDeadLoop (); >=20 > + } >=20 > +#endif >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/SaInit/Smm/SaLateInitSmm > .h > b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/SaInit/Smm/SaLateInitSmm > .h > new file mode 100644 > index 0000000000..c93f92305c > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/SaInit/Smm/SaLateInitSmm > .h > @@ -0,0 +1,122 @@ > +/** @file >=20 > + Header file for SA SMM Handler >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _SaLateInitSmm_H_ >=20 > +#define _SaLateInitSmm_H_ >=20 > + >=20 > +/// >=20 > +/// Driver Consumed Protocol Prototypes >=20 > +/// >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +extern EFI_SMM_IO_TRAP_DISPATCH2_PROTOCOL *mPchIoTrap; >=20 > +extern EFI_SMM_SX_DISPATCH2_PROTOCOL *mSxDispatch; >=20 > + >=20 > +/// >=20 > +/// The value before AutoConfig match the setting of PCI Express Base > Specification 1.1, please be careful for adding new feature >=20 > +/// >=20 > +typedef enum { >=20 > + PcieAspmDisabled, >=20 > + PcieAspmL0s, >=20 > + PcieAspmL1, >=20 > + PcieAspmL0sL1, >=20 > + PcieAspmAutoConfig, >=20 > + PcieAspmMax >=20 > +} CPU_PCIE_ASPM_CONFIG; >=20 > + >=20 > +typedef struct { >=20 > + UINT64 Address; >=20 > + S3_BOOT_SCRIPT_LIB_WIDTH Width; >=20 > + UINT32 Value; >=20 > +} BOOT_SCRIPT_PCI_REGISTER_SAVE; >=20 > + >=20 > + >=20 > +/** >=20 > + System Agent Initialization SMM Driver Entry Point >=20 > + - Introduction \n >=20 > + This is an optional driver to support PCIe ASPM initialization later= than > Option ROM initialization.\n >=20 > + In this scenario S3 Save Boot Script table has been closed per secur= ity > consideration so the ASPM settings will be stored in SMM memory and > restored during S3 resume. >=20 > + If platform does not support this scenario this driver can be exclud= ed and > SI_SA_POLICY_PPI -> PCIE_CONFIG -> InitPcieAspmAfterOprom must be set > to FALSE. \n >=20 > + Note: When InitPcieAspmAfterOprom enabled, the SMI callback handler > must be registered successfully, otherwise it will halt the system. >=20 > + >=20 > + - @pre >=20 > + - _EFI_SMM_BASE_PROTOCOL (or _EFI_SMM_BASE2_PROTOCOL for > EDK2): Provides SMM infrastructure services. >=20 > + - _EFI_SMM_IO_TRAP_DISPATCH_PROTOCOL (or > _EFI_SMM_IO_TRAP_DISPATCH2_PROTOCOL for EDK2): Interface structure > for the SMM IO trap specific SMI Dispatch Protocol >=20 > + - SA_POLICY_PROTOCOL: A protocol published by a platform DXE module > executed earlier; this is documented in this document as well. >=20 > + >=20 > + - @result >=20 > + PCIe ASPM has been initialized on all end point devices discovered a= nd > same settings will be restored during S3 resume. >=20 > + >=20 > + @param[in] ImageHandle - The image handle of Wake On Lan driver >=20 > + @param[in] SystemTable - The standard EFI system table >=20 > + >=20 > + @retval EFI_SUCCESS - SA SMM handler was installed or not necessary >=20 > + @retval EFI_NOT_FOUND - Fail to register SMI callback or required > protocol/hob missing. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +SaLateInitSmmEntryPoint ( >=20 > + IN EFI_HANDLE ImageHandle, >=20 > + IN EFI_SYSTEM_TABLE *SystemTable >=20 > + ); >=20 > + >=20 > +/** >=20 > +An IoTrap callback to config PCIE power management settings >=20 > + >=20 > +@param[in] DispatchHandle - The handle of this callback, obtained when > registering >=20 > +@param[in] DispatchContext - Pointer to the > EFI_SMM_IO_TRAP_DISPATCH_CALLBACK_CONTEXT >=20 > + >=20 > +**/ >=20 > +VOID >=20 > +EFIAPI >=20 > +CpuPcieIoTrapSmiCallback( >=20 > +IN EFI_HANDLE DispatchHandle, >=20 > +IN EFI_SMM_IO_TRAP_CONTEXT *CallbackContext, >=20 > +IN OUT VOID *CommBuffer, >=20 > +IN OUT UINTN *CommBufferSize >=20 > +); >=20 > + >=20 > +/** >=20 > + This function is used to set or clear flags at S3 entry >=20 > + Clear the Io trap executed flag before enter S3 >=20 > + >=20 > + @param[in] Handle Handle of the callback >=20 > + @param[in] Context The dispatch context >=20 > + @param[in,out] CommBuffer A pointer to a collection of data in > memory that will be conveyed from a non-SMM environment into an SMM > environment. >=20 > + @param[in,out] CommBufferSize The size of the CommBuffer. >=20 > + @retval EFI_SUCCESS SA register saved >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +CpuPcieS3EntryCallBack ( >=20 > + IN EFI_HANDLE Handle, >=20 > + IN CONST VOID *Context OPTIONAL, >=20 > + IN OUT VOID *CommBuffer OPTIONAL, >=20 > + IN OUT UINTN *CommBufferSize OPTIONAL >=20 > + ); >=20 > + >=20 > +/** >=20 > + Register PCIE Hotplug SMI dispatch function to handle Hotplug enabling >=20 > + >=20 > + @param[in] ImageHandle The image handle of this module >=20 > + @param[in] SystemTable The EFI System Table >=20 > + >=20 > + @retval EFI_SUCCESS The function completes successfully >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +InitializeCpuPcieSmm ( >=20 > + IN EFI_HANDLE ImageHandle, >=20 > + IN EFI_SYSTEM_TABLE *SystemTable >=20 > + ); >=20 > +#endif >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/SaInit/Smm/SaLateInitSmm > .inf > b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/SaInit/Smm/SaLateInitSmm > .inf > new file mode 100644 > index 0000000000..ef3486d2a6 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/SaInit/Smm/SaLateInitSmm > .inf > @@ -0,0 +1,72 @@ > +## @file >=20 > +# Component description file for the SA late initialization SMM module. >=20 > +# >=20 > +# Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > +# SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +# >=20 > +## >=20 > + >=20 > +[Defines] >=20 > +INF_VERSION =3D 0x00010017 >=20 > +BASE_NAME =3D SaLateInitSmm >=20 > +FILE_GUID =3D 2D1E361C-7B3F-4d15-8B1F-66E551FABDC7 >=20 > +VERSION_STRING =3D 1.0 >=20 > +MODULE_TYPE =3D DXE_SMM_DRIVER >=20 > +PI_SPECIFICATION_VERSION =3D 1.10 >=20 > +ENTRY_POINT =3D SaLateInitSmmEntryPoint >=20 > + >=20 > +[LibraryClasses] >=20 > +UefiDriverEntryPoint >=20 > +UefiBootServicesTableLib >=20 > +DxeServicesTableLib >=20 > +DebugLib >=20 > +HobLib >=20 > +BaseLib >=20 > +S3BootScriptLib >=20 > +PciSegmentLib >=20 > +SaPlatformLib >=20 > +TimerLib >=20 > +PciExpressHelpersLib >=20 > +PcdLib >=20 > +S3BootScriptLib >=20 > +CpuPcieInfoFruLib >=20 > +ConfigBlockLib >=20 > +CpuPcieRpLib >=20 > + >=20 > +[Packages] >=20 > +MdePkg/MdePkg.dec >=20 > +TigerlakeSiliconPkg/SiPkg.dec >=20 > + >=20 > +[Pcd] >=20 > +gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress >=20 > +gSiPkgTokenSpaceGuid.PcdSiliconInitTempPciBusMax >=20 > +gSiPkgTokenSpaceGuid.PcdSiliconInitTempPciBusMin >=20 > +gSiPkgTokenSpaceGuid.PcdCpuPcieEnable ## CONSUMES >=20 > + >=20 > + >=20 > +[Sources] >=20 > +SaLateInitSmm.c >=20 > +CpuPcieSmm.c >=20 > +SaLateInitSmm.h >=20 > + >=20 > +[Protocols] >=20 > +gSaPolicyProtocolGuid ## CONSUMES >=20 > +gEfiSmmIoTrapDispatch2ProtocolGuid ## CONSUMES >=20 > +gSaIotrapSmiProtocolGuid ## PRODUCES >=20 > +gCpuPcieIoTrapProtocolGuid ## PRODUCES >=20 > +gEfiSmmSxDispatch2ProtocolGuid ## CONSUMES >=20 > +gPchSmiDispatchProtocolGuid ## CONSUMES >=20 > +gPchPcieSmiDispatchProtocolGuid ## CONSUMES >=20 > + >=20 > +[Guids] >=20 > +gSaConfigHobGuid >=20 > +gCpuPcieHobGuid >=20 > +gPcieDxeConfigGuid >=20 > +gSaPegHobGuid >=20 > + >=20 > +[Depex] >=20 > +gEfiSmmBase2ProtocolGuid AND >=20 > +gEfiSmmSxDispatch2ProtocolGuid AND >=20 > +gEfiSmmIoTrapDispatch2ProtocolGuid AND >=20 > +gSaPolicyProtocolGuid >=20 > + >=20 > -- > 2.24.0.windows.2