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X-MS-Exchange-CrossTenant-userprincipalname: mtx7jejGFE3BMlTG5JgIZCj15u2FqlanZjvajR3a1ut4Cw8Qob6cDHfS4/7XA4qX07K4QQ39XdEraZFqkgH5L8+tcgkrMKr5HvlpRVUxsdE= X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN0PR11MB5760 Return-Path: nathaniel.l.desimone@intel.com X-OriginatorOrg: intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Nate DeSimone > -----Original Message----- > From: manickavasakam karpagavinayagam > Sent: Wednesday, June 16, 2021 2:47 PM > To: devel@edk2.groups.io > Cc: Oram, Isaac W ; Desimone, Nathaniel L > ; Felixp@ami.com; DOPPALAPUDI, > HARIKRISHNA ; Jha, Manish ; > Bobroff, Zachary ; KARPAGAVINAYAGAM, > MANICKAVASAKAM > Subject: [edk2-platforms] [PATCH V1 1/2] PurleyOpenBoardPkg : Support for > TiogaPass Platform >=20 > Add BoardTiogaPass packages to support TiogaPass Platform > Enabled Network, ISCSI,IPMI, SMBIOS, Performance Measurement > Remove AST2500 UEFI option ROM driver from PurleyOpenBoardPkg > AST2500 UEFI option ROM move to edk2-non-osi ASpeedGopBinPkg > Updated copyright headers > --- > .../IpmiFeaturePkg/GenericIpmi/Dxe/IpmiInit.c | 8 +- > .../Acpi/BoardAcpiDxe/AmlOffsetTable.c | 453 +- > .../Acpi/BoardAcpiDxe/BoardAcpiDxeDsdt.c | 3 + > .../BoardTiogaPass/CoreDxeInclude.dsc | 165 + > .../BoardTiogaPass/CoreUefiBootInclude.fdf | 79 + > .../BoardTiogaPass/GitEdk2MinTiogaPass.bat | 93 + > .../BasePlatformHookLib/BasePlatformHookLib.c | 389 + > .../BasePlatformHookLib.inf | 36 + > .../BoardAcpiLib/DxeBoardAcpiTableLib.c | 36 + > .../BoardAcpiLib/DxeBoardAcpiTableLib.inf | 40 + > .../BoardAcpiLib/DxeTiogaPassAcpiTableLib.c | 53 + > .../BoardAcpiLib/SmmBoardAcpiEnableLib.c | 62 + > .../BoardAcpiLib/SmmBoardAcpiEnableLib.inf | 41 + > .../BoardAcpiLib/SmmSiliconAcpiEnableLib.c | 120 + > .../BoardAcpiLib/SmmTiogaPassAcpiEnableLib.c | 37 + > .../Library/BoardInitLib/AllLanesEparam.c | 44 + > .../Library/BoardInitLib/GpioTable.c | 296 + > .../Library/BoardInitLib/IioBifur.c | 70 + > .../BoardInitLib/PeiBoardInitPostMemLib.c | 46 + > .../BoardInitLib/PeiBoardInitPostMemLib.inf | 37 + > .../BoardInitLib/PeiBoardInitPreMemLib.c | 112 + > .../BoardInitLib/PeiBoardInitPreMemLib.inf | 69 + > .../Library/BoardInitLib/PeiTiogaPassDetect.c | 28 + > .../BoardInitLib/PeiTiogaPassInitLib.h | 18 + > .../BoardInitLib/PeiTiogaPassInitPostMemLib.c | 86 + > .../BoardInitLib/PeiTiogaPassInitPreMemLib.c | 638 ++ > .../Library/BoardInitLib/UsbOC.c | 46 + > .../Library/PeiReportFvLib/PeiReportFvLib.c | 138 + > .../Library/PeiReportFvLib/PeiReportFvLib.inf | 51 + > .../BoardTiogaPass/OpenBoardPkg.dsc | 245 + > .../BoardTiogaPass/OpenBoardPkg.fdf | 600 ++ > .../BoardTiogaPass/PlatformPkgBuildOption.dsc | 84 + > .../BoardTiogaPass/PlatformPkgConfig.dsc | 58 + > .../BoardTiogaPass/PlatformPkgPcd.dsc | 392 ++ > .../BoardTiogaPass/StructureConfig.dsc | 6236 +++++++++++++++++ > .../BoardTiogaPass/__init__.py | 0 > .../PurleyOpenBoardPkg/BoardTiogaPass/bld.bat | 139 + > .../BoardTiogaPass/build_board.py | 195 + > .../BoardTiogaPass/build_config.cfg | 34 + > .../BoardTiogaPass/logo.txt | 10 + > .../BoardTiogaPass/postbuild.bat | 96 + > .../BoardTiogaPass/prebuild.bat | 213 + > .../Ipmi/Library/IpmiLibKcs/IpmiLibKcs.inf | 10 +- > .../IpmiPlatformHookLib.inf | 6 +- > .../Include/Guid/PchRcVariable.h | 6 + > .../Include/Guid/SetupVariable.h | 15 +- > .../Intel/PurleyOpenBoardPkg/OpenBoardPkg.dec | 1 + > Platform/Intel/build.cfg | 2 + > Platform/Intel/build_bios.py | 3 +- > 49 files changed, 11399 insertions(+), 240 deletions(-) > create mode 100644 > Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/CoreDxeInclude.dsc > create mode 100644 > Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/CoreUefiBootInclude.f > df > create mode 100644 > Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/GitEdk2MinTiogaPass. > bat > create mode 100644 > Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BasePlatformH > ookLib/BasePlatformHookLib.c > create mode 100644 > Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BasePlatformH > ookLib/BasePlatformHookLib.inf > create mode 100644 > Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardAcpiLib/ > DxeBoardAcpiTableLib.c > create mode 100644 > Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardAcpiLib/ > DxeBoardAcpiTableLib.inf > create mode 100644 > Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardAcpiLib/ > DxeTiogaPassAcpiTableLib.c > create mode 100644 > Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardAcpiLib/S > mmBoardAcpiEnableLib.c > create mode 100644 > Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardAcpiLib/S > mmBoardAcpiEnableLib.inf > create mode 100644 > Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardAcpiLib/S > mmSiliconAcpiEnableLib.c > create mode 100644 > Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardAcpiLib/S > mmTiogaPassAcpiEnableLib.c > create mode 100644 > Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardInitLib/Al > lLanesEparam.c > create mode 100644 > Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardInitLib/G > pioTable.c > create mode 100644 > Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardInitLib/Ii > oBifur.c > create mode 100644 > Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardInitLib/P > eiBoardInitPostMemLib.c > create mode 100644 > Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardInitLib/P > eiBoardInitPostMemLib.inf > create mode 100644 > Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardInitLib/P > eiBoardInitPreMemLib.c > create mode 100644 > Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardInitLib/P > eiBoardInitPreMemLib.inf > create mode 100644 > Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardInitLib/P > eiTiogaPassDetect.c > create mode 100644 > Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardInitLib/P > eiTiogaPassInitLib.h > create mode 100644 > Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardInitLib/P > eiTiogaPassInitPostMemLib.c > create mode 100644 > Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardInitLib/P > eiTiogaPassInitPreMemLib.c > create mode 100644 > Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardInitLib/U > sbOC.c > create mode 100644 > Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/PeiReportFvLib > /PeiReportFvLib.c > create mode 100644 > Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/PeiReportFvLib > /PeiReportFvLib.inf > create mode 100644 > Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/OpenBoardPkg.dsc > create mode 100644 > Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/OpenBoardPkg.fdf > create mode 100644 > Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/PlatformPkgBuildOptio > n.dsc > create mode 100644 > Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/PlatformPkgConfig.dsc > create mode 100644 > Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/PlatformPkgPcd.dsc > create mode 100644 > Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/StructureConfig.dsc > create mode 100644 > Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/__init__.py > create mode 100644 > Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/bld.bat > create mode 100644 > Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/build_board.py > create mode 100644 > Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/build_config.cfg > create mode 100644 > Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/logo.txt > create mode 100644 > Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/postbuild.bat > create mode 100644 > Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/prebuild.bat >=20 > diff --git > a/Features/Intel/OutOfBandManagement/IpmiFeaturePkg/GenericIpmi/Dx > e/IpmiInit.c > b/Features/Intel/OutOfBandManagement/IpmiFeaturePkg/GenericIpmi/Dx > e/IpmiInit.c > index 1e0c132508..d788b48867 100644 > --- > a/Features/Intel/OutOfBandManagement/IpmiFeaturePkg/GenericIpmi/Dx > e/IpmiInit.c > +++ > b/Features/Intel/OutOfBandManagement/IpmiFeaturePkg/GenericIpmi/Dx > e/IpmiInit.c > @@ -242,7 +242,7 @@ Returns: > EFI_STATUS Status; >=20 > UINT32 DataSize; >=20 > SM_CTRL_INFO *pBmcInfo; >=20 > - EFI_IPMI_MSG_GET_BMC_EXEC_RSP *pBmcExecContext; >=20 > + IPMI_MSG_GET_BMC_EXEC_RSP *pBmcExecContext; >=20 > UINT32 Retries; >=20 > #ifdef FAST_VIDEO_SUPPORT >=20 > EFI_VIDEOPRINT_PROTOCOL *VideoPrintProtocol; >=20 > @@ -301,14 +301,14 @@ Returns: > Status =3D IpmiSendCommand ( >=20 > &IpmiInstance->IpmiTransport, >=20 > IPMI_NETFN_FIRMWARE, 0, >=20 > - EFI_FIRMWARE_GET_BMC_EXECUTION_CONTEXT, >=20 > + IPMI_GET_BMC_EXECUTION_CONTEXT, >=20 > NULL, 0, >=20 > IpmiInstance->TempData, &DataSize >=20 > ); >=20 >=20 >=20 > - pBmcExecContext =3D > (EFI_IPMI_MSG_GET_BMC_EXEC_RSP*)&IpmiInstance->TempData[0]; >=20 > + pBmcExecContext =3D (IPMI_MSG_GET_BMC_EXEC_RSP*)&IpmiInstance- > >TempData[0]; >=20 > DEBUG ((DEBUG_INFO, "[IPMI] Operational status of BMC: 0x%x\n", > pBmcExecContext->CurrentExecutionContext)); >=20 > - if ((pBmcExecContext->CurrentExecutionContext =3D=3D > EFI_FIRMWARE_BMC_IN_FORCED_UPDATE_MODE) && >=20 > + if ((pBmcExecContext->CurrentExecutionContext =3D=3D > IPMI_BMC_IN_FORCED_UPDATE_MODE) && >=20 > !EFI_ERROR (Status)) { >=20 > DEBUG ((DEBUG_ERROR, "[IPMI] BMC in Forced Update mode, skip > waiting for BMC_READY.\n")); >=20 > IpmiInstance->BmcStatus =3D BMC_UPDATE_IN_PROGRESS; >=20 > diff --git > a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/AmlOffsetTable. > c > b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/AmlOffsetTable. > c > index abb484172e..4fdc9ac94e 100644 > --- > a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/AmlOffsetTable. > c > +++ > b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/AmlOffsetTable. > c > @@ -1,5 +1,6 @@ > /** @file >=20 > Copyright (c) 2018 - 2019, Intel Corporation. All rights reserved.
>=20 > + Copyright (c) 2021, American Megatrends International LLC.
>=20 > SPDX-License-Identifier: BSD-2-Clause-Patent >=20 >=20 >=20 > **/ >=20 > @@ -59,232 +60,232 @@ typedef struct { > */ >=20 > AML_OFFSET_TABLE_ENTRY DSDT_PLATWFP__OffsetTable[] =3D >=20 > { >=20 > - {"PSYS", 0x5B80, 0x0000038B, 0x0C, 0x00000391, > 0x0000000030584946}, /* OPERATIONREGION */ >=20 > - {"_SB_.PC00.FIX1", 0x0011, 0x00000000, 0x88, 0x0000D187, > 0x0000000000000000}, /* WORDBUSNUMBER */ >=20 > - {"_SB_.PC00.FIX2", 0x0011, 0x00000000, 0x88, 0x0000D1AF, > 0x0000000000000000}, /* WORDIO */ >=20 > - {"_SB_.PC00.FIX5", 0x0011, 0x00000000, 0x87, 0x0000D1BF, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > - {"_SB_.PC00.FIX3", 0x0011, 0x00000000, 0x87, 0x0000D20D, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > - {"_SB_.PC00.FIX4", 0x0011, 0x00000000, 0x8A, 0x0000D227, > 0x0000000000000000}, /* QWORDMEMORY */ >=20 > - {"_SB_.PC01.FIX1", 0x0011, 0x00000000, 0x88, 0x0000EA9B, > 0x0000000000000000}, /* WORDBUSNUMBER */ >=20 > - {"_SB_.PC01.FIX5", 0x0011, 0x00000000, 0x87, 0x0000EAAB, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > - {"_SB_.PC01.FIX2", 0x0011, 0x00000000, 0x88, 0x0000EAC5, > 0x0000000000000000}, /* WORDIO */ >=20 > - {"_SB_.PC01.FIX6", 0x0011, 0x00000000, 0x88, 0x0000EAD5, > 0x0000000000000000}, /* WORDIO */ >=20 > - {"_SB_.PC01.FIX7", 0x0011, 0x00000000, 0x88, 0x0000EAE5, > 0x0000000000000000}, /* WORDIO */ >=20 > - {"_SB_.PC01.FIX3", 0x0011, 0x00000000, 0x87, 0x0000EAF5, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > - {"_SB_.PC01.FIX4", 0x0011, 0x00000000, 0x8A, 0x0000EB0F, > 0x0000000000000000}, /* QWORDMEMORY */ >=20 > - {"_SB_.PC01.BR1A.MCTL", 0x5B80, 0x0000EB91, 0x0C, 0x0000EB97, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > - {"_SB_.PC01.BR1B.MCTL", 0x5B80, 0x0000F3B2, 0x0C, 0x0000F3B8, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > - {"_SB_.PC01.BR1C.MCTL", 0x5B80, 0x0000FBD3, 0x0C, 0x0000FBD9, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > - {"_SB_.PC01.BR1D.MCTL", 0x5B80, 0x000103F4, 0x0C, 0x000103FA, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > - {"_SB_.PC02.FIX1", 0x0011, 0x00000000, 0x88, 0x00010E93, > 0x0000000000000000}, /* WORDBUSNUMBER */ >=20 > - {"_SB_.PC02.FIX5", 0x0011, 0x00000000, 0x87, 0x00010EA3, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > - {"_SB_.PC02.FIX2", 0x0011, 0x00000000, 0x88, 0x00010EBD, > 0x0000000000000000}, /* WORDIO */ >=20 > - {"_SB_.PC02.FIX6", 0x0011, 0x00000000, 0x88, 0x00010ECD, > 0x0000000000000000}, /* WORDIO */ >=20 > - {"_SB_.PC02.FIX7", 0x0011, 0x00000000, 0x88, 0x00010EDD, > 0x0000000000000000}, /* WORDIO */ >=20 > - {"_SB_.PC02.FIX3", 0x0011, 0x00000000, 0x87, 0x00010EED, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > - {"_SB_.PC02.FIX4", 0x0011, 0x00000000, 0x8A, 0x00010F07, > 0x0000000000000000}, /* QWORDMEMORY */ >=20 > - {"_SB_.PC02.BR2A.MCTL", 0x5B80, 0x00010F89, 0x0C, 0x00010F8F, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > - {"_SB_.PC02.BR2B.MCTL", 0x5B80, 0x00011969, 0x0C, 0x0001196F, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > - {"_SB_.PC02.BR2C.MCTL", 0x5B80, 0x0001218A, 0x0C, 0x00012190, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > - {"_SB_.PC02.BR2D.MCTL", 0x5B80, 0x000129AB, 0x0C, 0x000129B1, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > - {"_SB_.PC03.FIX1", 0x0011, 0x00000000, 0x88, 0x000133E4, > 0x0000000000000000}, /* WORDBUSNUMBER */ >=20 > - {"_SB_.PC03.FIX5", 0x0011, 0x00000000, 0x87, 0x000133F4, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > - {"_SB_.PC03.FIX2", 0x0011, 0x00000000, 0x88, 0x0001340E, > 0x0000000000000000}, /* WORDIO */ >=20 > - {"_SB_.PC03.FIX6", 0x0011, 0x00000000, 0x88, 0x0001341E, > 0x0000000000000000}, /* WORDIO */ >=20 > - {"_SB_.PC03.FIX7", 0x0011, 0x00000000, 0x88, 0x0001342E, > 0x0000000000000000}, /* WORDIO */ >=20 > - {"_SB_.PC03.FIX3", 0x0011, 0x00000000, 0x87, 0x0001343E, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > - {"_SB_.PC03.FIX4", 0x0011, 0x00000000, 0x8A, 0x00013458, > 0x0000000000000000}, /* QWORDMEMORY */ >=20 > - {"_SB_.PC03.BR3A.MCTL", 0x5B80, 0x000134DA, 0x0C, 0x000134E0, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > - {"_SB_.PC03.BR3B.MCTL", 0x5B80, 0x00013CFB, 0x0C, 0x00013D01, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > - {"_SB_.PC03.BR3C.MCTL", 0x5B80, 0x0001451C, 0x0C, 0x00014522, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > - {"_SB_.PC03.BR3D.MCTL", 0x5B80, 0x00014D3D, 0x0C, 0x00014D43, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > - {"_SB_.PC04.FIX1", 0x0011, 0x00000000, 0x88, 0x000156F0, > 0x0000000000000000}, /* WORDBUSNUMBER */ >=20 > - {"_SB_.PC04.FIX5", 0x0011, 0x00000000, 0x87, 0x00015700, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > - {"_SB_.PC04.FIX2", 0x0011, 0x00000000, 0x88, 0x0001571A, > 0x0000000000000000}, /* WORDIO */ >=20 > - {"_SB_.PC04.FIX6", 0x0011, 0x00000000, 0x88, 0x0001572A, > 0x0000000000000000}, /* WORDIO */ >=20 > - {"_SB_.PC04.FIX7", 0x0011, 0x00000000, 0x88, 0x0001573A, > 0x0000000000000000}, /* WORDIO */ >=20 > - {"_SB_.PC04.FIX3", 0x0011, 0x00000000, 0x87, 0x0001574A, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > - {"_SB_.PC04.FIX4", 0x0011, 0x00000000, 0x8A, 0x00015764, > 0x0000000000000000}, /* QWORDMEMORY */ >=20 > - {"_SB_.PC04.MCP0.MCTL", 0x5B80, 0x000157E6, 0x0C, 0x000157EC, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > - {"_SB_.PC05.FIX1", 0x0011, 0x00000000, 0x88, 0x0001612D, > 0x0000000000000000}, /* WORDBUSNUMBER */ >=20 > - {"_SB_.PC05.FIX5", 0x0011, 0x00000000, 0x87, 0x0001613D, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > - {"_SB_.PC05.FIX2", 0x0011, 0x00000000, 0x88, 0x00016157, > 0x0000000000000000}, /* WORDIO */ >=20 > - {"_SB_.PC05.FIX6", 0x0011, 0x00000000, 0x88, 0x00016167, > 0x0000000000000000}, /* WORDIO */ >=20 > - {"_SB_.PC05.FIX7", 0x0011, 0x00000000, 0x88, 0x00016177, > 0x0000000000000000}, /* WORDIO */ >=20 > - {"_SB_.PC05.FIX3", 0x0011, 0x00000000, 0x87, 0x00016187, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > - {"_SB_.PC05.FIX4", 0x0011, 0x00000000, 0x8A, 0x000161A1, > 0x0000000000000000}, /* QWORDMEMORY */ >=20 > - {"_SB_.PC05.MCP1.MCTL", 0x5B80, 0x00016223, 0x0C, 0x00016229, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > - {"_SB_.PC06.FIX1", 0x0011, 0x00000000, 0x88, 0x00016FD9, > 0x0000000000000000}, /* WORDBUSNUMBER */ >=20 > - {"_SB_.PC06.FIX5", 0x0011, 0x00000000, 0x87, 0x00016FE9, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > - {"_SB_.PC06.FIX2", 0x0011, 0x00000000, 0x88, 0x00017003, > 0x0000000000000000}, /* WORDIO */ >=20 > - {"_SB_.PC06.FIX6", 0x0011, 0x00000000, 0x88, 0x00017013, > 0x0000000000000000}, /* WORDIO */ >=20 > - {"_SB_.PC06.FIX7", 0x0011, 0x00000000, 0x88, 0x00017023, > 0x0000000000000000}, /* WORDIO */ >=20 > - {"_SB_.PC06.FIX3", 0x0011, 0x00000000, 0x87, 0x00017033, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > - {"_SB_.PC06.FIX4", 0x0011, 0x00000000, 0x8A, 0x0001704D, > 0x0000000000000000}, /* QWORDMEMORY */ >=20 > - {"_SB_.PC06.QRP0.MCTL", 0x5B80, 0x00017149, 0x0C, 0x0001714F, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > - {"_SB_.PC07.FIX1", 0x0011, 0x00000000, 0x88, 0x00017BC4, > 0x0000000000000000}, /* WORDBUSNUMBER */ >=20 > - {"_SB_.PC07.FIX5", 0x0011, 0x00000000, 0x87, 0x00017BD4, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > - {"_SB_.PC07.FIX2", 0x0011, 0x00000000, 0x88, 0x00017BEE, > 0x0000000000000000}, /* WORDIO */ >=20 > - {"_SB_.PC07.FIX6", 0x0011, 0x00000000, 0x88, 0x00017BFE, > 0x0000000000000000}, /* WORDIO */ >=20 > - {"_SB_.PC07.FIX7", 0x0011, 0x00000000, 0x88, 0x00017C0E, > 0x0000000000000000}, /* WORDIO */ >=20 > - {"_SB_.PC07.FIX3", 0x0011, 0x00000000, 0x87, 0x00017C1E, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > - {"_SB_.PC07.FIX4", 0x0011, 0x00000000, 0x8A, 0x00017C38, > 0x0000000000000000}, /* QWORDMEMORY */ >=20 > - {"_SB_.PC07.QR1A.MCTL", 0x5B80, 0x00017CCA, 0x0C, 0x00017CD0, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > - {"_SB_.PC07.QR1B.MCTL", 0x5B80, 0x00018506, 0x0C, 0x0001850C, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > - {"_SB_.PC07.QR1C.MCTL", 0x5B80, 0x00018D42, 0x0C, 0x00018D48, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > - {"_SB_.PC07.QR1D.MCTL", 0x5B80, 0x0001957E, 0x0C, 0x00019584, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > - {"_SB_.PC08.FIX1", 0x0011, 0x00000000, 0x88, 0x0001A04E, > 0x0000000000000000}, /* WORDBUSNUMBER */ >=20 > - {"_SB_.PC08.FIX5", 0x0011, 0x00000000, 0x87, 0x0001A05E, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > - {"_SB_.PC08.FIX2", 0x0011, 0x00000000, 0x88, 0x0001A078, > 0x0000000000000000}, /* WORDIO */ >=20 > - {"_SB_.PC08.FIX6", 0x0011, 0x00000000, 0x88, 0x0001A088, > 0x0000000000000000}, /* WORDIO */ >=20 > - {"_SB_.PC08.FIX7", 0x0011, 0x00000000, 0x88, 0x0001A098, > 0x0000000000000000}, /* WORDIO */ >=20 > - {"_SB_.PC08.FIX3", 0x0011, 0x00000000, 0x87, 0x0001A0A8, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > - {"_SB_.PC08.FIX4", 0x0011, 0x00000000, 0x8A, 0x0001A0C2, > 0x0000000000000000}, /* QWORDMEMORY */ >=20 > - {"_SB_.PC08.QR2A.MCTL", 0x5B80, 0x0001A154, 0x0C, 0x0001A15A, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > - {"_SB_.PC08.QR2B.MCTL", 0x5B80, 0x0001A990, 0x0C, 0x0001A996, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > - {"_SB_.PC08.QR2C.MCTL", 0x5B80, 0x0001B1CC, 0x0C, 0x0001B1D2, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > - {"_SB_.PC08.QR2D.MCTL", 0x5B80, 0x0001BA08, 0x0C, 0x0001BA0E, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > - {"_SB_.PC09.FIX1", 0x0011, 0x00000000, 0x88, 0x0001C461, > 0x0000000000000000}, /* WORDBUSNUMBER */ >=20 > - {"_SB_.PC09.FIX5", 0x0011, 0x00000000, 0x87, 0x0001C471, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > - {"_SB_.PC09.FIX2", 0x0011, 0x00000000, 0x88, 0x0001C48B, > 0x0000000000000000}, /* WORDIO */ >=20 > - {"_SB_.PC09.FIX6", 0x0011, 0x00000000, 0x88, 0x0001C49B, > 0x0000000000000000}, /* WORDIO */ >=20 > - {"_SB_.PC09.FIX7", 0x0011, 0x00000000, 0x88, 0x0001C4AB, > 0x0000000000000000}, /* WORDIO */ >=20 > - {"_SB_.PC09.FIX3", 0x0011, 0x00000000, 0x87, 0x0001C4BB, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > - {"_SB_.PC09.FIX4", 0x0011, 0x00000000, 0x8A, 0x0001C4D5, > 0x0000000000000000}, /* QWORDMEMORY */ >=20 > - {"_SB_.PC09.QR3A.MCTL", 0x5B80, 0x0001C567, 0x0C, 0x0001C56D, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > - {"_SB_.PC09.QR3B.MCTL", 0x5B80, 0x0001CDA3, 0x0C, 0x0001CDA9, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > - {"_SB_.PC09.QR3C.MCTL", 0x5B80, 0x0001D5DF, 0x0C, 0x0001D5E5, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > - {"_SB_.PC09.QR3D.MCTL", 0x5B80, 0x0001DE1B, 0x0C, 0x0001DE21, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > - {"_SB_.PC10.FIX1", 0x0011, 0x00000000, 0x88, 0x0001E7EE, > 0x0000000000000000}, /* WORDBUSNUMBER */ >=20 > - {"_SB_.PC10.FIX5", 0x0011, 0x00000000, 0x87, 0x0001E7FE, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > - {"_SB_.PC10.FIX2", 0x0011, 0x00000000, 0x88, 0x0001E818, > 0x0000000000000000}, /* WORDIO */ >=20 > - {"_SB_.PC10.FIX6", 0x0011, 0x00000000, 0x88, 0x0001E828, > 0x0000000000000000}, /* WORDIO */ >=20 > - {"_SB_.PC10.FIX7", 0x0011, 0x00000000, 0x88, 0x0001E838, > 0x0000000000000000}, /* WORDIO */ >=20 > - {"_SB_.PC10.FIX3", 0x0011, 0x00000000, 0x87, 0x0001E848, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > - {"_SB_.PC10.FIX4", 0x0011, 0x00000000, 0x8A, 0x0001E862, > 0x0000000000000000}, /* QWORDMEMORY */ >=20 > - {"_SB_.PC10.MCP2.MCTL", 0x5B80, 0x0001E8F4, 0x0C, 0x0001E8FA, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > - {"_SB_.PC11.FIX1", 0x0011, 0x00000000, 0x88, 0x0001F250, > 0x0000000000000000}, /* WORDBUSNUMBER */ >=20 > - {"_SB_.PC11.FIX5", 0x0011, 0x00000000, 0x87, 0x0001F260, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > - {"_SB_.PC11.FIX2", 0x0011, 0x00000000, 0x88, 0x0001F27A, > 0x0000000000000000}, /* WORDIO */ >=20 > - {"_SB_.PC11.FIX6", 0x0011, 0x00000000, 0x88, 0x0001F28A, > 0x0000000000000000}, /* WORDIO */ >=20 > - {"_SB_.PC11.FIX7", 0x0011, 0x00000000, 0x88, 0x0001F29A, > 0x0000000000000000}, /* WORDIO */ >=20 > - {"_SB_.PC11.FIX3", 0x0011, 0x00000000, 0x87, 0x0001F2AA, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > - {"_SB_.PC11.FIX4", 0x0011, 0x00000000, 0x8A, 0x0001F2C4, > 0x0000000000000000}, /* QWORDMEMORY */ >=20 > - {"_SB_.PC11.MCP3.MCTL", 0x5B80, 0x0001F356, 0x0C, 0x0001F35C, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > - {"_SB_.PC12.FIX1", 0x0011, 0x00000000, 0x88, 0x0002011C, > 0x0000000000000000}, /* WORDBUSNUMBER */ >=20 > - {"_SB_.PC12.FIX5", 0x0011, 0x00000000, 0x87, 0x0002012C, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > - {"_SB_.PC12.FIX2", 0x0011, 0x00000000, 0x88, 0x00020146, > 0x0000000000000000}, /* WORDIO */ >=20 > - {"_SB_.PC12.FIX6", 0x0011, 0x00000000, 0x88, 0x00020156, > 0x0000000000000000}, /* WORDIO */ >=20 > - {"_SB_.PC12.FIX7", 0x0011, 0x00000000, 0x88, 0x00020166, > 0x0000000000000000}, /* WORDIO */ >=20 > - {"_SB_.PC12.FIX3", 0x0011, 0x00000000, 0x87, 0x00020176, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > - {"_SB_.PC12.FIX4", 0x0011, 0x00000000, 0x8A, 0x00020190, > 0x0000000000000000}, /* QWORDMEMORY */ >=20 > - {"_SB_.PC12.RRP0.MCTL", 0x5B80, 0x0002028C, 0x0C, 0x00020292, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > - {"_SB_.PC13.FIX1", 0x0011, 0x00000000, 0x88, 0x00020D07, > 0x0000000000000000}, /* WORDBUSNUMBER */ >=20 > - {"_SB_.PC13.FIX5", 0x0011, 0x00000000, 0x87, 0x00020D17, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > - {"_SB_.PC13.FIX2", 0x0011, 0x00000000, 0x88, 0x00020D31, > 0x0000000000000000}, /* WORDIO */ >=20 > - {"_SB_.PC13.FIX6", 0x0011, 0x00000000, 0x88, 0x00020D41, > 0x0000000000000000}, /* WORDIO */ >=20 > - {"_SB_.PC13.FIX7", 0x0011, 0x00000000, 0x88, 0x00020D51, > 0x0000000000000000}, /* WORDIO */ >=20 > - {"_SB_.PC13.FIX3", 0x0011, 0x00000000, 0x87, 0x00020D61, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > - {"_SB_.PC13.FIX4", 0x0011, 0x00000000, 0x8A, 0x00020D7B, > 0x0000000000000000}, /* QWORDMEMORY */ >=20 > - {"_SB_.PC13.RR1A.MCTL", 0x5B80, 0x00020E0D, 0x0C, 0x00020E13, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > - {"_SB_.PC13.RR1B.MCTL", 0x5B80, 0x00021649, 0x0C, 0x0002164F, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > - {"_SB_.PC13.RR1C.MCTL", 0x5B80, 0x00021E85, 0x0C, 0x00021E8B, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > - {"_SB_.PC13.RR1D.MCTL", 0x5B80, 0x000226C1, 0x0C, 0x000226C7, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > - {"_SB_.PC14.FIX1", 0x0011, 0x00000000, 0x88, 0x0002316F, > 0x0000000000000000}, /* WORDBUSNUMBER */ >=20 > - {"_SB_.PC14.FIX5", 0x0011, 0x00000000, 0x87, 0x0002317F, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > - {"_SB_.PC14.FIX2", 0x0011, 0x00000000, 0x88, 0x00023199, > 0x0000000000000000}, /* WORDIO */ >=20 > - {"_SB_.PC14.FIX6", 0x0011, 0x00000000, 0x88, 0x000231A9, > 0x0000000000000000}, /* WORDIO */ >=20 > - {"_SB_.PC14.FIX7", 0x0011, 0x00000000, 0x88, 0x000231B9, > 0x0000000000000000}, /* WORDIO */ >=20 > - {"_SB_.PC14.FIX3", 0x0011, 0x00000000, 0x87, 0x000231C9, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > - {"_SB_.PC14.FIX4", 0x0011, 0x00000000, 0x8A, 0x000231E3, > 0x0000000000000000}, /* QWORDMEMORY */ >=20 > - {"_SB_.PC14.RR2A.MCTL", 0x5B80, 0x00023275, 0x0C, 0x0002327B, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > - {"_SB_.PC14.RR2B.MCTL", 0x5B80, 0x00023AB1, 0x0C, 0x00023AB7, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > - {"_SB_.PC14.RR2C.MCTL", 0x5B80, 0x000242ED, 0x0C, 0x000242F3, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > - {"_SB_.PC14.RR2D.MCTL", 0x5B80, 0x00024B29, 0x0C, 0x00024B2F, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > - {"_SB_.PC15.FIX1", 0x0011, 0x00000000, 0x88, 0x00025582, > 0x0000000000000000}, /* WORDBUSNUMBER */ >=20 > - {"_SB_.PC15.FIX5", 0x0011, 0x00000000, 0x87, 0x00025592, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > - {"_SB_.PC15.FIX2", 0x0011, 0x00000000, 0x88, 0x000255AC, > 0x0000000000000000}, /* WORDIO */ >=20 > - {"_SB_.PC15.FIX6", 0x0011, 0x00000000, 0x88, 0x000255BC, > 0x0000000000000000}, /* WORDIO */ >=20 > - {"_SB_.PC15.FIX7", 0x0011, 0x00000000, 0x88, 0x000255CC, > 0x0000000000000000}, /* WORDIO */ >=20 > - {"_SB_.PC15.FIX3", 0x0011, 0x00000000, 0x87, 0x000255DC, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > - {"_SB_.PC15.FIX4", 0x0011, 0x00000000, 0x8A, 0x000255F6, > 0x0000000000000000}, /* QWORDMEMORY */ >=20 > - {"_SB_.PC15.RR3A.MCTL", 0x5B80, 0x00025688, 0x0C, 0x0002568E, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > - {"_SB_.PC15.RR3B.MCTL", 0x5B80, 0x00025EC4, 0x0C, 0x00025ECA, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > - {"_SB_.PC15.RR3C.MCTL", 0x5B80, 0x00026700, 0x0C, 0x00026706, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > - {"_SB_.PC15.RR3D.MCTL", 0x5B80, 0x00026F3C, 0x0C, 0x00026F42, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > - {"_SB_.PC16.FIX1", 0x0011, 0x00000000, 0x88, 0x0002790F, > 0x0000000000000000}, /* WORDBUSNUMBER */ >=20 > - {"_SB_.PC16.FIX5", 0x0011, 0x00000000, 0x87, 0x0002791F, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > - {"_SB_.PC16.FIX2", 0x0011, 0x00000000, 0x88, 0x00027939, > 0x0000000000000000}, /* WORDIO */ >=20 > - {"_SB_.PC16.FIX6", 0x0011, 0x00000000, 0x88, 0x00027949, > 0x0000000000000000}, /* WORDIO */ >=20 > - {"_SB_.PC16.FIX7", 0x0011, 0x00000000, 0x88, 0x00027959, > 0x0000000000000000}, /* WORDIO */ >=20 > - {"_SB_.PC16.FIX3", 0x0011, 0x00000000, 0x87, 0x00027969, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > - {"_SB_.PC16.FIX4", 0x0011, 0x00000000, 0x8A, 0x00027983, > 0x0000000000000000}, /* QWORDMEMORY */ >=20 > - {"_SB_.PC16.MCP4.MCTL", 0x5B80, 0x00027A15, 0x0C, 0x00027A1B, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > - {"_SB_.PC17.FIX1", 0x0011, 0x00000000, 0x88, 0x00028371, > 0x0000000000000000}, /* WORDBUSNUMBER */ >=20 > - {"_SB_.PC17.FIX5", 0x0011, 0x00000000, 0x87, 0x00028381, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > - {"_SB_.PC17.FIX2", 0x0011, 0x00000000, 0x88, 0x0002839B, > 0x0000000000000000}, /* WORDIO */ >=20 > - {"_SB_.PC17.FIX6", 0x0011, 0x00000000, 0x88, 0x000283AB, > 0x0000000000000000}, /* WORDIO */ >=20 > - {"_SB_.PC17.FIX7", 0x0011, 0x00000000, 0x88, 0x000283BB, > 0x0000000000000000}, /* WORDIO */ >=20 > - {"_SB_.PC17.FIX3", 0x0011, 0x00000000, 0x87, 0x000283CB, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > - {"_SB_.PC17.FIX4", 0x0011, 0x00000000, 0x8A, 0x000283E5, > 0x0000000000000000}, /* QWORDMEMORY */ >=20 > - {"_SB_.PC17.MCP5.MCTL", 0x5B80, 0x00028477, 0x0C, 0x0002847D, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > - {"_SB_.PC18.FIX1", 0x0011, 0x00000000, 0x88, 0x0002923D, > 0x0000000000000000}, /* WORDBUSNUMBER */ >=20 > - {"_SB_.PC18.FIX5", 0x0011, 0x00000000, 0x87, 0x0002924D, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > - {"_SB_.PC18.FIX2", 0x0011, 0x00000000, 0x88, 0x00029267, > 0x0000000000000000}, /* WORDIO */ >=20 > - {"_SB_.PC18.FIX6", 0x0011, 0x00000000, 0x88, 0x00029277, > 0x0000000000000000}, /* WORDIO */ >=20 > - {"_SB_.PC18.FIX7", 0x0011, 0x00000000, 0x88, 0x00029287, > 0x0000000000000000}, /* WORDIO */ >=20 > - {"_SB_.PC18.FIX3", 0x0011, 0x00000000, 0x87, 0x00029297, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > - {"_SB_.PC18.FIX4", 0x0011, 0x00000000, 0x8A, 0x000292B1, > 0x0000000000000000}, /* QWORDMEMORY */ >=20 > - {"_SB_.PC18.SRP0.MCTL", 0x5B80, 0x000293AD, 0x0C, 0x000293B3, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > - {"_SB_.PC19.FIX1", 0x0011, 0x00000000, 0x88, 0x00029E28, > 0x0000000000000000}, /* WORDBUSNUMBER */ >=20 > - {"_SB_.PC19.FIX5", 0x0011, 0x00000000, 0x87, 0x00029E38, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > - {"_SB_.PC19.FIX2", 0x0011, 0x00000000, 0x88, 0x00029E52, > 0x0000000000000000}, /* WORDIO */ >=20 > - {"_SB_.PC19.FIX6", 0x0011, 0x00000000, 0x88, 0x00029E62, > 0x0000000000000000}, /* WORDIO */ >=20 > - {"_SB_.PC19.FIX7", 0x0011, 0x00000000, 0x88, 0x00029E72, > 0x0000000000000000}, /* WORDIO */ >=20 > - {"_SB_.PC19.FIX3", 0x0011, 0x00000000, 0x87, 0x00029E82, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > - {"_SB_.PC19.FIX4", 0x0011, 0x00000000, 0x8A, 0x00029E9C, > 0x0000000000000000}, /* QWORDMEMORY */ >=20 > - {"_SB_.PC19.SR1A.MCTL", 0x5B80, 0x00029F2E, 0x0C, 0x00029F34, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > - {"_SB_.PC19.SR1B.MCTL", 0x5B80, 0x0002A76A, 0x0C, 0x0002A770, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > - {"_SB_.PC19.SR1C.MCTL", 0x5B80, 0x0002AFA6, 0x0C, 0x0002AFAC, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > - {"_SB_.PC19.SR1D.MCTL", 0x5B80, 0x0002B7E2, 0x0C, 0x0002B7E8, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > - {"_SB_.PC20.FIX1", 0x0011, 0x00000000, 0x88, 0x0002C2B2, > 0x0000000000000000}, /* WORDBUSNUMBER */ >=20 > - {"_SB_.PC20.FIX5", 0x0011, 0x00000000, 0x87, 0x0002C2C2, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > - {"_SB_.PC20.FIX2", 0x0011, 0x00000000, 0x88, 0x0002C2DC, > 0x0000000000000000}, /* WORDIO */ >=20 > - {"_SB_.PC20.FIX6", 0x0011, 0x00000000, 0x88, 0x0002C2EC, > 0x0000000000000000}, /* WORDIO */ >=20 > - {"_SB_.PC20.FIX7", 0x0011, 0x00000000, 0x88, 0x0002C2FC, > 0x0000000000000000}, /* WORDIO */ >=20 > - {"_SB_.PC20.FIX3", 0x0011, 0x00000000, 0x87, 0x0002C30C, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > - {"_SB_.PC20.FIX4", 0x0011, 0x00000000, 0x8A, 0x0002C326, > 0x0000000000000000}, /* QWORDMEMORY */ >=20 > - {"_SB_.PC20.SR2A.MCTL", 0x5B80, 0x0002C3B8, 0x0C, 0x0002C3BE, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > - {"_SB_.PC20.SR2B.MCTL", 0x5B80, 0x0002CBF4, 0x0C, 0x0002CBFA, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > - {"_SB_.PC20.SR2C.MCTL", 0x5B80, 0x0002D430, 0x0C, 0x0002D436, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > - {"_SB_.PC20.SR2D.MCTL", 0x5B80, 0x0002DC6C, 0x0C, 0x0002DC72, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > - {"_SB_.PC21.FIX1", 0x0011, 0x00000000, 0x88, 0x0002E6C5, > 0x0000000000000000}, /* WORDBUSNUMBER */ >=20 > - {"_SB_.PC21.FIX5", 0x0011, 0x00000000, 0x87, 0x0002E6D5, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > - {"_SB_.PC21.FIX2", 0x0011, 0x00000000, 0x88, 0x0002E6EF, > 0x0000000000000000}, /* WORDIO */ >=20 > - {"_SB_.PC21.FIX6", 0x0011, 0x00000000, 0x88, 0x0002E6FF, > 0x0000000000000000}, /* WORDIO */ >=20 > - {"_SB_.PC21.FIX7", 0x0011, 0x00000000, 0x88, 0x0002E70F, > 0x0000000000000000}, /* WORDIO */ >=20 > - {"_SB_.PC21.FIX3", 0x0011, 0x00000000, 0x87, 0x0002E71F, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > - {"_SB_.PC21.FIX4", 0x0011, 0x00000000, 0x8A, 0x0002E739, > 0x0000000000000000}, /* QWORDMEMORY */ >=20 > - {"_SB_.PC21.SR3A.MCTL", 0x5B80, 0x0002E7CB, 0x0C, 0x0002E7D1, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > - {"_SB_.PC21.SR3B.MCTL", 0x5B80, 0x0002F007, 0x0C, 0x0002F00D, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > - {"_SB_.PC21.SR3C.MCTL", 0x5B80, 0x0002F843, 0x0C, 0x0002F849, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > - {"_SB_.PC21.SR3D.MCTL", 0x5B80, 0x0003007F, 0x0C, 0x00030085, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > - {"_SB_.PC22.FIX1", 0x0011, 0x00000000, 0x88, 0x00030A52, > 0x0000000000000000}, /* WORDBUSNUMBER */ >=20 > - {"_SB_.PC22.FIX5", 0x0011, 0x00000000, 0x87, 0x00030A62, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > - {"_SB_.PC22.FIX2", 0x0011, 0x00000000, 0x88, 0x00030A7C, > 0x0000000000000000}, /* WORDIO */ >=20 > - {"_SB_.PC22.FIX6", 0x0011, 0x00000000, 0x88, 0x00030A8C, > 0x0000000000000000}, /* WORDIO */ >=20 > - {"_SB_.PC22.FIX7", 0x0011, 0x00000000, 0x88, 0x00030A9C, > 0x0000000000000000}, /* WORDIO */ >=20 > - {"_SB_.PC22.FIX3", 0x0011, 0x00000000, 0x87, 0x00030AAC, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > - {"_SB_.PC22.FIX4", 0x0011, 0x00000000, 0x8A, 0x00030AC6, > 0x0000000000000000}, /* QWORDMEMORY */ >=20 > - {"_SB_.PC22.MCP6.MCTL", 0x5B80, 0x00030B58, 0x0C, 0x00030B5E, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > - {"_SB_.PC23.FIX1", 0x0011, 0x00000000, 0x88, 0x000314B4, > 0x0000000000000000}, /* WORDBUSNUMBER */ >=20 > - {"_SB_.PC23.FIX5", 0x0011, 0x00000000, 0x87, 0x000314C4, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > - {"_SB_.PC23.FIX2", 0x0011, 0x00000000, 0x88, 0x000314DE, > 0x0000000000000000}, /* WORDIO */ >=20 > - {"_SB_.PC23.FIX6", 0x0011, 0x00000000, 0x88, 0x000314EE, > 0x0000000000000000}, /* WORDIO */ >=20 > - {"_SB_.PC23.FIX7", 0x0011, 0x00000000, 0x88, 0x000314FE, > 0x0000000000000000}, /* WORDIO */ >=20 > - {"_SB_.PC23.FIX3", 0x0011, 0x00000000, 0x87, 0x0003150E, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > - {"_SB_.PC23.FIX4", 0x0011, 0x00000000, 0x8A, 0x00031528, > 0x0000000000000000}, /* QWORDMEMORY */ >=20 > - {"_SB_.PC23.MCP7.MCTL", 0x5B80, 0x000315BA, 0x0C, 0x000315C0, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > + {"PSYS", 0x5B80, 0x00000465, 0x0C, 0x0000046B, > 0x0000000030584946}, /* OPERATIONREGION */ >=20 > + {"_SB_.PC00.FIX1", 0x0011, 0x00000000, 0x88, 0x0000D261, > 0x0000000000000000}, /* WORDBUSNUMBER */ >=20 > + {"_SB_.PC00.FIX2", 0x0011, 0x00000000, 0x88, 0x0000D289, > 0x0000000000000000}, /* WORDIO */ >=20 > + {"_SB_.PC00.FIX5", 0x0011, 0x00000000, 0x87, 0x0000D299, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > + {"_SB_.PC00.FIX3", 0x0011, 0x00000000, 0x87, 0x0000D2E7, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > + {"_SB_.PC00.FIX4", 0x0011, 0x00000000, 0x8A, 0x0000D301, > 0x0000000000000000}, /* QWORDMEMORY */ >=20 > + {"_SB_.PC01.FIX1", 0x0011, 0x00000000, 0x88, 0x0000EB75, > 0x0000000000000000}, /* WORDBUSNUMBER */ >=20 > + {"_SB_.PC01.FIX5", 0x0011, 0x00000000, 0x87, 0x0000EB85, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > + {"_SB_.PC01.FIX2", 0x0011, 0x00000000, 0x88, 0x0000EB9F, > 0x0000000000000000}, /* WORDIO */ >=20 > + {"_SB_.PC01.FIX6", 0x0011, 0x00000000, 0x88, 0x0000EBAF, > 0x0000000000000000}, /* WORDIO */ >=20 > + {"_SB_.PC01.FIX7", 0x0011, 0x00000000, 0x88, 0x0000EBBF, > 0x0000000000000000}, /* WORDIO */ >=20 > + {"_SB_.PC01.FIX3", 0x0011, 0x00000000, 0x87, 0x0000EBCF, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > + {"_SB_.PC01.FIX4", 0x0011, 0x00000000, 0x8A, 0x0000EBE9, > 0x0000000000000000}, /* QWORDMEMORY */ >=20 > + {"_SB_.PC01.BR1A.MCTL", 0x5B80, 0x0000EC6B, 0x0C, 0x0000EC71, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > + {"_SB_.PC01.BR1B.MCTL", 0x5B80, 0x0000F48A, 0x0C, 0x0000F490, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > + {"_SB_.PC01.BR1C.MCTL", 0x5B80, 0x0000FCA9, 0x0C, 0x0000FCAF, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > + {"_SB_.PC01.BR1D.MCTL", 0x5B80, 0x000104C8, 0x0C, 0x000104CE, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > + {"_SB_.PC02.FIX1", 0x0011, 0x00000000, 0x88, 0x00010F65, > 0x0000000000000000}, /* WORDBUSNUMBER */ >=20 > + {"_SB_.PC02.FIX5", 0x0011, 0x00000000, 0x87, 0x00010F75, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > + {"_SB_.PC02.FIX2", 0x0011, 0x00000000, 0x88, 0x00010F8F, > 0x0000000000000000}, /* WORDIO */ >=20 > + {"_SB_.PC02.FIX6", 0x0011, 0x00000000, 0x88, 0x00010F9F, > 0x0000000000000000}, /* WORDIO */ >=20 > + {"_SB_.PC02.FIX7", 0x0011, 0x00000000, 0x88, 0x00010FAF, > 0x0000000000000000}, /* WORDIO */ >=20 > + {"_SB_.PC02.FIX3", 0x0011, 0x00000000, 0x87, 0x00010FBF, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > + {"_SB_.PC02.FIX4", 0x0011, 0x00000000, 0x8A, 0x00010FD9, > 0x0000000000000000}, /* QWORDMEMORY */ >=20 > + {"_SB_.PC02.BR2A.MCTL", 0x5B80, 0x0001105B, 0x0C, 0x00011061, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > + {"_SB_.PC02.BR2B.MCTL", 0x5B80, 0x00011A39, 0x0C, 0x00011A3F, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > + {"_SB_.PC02.BR2C.MCTL", 0x5B80, 0x00012258, 0x0C, 0x0001225E, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > + {"_SB_.PC02.BR2D.MCTL", 0x5B80, 0x00012A77, 0x0C, 0x00012A7D, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > + {"_SB_.PC03.FIX1", 0x0011, 0x00000000, 0x88, 0x000134AE, > 0x0000000000000000}, /* WORDBUSNUMBER */ >=20 > + {"_SB_.PC03.FIX5", 0x0011, 0x00000000, 0x87, 0x000134BE, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > + {"_SB_.PC03.FIX2", 0x0011, 0x00000000, 0x88, 0x000134D8, > 0x0000000000000000}, /* WORDIO */ >=20 > + {"_SB_.PC03.FIX6", 0x0011, 0x00000000, 0x88, 0x000134E8, > 0x0000000000000000}, /* WORDIO */ >=20 > + {"_SB_.PC03.FIX7", 0x0011, 0x00000000, 0x88, 0x000134F8, > 0x0000000000000000}, /* WORDIO */ >=20 > + {"_SB_.PC03.FIX3", 0x0011, 0x00000000, 0x87, 0x00013508, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > + {"_SB_.PC03.FIX4", 0x0011, 0x00000000, 0x8A, 0x00013522, > 0x0000000000000000}, /* QWORDMEMORY */ >=20 > + {"_SB_.PC03.BR3A.MCTL", 0x5B80, 0x000135A4, 0x0C, 0x000135AA, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > + {"_SB_.PC03.BR3B.MCTL", 0x5B80, 0x00013DC3, 0x0C, 0x00013DC9, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > + {"_SB_.PC03.BR3C.MCTL", 0x5B80, 0x000145E2, 0x0C, 0x000145E8, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > + {"_SB_.PC03.BR3D.MCTL", 0x5B80, 0x00014E01, 0x0C, 0x00014E07, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > + {"_SB_.PC04.FIX1", 0x0011, 0x00000000, 0x88, 0x000157B2, > 0x0000000000000000}, /* WORDBUSNUMBER */ >=20 > + {"_SB_.PC04.FIX5", 0x0011, 0x00000000, 0x87, 0x000157C2, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > + {"_SB_.PC04.FIX2", 0x0011, 0x00000000, 0x88, 0x000157DC, > 0x0000000000000000}, /* WORDIO */ >=20 > + {"_SB_.PC04.FIX6", 0x0011, 0x00000000, 0x88, 0x000157EC, > 0x0000000000000000}, /* WORDIO */ >=20 > + {"_SB_.PC04.FIX7", 0x0011, 0x00000000, 0x88, 0x000157FC, > 0x0000000000000000}, /* WORDIO */ >=20 > + {"_SB_.PC04.FIX3", 0x0011, 0x00000000, 0x87, 0x0001580C, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > + {"_SB_.PC04.FIX4", 0x0011, 0x00000000, 0x8A, 0x00015826, > 0x0000000000000000}, /* QWORDMEMORY */ >=20 > + {"_SB_.PC04.MCP0.MCTL", 0x5B80, 0x000158A8, 0x0C, 0x000158AE, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > + {"_SB_.PC05.FIX1", 0x0011, 0x00000000, 0x88, 0x000161ED, > 0x0000000000000000}, /* WORDBUSNUMBER */ >=20 > + {"_SB_.PC05.FIX5", 0x0011, 0x00000000, 0x87, 0x000161FD, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > + {"_SB_.PC05.FIX2", 0x0011, 0x00000000, 0x88, 0x00016217, > 0x0000000000000000}, /* WORDIO */ >=20 > + {"_SB_.PC05.FIX6", 0x0011, 0x00000000, 0x88, 0x00016227, > 0x0000000000000000}, /* WORDIO */ >=20 > + {"_SB_.PC05.FIX7", 0x0011, 0x00000000, 0x88, 0x00016237, > 0x0000000000000000}, /* WORDIO */ >=20 > + {"_SB_.PC05.FIX3", 0x0011, 0x00000000, 0x87, 0x00016247, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > + {"_SB_.PC05.FIX4", 0x0011, 0x00000000, 0x8A, 0x00016261, > 0x0000000000000000}, /* QWORDMEMORY */ >=20 > + {"_SB_.PC05.MCP1.MCTL", 0x5B80, 0x000162E3, 0x0C, 0x000162E9, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > + {"_SB_.PC06.FIX1", 0x0011, 0x00000000, 0x88, 0x00017097, > 0x0000000000000000}, /* WORDBUSNUMBER */ >=20 > + {"_SB_.PC06.FIX5", 0x0011, 0x00000000, 0x87, 0x000170A7, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > + {"_SB_.PC06.FIX2", 0x0011, 0x00000000, 0x88, 0x000170C1, > 0x0000000000000000}, /* WORDIO */ >=20 > + {"_SB_.PC06.FIX6", 0x0011, 0x00000000, 0x88, 0x000170D1, > 0x0000000000000000}, /* WORDIO */ >=20 > + {"_SB_.PC06.FIX7", 0x0011, 0x00000000, 0x88, 0x000170E1, > 0x0000000000000000}, /* WORDIO */ >=20 > + {"_SB_.PC06.FIX3", 0x0011, 0x00000000, 0x87, 0x000170F1, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > + {"_SB_.PC06.FIX4", 0x0011, 0x00000000, 0x8A, 0x0001710B, > 0x0000000000000000}, /* QWORDMEMORY */ >=20 > + {"_SB_.PC06.QRP0.MCTL", 0x5B80, 0x00017207, 0x0C, 0x0001720D, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > + {"_SB_.PC07.FIX1", 0x0011, 0x00000000, 0x88, 0x00017C80, > 0x0000000000000000}, /* WORDBUSNUMBER */ >=20 > + {"_SB_.PC07.FIX5", 0x0011, 0x00000000, 0x87, 0x00017C90, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > + {"_SB_.PC07.FIX2", 0x0011, 0x00000000, 0x88, 0x00017CAA, > 0x0000000000000000}, /* WORDIO */ >=20 > + {"_SB_.PC07.FIX6", 0x0011, 0x00000000, 0x88, 0x00017CBA, > 0x0000000000000000}, /* WORDIO */ >=20 > + {"_SB_.PC07.FIX7", 0x0011, 0x00000000, 0x88, 0x00017CCA, > 0x0000000000000000}, /* WORDIO */ >=20 > + {"_SB_.PC07.FIX3", 0x0011, 0x00000000, 0x87, 0x00017CDA, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > + {"_SB_.PC07.FIX4", 0x0011, 0x00000000, 0x8A, 0x00017CF4, > 0x0000000000000000}, /* QWORDMEMORY */ >=20 > + {"_SB_.PC07.QR1A.MCTL", 0x5B80, 0x00017D86, 0x0C, 0x00017D8C, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > + {"_SB_.PC07.QR1B.MCTL", 0x5B80, 0x000185C0, 0x0C, 0x000185C6, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > + {"_SB_.PC07.QR1C.MCTL", 0x5B80, 0x00018DFA, 0x0C, 0x00018E00, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > + {"_SB_.PC07.QR1D.MCTL", 0x5B80, 0x00019634, 0x0C, 0x0001963A, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > + {"_SB_.PC08.FIX1", 0x0011, 0x00000000, 0x88, 0x0001A102, > 0x0000000000000000}, /* WORDBUSNUMBER */ >=20 > + {"_SB_.PC08.FIX5", 0x0011, 0x00000000, 0x87, 0x0001A112, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > + {"_SB_.PC08.FIX2", 0x0011, 0x00000000, 0x88, 0x0001A12C, > 0x0000000000000000}, /* WORDIO */ >=20 > + {"_SB_.PC08.FIX6", 0x0011, 0x00000000, 0x88, 0x0001A13C, > 0x0000000000000000}, /* WORDIO */ >=20 > + {"_SB_.PC08.FIX7", 0x0011, 0x00000000, 0x88, 0x0001A14C, > 0x0000000000000000}, /* WORDIO */ >=20 > + {"_SB_.PC08.FIX3", 0x0011, 0x00000000, 0x87, 0x0001A15C, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > + {"_SB_.PC08.FIX4", 0x0011, 0x00000000, 0x8A, 0x0001A176, > 0x0000000000000000}, /* QWORDMEMORY */ >=20 > + {"_SB_.PC08.QR2A.MCTL", 0x5B80, 0x0001A208, 0x0C, 0x0001A20E, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > + {"_SB_.PC08.QR2B.MCTL", 0x5B80, 0x0001AA42, 0x0C, 0x0001AA48, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > + {"_SB_.PC08.QR2C.MCTL", 0x5B80, 0x0001B27C, 0x0C, 0x0001B282, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > + {"_SB_.PC08.QR2D.MCTL", 0x5B80, 0x0001BAB6, 0x0C, 0x0001BABC, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > + {"_SB_.PC09.FIX1", 0x0011, 0x00000000, 0x88, 0x0001C50D, > 0x0000000000000000}, /* WORDBUSNUMBER */ >=20 > + {"_SB_.PC09.FIX5", 0x0011, 0x00000000, 0x87, 0x0001C51D, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > + {"_SB_.PC09.FIX2", 0x0011, 0x00000000, 0x88, 0x0001C537, > 0x0000000000000000}, /* WORDIO */ >=20 > + {"_SB_.PC09.FIX6", 0x0011, 0x00000000, 0x88, 0x0001C547, > 0x0000000000000000}, /* WORDIO */ >=20 > + {"_SB_.PC09.FIX7", 0x0011, 0x00000000, 0x88, 0x0001C557, > 0x0000000000000000}, /* WORDIO */ >=20 > + {"_SB_.PC09.FIX3", 0x0011, 0x00000000, 0x87, 0x0001C567, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > + {"_SB_.PC09.FIX4", 0x0011, 0x00000000, 0x8A, 0x0001C581, > 0x0000000000000000}, /* QWORDMEMORY */ >=20 > + {"_SB_.PC09.QR3A.MCTL", 0x5B80, 0x0001C613, 0x0C, 0x0001C619, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > + {"_SB_.PC09.QR3B.MCTL", 0x5B80, 0x0001CE4D, 0x0C, 0x0001CE53, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > + {"_SB_.PC09.QR3C.MCTL", 0x5B80, 0x0001D687, 0x0C, 0x0001D68D, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > + {"_SB_.PC09.QR3D.MCTL", 0x5B80, 0x0001DEC1, 0x0C, 0x0001DEC7, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > + {"_SB_.PC10.FIX1", 0x0011, 0x00000000, 0x88, 0x0001E892, > 0x0000000000000000}, /* WORDBUSNUMBER */ >=20 > + {"_SB_.PC10.FIX5", 0x0011, 0x00000000, 0x87, 0x0001E8A2, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > + {"_SB_.PC10.FIX2", 0x0011, 0x00000000, 0x88, 0x0001E8BC, > 0x0000000000000000}, /* WORDIO */ >=20 > + {"_SB_.PC10.FIX6", 0x0011, 0x00000000, 0x88, 0x0001E8CC, > 0x0000000000000000}, /* WORDIO */ >=20 > + {"_SB_.PC10.FIX7", 0x0011, 0x00000000, 0x88, 0x0001E8DC, > 0x0000000000000000}, /* WORDIO */ >=20 > + {"_SB_.PC10.FIX3", 0x0011, 0x00000000, 0x87, 0x0001E8EC, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > + {"_SB_.PC10.FIX4", 0x0011, 0x00000000, 0x8A, 0x0001E906, > 0x0000000000000000}, /* QWORDMEMORY */ >=20 > + {"_SB_.PC10.MCP2.MCTL", 0x5B80, 0x0001E998, 0x0C, 0x0001E99E, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > + {"_SB_.PC11.FIX1", 0x0011, 0x00000000, 0x88, 0x0001F2F2, > 0x0000000000000000}, /* WORDBUSNUMBER */ >=20 > + {"_SB_.PC11.FIX5", 0x0011, 0x00000000, 0x87, 0x0001F302, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > + {"_SB_.PC11.FIX2", 0x0011, 0x00000000, 0x88, 0x0001F31C, > 0x0000000000000000}, /* WORDIO */ >=20 > + {"_SB_.PC11.FIX6", 0x0011, 0x00000000, 0x88, 0x0001F32C, > 0x0000000000000000}, /* WORDIO */ >=20 > + {"_SB_.PC11.FIX7", 0x0011, 0x00000000, 0x88, 0x0001F33C, > 0x0000000000000000}, /* WORDIO */ >=20 > + {"_SB_.PC11.FIX3", 0x0011, 0x00000000, 0x87, 0x0001F34C, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > + {"_SB_.PC11.FIX4", 0x0011, 0x00000000, 0x8A, 0x0001F366, > 0x0000000000000000}, /* QWORDMEMORY */ >=20 > + {"_SB_.PC11.MCP3.MCTL", 0x5B80, 0x0001F3F8, 0x0C, 0x0001F3FE, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > + {"_SB_.PC12.FIX1", 0x0011, 0x00000000, 0x88, 0x000201BC, > 0x0000000000000000}, /* WORDBUSNUMBER */ >=20 > + {"_SB_.PC12.FIX5", 0x0011, 0x00000000, 0x87, 0x000201CC, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > + {"_SB_.PC12.FIX2", 0x0011, 0x00000000, 0x88, 0x000201E6, > 0x0000000000000000}, /* WORDIO */ >=20 > + {"_SB_.PC12.FIX6", 0x0011, 0x00000000, 0x88, 0x000201F6, > 0x0000000000000000}, /* WORDIO */ >=20 > + {"_SB_.PC12.FIX7", 0x0011, 0x00000000, 0x88, 0x00020206, > 0x0000000000000000}, /* WORDIO */ >=20 > + {"_SB_.PC12.FIX3", 0x0011, 0x00000000, 0x87, 0x00020216, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > + {"_SB_.PC12.FIX4", 0x0011, 0x00000000, 0x8A, 0x00020230, > 0x0000000000000000}, /* QWORDMEMORY */ >=20 > + {"_SB_.PC12.RRP0.MCTL", 0x5B80, 0x0002032C, 0x0C, 0x00020332, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > + {"_SB_.PC13.FIX1", 0x0011, 0x00000000, 0x88, 0x00020DA5, > 0x0000000000000000}, /* WORDBUSNUMBER */ >=20 > + {"_SB_.PC13.FIX5", 0x0011, 0x00000000, 0x87, 0x00020DB5, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > + {"_SB_.PC13.FIX2", 0x0011, 0x00000000, 0x88, 0x00020DCF, > 0x0000000000000000}, /* WORDIO */ >=20 > + {"_SB_.PC13.FIX6", 0x0011, 0x00000000, 0x88, 0x00020DDF, > 0x0000000000000000}, /* WORDIO */ >=20 > + {"_SB_.PC13.FIX7", 0x0011, 0x00000000, 0x88, 0x00020DEF, > 0x0000000000000000}, /* WORDIO */ >=20 > + {"_SB_.PC13.FIX3", 0x0011, 0x00000000, 0x87, 0x00020DFF, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > + {"_SB_.PC13.FIX4", 0x0011, 0x00000000, 0x8A, 0x00020E19, > 0x0000000000000000}, /* QWORDMEMORY */ >=20 > + {"_SB_.PC13.RR1A.MCTL", 0x5B80, 0x00020EAB, 0x0C, 0x00020EB1, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > + {"_SB_.PC13.RR1B.MCTL", 0x5B80, 0x000216E5, 0x0C, 0x000216EB, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > + {"_SB_.PC13.RR1C.MCTL", 0x5B80, 0x00021F1F, 0x0C, 0x00021F25, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > + {"_SB_.PC13.RR1D.MCTL", 0x5B80, 0x00022759, 0x0C, 0x0002275F, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > + {"_SB_.PC14.FIX1", 0x0011, 0x00000000, 0x88, 0x00023205, > 0x0000000000000000}, /* WORDBUSNUMBER */ >=20 > + {"_SB_.PC14.FIX5", 0x0011, 0x00000000, 0x87, 0x00023215, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > + {"_SB_.PC14.FIX2", 0x0011, 0x00000000, 0x88, 0x0002322F, > 0x0000000000000000}, /* WORDIO */ >=20 > + {"_SB_.PC14.FIX6", 0x0011, 0x00000000, 0x88, 0x0002323F, > 0x0000000000000000}, /* WORDIO */ >=20 > + {"_SB_.PC14.FIX7", 0x0011, 0x00000000, 0x88, 0x0002324F, > 0x0000000000000000}, /* WORDIO */ >=20 > + {"_SB_.PC14.FIX3", 0x0011, 0x00000000, 0x87, 0x0002325F, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > + {"_SB_.PC14.FIX4", 0x0011, 0x00000000, 0x8A, 0x00023279, > 0x0000000000000000}, /* QWORDMEMORY */ >=20 > + {"_SB_.PC14.RR2A.MCTL", 0x5B80, 0x0002330B, 0x0C, 0x00023311, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > + {"_SB_.PC14.RR2B.MCTL", 0x5B80, 0x00023B45, 0x0C, 0x00023B4B, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > + {"_SB_.PC14.RR2C.MCTL", 0x5B80, 0x0002437F, 0x0C, 0x00024385, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > + {"_SB_.PC14.RR2D.MCTL", 0x5B80, 0x00024BB9, 0x0C, 0x00024BBF, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > + {"_SB_.PC15.FIX1", 0x0011, 0x00000000, 0x88, 0x00025610, > 0x0000000000000000}, /* WORDBUSNUMBER */ >=20 > + {"_SB_.PC15.FIX5", 0x0011, 0x00000000, 0x87, 0x00025620, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > + {"_SB_.PC15.FIX2", 0x0011, 0x00000000, 0x88, 0x0002563A, > 0x0000000000000000}, /* WORDIO */ >=20 > + {"_SB_.PC15.FIX6", 0x0011, 0x00000000, 0x88, 0x0002564A, > 0x0000000000000000}, /* WORDIO */ >=20 > + {"_SB_.PC15.FIX7", 0x0011, 0x00000000, 0x88, 0x0002565A, > 0x0000000000000000}, /* WORDIO */ >=20 > + {"_SB_.PC15.FIX3", 0x0011, 0x00000000, 0x87, 0x0002566A, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > + {"_SB_.PC15.FIX4", 0x0011, 0x00000000, 0x8A, 0x00025684, > 0x0000000000000000}, /* QWORDMEMORY */ >=20 > + {"_SB_.PC15.RR3A.MCTL", 0x5B80, 0x00025716, 0x0C, 0x0002571C, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > + {"_SB_.PC15.RR3B.MCTL", 0x5B80, 0x00025F50, 0x0C, 0x00025F56, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > + {"_SB_.PC15.RR3C.MCTL", 0x5B80, 0x0002678A, 0x0C, 0x00026790, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > + {"_SB_.PC15.RR3D.MCTL", 0x5B80, 0x00026FC4, 0x0C, 0x00026FCA, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > + {"_SB_.PC16.FIX1", 0x0011, 0x00000000, 0x88, 0x00027995, > 0x0000000000000000}, /* WORDBUSNUMBER */ >=20 > + {"_SB_.PC16.FIX5", 0x0011, 0x00000000, 0x87, 0x000279A5, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > + {"_SB_.PC16.FIX2", 0x0011, 0x00000000, 0x88, 0x000279BF, > 0x0000000000000000}, /* WORDIO */ >=20 > + {"_SB_.PC16.FIX6", 0x0011, 0x00000000, 0x88, 0x000279CF, > 0x0000000000000000}, /* WORDIO */ >=20 > + {"_SB_.PC16.FIX7", 0x0011, 0x00000000, 0x88, 0x000279DF, > 0x0000000000000000}, /* WORDIO */ >=20 > + {"_SB_.PC16.FIX3", 0x0011, 0x00000000, 0x87, 0x000279EF, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > + {"_SB_.PC16.FIX4", 0x0011, 0x00000000, 0x8A, 0x00027A09, > 0x0000000000000000}, /* QWORDMEMORY */ >=20 > + {"_SB_.PC16.MCP4.MCTL", 0x5B80, 0x00027A9B, 0x0C, 0x00027AA1, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > + {"_SB_.PC17.FIX1", 0x0011, 0x00000000, 0x88, 0x000283F5, > 0x0000000000000000}, /* WORDBUSNUMBER */ >=20 > + {"_SB_.PC17.FIX5", 0x0011, 0x00000000, 0x87, 0x00028405, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > + {"_SB_.PC17.FIX2", 0x0011, 0x00000000, 0x88, 0x0002841F, > 0x0000000000000000}, /* WORDIO */ >=20 > + {"_SB_.PC17.FIX6", 0x0011, 0x00000000, 0x88, 0x0002842F, > 0x0000000000000000}, /* WORDIO */ >=20 > + {"_SB_.PC17.FIX7", 0x0011, 0x00000000, 0x88, 0x0002843F, > 0x0000000000000000}, /* WORDIO */ >=20 > + {"_SB_.PC17.FIX3", 0x0011, 0x00000000, 0x87, 0x0002844F, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > + {"_SB_.PC17.FIX4", 0x0011, 0x00000000, 0x8A, 0x00028469, > 0x0000000000000000}, /* QWORDMEMORY */ >=20 > + {"_SB_.PC17.MCP5.MCTL", 0x5B80, 0x000284FB, 0x0C, 0x00028501, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > + {"_SB_.PC18.FIX1", 0x0011, 0x00000000, 0x88, 0x000292BF, > 0x0000000000000000}, /* WORDBUSNUMBER */ >=20 > + {"_SB_.PC18.FIX5", 0x0011, 0x00000000, 0x87, 0x000292CF, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > + {"_SB_.PC18.FIX2", 0x0011, 0x00000000, 0x88, 0x000292E9, > 0x0000000000000000}, /* WORDIO */ >=20 > + {"_SB_.PC18.FIX6", 0x0011, 0x00000000, 0x88, 0x000292F9, > 0x0000000000000000}, /* WORDIO */ >=20 > + {"_SB_.PC18.FIX7", 0x0011, 0x00000000, 0x88, 0x00029309, > 0x0000000000000000}, /* WORDIO */ >=20 > + {"_SB_.PC18.FIX3", 0x0011, 0x00000000, 0x87, 0x00029319, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > + {"_SB_.PC18.FIX4", 0x0011, 0x00000000, 0x8A, 0x00029333, > 0x0000000000000000}, /* QWORDMEMORY */ >=20 > + {"_SB_.PC18.SRP0.MCTL", 0x5B80, 0x0002942F, 0x0C, 0x00029435, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > + {"_SB_.PC19.FIX1", 0x0011, 0x00000000, 0x88, 0x00029EA8, > 0x0000000000000000}, /* WORDBUSNUMBER */ >=20 > + {"_SB_.PC19.FIX5", 0x0011, 0x00000000, 0x87, 0x00029EB8, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > + {"_SB_.PC19.FIX2", 0x0011, 0x00000000, 0x88, 0x00029ED2, > 0x0000000000000000}, /* WORDIO */ >=20 > + {"_SB_.PC19.FIX6", 0x0011, 0x00000000, 0x88, 0x00029EE2, > 0x0000000000000000}, /* WORDIO */ >=20 > + {"_SB_.PC19.FIX7", 0x0011, 0x00000000, 0x88, 0x00029EF2, > 0x0000000000000000}, /* WORDIO */ >=20 > + {"_SB_.PC19.FIX3", 0x0011, 0x00000000, 0x87, 0x00029F02, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > + {"_SB_.PC19.FIX4", 0x0011, 0x00000000, 0x8A, 0x00029F1C, > 0x0000000000000000}, /* QWORDMEMORY */ >=20 > + {"_SB_.PC19.SR1A.MCTL", 0x5B80, 0x00029FAE, 0x0C, 0x00029FB4, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > + {"_SB_.PC19.SR1B.MCTL", 0x5B80, 0x0002A7E8, 0x0C, 0x0002A7EE, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > + {"_SB_.PC19.SR1C.MCTL", 0x5B80, 0x0002B022, 0x0C, 0x0002B028, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > + {"_SB_.PC19.SR1D.MCTL", 0x5B80, 0x0002B85C, 0x0C, 0x0002B862, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > + {"_SB_.PC20.FIX1", 0x0011, 0x00000000, 0x88, 0x0002C32A, > 0x0000000000000000}, /* WORDBUSNUMBER */ >=20 > + {"_SB_.PC20.FIX5", 0x0011, 0x00000000, 0x87, 0x0002C33A, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > + {"_SB_.PC20.FIX2", 0x0011, 0x00000000, 0x88, 0x0002C354, > 0x0000000000000000}, /* WORDIO */ >=20 > + {"_SB_.PC20.FIX6", 0x0011, 0x00000000, 0x88, 0x0002C364, > 0x0000000000000000}, /* WORDIO */ >=20 > + {"_SB_.PC20.FIX7", 0x0011, 0x00000000, 0x88, 0x0002C374, > 0x0000000000000000}, /* WORDIO */ >=20 > + {"_SB_.PC20.FIX3", 0x0011, 0x00000000, 0x87, 0x0002C384, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > + {"_SB_.PC20.FIX4", 0x0011, 0x00000000, 0x8A, 0x0002C39E, > 0x0000000000000000}, /* QWORDMEMORY */ >=20 > + {"_SB_.PC20.SR2A.MCTL", 0x5B80, 0x0002C430, 0x0C, 0x0002C436, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > + {"_SB_.PC20.SR2B.MCTL", 0x5B80, 0x0002CC6A, 0x0C, 0x0002CC70, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > + {"_SB_.PC20.SR2C.MCTL", 0x5B80, 0x0002D4A4, 0x0C, 0x0002D4AA, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > + {"_SB_.PC20.SR2D.MCTL", 0x5B80, 0x0002DCDE, 0x0C, 0x0002DCE4, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > + {"_SB_.PC21.FIX1", 0x0011, 0x00000000, 0x88, 0x0002E735, > 0x0000000000000000}, /* WORDBUSNUMBER */ >=20 > + {"_SB_.PC21.FIX5", 0x0011, 0x00000000, 0x87, 0x0002E745, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > + {"_SB_.PC21.FIX2", 0x0011, 0x00000000, 0x88, 0x0002E75F, > 0x0000000000000000}, /* WORDIO */ >=20 > + {"_SB_.PC21.FIX6", 0x0011, 0x00000000, 0x88, 0x0002E76F, > 0x0000000000000000}, /* WORDIO */ >=20 > + {"_SB_.PC21.FIX7", 0x0011, 0x00000000, 0x88, 0x0002E77F, > 0x0000000000000000}, /* WORDIO */ >=20 > + {"_SB_.PC21.FIX3", 0x0011, 0x00000000, 0x87, 0x0002E78F, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > + {"_SB_.PC21.FIX4", 0x0011, 0x00000000, 0x8A, 0x0002E7A9, > 0x0000000000000000}, /* QWORDMEMORY */ >=20 > + {"_SB_.PC21.SR3A.MCTL", 0x5B80, 0x0002E83B, 0x0C, 0x0002E841, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > + {"_SB_.PC21.SR3B.MCTL", 0x5B80, 0x0002F075, 0x0C, 0x0002F07B, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > + {"_SB_.PC21.SR3C.MCTL", 0x5B80, 0x0002F8AF, 0x0C, 0x0002F8B5, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > + {"_SB_.PC21.SR3D.MCTL", 0x5B80, 0x000300E9, 0x0C, 0x000300EF, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > + {"_SB_.PC22.FIX1", 0x0011, 0x00000000, 0x88, 0x00030ABA, > 0x0000000000000000}, /* WORDBUSNUMBER */ >=20 > + {"_SB_.PC22.FIX5", 0x0011, 0x00000000, 0x87, 0x00030ACA, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > + {"_SB_.PC22.FIX2", 0x0011, 0x00000000, 0x88, 0x00030AE4, > 0x0000000000000000}, /* WORDIO */ >=20 > + {"_SB_.PC22.FIX6", 0x0011, 0x00000000, 0x88, 0x00030AF4, > 0x0000000000000000}, /* WORDIO */ >=20 > + {"_SB_.PC22.FIX7", 0x0011, 0x00000000, 0x88, 0x00030B04, > 0x0000000000000000}, /* WORDIO */ >=20 > + {"_SB_.PC22.FIX3", 0x0011, 0x00000000, 0x87, 0x00030B14, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > + {"_SB_.PC22.FIX4", 0x0011, 0x00000000, 0x8A, 0x00030B2E, > 0x0000000000000000}, /* QWORDMEMORY */ >=20 > + {"_SB_.PC22.MCP6.MCTL", 0x5B80, 0x00030BC0, 0x0C, 0x00030BC6, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > + {"_SB_.PC23.FIX1", 0x0011, 0x00000000, 0x88, 0x0003151A, > 0x0000000000000000}, /* WORDBUSNUMBER */ >=20 > + {"_SB_.PC23.FIX5", 0x0011, 0x00000000, 0x87, 0x0003152A, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > + {"_SB_.PC23.FIX2", 0x0011, 0x00000000, 0x88, 0x00031544, > 0x0000000000000000}, /* WORDIO */ >=20 > + {"_SB_.PC23.FIX6", 0x0011, 0x00000000, 0x88, 0x00031554, > 0x0000000000000000}, /* WORDIO */ >=20 > + {"_SB_.PC23.FIX7", 0x0011, 0x00000000, 0x88, 0x00031564, > 0x0000000000000000}, /* WORDIO */ >=20 > + {"_SB_.PC23.FIX3", 0x0011, 0x00000000, 0x87, 0x00031574, > 0x0000000000000000}, /* DWORDMEMORY */ >=20 > + {"_SB_.PC23.FIX4", 0x0011, 0x00000000, 0x8A, 0x0003158E, > 0x0000000000000000}, /* QWORDMEMORY */ >=20 > + {"_SB_.PC23.MCP7.MCTL", 0x5B80, 0x00031620, 0x0C, 0x00031626, > 0x0000000038584946}, /* OPERATIONREGION */ >=20 > {NULL,0,0,0,0,0} /* Table terminator */ >=20 > }; >=20 >=20 >=20 > diff --git > a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxeDs > dt.c > b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxeDs > dt.c > index a4d58cab60..110f1cd7fe 100644 > --- > a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxeDs > dt.c > +++ > b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxeDs > dt.c > @@ -1,6 +1,7 @@ > /** @file >=20 >=20 >=20 > Copyright (c) 2018, Intel Corporation. All rights reserved.
>=20 > +Copyright (c) 2021, American Megatrends International LLC.
>=20 > SPDX-License-Identifier: BSD-2-Clause-Patent >=20 >=20 >=20 > **/ >=20 > @@ -292,6 +293,8 @@ PatchDsdtTable ( > case (SIGNATURE_32 ('F', 'I', 'X', '0')): >=20 > DEBUG ((DEBUG_INFO, "FIX0 - 0x%x\n", mAcpiParameter)); >=20 > * (UINT32 *) DsdtPointer =3D (UINT32) (UINTN) mAcpiParameter; >=20 > + Fixes++; >=20 > + break; >=20 > // >=20 > // "FIX8" OperationRegion() in Acpi\AcpiTables\Dsdt\PcieHp.asi >=20 > // >=20 > diff --git > a/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/CoreDxeInclude.dsc > b/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/CoreDxeInclude.dsc > new file mode 100644 > index 0000000000..7dcb892dd5 > --- /dev/null > +++ > b/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/CoreDxeInclude.dsc > @@ -0,0 +1,165 @@ > +## @file > +# Platform description. > +# > +# Copyright (c) 2018, Intel Corporation. All rights reserved.
> +# Copyright (c) 2021, American Megatrends International LLC.
> +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > +## > + > + > + # > + # Generic EDKII Driver > + # > + MdeModulePkg/Core/Dxe/DxeMain.inf { > + > + > NULL|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDec > ompressLib.inf > + } > + MdeModulePkg/Universal/PCD/Dxe/Pcd.inf { > + > + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf > + } > + > + > MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportSt > atusCodeRouterRuntimeDxe.inf > + > MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHan > dlerRuntimeDxe.inf > + > + UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf > + MdeModulePkg/Universal/Metronome/Metronome.inf > + MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf > + > PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntime > Dxe.inf > + MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf > + > +!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly =3D=3D FALSE > + > MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteSmm.i > nf > + > MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmmRuntimeDxe.i > nf > + MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmm.inf { > + > + NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf > + NULL|MdeModulePkg/Library/VarCheckHiiLib/VarCheckHiiLib.inf > + NULL|MdeModulePkg/Library/VarCheckPolicyLib/VarCheckPolicyLib.inf > + } > +!else > + MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf > { > + > + > gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvModeEnable|TRUE > + } > +!endif > + > + > MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCoun > terRuntimeDxe.inf > + > + MdeModulePkg/Universal/BdsDxe/BdsDxe.inf { > + > +!if gMinPlatformPkgTokenSpaceGuid.PcdSerialTerminalEnable =3D=3D TRUE > + > NULL|MinPlatformPkg/Library/SerialPortTerminalLib/SerialPortTerminalLib.i= n > f > +!endif > + } > + > +!if gMinPlatformPkgTokenSpaceGuid.PcdSerialTerminalEnable =3D=3D TRUE > + MdeModulePkg/Universal/SerialDxe/SerialDxe.inf > + MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf > +!endif > + > + > MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManager > Dxe.inf > + MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf { > + > +!if gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable =3D=3D TRUE > + > NULL|SecurityPkg/Library/DxeImageVerificationLib/DxeImageVerificationLib > .inf > +!endif > +!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable =3D=3D TRUE > + > NULL|SecurityPkg/Library/DxeTpm2MeasureBootLib/DxeTpm2MeasureBoot > Lib.inf > +!endif > + } > + > + MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf > + > + #UefiCpuPkg/CpuDxe/CpuDxe.inf > + > + > MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntime > Dxe.inf > + PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf > + > + #MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf > + MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf > + > + MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf > + MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf > + MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf > + MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf > + MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf > + MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf > + MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf > + MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf > + MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf > + > + MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf > + MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf > + > MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf > + FatPkg/EnhancedFatDxe/Fat.inf > + > + > #MdeModulePkg/Universal/Console/GraphicsOutputDxe/GraphicsOutputD > xe.inf > + > MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleD > xe.inf > + > + MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf > + MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf > + > + MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf > + > + > MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryT > estDxe.inf > + > + MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf > + MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf > + > + MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf > + > + MdeModulePkg/Application/UiApp/UiApp.inf { > + > + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf > + > NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf > + > NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf > + > NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMainte > nanceManagerUiLib.inf > + } > + > MdeModulePkg/Application/BootManagerMenuApp/BootManagerMenuAp > p.inf { > + > + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf > + } > + > +!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly =3D=3D FALSE > + MdeModulePkg/Core/PiSmmCore/PiSmmIpl.inf > + MdeModulePkg/Core/PiSmmCore/PiSmmCore.inf > + > + > MdeModulePkg/Universal/ReportStatusCodeRouter/Smm/ReportStatusCod > eRouterSmm.inf > + > MdeModulePkg/Universal/StatusCodeHandler/Smm/StatusCodeHandlerSm > m.inf > + > + #UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf > + > + UefiCpuPkg/CpuIo2Smm/CpuIo2Smm.inf > + > MdeModulePkg/Universal/SmmCommunicationBufferDxe/SmmCommunica > tionBufferDxe.inf > +!endif > + > +!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly =3D=3D FALSE > + MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf > + > MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTableDxe/Firmw > arePerformanceDxe.inf > + > MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTableSmm/Firm > warePerformanceSmm.inf > + > MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraph > icsResourceTableDxe.inf > +!endif > + > +!if gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable =3D=3D TRUE > + > SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfi > gDxe.inf > +!endif > + > +!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable =3D=3D TRUE > + SecurityPkg/Tcg/MemoryOverwriteControl/TcgMor.inf > + SecurityPkg/Tcg/Tcg2Dxe/Tcg2Dxe.inf { > + > + > Tpm2DeviceLib|SecurityPkg/Library/Tpm2DeviceLibRouter/Tpm2DeviceLibR > outerDxe.inf > + > NULL|SecurityPkg/Library/Tpm2DeviceLibDTpm/Tpm2InstanceLibDTpm.inf > + > NULL|SecurityPkg/Library/HashInstanceLibSha256/HashInstanceLibSha256.in > f > + } > + SecurityPkg/Tcg/Tcg2Smm/Tcg2Smm.inf > + SecurityPkg/Tcg/Tcg2Acpi/Tcg2Acpi.inf > + SecurityPkg/Tcg/Tcg2Config/Tcg2ConfigDxe.inf > +!endif > + > +!if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable =3D=3D TRUE > + > ShellPkg/DynamicCommand/DpDynamicCommand/DpDynamicCommand.inf > +!endif > + > diff --git > a/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/CoreUefiBootInclud > e.fdf > b/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/CoreUefiBootInclud > e.fdf > new file mode 100644 > index 0000000000..478a818546 > --- /dev/null > +++ > b/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/CoreUefiBootInclud > e.fdf > @@ -0,0 +1,79 @@ > +## @file > +# FDF file of Platform. > +# > +# Copyright (c) 2018, Intel Corporation. All rights reserved.
> +# Copyright (c) 2021, American Megatrends International LLC.
> +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > +## > + > +INF MdeModulePkg/Core/Dxe/DxeMain.inf > + > +INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf > +INF > MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportSt > atusCodeRouterRuntimeDxe.inf > +INF > MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHan > dlerRuntimeDxe.inf > + > +INF UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf > +INF MdeModulePkg/Universal/Metronome/Metronome.inf > +INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf > +INF > PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntime > Dxe.inf > +INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf > + > +!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly =3D=3D TRUE > +INF > MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf > +!endif > + > +INF > MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCoun > terRuntimeDxe.inf > + > +INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf > + > +!if gMinPlatformPkgTokenSpaceGuid.PcdSerialTerminalEnable =3D=3D TRUE > +INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf > +INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf > +!endif > + > +INF > MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManager > Dxe.inf > +INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf > +INF > MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf > + > +#INF UefiCpuPkg/CpuDxe/CpuDxe.inf > + > +INF > MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntime > Dxe.inf > +INF PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf > + > +#INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf > +INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf > + > +INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf > +INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf > +INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf > + > +INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf > +INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf > +INF MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf > +INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf > +INF > MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf > +INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf > + > +INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf > +INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf > +INF > MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf > +INF FatPkg/EnhancedFatDxe/Fat.inf > + > +#INF > MdeModulePkg/Universal/Console/GraphicsOutputDxe/GraphicsOutputDx > e.inf > +INF > MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleD > xe.inf > + > +INF > MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf > +INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf > + > +INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf > + > +INF > MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryT > estDxe.inf > + > +INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf > +INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf > +INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf > + > +INF MdeModulePkg/Application/UiApp/UiApp.inf > +INF > MdeModulePkg/Application/BootManagerMenuApp/BootManagerMenuAp > p.inf > + > diff --git > a/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/GitEdk2MinTiogaPas > s.bat > b/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/GitEdk2MinTiogaPas > s.bat > new file mode 100644 > index 0000000000..6b899f7f31 > --- /dev/null > +++ > b/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/GitEdk2MinTiogaPas > s.bat > @@ -0,0 +1,93 @@ > +@REM @file > +@REM > +@REM Copyright (c) 2018, Intel Corporation. All rights reserved.
> +@REM Copyright (c) 2021, American Megatrends International LLC.
> +@REM SPDX-License-Identifier: BSD-2-Clause-Patent > +@REM > + > +@echo off > + > +pushd ..\..\..\..\..\ > + > +@REM Set WORKSPACE environment. > +set WORKSPACE=3D%cd% > +echo. > +echo Set WORKSPACE as: %WORKSPACE% > +echo. > + > +@REM Check whether Git has been installed and been added to system > path. > +git --help >nul 2>nul > +if %ERRORLEVEL% NEQ 0 ( > + echo. > + echo The 'git' command is not recognized. > + echo Please make sure that Git is installed and has been added to syst= em > path. > + echo. > + goto :EOF > +) > + > +@REM Create the Conf directory under WORKSPACE > +if not exist %WORKSPACE%\Conf ( > + mkdir Conf > +) > + > +@REM Set other environments. > +@REM Basic Rule: > +@REM Platform override Silicon override Core > +@REM Source override Binary > + > +set PACKAGES_PATH=3D%WORKSPACE%\edk2- > platforms\Platform\Intel;%WORKSPACE%\edk2- > platforms\Silicon\Intel;%WORKSPACE%\edk2- > platforms\Features\Intel;%WORKSPACE%\edk2- > platforms\Features\Intel\Debugging;%WORKSPACE%\edk2- > platforms\Features\Intel\Network;%WORKSPACE%\edk2- > platforms\Features\Intel\OutOfBandManagement;%WORKSPACE%\edk2- > platforms\Features\Intel\PowerManagement;%WORKSPACE%\edk2- > platforms\Features\Intel\SystemInformation;%WORKSPACE%\edk2- > platforms\Features\Intel\UserInterface;%WORKSPACE%\edk2-non- > osi\Silicon\Intel;%WORKSPACE%\edk2;%WORKSPACE% > + > +set EDK_TOOLS_BIN=3D%WORKSPACE%\edk2-BaseTools-win32 > + > +@if not defined PYTHON_HOME ( > + @if exist C:\Python27 ( > + set PYTHON_HOME=3DC:\Python27 > + ) > +) > + > +set EDK_SETUP_OPTION=3D > +@rem if python is installed, disable the binary base tools. > +if defined PYTHON_HOME ( > + set EDK_TOOLS_BIN=3D > + set EDK_SETUP_OPTION=3DRebuild > +) > +pushd %WORKSPACE%\edk2 > +call edksetup.bat %EDK_SETUP_OPTION% > +popd > + > + if exist "ProgramFiles(x86)%\Windows Kits\8.1\bin" ( > + echo "ProgramFiles(x86)\Windows Kits\8.1\bin present" > + echo "No need to override WINSDK81_PREFIX/WINSDK81x86_PREFIX" > + ) else ( > + echo "ProgramFiles(x86)\Windows Kits\8.1\bin not present" > + echo "Need to override WINSDK81_PREFIX/WINSDK81x86_PREFIX with > WINSDK10_PREFIX " > + echo WINSDK81_PREFIX defined "%WINSDK81_PREFIX%" > + echo WINSDK81x86_PREFIX "%WINSDK81x86_PREFIX%" > + if defined WINSDK10_PREFIX ( > + echo WINSDK10_PREFIX defined 1 "%WINSDK10_PREFIX%" > + set "WINSDK81_PREFIX=3D%WINSDK10_PREFIX%" > + set "WINSDK81x86_PREFIX=3D%WINSDK10_PREFIX%" > + ) else ( > + echo Build may fail when trying to find RC.exe > + goto :EOF > + ) > + ) > + > +set openssl_path=3D%WORKSPACE% > + > +popd > + > +goto :EOF > + > +:Help > +echo. > +echo Usage: > +echo GitEdk2.bat [-w Workspace_Directory] (optional) [-b Branch_Name] > (optional) > +echo. > +echo -w A absolute/relative path to be the workspace. > +echo Default value is the current directory. > +echo. > +echo -b The branch name of the repository. Currently, only master, > udk2015, > +echo trunk (same as master) and bp13 (same as udk2015) are support= ed. > +echo Default value is master. > +echo. > diff --git > a/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BasePlatfor > mHookLib/BasePlatformHookLib.c > b/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BasePlatfor > mHookLib/BasePlatformHookLib.c > new file mode 100644 > index 0000000000..cadc89ccf1 > --- /dev/null > +++ > b/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BasePlatfor > mHookLib/BasePlatformHookLib.c > @@ -0,0 +1,389 @@ > +/** @file > + > +Copyright (c) 2018, Intel Corporation. All rights reserved.
> +Copyright (c) 2021, American Megatrends International LLC.
> +SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > + > + > +#include > +#include > +#include > +#include > +#include > + > +#define R_ICH_IOPORT_PCI_INDEX 0xCF8 > +#define R_ICH_IOPORT_PCI_DATA 0xCFC > +#define R_ICH_LPC_IO_DEC 0x80 > + > +#define PCI_DEVICE_NUMBER_ICH_LPC 31 > +#define PCI_FUNCTION_NUMBER_ICH_LPC 0 > + > +#define PCI_CF8_ADDR(Bus, Dev, Func, Off) \ > + (((Off) & 0xFF) | (((Func) & 0x07) << 8) | (((Dev) & 0x1F) << = 11) | > (((Bus) & 0xFF) << 16) | (1 << 31)) > +#define ICH_LPC_CF8_ADDR(Offset) PCI_CF8_ADDR(0, > PCI_DEVICE_NUMBER_ICH_LPC, PCI_FUNCTION_NUMBER_ICH_LPC, Offset) > + > +#include "SioRegs.h" > + > +// > +// --------------------------------------------- > +// Additional SIO Regs for Tioga Pass > +// --------------------------------------------- > +// > +#define SCU_BASE 0x1E6E2000 > + > +#include > +#include > + > +// > +// --------------------------------------------- > +// UART Register Offsets > +// --------------------------------------------- > +// > +#define BAUD_LOW_OFFSET 0x00 > +#define BAUD_HIGH_OFFSET 0x01 > +#define IER_OFFSET 0x01 > +#define LCR_SHADOW_OFFSET 0x01 > +#define FCR_SHADOW_OFFSET 0x02 > +#define IR_CONTROL_OFFSET 0x02 > +#define FCR_OFFSET 0x02 > +#define EIR_OFFSET 0x02 > +#define BSR_OFFSET 0x03 > +#define LCR_OFFSET 0x03 > +#define MCR_OFFSET 0x04 > +#define LSR_OFFSET 0x05 > +#define MSR_OFFSET 0x06 > + > +// > +// --------------------------------------------- > +// UART Register Bit Defines > +// --------------------------------------------- > +// > +#define LSR_TXRDY 0x20 > +#define LSR_RXDA 0x01 > +#define DLAB 0x01 > + > +#define UART_DATA 8 > +#define UART_STOP 1 > +#define UART_PARITY 0 > +#define UART_BREAK_SET 0 > + > +UINT16 gComBase =3D 0x3f8; > +UINTN gBps =3D 115200; > +UINT8 gData =3D 8; > +UINT8 gStop =3D 1; > +UINT8 gParity =3D 0; > +UINT8 gBreakSet =3D 0; > + > +/** > + > + Write AHB register. > + > + @param RegIndex: register index. > + @param Value: Value to write > + > + @retval None. > + > +**/ > +VOID > +WriteAHBDword( > + UINT32 RegIndex, > + UINT32 Value > +) > +{ > + UINT8 bValue; > + > + IoWrite8 (SIO_INDEX_PORT, SIO_UNLOCK); > + IoWrite8 (SIO_INDEX_PORT, SIO_UNLOCK); > + > + IoWrite8 (SIO_INDEX_PORT, REG_LOGICAL_DEVICE); > + IoWrite8 (0xED, 0);//short delay. > + IoWrite8 (SIO_DATA_PORT, SIO_SMI); > + IoWrite8 (0xED, 0);//short delay. > + > + IoWrite8 (SIO_INDEX_PORT, 0x30); > + IoWrite8 (0xED, 0);//short delay. > + IoWrite8 (SIO_DATA_PORT, 1); > + IoWrite8 (0xED, 0);//short delay. > + > + IoWrite8 (SIO_INDEX_PORT, 0xf8); > + bValue =3D IoRead8(SIO_DATA_PORT); > + bValue &=3D 0xfc; > + bValue |=3D 2; // 4 byte window. > + IoWrite8 (SIO_DATA_PORT, bValue); > + IoWrite8 (0xED, 0);//short delay. > + > + IoWrite8 (SIO_INDEX_PORT, 0xf0); > + IoWrite8 (0xED, 0);//short delay. > + IoWrite8 (SIO_DATA_PORT, (UINT8)((RegIndex >> 24)& 0xff)); > + > + IoWrite8 (SIO_INDEX_PORT, 0xf1); > + IoWrite8 (0xED, 0);//short delay. > + IoWrite8 (SIO_DATA_PORT, (UINT8)((RegIndex >> 16)& 0xff)); > + > + IoWrite8 (SIO_INDEX_PORT, 0xf2); > + IoWrite8 (0xED, 0);//short delay. > + IoWrite8 (SIO_DATA_PORT, (UINT8)((RegIndex >> 8) & 0xff)); > + > + IoWrite8 (SIO_INDEX_PORT, 0xf3); > + IoWrite8 (0xED, 0);//short delay. > + IoWrite8 (SIO_DATA_PORT, (UINT8)((RegIndex )& 0xff)); > + > + IoWrite8 (SIO_INDEX_PORT, 0xf4); > + IoWrite8 (0xED, 0);//short delay. > + IoWrite8 (SIO_DATA_PORT, (UINT8)((Value >> 24)& 0xff)); > + > + IoWrite8 (SIO_INDEX_PORT, 0xf5); > + IoWrite8 (0xED, 0);//short delay. > + IoWrite8 (SIO_DATA_PORT, (UINT8)((Value >> 16)& 0xff)); > + > + IoWrite8 (SIO_INDEX_PORT, 0xf6); > + IoWrite8 (0xED, 0);//short delay. > + IoWrite8 (SIO_DATA_PORT, (UINT8)((Value >> 8) & 0xff)); > + > + IoWrite8 (SIO_INDEX_PORT, 0xf7); > + IoWrite8 (0xED, 0);//short delay. > + IoWrite8 (SIO_DATA_PORT, (UINT8)((Value )& 0xff)); > + > + // trigger write > + IoWrite8 (SIO_INDEX_PORT, 0xfe); > + IoWrite8 (SIO_DATA_PORT, 0xcf); > + > + IoWrite8 (SIO_INDEX_PORT, SIO_LOCK); > +} > + > +/** > + > + Read AHB register. > + > + @param RegIndex: register index. > + > + @retval value of register. > + > +**/ > +UINT32 > +ReadAHBDword( > + UINT32 RegIndex > +){ > + UINT8 bValue; > + UINT32 rdValue =3D 0; > + > + > + IoWrite8 (SIO_INDEX_PORT, SIO_UNLOCK); > + IoWrite8 (SIO_INDEX_PORT, SIO_UNLOCK); > + > + IoWrite8 (SIO_INDEX_PORT, REG_LOGICAL_DEVICE); > + IoWrite8 (0xED, 0);//short delay. > + IoWrite8 (SIO_DATA_PORT, SIO_SMI); > + IoWrite8 (0xED, 0);//short delay. > + > + IoWrite8 (SIO_INDEX_PORT, 0x30); > + IoWrite8 (0xED, 0);//short delay. > + IoWrite8 (SIO_DATA_PORT, 1); > + IoWrite8 (0xED, 0);//short delay. > + > + IoWrite8 (SIO_INDEX_PORT, 0xf8); > + bValue =3D IoRead8(SIO_DATA_PORT); > + bValue &=3D 0xfc; > + bValue |=3D 2; // 4 byte window. > + IoWrite8 (SIO_DATA_PORT, bValue); > + IoWrite8 (0xED, 0);//short delay. > + > + IoWrite8 (SIO_INDEX_PORT, 0xf0); > + IoWrite8 (0xED, 0);//short delay. > + IoWrite8 (SIO_DATA_PORT, (UINT8)((RegIndex >> 24)& 0xff)); > + > + IoWrite8 (SIO_INDEX_PORT, 0xf1); > + IoWrite8 (0xED, 0);//short delay. > + IoWrite8 (SIO_DATA_PORT, (UINT8)((RegIndex >> 16)& 0xff)); > + > + IoWrite8 (SIO_INDEX_PORT, 0xf2); > + IoWrite8 (0xED, 0);//short delay. > + IoWrite8 (SIO_DATA_PORT, (UINT8)((RegIndex >> 8) & 0xff)); > + > + IoWrite8 (SIO_INDEX_PORT, 0xf3); > + IoWrite8 (0xED, 0);//short delay. > + IoWrite8 (SIO_DATA_PORT, (UINT8)((RegIndex )& 0xff)); > + > + // trigger read > + IoWrite8 (SIO_INDEX_PORT, 0xfe); > + IoRead8 (SIO_DATA_PORT); > + > + > + IoWrite8 (SIO_INDEX_PORT, 0xf4); > + rdValue +=3D IoRead8 (SIO_DATA_PORT); > + rdValue <<=3D 8; > + > + IoWrite8 (SIO_INDEX_PORT, 0xf5); > + rdValue +=3D IoRead8 (SIO_DATA_PORT); > + rdValue <<=3D 8; > + > + IoWrite8 (SIO_INDEX_PORT, 0xf6); > + rdValue +=3D IoRead8 (SIO_DATA_PORT); > + rdValue <<=3D 8; > + > + IoWrite8 (SIO_INDEX_PORT, 0xf7); > + rdValue +=3D IoRead8 (SIO_DATA_PORT); > + > + IoWrite8 (SIO_INDEX_PORT, SIO_LOCK); > + return rdValue; > + > +} > + > +/** > + > + Initialize the AST2500 SIO. > + > + @param None > + > + @retval None > + > +**/ > +VOID > +InitializeSio ( > + VOID > + ) > +{ > + UINT32 Decode; > + UINT32 Enable; > + UINT32 Value; > + UINT32 Address; > + > + // > + // Enable LPC decode > + // Set COMA/COMB base > + // > + > + Decode =3D ((V_PCH_LPC_IOD_COMA_3F8 << N_PCH_LPC_IOD_COMA) | > (V_PCH_LPC_IOD_COMB_2F8 << N_PCH_LPC_IOD_COMB)); > + Enable =3D ( B_PCH_LPC_IOE_ME2 | B_PCH_LPC_IOE_SE | > B_PCH_LPC_IOE_ME1 \ > + | B_PCH_LPC_IOE_KE | B_PCH_LPC_IOE_CBE | > B_PCH_LPC_IOE_CAE); > + IoWrite32 (R_ICH_IOPORT_PCI_INDEX, (UINT32) (ICH_LPC_CF8_ADDR > (R_ICH_LPC_IO_DEC))); > + > + IoWrite32 (R_ICH_IOPORT_PCI_DATA, Decode | (Enable << 16)); > + > + MmioWrite16 (PCH_PCR_ADDRESS(PID_DMI, R_PCH_PCR_DMI_LPCIOD), > (UINT16)Decode); > + MmioWrite16 (PCH_PCR_ADDRESS(PID_DMI, R_PCH_PCR_DMI_LPCIOE), > (UINT16)Enable); > + > + > + > + IoWrite8 (SIO_INDEX_PORT, SIO_UNLOCK); > + IoWrite8 (SIO_INDEX_PORT, SIO_UNLOCK); > + > + // > + // Initialize COM1 > + // > + IoWrite8 (SIO_INDEX_PORT, REG_LOGICAL_DEVICE); > + IoWrite8 (SIO_DATA_PORT, SIO_UART1); > + > + IoWrite8 (SIO_INDEX_PORT, ACTIVATE); > + IoWrite8 (SIO_DATA_PORT, 0); > + > + IoWrite8 (SIO_INDEX_PORT, 0x70); > + IoWrite8 (SIO_DATA_PORT, 0x04); > + > + // > + // Set Base Address to gComBase > + // > + IoWrite8 (SIO_INDEX_PORT, BASE_ADDRESS_LOW0); > + IoWrite8 (SIO_DATA_PORT, (UINT8) (gComBase & 0xFF)); > + IoWrite8 (SIO_INDEX_PORT, BASE_ADDRESS_HIGH0); > + IoWrite8 (SIO_DATA_PORT, (UINT8)((gComBase >> 8) & 0xff)); > + > + // > + // Activate COM1 > + // > + IoWrite8 (SIO_INDEX_PORT, ACTIVATE); > + IoWrite8 (SIO_DATA_PORT, 1); > + > + IoWrite8 (SIO_INDEX_PORT, SIO_LOCK); > + > + // Initialize SCU part. > + Address =3D (UINT32)(SCU_BASE | 0x00); > + Value =3D ReadAHBDword(Address); > + Value &=3D 0x00000000; > + Value |=3D 0x1688A8A8; // Unlock SCU Registers > + WriteAHBDword(Address,Value); > + > + Address =3D (UINT32)(SCU_BASE | 0x84); > + Value =3D ReadAHBDword(Address); > + Value &=3D 0xFF3FFFFF; > + Value |=3D 0x00C00000; // SCU84[23:22]=3D"11b" Enable UART1 or video= VPB > Multi-Function pins > + WriteAHBDword(Address,Value); > + > + Address =3D (UINT32)(SCU_BASE | 0x90); > + Value =3D ReadAHBDword(Address); > + Value &=3D 0xFFFFFFDF; > + Value |=3D 0x00000000; // SCU90[5]=3D"0b" Disable digital video Mult= i- > Function pins > + WriteAHBDword(Address,Value); > + > + Address =3D (UINT32)(SCU_BASE | 0x94); > + Value =3D ReadAHBDword(Address); > + Value &=3D 0xFFFFFFFC; > + Value |=3D 0x00000000; // SCU94[1:0]=3D"00b" Disable digital video M= ulti- > Function pins > + WriteAHBDword(Address,Value); > + > + Address =3D (UINT32)(SCU_BASE | 0x00); > + Value =3D ReadAHBDword(Address); > + Value &=3D 0x00000000; > + Value |=3D 0x00000000; // Lock SCU Registers > + WriteAHBDword(Address,Value); > +} > + > +/** > + Performs platform specific initialization required for the CPU to acce= ss > + the hardware associated with a SerialPortLib instance. This function = does > + not initialize the serial port hardware itself. Instead, it initializ= es > + hardware devices that are required for the CPU to access the serial po= rt > + hardware. This function may be called more than once. > + > + @retval RETURN_SUCCESS The platform specific initialization > succeeded. > + @retval RETURN_DEVICE_ERROR The platform specific initialization coul= d > not be completed. > + > +**/ > +RETURN_STATUS > +EFIAPI > +PlatformHookSerialPortInitialize ( > + VOID > + ) > +{ > + UINTN Divisor; > + UINT8 OutputData; > + UINT8 Data; > + > + InitializeSio(); > + // > + // Some init is done by the platform status code initialization. > + // > + // > + // Map 5..8 to 0..3 > + // > + Data =3D (UINT8) (gData - (UINT8) 5); > + > + // > + // Calculate divisor for baud generator > + // > + Divisor =3D 115200 / gBps; > + > + // > + // Set communications format > + // > + OutputData =3D (UINT8) ((DLAB << 7) | ((gBreakSet << 6) | ((gParity <<= 3) | > ((gStop << 2) | Data)))); > + IoWrite8 (gComBase + LCR_OFFSET, OutputData); > + > + // > + // Configure baud rate > + // > + IoWrite8 (gComBase + BAUD_HIGH_OFFSET, (UINT8) (Divisor >> 8)); > + IoWrite8 (gComBase + BAUD_LOW_OFFSET, (UINT8) (Divisor & 0xff)); > + > + // > + // Switch back to bank 0 > + // > + OutputData =3D (UINT8) ((~DLAB << 7) | ((gBreakSet << 6) | ((gParity <= < 3) | > ((gStop << 2) | Data)))); > + IoWrite8 (gComBase + LCR_OFFSET, OutputData); > + > + return RETURN_SUCCESS; > +} > + > diff --git > a/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BasePlatfor > mHookLib/BasePlatformHookLib.inf > b/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BasePlatfor > mHookLib/BasePlatformHookLib.inf > new file mode 100644 > index 0000000000..cec595c38e > --- /dev/null > +++ > b/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BasePlatfor > mHookLib/BasePlatformHookLib.inf > @@ -0,0 +1,36 @@ > +## @file > +# > +# Copyright (c) 2018, Intel Corporation. All rights reserved.
> +# Copyright (c) 2021, American Megatrends International LLC.
> +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > +## > + > +[Defines] > + INF_VERSION =3D 0x00010017 > + BASE_NAME =3D BasePlatformHookLib > + FILE_GUID =3D E22ADCC6-ED90-4A90-9837-C8E7FF9E963= D > + VERSION_STRING =3D 1.0 > + MODULE_TYPE =3D BASE > + LIBRARY_CLASS =3D PlatformHookLib > +# > +# The following information is for reference only and not required by th= e > build tools. > +# > +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC > +# > + > +[LibraryClasses] > + BaseLib > + IoLib > + PciLib > + > +[Packages] > + MdePkg/MdePkg.dec > + MdeModulePkg/MdeModulePkg.dec > + PurleyOpenBoardPkg/OpenBoardPkg.dec > + PurleyRefreshSiliconPkg/SiPkg.dec > + > +[FixedPcd] > + > +[Sources] > + BasePlatformHookLib.c > diff --git > a/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardAcpiLib > /DxeBoardAcpiTableLib.c > b/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardAcpiLi > b/DxeBoardAcpiTableLib.c > new file mode 100644 > index 0000000000..5e5c473505 > --- /dev/null > +++ > b/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardAcpiLi > b/DxeBoardAcpiTableLib.c > @@ -0,0 +1,36 @@ > +/** @file > + > +Copyright (c) 2018, Intel Corporation. All rights reserved.
> +Copyright (c) 2021, American Megatrends International LLC.
> +SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +EFI_STATUS > +EFIAPI > +TiogaPassBoardUpdateAcpiTable ( > + IN OUT EFI_ACPI_COMMON_HEADER *Table, > + IN OUT EFI_ACPI_TABLE_VERSION *Version > + ); > + > +EFI_STATUS > +EFIAPI > +BoardUpdateAcpiTable ( > + IN OUT EFI_ACPI_COMMON_HEADER *Table, > + IN OUT EFI_ACPI_TABLE_VERSION *Version > + ) > +{ > + TiogaPassBoardUpdateAcpiTable (Table, Version); > + > + return EFI_SUCCESS; > +} > + > diff --git > a/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardAcpiLib > /DxeBoardAcpiTableLib.inf > b/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardAcpiLi > b/DxeBoardAcpiTableLib.inf > new file mode 100644 > index 0000000000..d35087edb2 > --- /dev/null > +++ > b/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardAcpiLi > b/DxeBoardAcpiTableLib.inf > @@ -0,0 +1,40 @@ > +## @file > +# > +# Copyright (c) 2018, Intel Corporation. All rights reserved.
> +# Copyright (c) 2021, American Megatrends International LLC.
> +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > +## > + > +[Defines] > + INF_VERSION =3D 0x00010017 > + BASE_NAME =3D DxeBoardAcpiTableLib > + FILE_GUID =3D 6562E0AE-90D8-4D41-8C97-81286B4BE7D= 2 > + VERSION_STRING =3D 1.0 > + MODULE_TYPE =3D BASE > + LIBRARY_CLASS =3D BoardAcpiTableLib > + > +# > +# The following information is for reference only and not required by th= e > build tools. > +# > +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC > +# > + > +[LibraryClasses] > + BaseLib > + IoLib > + PciLib > + > +[Packages] > + MdePkg/MdePkg.dec > + MdeModulePkg/MdeModulePkg.dec > + MinPlatformPkg/MinPlatformPkg.dec > + PurleyOpenBoardPkg/OpenBoardPkg.dec > + PurleyRefreshSiliconPkg/SiPkg.dec > + > +[Pcd] > + gOemSkuTokenSpaceGuid.PcdAcpiGnvsAddress > + > +[Sources] > + DxeTiogaPassAcpiTableLib.c > + DxeBoardAcpiTableLib.c > diff --git > a/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardAcpiLib > /DxeTiogaPassAcpiTableLib.c > b/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardAcpiLi > b/DxeTiogaPassAcpiTableLib.c > new file mode 100644 > index 0000000000..6e5e7490be > --- /dev/null > +++ > b/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardAcpiLi > b/DxeTiogaPassAcpiTableLib.c > @@ -0,0 +1,53 @@ > +/** @file > + > +Copyright (c) 2018, Intel Corporation. All rights reserved.
> +Copyright (c) 2021, American Megatrends International LLC.
> +SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +GLOBAL_REMOVE_IF_UNREFERENCED BIOS_ACPI_PARAM > *mGlobalNvsArea; > + > +VOID > +TiogaPassUpdateGlobalNvs ( > + VOID > + ) > +{ > + > + // > + // Allocate and initialize the NVS area for SMM and ASL communication. > + // > + mGlobalNvsArea =3D (VOID *)(UINTN)PcdGet64 (PcdAcpiGnvsAddress); > + > + // > + // Update global NVS area for ASL and SMM init code to use > + // > + > + > +} > + > +EFI_STATUS > +EFIAPI > +TiogaPassBoardUpdateAcpiTable ( > + IN OUT EFI_ACPI_COMMON_HEADER *Table, > + IN OUT EFI_ACPI_TABLE_VERSION *Version > + ) > +{ > + if (Table->Signature =3D=3D > EFI_ACPI_2_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE > ) { > + TiogaPassUpdateGlobalNvs (); > + } > + > + return EFI_SUCCESS; > +} > + > diff --git > a/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardAcpiLib > /SmmBoardAcpiEnableLib.c > b/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardAcpiLi > b/SmmBoardAcpiEnableLib.c > new file mode 100644 > index 0000000000..53ad66359c > --- /dev/null > +++ > b/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardAcpiLi > b/SmmBoardAcpiEnableLib.c > @@ -0,0 +1,62 @@ > +/** @file > + > +Copyright (c) 2018, Intel Corporation. All rights reserved.
> +Copyright (c) 2021, American Megatrends International LLC.
> +SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +EFI_STATUS > +EFIAPI > +TiogaPassBoardEnableAcpi ( > + IN BOOLEAN EnableSci > + ); > + > +EFI_STATUS > +EFIAPI > +TiogaPassBoardDisableAcpi ( > + IN BOOLEAN DisableSci > + ); > + > +EFI_STATUS > +EFIAPI > +SiliconEnableAcpi ( > + IN BOOLEAN EnableSci > + ); > + > +EFI_STATUS > +EFIAPI > +SiliconDisableAcpi ( > + IN BOOLEAN DisableSci > + ); > + > +EFI_STATUS > +EFIAPI > +BoardEnableAcpi ( > + IN BOOLEAN EnableSci > + ) > +{ > + SiliconEnableAcpi (EnableSci); > + return TiogaPassBoardEnableAcpi (EnableSci); > +} > + > +EFI_STATUS > +EFIAPI > +BoardDisableAcpi ( > + IN BOOLEAN DisableSci > + ) > +{ > + SiliconDisableAcpi (DisableSci); > + return TiogaPassBoardDisableAcpi (DisableSci); > +} > + > + > diff --git > a/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardAcpiLib > /SmmBoardAcpiEnableLib.inf > b/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardAcpiLi > b/SmmBoardAcpiEnableLib.inf > new file mode 100644 > index 0000000000..688ad3b911 > --- /dev/null > +++ > b/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardAcpiLi > b/SmmBoardAcpiEnableLib.inf > @@ -0,0 +1,41 @@ > +## @file > +# > +# Copyright (c) 2018, Intel Corporation. All rights reserved.
> +# Copyright (c) 2021, American Megatrends International LLC.
> +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > +## > + > +[Defines] > + INF_VERSION =3D 0x00010017 > + BASE_NAME =3D SmmBoardAcpiEnableLib > + FILE_GUID =3D 549E69AE-D3B3-485B-9C17-AF16E20A58A= D > + VERSION_STRING =3D 1.0 > + MODULE_TYPE =3D BASE > + LIBRARY_CLASS =3D BoardAcpiEnableLib > + > +# > +# The following information is for reference only and not required by th= e > build tools. > +# > +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC > +# > + > +[LibraryClasses] > + BaseLib > + IoLib > + PciLib > + MmPciLib > + PchCycleDecodingLib > + > +[Packages] > + MdePkg/MdePkg.dec > + MdeModulePkg/MdeModulePkg.dec > + MinPlatformPkg/MinPlatformPkg.dec > + PurleyOpenBoardPkg/OpenBoardPkg.dec > + PurleyRefreshSiliconPkg/SiPkg.dec > + > +[Sources] > + SmmTiogaPassAcpiEnableLib.c > + SmmSiliconAcpiEnableLib.c > + SmmBoardAcpiEnableLib.c > + > diff --git > a/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardAcpiLib > /SmmSiliconAcpiEnableLib.c > b/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardAcpiLi > b/SmmSiliconAcpiEnableLib.c > new file mode 100644 > index 0000000000..d7e88d6109 > --- /dev/null > +++ > b/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardAcpiLi > b/SmmSiliconAcpiEnableLib.c > @@ -0,0 +1,120 @@ > +/** @file > + > +Copyright (c) 2018, Intel Corporation. All rights reserved.
> +Copyright (c) 2021, American Megatrends International LLC.
> +SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +/** > + Clear Port 80h > + > + SMI handler to enable ACPI mode > + > + Dispatched on reads from APM port with value > EFI_ACPI_ENABLE_SW_SMI > + > + Disables the SW SMI Timer. > + ACPI events are disabled and ACPI event status is cleared. > + SCI mode is then enabled. > + > + Clear SLP SMI status > + Enable SLP SMI > + > + Disable SW SMI Timer > + > + Clear all ACPI event status and disable all ACPI events > + > + Disable PM sources except power button > + Clear status bits > + > + Disable GPE0 sources > + Clear status bits > + > + Disable GPE1 sources > + Clear status bits > + > + Guarantee day-of-month alarm is invalid (ACPI 1.0 section 4.7.2.4) > + > + Enable SCI > +**/ > +EFI_STATUS > +EFIAPI > +SiliconEnableAcpi ( > + IN BOOLEAN EnableSci > + ) > +{ > + UINT32 SmiEn; > + UINT16 Pm1En; > + UINT16 Pm1Cnt; > + UINT16 PchPmBase; > + > + // > + // Init Power Management I/O Base aka ACPI Base > + // > + PchAcpiBaseGet (&PchPmBase); > + > + SmiEn =3D IoRead32 (PchPmBase + R_PCH_SMI_EN); > + > + // > + // Disable SW SMI Timer and legacy USB > + // > + SmiEn &=3D ~(B_PCH_SMI_EN_SWSMI_TMR | > B_PCH_SMI_EN_LEGACY_USB | B_PCH_SMI_EN_LEGACY_USB2); > + > + // > + // And enable SMI on write to B_PCH_ACPI_PM1_CNT_SLP_EN when > SLP_TYP is written > + // > + SmiEn |=3D B_PCH_SMI_EN_ON_SLP_EN; > + IoWrite32 (PchPmBase + R_PCH_SMI_EN, SmiEn); > + > + // > + // Disable PM sources except power button > + // > + Pm1En =3D B_PCH_ACPI_PM1_EN_PWRBTN; > + IoWrite16 (PchPmBase + R_PCH_ACPI_PM1_EN, Pm1En); > + > + // > + // Enable SCI > + // > + Pm1Cnt =3D IoRead16 (PchPmBase + R_PCH_ACPI_PM1_CNT); > + Pm1Cnt |=3D B_PCH_ACPI_PM1_CNT_SCI_EN; > + IoWrite16 (PchPmBase + R_PCH_ACPI_PM1_CNT, Pm1Cnt); > + > + return EFI_SUCCESS; > +} > + > +EFI_STATUS > +EFIAPI > +SiliconDisableAcpi ( > + IN BOOLEAN DisableSci > + ) > +{ > + UINT16 Pm1Cnt; > + UINT16 PchPmBase; > + > + // > + // Init Power Management I/O Base aka ACPI Base > + // > + PchAcpiBaseGet (&PchPmBase); > + > + Pm1Cnt =3D IoRead16 (PchPmBase + R_PCH_ACPI_PM1_CNT); > + > + // > + // Disable SCI > + // > + Pm1Cnt &=3D ~B_PCH_ACPI_PM1_CNT_SCI_EN; > + > + IoWrite16 (PchPmBase + R_PCH_ACPI_PM1_CNT, Pm1Cnt); > + > + return EFI_SUCCESS; > +} > diff --git > a/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardAcpiLib > /SmmTiogaPassAcpiEnableLib.c > b/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardAcpiLi > b/SmmTiogaPassAcpiEnableLib.c > new file mode 100644 > index 0000000000..0661c4cd01 > --- /dev/null > +++ > b/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardAcpiLi > b/SmmTiogaPassAcpiEnableLib.c > @@ -0,0 +1,37 @@ > +/** @file > + > +Copyright (c) 2018, Intel Corporation. All rights reserved.
> +Copyright (c) 2021, American Megatrends International LLC.
> +SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +EFI_STATUS > +EFIAPI > +TiogaPassBoardEnableAcpi ( > + IN BOOLEAN EnableSci > + ) > +{ > + // enable additional board register > + return EFI_SUCCESS; > +} > + > +EFI_STATUS > +EFIAPI > +TiogaPassBoardDisableAcpi ( > + IN BOOLEAN DisableSci > + ) > +{ > + // enable additional board register > + return EFI_SUCCESS; > +} > + > diff --git > a/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardInitLib/ > AllLanesEparam.c > b/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardInitLib > /AllLanesEparam.c > new file mode 100644 > index 0000000000..f38e5123e0 > --- /dev/null > +++ > b/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardInitLib > /AllLanesEparam.c > @@ -0,0 +1,44 @@ > +/** @file > + > +Copyright (c) 2018, Intel Corporation. All rights reserved.
> +Copyright (c) 2021, American Megatrends International LLC.
> +SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > +#ifndef MINIBIOS_BUILD > +#include > +#include > +#include > +#include > +#endif > + > +#include > + > +#define SPEED_REC_96GT 0 > +#define SPEED_REC_104GT 1 > +#define ADAPTIVE_CTLE 0x3f > + > +#pragma pack(1) > + > +ALL_LANES_EPARAM_LINK_INFO KtiTiogaPassAllLanesEparamTable[] =3D { > + // > + // SocketID, Freq, Link, TXEQL, CTLEPEAK > + // > + > + // > + // Socket 0 > + // > + {0x0, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << > KTI_LINK0), 0x2A34353F, ADAPTIVE_CTLE}, > + {0x0, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << > KTI_LINK1), 0x2B33373F, ADAPTIVE_CTLE}, > + > + // > + // Socket 1 > + // > + {0x1, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << > KTI_LINK0), 0x2D3A323F, ADAPTIVE_CTLE}, > + {0x1, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << > KTI_LINK1), 0x2A32373F, ADAPTIVE_CTLE} > +}; > + > +#pragma pack() > + > +UINT32 KtiTiogaPassAllLanesEparamTableSize =3D > sizeof(KtiTiogaPassAllLanesEparamTable); > diff --git > a/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardInitLib/ > GpioTable.c > b/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardInitLib > /GpioTable.c > new file mode 100644 > index 0000000000..191a5bf6ba > --- /dev/null > +++ > b/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardInitLib > /GpioTable.c > @@ -0,0 +1,296 @@ > +/** @file > + > +Copyright (c) 2018, Intel Corporation. All rights reserved.
> +Copyright (c) 2021, American Megatrends International LLC.
> +SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > +#include > +#include > + > +#include > +#include > +#include > + > +#include > +#include > +#include > + > +GPIO_INIT_CONFIG mGpioTableTiogaPass[] =3D > +{ > +// Group A > + //ME{GPIO_SKL_H_GPP_A0, { GpioPadModeNative1, > GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_A0_RCIN_N_ESPI_ALERT1_N [PU_FM_RCIN_N] > + {GPIO_SKL_H_GPP_A1, { GpioPadModeNative1, GpioHostOwnGpio, > GpioDirInOut, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_A1_LAD0_ESPI_IO0 [LPC_LAD_IO0] > + {GPIO_SKL_H_GPP_A2, { GpioPadModeNative1, GpioHostOwnGpio, > GpioDirInOut, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_A2_LAD1_ESPI_IO1 [LPC_LAD_IO1] > + {GPIO_SKL_H_GPP_A3, { GpioPadModeNative1, GpioHostOwnGpio, > GpioDirInOut, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_A3_LAD2_ESPI_IO2 [LPC_LAD_IO2] > + {GPIO_SKL_H_GPP_A4, { GpioPadModeNative1, GpioHostOwnGpio, > GpioDirInOut, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_A4_LAD3_ESPI_IO3 [LPC_LAD_IO2] > + {GPIO_SKL_H_GPP_A5, { GpioPadModeNative1, GpioHostOwnGpio, > GpioDirOut, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_A5_LFRAME_N_ESPI_CS0_N > [LPC_LFRAME_N_CS0_N] > + {GPIO_SKL_H_GPP_A6, { GpioPadModeNative1, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_A6_SERIRQ_ESPI_CS1_N [IRQ_LPC_SERIRQ_N] > + {GPIO_SKL_H_GPP_A7, { GpioPadModeNative1, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_A7_PIRQA_N_ESPI_ALERT0_N > [IRQ_PIRQA_SPI_TPM_N] > + {GPIO_SKL_H_GPP_A8, { GpioPadModeNative1, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_A8_CLKRUN_N [PU_LPC_CLKRUN_N] > + {GPIO_SKL_H_GPP_A9, { GpioPadModeNative1, GpioHostOwnGpio, > GpioDirOut, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_A9_CLKOUT_LPC0_ESPI_CLK [CLK_24M_BMC_LPC] > + {GPIO_SKL_H_GPP_A10, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_A10_CLKOUT_LPC1 [NOT USED] > + {GPIO_SKL_H_GPP_A11, { GpioPadModeNative1, > GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_A11_PME_N [PU_LPC_PME_N] > + {GPIO_SKL_H_GPP_A12, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetNormal, > GpioTermNone}},//GPP_A12_BMBUSY_N_SXEXITHLDOFF_N > [PU_IRQ_PCH_SCI_WHEA_N] > + {GPIO_SKL_H_GPP_A13, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_A13_SUSWARN_N_SUSPWRDNACK > [FM_MB_SLOT_ID0] > + {GPIO_SKL_H_GPP_A14, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_A14_ESPI_RESET_N [FM_MB_SLOT_ID1] > + {GPIO_SKL_H_GPP_A15, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_A15_SUSACK_N [FM_MB_SLOT_ID2] > + {GPIO_SKL_H_GPP_A16, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_A16_CLKOUT_LPC2 [FM_UART_PRES_N] > + {GPIO_SKL_H_GPP_A17, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_A17 [FM_CPU_BMC_INIT] > + {GPIO_SKL_H_GPP_A18, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, > GpioIntDis,GpioResetDeep,GpioTermNone}},//GPP_A18 > [RST_PCH_SYSRST_BTN_OUT_N] > + //ME{GPIO_SKL_H_GPP_A19, { GpioPadModeGpio, > GpioHostOwnGpio, GpioDirIn, GpioOutDefault, > GpioIntDis,GpioResetDeep,GpioTermNone}},//GPP_A19 > [FM_ME_RECOVER_N] > + {GPIO_SKL_H_GPP_A20, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_A20 [NOT USED] > + {GPIO_SKL_H_GPP_A21, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_A21 [FM_OCP_MEZZA_PRES_N] > + {GPIO_SKL_H_GPP_A22, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_A22 [FM_TPM_PRES_N] > + {GPIO_SKL_H_GPP_A23, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_A23 [FM_BMC_READY_N] > +// Group B > + {GPIO_SKL_H_GPP_B0, { GpioPadModeNative1, GpioHostOwnGpio, > GpioDirOut, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_B0_CORE_VID0 > [VID_PCH_CORE_PVNN_AUX_VID_0] > + {GPIO_SKL_H_GPP_B1, { GpioPadModeNative1, GpioHostOwnGpio, > GpioDirOut, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_B1_CORE_VID1 > [VID_PCH_CORE_PVNN_AUX_VID_1] > + {GPIO_SKL_H_GPP_B2, { GpioPadModeNative1, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_B2 [PU_IRQ_VRALERT_N] > + {GPIO_SKL_H_GPP_B3, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_B3_CPU_GP2 [FM_QAT_EN_N] > + {GPIO_SKL_H_GPP_B4, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_B4_CPU_GP3 [IRQ_PVDDQ_ABC_VRHOT_LVT3_N] > + {GPIO_SKL_H_GPP_B5, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_B5_SRCCLKREQ0_N > [IRQ_PVDDQ_DEF_VRHOT_LVT3_N] > + {GPIO_SKL_H_GPP_B6, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, > GpioIntDis,GpioResetNormal,GpioTermNone}},//GPP_B6_SRCCLKREQ1_N > [IRQ_PVDDQ_GHJ_VRHOT_LVT3_N] > + {GPIO_SKL_H_GPP_B7, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, > GpioIntDis,GpioResetNormal,GpioTermNone}},//GPP_B7_SRCCLKREQ2_N > [IRQ_PVDDQ_KLM_VRHOT_LVT3_N] > + {GPIO_SKL_H_GPP_B8, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_B8_SRCCLKREQ3_N [FP_NMI_BTN_N] > + {GPIO_SKL_H_GPP_B9, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_B9_SRCCLKREQ4_N [FM_PWR_BTN_N] > + {GPIO_SKL_H_GPP_B10, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_B10_SRCCLKREQ5_N [RST_SYSTEM_BTN_N] > + {GPIO_SKL_H_GPP_B11, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutLow, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_B11 [FM_PMBUS_ALERT_BUF_EN_N] > + {GPIO_SKL_H_GPP_B12, { GpioPadModeNative1, > GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_B12_GLB_RST_WARN_N > [FM_GLOBAL_RST_WARN_N] > + {GPIO_SKL_H_GPP_B13, { GpioPadModeNative1, > GpioHostOwnGpio, GpioDirOut, GpioOutDefault, > GpioIntDis,GpioResetDeep, GpioTermNone}},//GPP_B13_PLTRST_N > [RST_PLTRST_N] > + {GPIO_SKL_H_GPP_B14, { GpioPadModeNative1, > GpioHostOwnGpio, GpioDirOut, GpioOutLow, > GpioIntDis,GpioResetDeep,GpioTermNone}},//GPP_B14_SPKR > [FM_BIOS_TOP_SWAP_SPKR] > + {GPIO_SKL_H_GPP_B15, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_B15 [FM_UART_ALERT_N] > + {GPIO_SKL_H_GPP_B16, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_B16 [IRQ_PCH_NIC_ALERT_N] > + {GPIO_SKL_H_GPP_B17, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_B17 [FM_PCH_PWRBTN_OUT_N] > + {GPIO_SKL_H_GPP_B18, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_B18 [FM_UV_ADR_TRIGGER_EN] > + {GPIO_SKL_H_GPP_B19, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirOut, GpioOutHigh, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_B19 [FM_BIOS_PREFRB2_GOOD] > + {GPIO_SKL_H_GPP_B20, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirOut, GpioOutLow , > GpioIntDis,GpioResetDeep,GpioTermNone}},//GPP_B20 > [FM_BIOS_POST_CMPLT_N] > + {GPIO_SKL_H_GPP_B21, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_B21 [FM_FAST_PROCHOT_EN_N] > + {GPIO_SKL_H_GPP_B22, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirOut, GpioOutLow, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_B22 [FM_USB_P0_EN_BOOT_BIOS_STRAP_N] > + {GPIO_SKL_H_GPP_B23, { GpioPadModeNative2, > GpioHostOwnGpio, GpioDirOut, GpioOutDefault, > GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_B23_MEIE_SML1ALRT_N_PHOT_N > [FM_PCH_BMC_THERMTRIP_EXI_STRAP_N] > +// Group C > + {GPIO_SKL_H_GPP_C0, { GpioPadModeNative1, GpioHostOwnGpio, > GpioDirOut, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_C0_SMBCLK [SMB_HOST_STBY_LVC3_SCL_R1] > + {GPIO_SKL_H_GPP_C1, { GpioPadModeNative1, GpioHostOwnGpio, > GpioDirOut, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_C1_SMBDATA [SMB_HOST_STBY_LVC3_SDA_R1] > + {GPIO_SKL_H_GPP_C2, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_C2_SMBALERT_N [PU_PCH_TLS_ENABLE_STRAP] > + //ME{GPIO_SKL_H_GPP_C3, { GpioPadModeNative1, > GpioHostOwnGpio, GpioDirOut, GpioOutDefault, > GpioIntDis,GpioResetDeep, GpioTermNone}},//GPP_C3_SML0CLK_IE > [SMB_SMLINK0_STBY_LVC3_SCL_R1] > + //ME{GPIO_SKL_H_GPP_C4, { GpioPadModeNative1, > GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, > GpioIntDis,GpioResetDeep, GpioTermNone}},//GPP_C4_SML0DATA_IE > [SMB_SMLINK0_STBY_LVC3_SDA_R1] > + {GPIO_SKL_H_GPP_C5, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirOut, GpioOutHigh, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_C5_SML0ALERT_IE_N [IRQ_SML0_ALERT_N] > + //ME{GPIO_SKL_H_GPP_C6, { GpioPadModeNative1, > GpioHostOwnGpio, GpioDirOut, GpioOutDefault, > GpioIntDis,GpioResetDeep, GpioTermNone}},//GPP_C6_SML1CLK_IE > [SMB_PMBUS_BMC_STBY_LVC3_SCL_R1] > + //ME{GPIO_SKL_H_GPP_C7, { GpioPadModeNative1, > GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, > GpioIntDis,GpioResetDeep, GpioTermNone}},//GPP_C7_SML1DATA_IE > [SMB_PMBUS_BMC_STBY_LVC3_SDA_R1] > + {GPIO_SKL_H_GPP_C8, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, > GpioIntDis,GpioResetDeep,GpioTermNone}},//GPP_C8 > [FM_PASSWORD_CLEAR_N] > + {GPIO_SKL_H_GPP_C9, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, > GpioIntDis,GpioResetDeep,GpioTermNone}},//GPP_C9 [FM_CPU1_RC_EN] > + {GPIO_SKL_H_GPP_C10, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutHigh, > GpioIntDis,GpioResetNormal,GpioTermNone}},//GPP_C10 > [FM_PCH_SATA_RAID_KEY] > + {GPIO_SKL_H_GPP_C11, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, > GpioIntDis,GpioResetDeep,GpioTermNone}},//GPP_C11 > [FM_BOARD_REV_ID2] > + {GPIO_SKL_H_GPP_C12, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_C12 [FM_BOARD_REV_ID0] > + {GPIO_SKL_H_GPP_C13, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_C13 [FM_BOARD_REV_ID1] > + {GPIO_SKL_H_GPP_C14, { GpioPadModeGpio, GpioHostOwnAcpi, > GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntSci,GpioResetNormal, > GpioTermNone}},//GPP_C14 [IRQ_BMC_PCH_SCI_LPC_N] > + {GPIO_SKL_H_GPP_C15, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, > GpioIntDis,GpioResetDeep,GpioTermNone}},//GPP_C15 [FM_SLT_CFG0] > + {GPIO_SKL_H_GPP_C16, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, > GpioIntDis,GpioResetDeep,GpioTermNone}},//GPP_C16 [FM_SLT_CFG1] > + {GPIO_SKL_H_GPP_C17, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, > GpioIntDis,GpioResetDeep,GpioTermNone}},//GPP_C17 [FM_SLT_CFG2_R] > + {GPIO_SKL_H_GPP_C18, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, > GpioIntDis,GpioResetDeep,GpioTermNone}},//GPP_C18 > [FM_PMBUS_ALERT_BUF_EN_N] > + {GPIO_SKL_H_GPP_C19, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, > GpioIntDis,GpioResetDeep,GpioTermNone}},//GPP_C19 > [FM_BB_BMC_MP_GPIO] > + //ME{GPIO_SKL_H_GPP_C20, { GpioPadModeGpio, > GpioHostOwnGpio, GpioDirOut, GpioOutHigh, > GpioIntDis,GpioResetDeep,GpioTermNone}},//GPP_C20 [FM_THROTTLE_N] > + {GPIO_SKL_H_GPP_C21, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, > GpioIntDis,GpioResetDeep,GpioTermNone}},//GPP_C21 > [FM_BIOS_POST_CMPLT_N] > + {GPIO_SKL_H_GPP_C22, { GpioPadModeGpio, GpioHostOwnAcpi, > GpioDirInInv, GpioOutDefault, GpioIntLevel | > GpioIntSmi,GpioResetNormal, GpioTermNone}},//GPP_C22 > [IRQ_BMC_PCH_SMI_LPC_N] > + {GPIO_SKL_H_GPP_C23, { GpioPadModeGpio, GpioHostOwnAcpi, > GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntSmi,GpioResetDeep, > GpioTermNone}},//GPP_C23 [FM_CPU_CATERR_DLY_LVT3_R_N] > +// Group D > + {GPIO_SKL_H_GPP_D0, { GpioPadModeGpio, GpioHostOwnAcpi, > GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntNmi,GpioResetNormal, > GpioTermNone}},//GPP_D0 [IRQ_BMC_PCH_NMI_STBY_R_N] > + {GPIO_SKL_H_GPP_D1, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirOut, GpioOutLow, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_D1 [FM_PWR_LED_N] > + {GPIO_SKL_H_GPP_D2, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, > GpioIntDis,GpioResetNormal,GpioTermNone}},//GPP_D2 > [IRQ_HSC_FAULT_N] > + {GPIO_SKL_H_GPP_D3, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetNormal, > GpioTermNone}},//GPP_D3 [IRQ_MEZZ_LAN_ALERT_N] > + {GPIO_SKL_H_GPP_D4, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirOut, GpioOutHigh, > GpioIntDis,GpioResetDeep,GpioTermNone}},//GPP_D4 > [FM_PCH_PLD_DATA_R] > + {GPIO_SKL_H_GPP_D5, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_D5 [FM_BMC_ENABLE_N] > + {GPIO_SKL_H_GPP_D6, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_D6 [FM_CPLD_BMC_PWRDN_N] > + {GPIO_SKL_H_GPP_D7, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_D7 [FM_BMC_CPLD_GPO] > + {GPIO_SKL_H_GPP_D8, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_D8 [FM_BMC_FAULT_LED_N] > + {GPIO_SKL_H_GPP_D9, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_D9_SSATA_DEVSLP3 > [IRQ_FORCE_NM_THROTTLE_N] > + {GPIO_SKL_H_GPP_D10, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_D10_SSATA_DEVSLP4 > [H_CPU0_FAST_WAKE_LVT3_N] > + {GPIO_SKL_H_GPP_D11, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_D11_SSATA_DEVSLP5 [IRQ_LOM_ALERT_N] > + {GPIO_SKL_H_GPP_D12, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_D12_SSATA_SDATAOUT1 [FM_TPM_PRES_RST_N] > + {GPIO_SKL_H_GPP_D13, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_D13_SML0BCLK_IE > [SMB_SLOTX24_STBY_LVC3_SCL_R1] > + {GPIO_SKL_H_GPP_D14, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_D14_SML0BDATA_IE > [SMB_SLOTX24_STBY_LVC3_SDA_R1] > + {GPIO_SKL_H_GPP_D15, { GpioPadModeNative3, > GpioHostOwnGpio, GpioDirOut, GpioOutDefault, > GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_D15_SSATA_SDATAOUT0 > [SGPIO_PCH_SSATA_DOUT0] > + {GPIO_SKL_H_GPP_D16, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_D16_SML0BALERT_IE_N > [IRQ_OOB_MGMT_RISER_ALERT_N] > + {GPIO_SKL_H_GPP_D17, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_D17 [FM_XRC_PRESENT_N] > + {GPIO_SKL_H_GPP_D18, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, > GpioIntDis,GpioResetDeep,GpioTermNone}},//GPP_D18 > [FM_XRC_READY_N] > + {GPIO_SKL_H_GPP_D19, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirOut, GpioOutLow, > GpioIntDis,GpioResetDeep,GpioTermNone}},//GPP_D19 > [FM_ADR_MODE_SEL_R] > + {GPIO_SKL_H_GPP_D20, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_D20 [FM_BMC_HEARTBEAT_N] > + {GPIO_SKL_H_GPP_D21, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_D21_IE_UART_RX [NOT USED] > + {GPIO_SKL_H_GPP_D22, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_D22_IE_UART_TX [NOT USED] > + {GPIO_SKL_H_GPP_D23, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_D23 [FM_CPU0_THERMTRIP_LATCH_LVT3_N] > +// Group E > + {GPIO_SKL_H_GPP_E0, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_E0_SATAXPCIE0_SATAGP0 > [FM_CPU0_RC_ERROR_N] > + {GPIO_SKL_H_GPP_E1, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_E1_SATAXPCIE1_SATAGP1 > [FM_CPU1_RC_ERROR_N] > + {GPIO_SKL_H_GPP_E2, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_E2_SATAXPCIE2_SATAGP2 > [FM_POST_CARD_PRES_BMC_N] > + {GPIO_SKL_H_GPP_E3, { GpioPadModeNative1, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_E3_CPU_GP0 [FM_CPLD_ADR_TRIGGER_N] > + {GPIO_SKL_H_GPP_E4, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_E4_SATA_DEVSLP0 [FM_CPU_ERR2_LVT3_N] > + {GPIO_SKL_H_GPP_E5, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_E5_SATA_DEVSLP1 [FM_CPU_MSMI_LVT3_N] > + {GPIO_SKL_H_GPP_E6, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_E6_SATA_DEVSLP2 [IRQ_BMC_PCH_NMI_STBY_N] > + {GPIO_SKL_H_GPP_E7, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_E7_CPU_GP1 [FM_ADR_SMI_GPIO_N] > + {GPIO_SKL_H_GPP_E8, { GpioPadModeNative1, GpioHostOwnGpio, > GpioDirOut, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_E8_SATA_LED_N [LED_PCH_SATA_HDD_N] > + {GPIO_SKL_H_GPP_E9, { GpioPadModeNative1, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_E9_USB2_OC0_N [FM_OC0_USB_N] > + {GPIO_SKL_H_GPP_E10, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_E10_USB2_OC1_N [IRQ_BMC_PCH_SCI_LPC_N] > + {GPIO_SKL_H_GPP_E11, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_E11_USB2_OC2_N [IRQ_BMC_PCH_SMI_LPC_N] > + {GPIO_SKL_H_GPP_E12, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_E12_USB2_OC3_N [IRQ_UV_DETECT_N > +// Group F > + {GPIO_SKL_H_GPP_F0, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_F0_SATAXPCIE3_SATAGP3 [IRQ_OC_DETECT_N] > + {GPIO_SKL_H_GPP_F1, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_F1_SATAXPCIE4_SATAGP4 > [FM_HSC_TIMER_EXP_N] > + {GPIO_SKL_H_GPP_F2, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_F2_SATAXPCIE5_SATAGP5 [FM_MP_PS_FAIL_N] > + {GPIO_SKL_H_GPP_F3, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_F3_SATAXPCIE6_SATAGP6 > [FM_MP_PS_REDUNDANT_LOST_N] > + {GPIO_SKL_H_GPP_F4, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_F4_SATAXPCIE7_SATAGP7 [FM_BMC_READY_N] > + {GPIO_SKL_H_GPP_F5, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_F5_SATA_DEVSLP3 [FM_BIOS_USB_RECOVERY] > + {GPIO_SKL_H_GPP_F6, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirOut, GpioOutLow, > GpioIntDis,GpioResetNormal,GpioTermNone}},//GPP_F6_SATA_DEVSLP4 > [JTAG_PCH_PLD_TCK] > + {GPIO_SKL_H_GPP_F7, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirOut, GpioOutLow, > GpioIntDis,GpioResetNormal,GpioTermNone}},//GPP_F7_SATA_DEVSLP5 > [JTAG_PCH_PLD_TDI] > + {GPIO_SKL_H_GPP_F8, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirOut, GpioOutLow, > GpioIntDis,GpioResetNormal,GpioTermNone}},//GPP_F8_SATA_DEVSLP6 > [JTAG_PCH_PLD_TMS] > + {GPIO_SKL_H_GPP_F9, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, > GpioIntDis,GpioResetNormal,GpioTermNone}},//GPP_F9_SATA_DEVSLP7 > [JTAG_PCH_PLD_TDO] > + {GPIO_SKL_H_GPP_F10, { GpioPadModeNative1, > GpioHostOwnGpio, GpioDirOut, GpioOutDefault, > GpioIntDis,GpioResetDeep, GpioTermNone}},//GPP_F10_SATA_SCLOCK > [SGPIO_PCH_SATA_CLOCK] > + {GPIO_SKL_H_GPP_F11, { GpioPadModeNative1, > GpioHostOwnGpio, GpioDirOut, GpioOutDefault, > GpioIntDis,GpioResetDeep, GpioTermNone}},//GPP_F11_SATA_SLOAD > [SGPIO_PCH_SATA_LOAD > + {GPIO_SKL_H_GPP_F12, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_F12_SATA_SDATAOUT1 > [IRQ_SML1_PMBUS_ALERT_R1_N] > + {GPIO_SKL_H_GPP_F13, { GpioPadModeNative1, > GpioHostOwnGpio, GpioDirOut, GpioOutDefault, > GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_F13_SATA_SDATAOUT0 > [SGPIO_PCH_SATA_DOUT0] > + {GPIO_SKL_H_GPP_F14, { GpioPadModeNative3, > GpioHostOwnGpio, GpioDirOut, GpioOutDefault, > GpioIntDis,GpioResetDeep, GpioTermNone}},//GPP_F14_SSATA_LED_N > [LED_PCH_SSATA_HDD_N > + {GPIO_SKL_H_GPP_F15, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_F15_USB2_OC4_N [FM_FORCE_ADR_N] > + {GPIO_SKL_H_GPP_F16, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_F16_USB2_OC5_N [FM_IE_DISABLE_N] > + {GPIO_SKL_H_GPP_F17, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_F17_USB2_OC6_N [FM_BIOS_TOP_SWAP] > + {GPIO_SKL_H_GPP_F18, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_F18_USB2_OC7_N > [FM_MEM_THERM_EVENT_PCH_N] > + {GPIO_SKL_H_GPP_F19, { GpioPadModeNative1, > GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_F19_LAN_SMBCLK [SMB_LAN_STBY_LVC3_SCL_R2] > + {GPIO_SKL_H_GPP_F20, { GpioPadModeNative1, > GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_F20_LAN_SMBDATA > [SMB_LAN_STBY_LVC3_SDA_R2] > + {GPIO_SKL_H_GPP_F21, { GpioPadModeNative1, > GpioHostOwnGpio, GpioDirOut, GpioOutDefault, > GpioIntDis,GpioResetDeep, GpioTermNone}},//GPP_F21_LAN_SMBALRT_N > [IRQ_PCH_NIC_ALERT_N] > + {GPIO_SKL_H_GPP_F22, { GpioPadModeNative3, > GpioHostOwnGpio, GpioDirOut, GpioOutDefault, > GpioIntDis,GpioResetDeep, GpioTermNone}},//GPP_F22_SSATA_SCLOCK > [SGPIO_PCH_SSATA_CLOCK] > + {GPIO_SKL_H_GPP_F23, { GpioPadModeNative3, > GpioHostOwnGpio, GpioDirOut, GpioOutDefault, > GpioIntDis,GpioResetDeep, GpioTermNone}},//GPP_F23_SSATA_SLOAD > [SGPIO_PCH_SSATA_LOAD] > +// Group G > + {GPIO_SKL_H_GPP_G0, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_G0_FANTACH0_FANTACH0IE [NOT USED] > + {GPIO_SKL_H_GPP_G1, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_G1_FANTACH1_FANTACH1IE [NOT USED] > + {GPIO_SKL_H_GPP_G2, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_G2_FANTACH2_FANTACH2IE [NOT USED] > + {GPIO_SKL_H_GPP_G3, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_G3_FANTACH3_FANTACH3IE [NOT USED] > + {GPIO_SKL_H_GPP_G4, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_G4_FANTACH4_FANTACH4IE [NOT USED] > + {GPIO_SKL_H_GPP_G5, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_G5_FANTACH5_FANTACH5IE [NOT USED] > + {GPIO_SKL_H_GPP_G6, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_G6_FANTACH6_FANTACH6IE > [FM_CPU1_THERMTRIP_LATCH_LVT3_N] > + {GPIO_SKL_H_GPP_G7, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_G7_FANTACH7_FANTACH7IE [NOT USED] > + {GPIO_SKL_H_GPP_G8, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_G8_FANPWM0_FANPWM0IE [NOT USED] > + {GPIO_SKL_H_GPP_G9, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_G9_FANPWM1_FANPWM1IE [NOT USED] > + {GPIO_SKL_H_GPP_G10, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_G10_FANPWM2_FANPWM2IE [NOT USED] > + {GPIO_SKL_H_GPP_G11, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_G11_FANPWM3_FANPWM3IE [NOT USED] > + {GPIO_SKL_H_GPP_G12, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, > GpioIntDis,GpioResetDeep,GpioTermNone}},//GPP_G12 > [FM_BOARD_SKU_ID0] > + {GPIO_SKL_H_GPP_G13, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, > GpioIntDis,GpioResetDeep,GpioTermNone}},//GPP_G13 > [FM_BOARD_SKU_ID1] > + {GPIO_SKL_H_GPP_G14, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, > GpioIntDis,GpioResetDeep,GpioTermNone}},//GPP_G14 > [FM_BOARD_SKU_ID2] > + {GPIO_SKL_H_GPP_G15, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, > GpioIntDis,GpioResetDeep,GpioTermNone}},//GPP_G15 > [FM_BOARD_SKU_ID3] > + {GPIO_SKL_H_GPP_G16, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, > GpioIntDis,GpioResetDeep,GpioTermNone}},//GPP_G16 > [FM_BOARD_SKU_ID4] > + {GPIO_SKL_H_GPP_G17, { GpioPadModeNative1, > GpioHostOwnGpio, GpioDirOut, GpioOutDefault, > GpioIntDis,GpioResetDeep, GpioTermNone}},//GPP_G17_ADR_COMPLETE > [FM_ADR_COMPLETE] > + {GPIO_SKL_H_GPP_G18, { GpioPadModeNative1, > GpioHostOwnGpio, GpioDirOut, GpioOutDefault, > GpioIntDis,GpioResetDeep, GpioTermNone}},//GPP_G18_NMI_N > [FM_NMI_EVENT_N] > + {GPIO_SKL_H_GPP_G19, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_G19_SMI_N [FM_BIOS_SMI_ACTIVE_N] > + {GPIO_SKL_H_GPP_G20, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_G20_SSATA_DEVSLP0 > [IRQ_FORCE_NM_THROTTLE_N] > + {GPIO_SKL_H_GPP_G21, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_G21_SSATA_DEVSLP1 [FM_SOL_UART_CH_SEL > + {GPIO_SKL_H_GPP_G22, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_G22_SSATA_DEVSLP2 [FM_CPU0_RC_EN > + {GPIO_SKL_H_GPP_G23, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_G23_SSATAXPCIE0_SSATAGP0 > [FM_UARTSW_MSB_N > +// Group H > + {GPIO_SKL_H_GPP_H0, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_H0_SRCCLKREQ6_N [FM_UARTSW_LSB_N] > + {GPIO_SKL_H_GPP_H1, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_H1_SRCCLKREQ7_N [FM_BACKUP_BIOS_SEL_N] > + {GPIO_SKL_H_GPP_H2, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_H2_SRCCLKREQ8_N [NOT USED] > + {GPIO_SKL_H_GPP_H3, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_H3_SRCCLKREQ9_N [NOT USED] > + {GPIO_SKL_H_GPP_H4, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_H4_SRCCLKREQ10_N [NOT USED] > + {GPIO_SKL_H_GPP_H5, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_H5_SRCCLKREQ11_N [NOT USED] > + {GPIO_SKL_H_GPP_H6, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_H6_SRCCLKREQ12_N [NOT USED] > + {GPIO_SKL_H_GPP_H7, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_H7_SRCCLKREQ13_N [NOT USED] > + {GPIO_SKL_H_GPP_H8, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_H8_SRCCLKREQ14_N [NOT USED] > + {GPIO_SKL_H_GPP_H9, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_H9_SRCCLKREQ15_N [NOT USED] > + {GPIO_SKL_H_GPP_H10, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_H10_SML2CLK_IE [SMB_VR_STBY_LVC3_SCL_R1] > + {GPIO_SKL_H_GPP_H11, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_H11_SML2DATA_IE [SMB_VR_STBY_LVC3_SDA_R1] > + {GPIO_SKL_H_GPP_H12, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_H12_SML2ALERT_N_IE_N > [FM_FLASH_ATTACH_CFG_STRAP] > + {GPIO_SKL_H_GPP_H13, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_H13_SML3CLK_IE [NOT USED] > + {GPIO_SKL_H_GPP_H14, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_H14_SML3DATA_IE [NOT USED] > + {GPIO_SKL_H_GPP_H15, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, > GpioIntDis,GpioResetNormal,GpioTermNone}},//GPP_H15_SML3ALERT_N_I > E_N [PU_ADR_TIMER_HOLD_OFF_N] > + {GPIO_SKL_H_GPP_H16, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_H16_SML4CLK_IE [SMB_LAN_STBY_LVC3_SCL_R1] > + {GPIO_SKL_H_GPP_H17, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_H17_SML4DATA_IE > [SMB_LAN_STBY_LVC3_SDA_R1] > + {GPIO_SKL_H_GPP_H18, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_H18_SML4ALERT_N_IE_N [FM_OC_DETECT_EN_N] > + {GPIO_SKL_H_GPP_H19, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, > GpioIntDis,GpioResetNormal,GpioTermNone}},//GPP_H19_SSATAXPCIE1_SS > ATAGP1 [FP_PWR_ID_LED_N] > + {GPIO_SKL_H_GPP_H20, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, > GpioIntDis,GpioResetDeep,GpioTermNone}},//GPP_H20_SSATAXPCIE2_SSA > TAGP2 [FM_BMC_NMI_N] > + {GPIO_SKL_H_GPP_H21, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, > GpioIntDis,GpioResetDeep,GpioTermNone}},//GPP_H21_SSATAXPCIE3_SSA > TAGP3 [FM_BIOS_SMI_ACTIVE_N] > + {GPIO_SKL_H_GPP_H22, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, > GpioIntDis,GpioResetDeep,GpioTermNone}},//GPP_H22_SSATAXPCIE4_SSA > TAGP4 [FM_PCH_BMC_THERMTRIP_N] > + {GPIO_SKL_H_GPP_H23, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, > GpioIntDis,GpioResetDeep,GpioTermNone}},//GPP_H23_SSATAXPCIE5_SSA > TAGP5 [FM_SSATA_PCIE_M2_SEL] > +// Group I > + {GPIO_SKL_H_GPP_I0, { GpioPadModeNative1, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_I0_LAN_TDO [JTAG_PCH_GBE_TDO] > + {GPIO_SKL_H_GPP_I1, { GpioPadModeNative1, GpioHostOwnGpio, > GpioDirOut, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_I1_LAN_TCK [JTAG_PCH_GBE_CLK] > + {GPIO_SKL_H_GPP_I2, { GpioPadModeNative1, GpioHostOwnGpio, > GpioDirOut, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_I2_LAN_TMS [JTAG_PCH_GBE_TMS] > + {GPIO_SKL_H_GPP_I3, { GpioPadModeNative1, GpioHostOwnGpio, > GpioDirOut, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_I3_LAN_TDI [JTAG_PCH_GBE_TDI] > + {GPIO_SKL_H_GPP_I4, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_I4_DO_RESET_IN_N [IRQ_DIMM_SAVE_LVT3_N] > + {GPIO_SKL_H_GPP_I5, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_I5_DO_RESET_OUT_N > [IRQ_BOARD_BMC_ALERT_N] > + {GPIO_SKL_H_GPP_I6, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_I6_RESET_DONE [FM_CPU1_RC_ERROR_N] > + {GPIO_SKL_H_GPP_I7, { GpioPadModeNative1, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_I7_LAN_TRST_N [JTAG_PCH_GBE_TRST_N] > + {GPIO_SKL_H_GPP_I8, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_I8_PCI_DIS_N [PU_10GBE_LOM_PCI_DISABLE_N] > + {GPIO_SKL_H_GPP_I9, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_I9_LAN_DIS_N [FM_10GBE_LOM_DISABLE_N] > + {GPIO_SKL_H_GPP_I10, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_I10 [FM_BIOS_MRC_DEBUG_MSG_DIS_N] > +// Group GPD > + {GPIO_SKL_H_GPD0, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPD0 [XDP_PCH_PWR_DEBUG_N] > + {GPIO_SKL_H_GPD1, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetPwrGood, > GpioTermNone}},//GPD1_ACPRESENT [FM_CPU1_SKTOCC_LVT3_N] > + {GPIO_SKL_H_GPD2, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetPwrGood, > GpioTermNone}},//GPD2_GBE_WAKE_N [RST_BMC_SRST_R_N] > + {GPIO_SKL_H_GPD3, { GpioPadModeNative1, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetPwrGood, > GpioTermNone}},//GPD3_PWRBTN_N [FM_PCH_PWRBTN_N] > + {GPIO_SKL_H_GPD4, { GpioPadModeNative1, GpioHostOwnGpio, > GpioDirOut, GpioOutDefault, GpioIntDis,GpioResetPwrGood, > GpioTermNone}},//GPD4_SLP_S3_N [FM_SLPS3_N] > + {GPIO_SKL_H_GPD5, { GpioPadModeNative1, GpioHostOwnGpio, > GpioDirOut, GpioOutDefault, GpioIntDis,GpioResetPwrGood, > GpioTermNone}},//GPD5_SLP_S4_N [FM_SLPS4_N] > + {GPIO_SKL_H_GPD6, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetPwrGood, > GpioTermNone}},//GPD6_SLP_A_N [FM_CPU0_SKTOCC_LVT3_N] > + {GPIO_SKL_H_GPD7, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetPwrGood, > GpioTermNone}},//GPD7 [FM_BATTERY_SENSE_EN_N] > + {GPIO_SKL_H_GPD8, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetPwrGood, > GpioTermNone}},//GPD8_SUSCLK [NOT USED] > + {GPIO_SKL_H_GPD9, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetPwrGood, > GpioTermNone}},//GPD9 [FM_BMC_CPLD_MP_RST_N] > + {GPIO_SKL_H_GPD10, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetPwrGood, > GpioTermNone}},//GPD10_SLP_S5_N [FM_CPU0_RC_ERROR_N] > + {GPIO_SKL_H_GPD11, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirOut, GpioOutHigh, GpioIntDis,GpioResetPwrGood, > GpioTermNone}},//GPD11_GBEPHY [FM_GBE_LOM_DISABLE_N] > +// Group J > + {GPIO_SKL_H_GPP_J0, { GpioPadModeNative1, GpioHostOwnGpio, > GpioDirOut, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_J0_LAN_LED_P0_0 [LED_GBE_P0_0] > + {GPIO_SKL_H_GPP_J1, { GpioPadModeNative1, GpioHostOwnGpio, > GpioDirOut, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_J1_LAN_LED_P0_1 [LED_GBE_P0_1] > + {GPIO_SKL_H_GPP_J2, { GpioPadModeNative1, GpioHostOwnGpio, > GpioDirOut, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_J2_LAN_LED_P1_0 [LED_GBE_P1_0] > + {GPIO_SKL_H_GPP_J3, { GpioPadModeNative1, GpioHostOwnGpio, > GpioDirOut, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_J3_LAN_LED_P1_1 [LED_GBE_P1_1] > + {GPIO_SKL_H_GPP_J4, { GpioPadModeNative1, GpioHostOwnGpio, > GpioDirOut, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_J4_LAN_LED_P2_0 [LED_GBE_P2_0] > + {GPIO_SKL_H_GPP_J5, { GpioPadModeNative1, GpioHostOwnGpio, > GpioDirOut, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_J5_LAN_LED_P2_1 [LED_GBE_P2_1] > + {GPIO_SKL_H_GPP_J6, { GpioPadModeNative1, GpioHostOwnGpio, > GpioDirOut, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_J6_LAN_LED_P3_0 [LED_GBE_P3_0] > + {GPIO_SKL_H_GPP_J7, { GpioPadModeNative1, GpioHostOwnGpio, > GpioDirOut, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_J7_LAN_LED_P3_1 [LED_GBE_P3_1] > + {GPIO_SKL_H_GPP_J8, { GpioPadModeNative1, GpioHostOwnGpio, > GpioDirOut, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_J8_LAN_I2C_SCL_MDC_P0 > [SMB_PCH_MEZZ_LOM0_SCL] > + {GPIO_SKL_H_GPP_J9, { GpioPadModeNative1, GpioHostOwnGpio, > GpioDirInOut, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_J9_LAN_I2C_SDA_MDIO_P0 > [SMB_PCH_MEZZ_LOM0_SDA] > + {GPIO_SKL_H_GPP_J10, { GpioPadModeNative1, GpioHostOwnGpio, > GpioDirOut, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_J10_LAN_I2C_SCL_MDC_P1 > [SMB_PCH_MEZZ_LOM1_SCL] > + {GPIO_SKL_H_GPP_J11, { GpioPadModeNative1, GpioHostOwnGpio, > GpioDirInOut, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_J_11_SMB_GBE1_LVC3_R_SDA > [SMB_PCH_MEZZ_LOM1_SDA] > + {GPIO_SKL_H_GPP_J12, { GpioPadModeNative1, GpioHostOwnGpio, > GpioDirOut, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_J12_LAN_I2C_SCL_MDC_P2 > [SMB_PCH_MEZZ_LOM2_SCL] > + {GPIO_SKL_H_GPP_J13, { GpioPadModeNative1, GpioHostOwnGpio, > GpioDirInOut, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_J13_LAN_I2C_SDA_MDIO_P2 > [SMB_PCH_MEZZ_LOM2_SDA] > + {GPIO_SKL_H_GPP_J14, { GpioPadModeNative1, GpioHostOwnGpio, > GpioDirOut, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_J14_LAN_I2C_SCL_MDC_P3 > [SMB_PCH_MEZZ_LOM3_SCL] > + {GPIO_SKL_H_GPP_J15, { GpioPadModeNative1, GpioHostOwnGpio, > GpioDirInOut, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_J15_LAN_I2C_SDA_MDIO_P3 > [SMB_PCH_MEZZ_LOM3_SDA] > + {GPIO_SKL_H_GPP_J16, { GpioPadModeNative1, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_J16_LAN_SDP_P0_0 [FM_GBE0_LVC3_MOD_ABS] > + {GPIO_SKL_H_GPP_J17, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_J17_LAN_SDP_P0_1 [TP_PCH_GPP_J17] > + {GPIO_SKL_H_GPP_J18, { GpioPadModeNative1, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_J18_LAN_SDP_P1_0 [FM_GBE1_LVC3_MOD_ABS] > + {GPIO_SKL_H_GPP_J19, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_J19_LAN_SDP_P1_1 [TP_PCH_GPP_J19] > + {GPIO_SKL_H_GPP_J20, { GpioPadModeNative1, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_J20_LAN_SDP_P2_0 [FM_GBE2_LVC3_MOD_ABS] > + {GPIO_SKL_H_GPP_J21, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_J21_LAN_SDP_P2_1 [TP_PCH_GPP_J21] > + {GPIO_SKL_H_GPP_J22, { GpioPadModeNative1, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_J22_LAN_SDP_P3_0 [FM_GBE3_LVC3_MOD_ABS] > + {GPIO_SKL_H_GPP_J23, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_J23_LAN_SDP_P3_1 [TP_PCH_GPP_J23] > +// Group K > + {GPIO_SKL_H_GPP_K0, { GpioPadModeNative1, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_K0_LAN_NCSI_CLK_IN > [CLK_50M_CKMNG_PCH_10GBE] > + {GPIO_SKL_H_GPP_K1, { GpioPadModeNative1, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_K1_LAN_NCSI_TXD0 > [RMII_BMC_PCH_SPRNGVLLE_TXD0] > + {GPIO_SKL_H_GPP_K2, { GpioPadModeNative1, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_K2_LAN_NCSI_TXD1 > [RMII_BMC_PCH_SPRNGVLLE_TXD1] > + {GPIO_SKL_H_GPP_K3, { GpioPadModeNative1, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_K3_LAN_NCSI_TX_EN > [RMII_BMC_PCH_SPRNGVLLE_TXEN] > + {GPIO_SKL_H_GPP_K4, { GpioPadModeNative1, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_K4_LAN_NCSI_CRS_DV > [RMII_BMC_PCH_SPRNGVLLE_CRSDV_R1] > + {GPIO_SKL_H_GPP_K5, { GpioPadModeNative1, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_K5_LAN_NCSI_RXD0 > [RMII_SPRNGVLLE_BMC_PCH_RXD0_R1] > + {GPIO_SKL_H_GPP_K6, { GpioPadModeNative1, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_K6_LAN_NCSI_RXD1 > [RMII_SPRNGVLLE_BMC_PCH_RXD1_R1] > + {GPIO_SKL_H_GPP_K7, { GpioPadModeNative1, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_K7 [RMII_BMC_PCH_SPRNGVLLE_RXER_R] > + {GPIO_SKL_H_GPP_K8, { GpioPadModeNative1, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_K8_LAN_NCSI_ARB_IN > [RMII_PCH_SPRNGVLLE_ARB_IN] > + {GPIO_SKL_H_GPP_K9, { GpioPadModeNative1, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_K9_LAN_NCSI_ARB_OUT > [RMII_PCH_SPRNGVLLE_ARB_OUT_R] > + {GPIO_SKL_H_GPP_K10, { GpioPadModeNative1, > GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_K10_PE_RST_N [RST_PCIE_PCH_PERST_N] > +// Group L > + //{GPIO_SKL_H_GPP_L0, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_L0 > + //{GPIO_SKL_H_GPP_L1, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirOut, GpioOutHigh, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_L1 > + {GPIO_SKL_H_GPP_L2, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_L2_TESTCH0_D0 [FM_PRSNT_2_1_N] > + {GPIO_SKL_H_GPP_L3, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_L3_TESTCH0_D1 [FM_PRSNT_2_2_N] > + {GPIO_SKL_H_GPP_L4, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_L4_TESTCH0_D2 [FM_PRSNT_2_3_N] > + {GPIO_SKL_H_GPP_L5, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_L5_TESTCH0_D3 [FM_PRSNT_2_4_N] > + {GPIO_SKL_H_GPP_L6, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_L6_TESTCH0_D4 [FM_PRSNT_2_5_N] > + {GPIO_SKL_H_GPP_L7, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_L7_TESTCH0_D5 [FM_PRSNT_2_6_N] > + {GPIO_SKL_H_GPP_L8, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_L8_TESTCH0_D6 [FM_OCP_MEZZB_PRES_N] > + {GPIO_SKL_H_GPP_L9, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_L9_TESTCH0_D7 [FM_OCP_MEZZC_PRES_N] > + {GPIO_SKL_H_GPP_L10, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_L10_TESTCH0_CLK [TP_PCH_GPP_L10] > + {GPIO_SKL_H_GPP_L11, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_L11_TESTCH1_D0 [TP_PCH_GPP_L11] > + {GPIO_SKL_H_GPP_L12, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_L12_TESTCH1_D1 > [H_CPU0_MEMABC_MEMHOT_PCH_N] > + {GPIO_SKL_H_GPP_L13, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_L13_TESTCH1_D2 > [H_CPU0_MEMDEF_MEMHOT_PCH_N] > + {GPIO_SKL_H_GPP_L14, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_L14_TESTCH1_D3 > [H_CPU1_MEMGHJ_MEMHOT_PCH_N > + {GPIO_SKL_H_GPP_L15, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_L15_TESTCH1_D4 > [H_CPU1_MEMKLM_MEMHOT_PCH_N] > + {GPIO_SKL_H_GPP_L16, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_L16_TESTCH1_D5 [FM_CPU0_PROCHOT_PCH_N] > + {GPIO_SKL_H_GPP_L17, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_L17_TESTCH1_D6 [FM_CPU1_PROCHOT_PCH_N > + {GPIO_SKL_H_GPP_L18, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_L18_TESTCH1_D7 [FM_CPU_ERR0_PCH_N] > + {GPIO_SKL_H_GPP_L19, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, > GpioTermNone}},//GPP_L19_TESTCH1_CLK [FM_CPU_ERR1_PCH_N] > +}; > + > +UINTN mGpioTableSizeTiogaPass =3D sizeof(mGpioTableTiogaPass); > diff --git > a/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardInitLib/ > IioBifur.c > b/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardInitLib > /IioBifur.c > new file mode 100644 > index 0000000000..23c6f0eb1e > --- /dev/null > +++ > b/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardInitLib > /IioBifur.c > @@ -0,0 +1,70 @@ > +/** @file > + > +Copyright (c) 2018, Intel Corporation. All rights reserved.
> +Copyright (c) 2021, American Megatrends International LLC.
> +SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > +#include > +#include > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > + > +#define ENABLE 1 > +#define DISABLE 0 > +#define NO_SLT_IMP 0xFF > +#define SLT_IMP 1 > +#define HIDE 1 > +#define NOT_HIDE 0 > +#define VPP_PORT_0 0 > +#define VPP_PORT_1 1 > +#define VPP_PORT_MAX 0xFF > +#define VPP_ADDR_MAX 0xFF > +#define PWR_VAL_MAX 0xFF > +#define PWR_SCL_MAX 0xFF > + > + > +IIO_BIFURCATION_ENTRY mIioBifurcationTable[] =3D > +{ > + { Iio_Socket0, Iio_Iou0, IIO_BIFURCATE_xxxxxx16 }, // Uplink x16 > + { Iio_Socket0, Iio_Iou1, IIO_BIFURCATE_x4x4x4x4 }, // x24 upper x16 > + { Iio_Socket0, Iio_Iou2, IIO_BIFURCATE_xxxxxx16 }, // OCP-Mezz > + { Iio_Socket0, Iio_Mcp0, IIO_BIFURCATE_xxxxxx16 }, > + { Iio_Socket0, Iio_Mcp1, IIO_BIFURCATE_xxxxxx16 }, > + { Iio_Socket1, Iio_Iou0, IIO_BIFURCATE_xxxxxx16 }, // un-used > + { Iio_Socket1, Iio_Iou1, IIO_BIFURCATE_xxxxxx16 }, // un-used > + { Iio_Socket1, Iio_Iou2, IIO_BIFURCATE_xxxxxx16 }, // combine AirMax A= & > B to x16 > + { Iio_Socket1, Iio_Mcp0, IIO_BIFURCATE_xxxxxx16 }, > + { Iio_Socket1, Iio_Mcp1, IIO_BIFURCATE_xxxxxx16 }, > +}; > + > +UINT8 mIioBifurcationTableEntries =3D > sizeof(mIioBifurcationTable)/sizeof(IIO_BIFURCATION_ENTRY); > + > +IIO_SLOT_CONFIG_ENTRY mIioSlotTable[] =3D { > + // Port | Slot | Inter | Power Limit | Power Limit= | Hot | Vpp > | Vpp | PcieSSD | PcieSSD | PcieSSD | Hidden > + // Index | | lock | Scale | Value = | Plug | Port | Addr > | Cap | VppPort | VppAddr | > + { PORT_1A_INDEX, NO_SLT_IMP, DISABLE , PWR_SCL_MAX , > PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE, > VPP_PORT_MAX, VPP_ADDR_MAX , NOT_HIDE}, // x16 uplink[15:0] > + { PORT_2A_INDEX, 4 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX= , > ENABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE, VPP_PORT_MAX, > VPP_ADDR_MAX , NOT_HIDE}, // x24 upper x16 > + { PORT_2B_INDEX, 9 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX= , > ENABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE, VPP_PORT_MAX, > VPP_ADDR_MAX , NOT_HIDE}, // x24 upper x16 > + { PORT_2C_INDEX, 10 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX= , > ENABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE, VPP_PORT_MAX, > VPP_ADDR_MAX , NOT_HIDE}, // x24 upper x16 > + { PORT_2D_INDEX, 11 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX= , > ENABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE, VPP_PORT_MAX, > VPP_ADDR_MAX , NOT_HIDE}, // x24 upper x16 > + { PORT_3A_INDEX, 7 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX= , > ENABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE, VPP_PORT_MAX, > VPP_ADDR_MAX , NOT_HIDE}, // OCP Mezz > + { SOCKET_1_INDEX + > + PORT_0_INDEX, NO_SLT_IMP, DISABLE , PWR_SCL_MAX , > PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE, > VPP_PORT_MAX, VPP_ADDR_MAX , HIDE }, // CPU1 DMI unused > + { SOCKET_1_INDEX + > + PORT_1A_INDEX, NO_SLT_IMP, DISABLE , PWR_SCL_MAX , > PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE, > VPP_PORT_MAX, VPP_ADDR_MAX , HIDE }, // CPU1 Port1 unused > + { SOCKET_1_INDEX + > + PORT_2A_INDEX, NO_SLT_IMP, DISABLE , PWR_SCL_MAX , > PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE, > VPP_PORT_MAX, VPP_ADDR_MAX , HIDE }, // CPU1 Port2 unused > + { SOCKET_1_INDEX + > + PORT_3A_INDEX, NO_SLT_IMP, DISABLE , PWR_SCL_MAX , > PWR_VAL_MAX , ENABLE , VPP_PORT_0 , 0x40 , DISABLE, > VPP_PORT_MAX, VPP_ADDR_MAX , HIDE}, // Airmax A & B > +}; > + > +UINT8 mIioSlotTableEntries =3D > sizeof(mIioSlotTable)/sizeof(IIO_SLOT_CONFIG_ENTRY); > \ No newline at end of file > diff --git > a/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardInitLib/ > PeiBoardInitPostMemLib.c > b/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardInitLib > /PeiBoardInitPostMemLib.c > new file mode 100644 > index 0000000000..fdc906065a > --- /dev/null > +++ > b/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardInitLib > /PeiBoardInitPostMemLib.c > @@ -0,0 +1,46 @@ > +/** @file > + > +Copyright (c) 2018, Intel Corporation. All rights reserved.
> +Copyright (c) 2021, American Megatrends International LLC.
> +SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > +#include > +#include > +#include > +#include > +#include > +#include > + > +EFI_STATUS > +EFIAPI > +TiogaPassBoardInitBeforeSiliconInit ( > + VOID > + ); > + > +EFI_STATUS > +EFIAPI > +TiogaPassBoardInitAfterSiliconInit ( > + VOID > + ); > + > +EFI_STATUS > +EFIAPI > +BoardInitBeforeSiliconInit ( > + VOID > + ) > +{ > + TiogaPassBoardInitBeforeSiliconInit (); > + return EFI_SUCCESS; > +} > + > +EFI_STATUS > +EFIAPI > +BoardInitAfterSiliconInit ( > + VOID > + ) > +{ > + TiogaPassBoardInitAfterSiliconInit (); > + return EFI_SUCCESS; > +} > diff --git > a/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardInitLib/ > PeiBoardInitPostMemLib.inf > b/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardInitLib > /PeiBoardInitPostMemLib.inf > new file mode 100644 > index 0000000000..b8f756ec88 > --- /dev/null > +++ > b/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardInitLib > /PeiBoardInitPostMemLib.inf > @@ -0,0 +1,37 @@ > +## @file > +# > +# Copyright (c) 2018, Intel Corporation. All rights reserved.
> +# Copyright (c) 2021, American Megatrends International LLC.
> +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > +## > + > +[Defines] > + INF_VERSION =3D 0x00010005 > + BASE_NAME =3D PeiBoardPostMemInitLib > + FILE_GUID =3D 30F407D6-6B92-412A-B2DA-8E73E2B386E= 6 > + MODULE_TYPE =3D BASE > + VERSION_STRING =3D 1.0 > + LIBRARY_CLASS =3D BoardInitLib > + > +[LibraryClasses] > + BaseLib > + DebugLib > + BaseMemoryLib > + MemoryAllocationLib > + PcdLib > + > +[Packages] > + MdePkg/MdePkg.dec > + MdeModulePkg/MdeModulePkg.dec > + MinPlatformPkg/MinPlatformPkg.dec > + PurleyRefreshSiliconPkg/SiPkg.dec > + > +[Sources] > + PeiTiogaPassInitPostMemLib.c > + PeiBoardInitPostMemLib.c > + > +[FixedPcd] > + > +[Pcd] > + > diff --git > a/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardInitLib/ > PeiBoardInitPreMemLib.c > b/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardInitLib > /PeiBoardInitPreMemLib.c > new file mode 100644 > index 0000000000..408fc37667 > --- /dev/null > +++ > b/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardInitLib > /PeiBoardInitPreMemLib.c > @@ -0,0 +1,112 @@ > +/** @file > + > +Copyright (c) 2018, Intel Corporation. All rights reserved.
> +Copyright (c) 2021, American Megatrends International LLC.
> +SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > +#include > +#include > +#include > +#include > +#include > +#include > + > +EFI_STATUS > +EFIAPI > +TiogaPassBoardDetect ( > + VOID > + ); > + > +EFI_BOOT_MODE > +EFIAPI > +TiogaPassBoardBootModeDetect ( > + VOID > + ); > + > +EFI_STATUS > +EFIAPI > +TiogaPassBoardDebugInit ( > + VOID > + ); > + > +EFI_STATUS > +EFIAPI > +TiogaPassBoardInitBeforeMemoryInit ( > + VOID > + ); > + > +EFI_STATUS > +EFIAPI > +TiogaPassBoardInitAfterMemoryInit ( > + VOID > + ); > + > +EFI_STATUS > +EFIAPI > +BoardDetect ( > + VOID > + ) > +{ > + TiogaPassBoardDetect (); > + return EFI_SUCCESS; > +} > + > +EFI_STATUS > +EFIAPI > +BoardDebugInit ( > + VOID > + ) > +{ > + TiogaPassBoardDebugInit (); > + return EFI_SUCCESS; > +} > + > +EFI_BOOT_MODE > +EFIAPI > +BoardBootModeDetect ( > + VOID > + ) > +{ > + return TiogaPassBoardBootModeDetect (); > +} > + > +EFI_STATUS > +EFIAPI > +BoardInitBeforeMemoryInit ( > + VOID > + ) > +{ > + TiogaPassBoardInitBeforeMemoryInit (); > + return EFI_SUCCESS; > +} > + > +EFI_STATUS > +EFIAPI > +BoardInitAfterMemoryInit ( > + VOID > + ) > +{ > + TiogaPassBoardInitAfterMemoryInit (); > + return EFI_SUCCESS; > +} > + > +EFI_STATUS > +EFIAPI > +BoardInitBeforeTempRamExit ( > + VOID > + ) > +{ > + return EFI_SUCCESS; > +} > + > +EFI_STATUS > +EFIAPI > +BoardInitAfterTempRamExit ( > + VOID > + ) > +{ > + return EFI_SUCCESS; > +} > + > diff --git > a/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardInitLib/ > PeiBoardInitPreMemLib.inf > b/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardInitLib > /PeiBoardInitPreMemLib.inf > new file mode 100644 > index 0000000000..0c305358a6 > --- /dev/null > +++ > b/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardInitLib > /PeiBoardInitPreMemLib.inf > @@ -0,0 +1,69 @@ > +## @file > +# > +# Copyright (c) 2018, Intel Corporation. All rights reserved.
> +# Copyright (c) 2021, American Megatrends International LLC.
> +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > +## > + > +[Defines] > + INF_VERSION =3D 0x00010005 > + BASE_NAME =3D PeiBoardInitPreMemLib > + FILE_GUID =3D 73AA24AE-FB20-43F9-A3BA-448953A03A7= 8 > + MODULE_TYPE =3D BASE > + VERSION_STRING =3D 1.0 > + LIBRARY_CLASS =3D BoardInitLib > + > +[LibraryClasses] > + BaseLib > + DebugLib > + BaseMemoryLib > + MemoryAllocationLib > + PcdLib > + GpioLib > + > +[Packages] > + MdePkg/MdePkg.dec > + MdeModulePkg/MdeModulePkg.dec > + MinPlatformPkg/MinPlatformPkg.dec > + PurleyOpenBoardPkg/OpenBoardPkg.dec > + PurleyRefreshSiliconPkg/SiPkg.dec > + > +[Sources] > + PeiTiogaPassDetect.c > + PeiTiogaPassInitPreMemLib.c > + PeiBoardInitPreMemLib.c > + GpioTable.c > + UsbOC.c > + IioBifur.c > + AllLanesEparam.c > + > +[Pcd] > + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress > + gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuSocketCount > + gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicEnable > + gOemSkuTokenSpaceGuid.PcdMemTsegSize > + gOemSkuTokenSpaceGuid.PcdMemIedSize > + > + gOemSkuTokenSpaceGuid.PcdSetupData > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData > + gOemSkuTokenSpaceGuid.PcdSocketCommonRcConfigData > + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData > + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData > + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData > + > + gOemSkuTokenSpaceGuid.PcdUsb20OverCurrentMappings > + gOemSkuTokenSpaceGuid.PcdUsb30OverCurrentMappings > + gOemSkuTokenSpaceGuid.PcdIioBifurcationTable > + gOemSkuTokenSpaceGuid.PcdIioBifurcationTableEntries > + gOemSkuTokenSpaceGuid.PcdIioSlotTable > + gOemSkuTokenSpaceGuid.PcdIioSlotTableEntries > + gOemSkuTokenSpaceGuid.PcdAllLanesEparamTable > + gOemSkuTokenSpaceGuid.PcdAllLanesEparamTableSize > + > +[FixedPcd] > + gEfiPchTokenSpaceGuid.PcdPchAcpiIoPortBaseAddress > + gEfiPchTokenSpaceGuid.PcdTcoBaseAddress > + > diff --git > a/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardInitLib/ > PeiTiogaPassDetect.c > b/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardInitLib > /PeiTiogaPassDetect.c > new file mode 100644 > index 0000000000..ddbc24e680 > --- /dev/null > +++ > b/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardInitLib > /PeiTiogaPassDetect.c > @@ -0,0 +1,28 @@ > +/** @file > + > +Copyright (c) 2018, Intel Corporation. All rights reserved.
> +Copyright (c) 2021, American Megatrends International LLC.
> +SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +EFI_STATUS > +EFIAPI > +TiogaPassBoardDetect ( > + VOID > + ) > +{ > + DEBUG ((EFI_D_INFO, "TiogaPassBoardDetect\n")); > + return EFI_SUCCESS; > +} > diff --git > a/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardInitLib/ > PeiTiogaPassInitLib.h > b/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardInitLib > /PeiTiogaPassInitLib.h > new file mode 100644 > index 0000000000..289e5d3194 > --- /dev/null > +++ > b/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardInitLib > /PeiTiogaPassInitLib.h > @@ -0,0 +1,18 @@ > +/** @file > + > +Copyright (c) 2018, Intel Corporation. All rights reserved.
> +Copyright (c) 2021, American Megatrends International LLC.
> +SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > +#ifndef _PEI_TIOGA_PASS_BOARD_INIT_LIB_H_ > +#define _PEI_TIOGA_PASS_BOARD_INIT_LIB_H_ > + > +#include > +#include > +#include > +#include > +#include > + > +#endif > diff --git > a/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardInitLib/ > PeiTiogaPassInitPostMemLib.c > b/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardInitLib > /PeiTiogaPassInitPostMemLib.c > new file mode 100644 > index 0000000000..e76e6188e1 > --- /dev/null > +++ > b/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardInitLib > /PeiTiogaPassInitPostMemLib.c > @@ -0,0 +1,86 @@ > +/** @file > + > +Copyright (c) 2018, Intel Corporation. All rights reserved.
> +Copyright (c) 2021, American Megatrends International LLC.
> +SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include > + > +#include "PeiTiogaPassInitLib.h" > + > +VOID > +GetIioUdsHob ( > + IN IIO_UDS **UdsHobPtr > + ) > +{ > + EFI_GUID UniversalDataGuid =3D IIO_UNIVERSAL_DATA_GUID; > + EFI_HOB_GUID_TYPE *GuidHob; > + > + ASSERT(UdsHobPtr); > + > + *UdsHobPtr =3D NULL; > + > + GuidHob =3D GetFirstGuidHob (&UniversalDataGuid); > + if (GuidHob){ > + *UdsHobPtr =3D GET_GUID_HOB_DATA (GuidHob); > + return; > + } > + > + ASSERT(FALSE); > +} > + > +EFI_STATUS > +EFIAPI > +TiogaPassBoardInitBeforeSiliconInit ( > + VOID > + ) > +{ > + return EFI_SUCCESS; > +} > + > +EFI_STATUS > +EFIAPI > +TiogaPassBoardInitAfterSiliconInit ( > + VOID > + ) > +{ > + IIO_UDS *IioUds; > + > + DEBUG((EFI_D_ERROR, "TiogaPassBoardInitAfterSiliconInit\n")); > + > + GetIioUdsHob(&IioUds); > + > + DEBUG ((EFI_D_ERROR, "Memory TOLM: %X\n", IioUds- > >PlatformData.MemTolm)); > + DEBUG ( > + (EFI_D_ERROR, > + "PCIE BASE: %lX Size : %X\n", > + IioUds->PlatformData.PciExpressBase, > + IioUds->PlatformData.PciExpressSize) > + ); > + DEBUG ( > + (EFI_D_ERROR, > + "PCI32 BASE: %X Limit: %X\n", > + IioUds->PlatformData.PlatGlobalMmiolBase, > + IioUds->PlatformData.PlatGlobalMmiolLimit) > + ); > + DEBUG ( > + (EFI_D_ERROR, > + "PCI64 BASE: %lX Limit: %lX\n", > + IioUds->PlatformData.PlatGlobalMmiohBase, > + IioUds->PlatformData.PlatGlobalMmiohLimit) > + ); > + DEBUG ((EFI_D_ERROR, "UC START: %lX End : %lX\n", IioUds- > >PlatformData.PlatGlobalMmiohBase, (IioUds- > >PlatformData.PlatGlobalMmiohLimit + 1))); > + > + return EFI_SUCCESS; > +} > diff --git > a/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardInitLib/ > PeiTiogaPassInitPreMemLib.c > b/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardInitLib > /PeiTiogaPassInitPreMemLib.c > new file mode 100644 > index 0000000000..a470b7b103 > --- /dev/null > +++ > b/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardInitLib > /PeiTiogaPassInitPreMemLib.c > @@ -0,0 +1,638 @@ > +/** @file > + > +Copyright (c) 2018, Intel Corporation. All rights reserved.
> +Copyright (c) 2021, American Megatrends International LLC.
> +SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include "PeiTiogaPassInitLib.h" > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include > +#include > +#include > + > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include "SioRegs.h" > + > +#define LEGACY_8259_MASK_REGISTER_MASTER 0x21 > +#define LEGACY_8259_MASK_REGISTER_SLAVE 0xA1 > + > +extern GPIO_INIT_CONFIG mGpioTableTiogaPass[]; > +extern UINTN mGpioTableSizeTiogaPass; > + > +extern PCH_USB_OVERCURRENT_PIN > Usb20OverCurrentMappings[PCH_MAX_USB2_PORTS]; > +extern PCH_USB_OVERCURRENT_PIN > Usb30OverCurrentMappings[PCH_MAX_USB3_PORTS]; > + > +extern IIO_BIFURCATION_ENTRY mIioBifurcationTable[]; > +extern UINT8 mIioBifurcationTableEntries; > +extern IIO_SLOT_CONFIG_ENTRY mIioSlotTable[]; > +extern UINT8 mIioSlotTableEntries; > +extern ALL_LANES_EPARAM_LINK_INFO > KtiTiogaPassAllLanesEparamTable[]; > +extern UINT32 KtiTiogaPassAllLanesEparamTableSize; > + > +/** > + > + Initialize the GPIO IO selection, GPIO USE selection, and GPIO signal > inversion registers. > + > + @param PeiServices - PeiService point. > + @param CpuIo - CpuIo PPI to read/write IO ports. > + > + @retval EFI_SUCCESS - Init succeed. > + > +**/ > +VOID > +LpcSioEarlyInit ( > + VOID > + ) > +{ > + PchLpcGenIoRangeSet ((0x600 & 0xFF0), 0x10, LPC_ESPI_FIRST_SLAVE); > + > + IoWrite8 (SIO_INDEX_PORT, SIO_UNLOCK); > + IoWrite8 (SIO_INDEX_PORT, SIO_UNLOCK); > + > + // > + //mailbox > + // > + IoWrite8 (SIO_INDEX_PORT, REG_LOGICAL_DEVICE); > + IoWrite8 (SIO_DATA_PORT, SIO_MAILBOX); > + > + IoWrite8 (SIO_INDEX_PORT, BASE_ADDRESS_HIGH0); > + IoWrite8 (SIO_DATA_PORT, (UINT8)(0x600 >> 8)); > + > + IoWrite8 (SIO_INDEX_PORT, BASE_ADDRESS_LOW0); > + IoWrite8 (SIO_DATA_PORT, (UINT8)(0x600 & 0xFF)); > + // > + //active mailbox > + // > + IoWrite8 (SIO_INDEX_PORT, ACTIVATE); > + IoWrite8 (SIO_DATA_PORT, 1); > + > + IoWrite8 (SIO_INDEX_PORT, SIO_LOCK); > +} > + > + > +VOID > +EarlyPlatformPchInit ( > + IN EFI_PEI_SERVICES **PeiServices, > + IN SYSTEM_CONFIGURATION *SystemConfiguration, > + IN PCH_RC_CONFIGURATION *PchRcConfiguration > + ) > +{ > + UINT16 Data16; > + UINT8 Data8; > + UINT8 TcoRebootHappened; > + UINTN SpiBaseAddress; > + UINTN P2sbBase; > + > + DEBUG((DEBUG_ERROR, "EarlyPlatformPchInit - Start\n")); > + > + SpiBaseAddress =3D MmPciBase ( > + DEFAULT_PCI_BUS_NUMBER_PCH, > + PCI_DEVICE_NUMBER_PCH_SPI, > + PCI_FUNCTION_NUMBER_PCH_SPI > + ); > + > + // > + // Program bar > + // > + P2sbBase =3D MmPciBase ( > + DEFAULT_PCI_BUS_NUMBER_PCH, > + PCI_DEVICE_NUMBER_PCH_P2SB, > + PCI_FUNCTION_NUMBER_PCH_P2SB > + ); > + > + MmioWrite32 (P2sbBase + R_PCH_P2SB_SBREG_BAR, > PCH_PCR_BASE_ADDRESS); > + MmioOr8 (P2sbBase + PCI_COMMAND_OFFSET, > EFI_PCI_COMMAND_MEMORY_SPACE); > + > + // > + // LPC I/O Configuration > + // > + PchLpcIoDecodeRangesSet ( > + (V_PCH_LPC_IOD_LPT_378 << N_PCH_LPC_IOD_LPT) | > + (V_PCH_LPC_IOD_COMB_3E8 << N_PCH_LPC_IOD_COMB) | > + (V_PCH_LPC_IOD_COMA_3F8 << N_PCH_LPC_IOD_COMA) > + ); > + > + PchLpcIoEnableDecodingSet ( > + B_PCH_LPC_IOE_ME2 | > + B_PCH_LPC_IOE_SE | > + B_PCH_LPC_IOE_ME1 | > + B_PCH_LPC_IOE_KE | > + B_PCH_LPC_IOE_HGE | > + B_PCH_LPC_IOE_LGE | > + B_PCH_LPC_IOE_FDE | > + B_PCH_LPC_IOE_PPE | > + B_PCH_LPC_IOE_CBE | > + B_PCH_LPC_IOE_CAE, > + LPC_ESPI_FIRST_SLAVE > + ); > + > + // > + // Enable the upper 128-byte bank of RTC RAM > + // > + PchPcrAndThenOr32 (PID_RTC, R_PCH_PCR_RTC_CONF, (UINT32)~0, > B_PCH_PCR_RTC_CONF_UCMOS_EN); > + > + // > + // Disable the Watchdog timer expiration from causing a system reset > + // > + PchPcrAndThenOr32 (PID_ITSS, R_PCH_PCR_ITSS_GIC, (UINT32)~0, > B_PCH_PCR_ITSS_GIC_AME); > + > + // > + // Halt the TCO timer > + // > + Data16 =3D IoRead16 (PcdGet16 (PcdTcoBaseAddress) + R_PCH_TCO1_CNT); > + Data16 |=3D B_PCH_TCO_CNT_TMR_HLT; > + IoWrite16 (PcdGet16 (PcdTcoBaseAddress) + R_PCH_TCO1_CNT, Data16); > + > + // > + // Read the Second TO status bit > + // > + Data8 =3D IoRead8 (PcdGet16 (PcdTcoBaseAddress) + R_PCH_TCO2_STS); > + DEBUG((EFI_D_ERROR, "pre read:%x\n", Data8)); > + > + Data8 =3D IoRead8 (PcdGet16 (PcdTcoBaseAddress) + R_PCH_TCO2_STS); > + DEBUG((EFI_D_ERROR, "read:%x\n", Data8)); > + if ((Data8 & B_PCH_TCO2_STS_SECOND_TO) =3D=3D > B_PCH_TCO2_STS_SECOND_TO) { > + TcoRebootHappened =3D 1; > + } else { > + TcoRebootHappened =3D 0; > + } > + if (TcoRebootHappened) { > + DEBUG ((EFI_D_ERROR, "EarlyPlatformPchInit - TCO Second TO status bi= t > is set. This might be a TCO reboot\n")); > + } > + > + // > + // Clear the Second TO status bit > + // > + Data8 |=3D B_PCH_TCO2_STS_SECOND_TO; > + IoWrite8 (PcdGet16 (PcdTcoBaseAddress) + R_PCH_TCO2_STS, Data8); > + > + // > + // Disable SERR NMI and IOCHK# NMI in port 61 > + // > + Data8 =3D IoRead8 (R_PCH_NMI_SC); > + Data8 |=3D (B_PCH_NMI_SC_PCI_SERR_EN | > B_PCH_NMI_SC_IOCHK_NMI_EN); > + IoWrite8 (R_PCH_NMI_SC, Data8); > + > + PchPcrAndThenOr32 (PID_ITSS, R_PCH_PCR_ITSS_GIC, > (UINT32)~B_PCH_PCR_ITSS_GIC_AME, 0); > + > + // > + // Clear EISS bit to allow for SPI use > + // > + MmioAnd8 (SpiBaseAddress + R_PCH_SPI_BC, > (UINT8)~B_PCH_SPI_BC_EISS); > + > + // > + // Disable/hide ME IDE-R device. > + // > + > + /*MmioWrite32( > + (MmPciBase(DEFAULT_PCI_BUS_NUMBER_PCH, 0x16, 0x02) + 0x54), > + 0x03 > + );*/ > + > + PchPcrAndThenOr32 ( > + PID_PSF1, > + R_PCH_H_PCR_PSF1_T0_SHDW_IDER_REG_BASE + > R_PCH_PCR_PSFX_T0_SHDW_PCIEN, > + (UINT32)~0, > + B_PCH_PCR_PSFX_T0_SHDW_PCIEN_FUNDIS > + ); > + > + /*MmioWrite32( > + (MmPciBase(DEFAULT_PCI_BUS_NUMBER_PCH, 0x16, 0x03) + 0x54), > + 0x03 > + );*/ > + > + PchPcrAndThenOr32 ( > + PID_PSF1, > + R_PCH_H_PCR_PSF1_T0_SHDW_KT_REG_BASE + > R_PCH_PCR_PSFX_T0_SHDW_PCIEN, > + (UINT32)~0, > + B_PCH_PCR_PSFX_T0_SHDW_PCIEN_FUNDIS > + ); > + > + PchPcrAndThenOr32 ( > + PID_PSF2, > + R_PCH_PCR_PSF2_T0_SHDW_TRH_REG_BASE + > R_PCH_PCR_PSFX_T0_SHDW_PCIEN, > + (UINT32)~0, > + B_PCH_PCR_PSFX_T0_SHDW_PCIEN_FUNDIS > + ); > + > + DEBUG((DEBUG_ERROR, "EarlyPlatformPchInit - End\n")); > +} > + > + > +/** > + > + Initialize POC register by Variable. > + > + @param *SystemConfiguration - Pointer to SystemConfiguration > variables. > + > + @retval EFI_SUCCESS - Success. > + > +**/ > +EFI_STATUS > +UpdatePlatformInfo ( > + IN SYSTEM_CONFIGURATION *SystemConfiguration, > + IN SOCKET_CONFIGURATION *SocketConfiguration > + ) > +{ > + SOCKET_PROCESSORCORE_CONFIGURATION > *SocketProcessorCoreConfig; > + SOCKET_IIO_CONFIGURATION *SocketIioConfig; > + EFI_STATUS Status; > + UINT32 PcIoApicEnable; > +#if MAX_SOCKET <=3D 4 > + UINTN Index; > +#endif > + > + DEBUG((EFI_D_ERROR, "platform update platform info entry\n")); > + > + SocketProcessorCoreConfig =3D &SocketConfiguration- > >SocketProcessorCoreConfiguration; > + SocketIioConfig =3D &SocketConfiguration->IioConfig; > + > +#if MAX_SOCKET <=3D 4 > + for (Index =3D 0; Index < 24; Index++) { > + if (SocketIioConfig->DevPresIoApicIio[Index]) { > + PcIoApicEnable |=3D (1 << Index); > + } > + } > + > +#else > + // Enable all 32 IOxAPIC > + PcIoApicEnable =3D 0xFFFFFFFF; > +#endif > + Status =3D PcdSet32S (PcdPcIoApicEnable, PcIoApicEnable); > + ASSERT_EFI_ERROR (Status); > + // > + // Check to make sure TsegSize is in range, if not use default. > + // > + if (SocketProcessorCoreConfig->TsegSize > MAX_PROCESSOR_TSEG) { > + SocketProcessorCoreConfig->TsegSize =3D MAX_PROCESSOR_TSEG; // if > out of range make default 64M > + } > + Status =3D PcdSet32S (PcdMemTsegSize, (0x400000 << > SocketProcessorCoreConfig->TsegSize)); > + ASSERT_EFI_ERROR (Status); > + if (SocketProcessorCoreConfig->IedSize > 0) { > + Status =3D PcdSet32S (PcdMemIedSize, (0x400000 << > (SocketProcessorCoreConfig->IedSize - 1))); > + ASSERT_EFI_ERROR (Status); > + } else { > + Status =3D PcdSet32S (PcdMemIedSize, 0); > + ASSERT_EFI_ERROR (Status); > + } > + > + // > + // Minimum SMM range in TSEG should be larger than 3M > + // > + ASSERT (PcdGet32 (PcdMemTsegSize) - PcdGet32 (PcdMemIedSize) >=3D > 0x300000); > + > + return EFI_SUCCESS; > +} > + > +/** > + Clear any SMI status or wake status left from boot. > + > + @retval EFI_SUCCESS The function completed successfully. > +**/ > +EFI_STATUS > +ClearPchSmiAndWake ( > + VOID > + ) > +{ > + UINT16 ABase; > + UINT16 Pm1Sts =3D 0; > + > + > + // > + // Clear any SMI or wake state from the boot > + // > + Pm1Sts |=3D > + ( > + B_PCH_ACPI_PM1_STS_PWRBTN > + ); > + PchAcpiBaseGet (&ABase); > + // > + // Write them back > + // > + IoWrite16 (ABase + R_PCH_ACPI_PM1_STS, Pm1Sts); > + > + // > + // Clear the GPE and PM enable > + // > + IoWrite16 (ABase + R_PCH_ACPI_PM1_EN, 0); > + IoWrite32 (ABase + R_PCH_ACPI_GPE0_EN_127_96, 0); > + > + return EFI_SUCCESS; > +} > + > +EFI_STATUS > +PlatformInitGpios ( > + VOID > + ) > +{ > + EFI_STATUS Status; > + GPIO_INIT_CONFIG *GpioTable; > + UINTN TableSize; > + > + TableSize =3D mGpioTableSizeTiogaPass; > + DEBUG ((DEBUG_ERROR, "UBA:Size of GpioTable 0x%X, blocks: 0x%X.\n", > TableSize, (TableSize/sizeof (GPIO_INIT_CONFIG)) )); > + > + GpioTable =3D mGpioTableTiogaPass; > + DEBUG ((DEBUG_ERROR, "UBA: ConfigureGpio() TiogaPass Start.\n")); > + Status =3D GpioConfigurePads (TableSize/sizeof (GPIO_INIT_CONFIG), > GpioTable); > + DEBUG ((DEBUG_ERROR, "UBA: ConfigureGpio() TiogaPass End.\n")); > + > + return EFI_SUCCESS; > +} > + > +VOID > +SetUsbConfig ( > + VOID > + ) > +{ > + EFI_STATUS Status; > + > + Status =3D PcdSet64S (PcdUsb20OverCurrentMappings, > (UINT64)(UINTN)Usb20OverCurrentMappings); > + ASSERT_EFI_ERROR (Status); > + Status =3D PcdSet64S (PcdUsb30OverCurrentMappings, > (UINT64)(UINTN)Usb30OverCurrentMappings); > + ASSERT_EFI_ERROR (Status); > +} > + > +VOID > +IioPortBifurcationConfig ( > + VOID > + ) > +{ > + EFI_STATUS Status; > + > + Status =3D PcdSet64S (PcdIioBifurcationTable, > (UINT64)(UINTN)mIioBifurcationTable); > + ASSERT_EFI_ERROR (Status); > + Status =3D PcdSet8S (PcdIioBifurcationTableEntries, > mIioBifurcationTableEntries); > + ASSERT_EFI_ERROR (Status); > + Status =3D PcdSet64S (PcdIioSlotTable, (UINT64)(UINTN)mIioSlotTable); > + ASSERT_EFI_ERROR (Status); > + Status =3D PcdSet8S (PcdIioSlotTableEntries, mIioSlotTableEntries); > + ASSERT_EFI_ERROR (Status); > +} > + > +VOID > +AllLanesEparamTableConfig ( > + VOID > + ) > +{ > + EFI_STATUS Status; > + > + Status =3D PcdSet64S (PcdAllLanesEparamTable, > (UINT64)(UINTN)KtiTiogaPassAllLanesEparamTable); > + ASSERT_EFI_ERROR (Status); > + Status =3D PcdSet32S (PcdAllLanesEparamTableSize, > KtiTiogaPassAllLanesEparamTableSize); > + ASSERT_EFI_ERROR (Status); > +} > + > +EFI_STATUS > +PchLanConfig ( > + IN SYSTEM_CONFIGURATION *SystemConfig > + ) > +{ > + GpioSetOutputValue (GPIO_SKL_H_GPP_I9, (UINT32)SystemConfig- > >LomDisableByGpio); > + > + return EFI_SUCCESS; > +} > + > +/** > + Write to mask registers of master and slave 8259 PICs. > + > +**/ > +VOID > +STATIC > +Mask8259Interrupts ( > + VOID > + ) > +{ > + IoWrite8 (LEGACY_8259_MASK_REGISTER_MASTER, 0xFF); > + IoWrite8 (LEGACY_8259_MASK_REGISTER_SLAVE, 0xFF); > +} > + > +EFI_STATUS > +EFIAPI > +TiogaPassBoardInitBeforeMemoryInit ( > + VOID > + ) > +{ > + EFI_STATUS Status; > + SETUP_DATA SetupData; > + SYSTEM_CONFIGURATION SystemConfiguration; > + PCH_RC_CONFIGURATION PchRcConfiguration; > + SOCKET_CONFIGURATION SocketConfiguration; > + UINT16 ABase; > + UINT16 Pm1Sts; > + UINT32 Pm1Cnt; > + CONST EFI_PEI_SERVICES ** PeiServices; > + > + PeiServices =3D GetPeiServicesTablePointer (); > + > + ZeroMem (&SetupData, sizeof(SETUP_DATA)); > + CopyMem (&SetupData.SocketConfig.IioConfig, > PcdGetPtr(PcdSocketIioConfigData), sizeof(SOCKET_IIO_CONFIGURATION)); > + CopyMem (&SetupData.SocketConfig.CommonRcConfig, > PcdGetPtr(PcdSocketCommonRcConfigData), > sizeof(SOCKET_COMMONRC_CONFIGURATION)); > + CopyMem (&SetupData.SocketConfig.CsiConfig, > PcdGetPtr(PcdSocketMpLinkConfigData), > sizeof(SOCKET_MP_LINK_CONFIGURATION)); > + CopyMem (&SetupData.SocketConfig.MemoryConfig, > PcdGetPtr(PcdSocketMemoryConfigData), > sizeof(SOCKET_MEMORY_CONFIGURATION)); > + CopyMem (&SetupData.SocketConfig.PowerManagementConfig, > PcdGetPtr(PcdSocketPowerManagementConfigData), > sizeof(SOCKET_POWERMANAGEMENT_CONFIGURATION)); > + CopyMem (&SetupData.SocketConfig.SocketProcessorCoreConfiguration, > PcdGetPtr(PcdSocketProcessorCoreConfigData), > sizeof(SOCKET_PROCESSORCORE_CONFIGURATION)); > + CopyMem (&SetupData.SystemConfig, PcdGetPtr(PcdSetupData), > sizeof(SYSTEM_CONFIGURATION)); > + CopyMem (&SetupData.PchRcConfig, > PcdGetPtr(PcdPchRcConfigurationData), sizeof(PCH_RC_CONFIGURATION)); > + > + CopyMem (&SocketConfiguration, &(SetupData.SocketConfig), sizeof > (SOCKET_CONFIGURATION)); > + CopyMem (&PchRcConfiguration, &(SetupData.PchRcConfig), sizeof > (PCH_RC_CONFIGURATION)); > + CopyMem (&SystemConfiguration, &(SetupData.SystemConfig), sizeof > (SYSTEM_CONFIGURATION)); > + > + /// > + /// Set LPC SIO > + /// > + MmioOr16( > + (MmPciBase(DEFAULT_PCI_BUS_NUMBER_PCH, > PCI_DEVICE_NUMBER_PCH_LPC, PCI_FUNCTION_NUMBER_PCH_LPC) + > R_PCH_LPC_IOE), > + B_PCH_LPC_IOE_SE > + ); > + > + LpcSioEarlyInit (); > + > + Status =3D PlatformInitGpios (); > + ASSERT_EFI_ERROR (Status); > + > + SetUsbConfig (); > + IioPortBifurcationConfig (); > + AllLanesEparamTableConfig (); > + > + /// > + /// Do Early PCH init > + /// > + EarlyPlatformPchInit ((EFI_PEI_SERVICES**)PeiServices, > &SystemConfiguration, &PchRcConfiguration); > + > + /// > + /// Clear PCH SMI and Wake > + /// Clear all pending SMI. On S3 clear power button enable so it will = not > generate an SMI. > + /// > + Status =3D ClearPchSmiAndWake(); > + ASSERT_EFI_ERROR (Status); > + ///-------------------------------------------------------------------= --------------- > + /// > + /// BIOS should check the WAK_STS bit in PM1_STS[15] (PCH register > ABASE+00h) before memory > + /// initialization to determine if ME has reset the system while the h= ost > was in a sleep state. > + /// If WAK_STS is not set, BIOS should ensure a non-sleep exit path is > taken by overwriting > + /// PM1_CNT[12:10] (PCH register ABASE+04h) to 111b to force an s5 exi= t. > + /// > + PchAcpiBaseGet (&ABase); > + Pm1Sts =3D IoRead16 (ABase + R_PCH_ACPI_PM1_STS); > + if ((Pm1Sts & B_PCH_ACPI_PM1_STS_WAK) =3D=3D 0) { > + Pm1Cnt =3D IoRead32 (ABase + R_PCH_ACPI_PM1_CNT); > + Pm1Cnt |=3D V_PCH_ACPI_PM1_CNT_S5; > + IoWrite32 (ABase + R_PCH_ACPI_PM1_CNT, Pm1Cnt); > + } > + > + UpdatePlatformInfo (&SystemConfiguration, &SocketConfiguration); > + > + // > + // Do platform specific on-board Zoar init > + // > + PchLanConfig (&SystemConfiguration); > + > + // > + // The 8259 PIC is still functional and not masked by default even if = APIC is > + // enabled. So need to disable all 8259 interrupts. > + // > + Mask8259Interrupts (); > + > + return EFI_SUCCESS; > +} > + > +/** > + > + Turn off system if needed. > + > + @param PeiServices Pointer to PEI Services > + @param CpuIo Pointer to CPU I/O Protocol > + > + @retval None. > + > +**/ > +VOID > +CheckPowerOffNow ( > + VOID > + ) > +{ > + > + UINT16 Pm1Sts; > + > + // > + // Read and check the ACPI registers > + // > + Pm1Sts =3D IoRead16 (PcdGet16 (PcdPchAcpiIoPortBaseAddress) + > R_PCH_ACPI_PM1_STS); > + DEBUG ((EFI_D_ERROR, "CheckPowerOffNow()- Pm1Sts=3D 0x%04x\n", > Pm1Sts )); > + > + if ((Pm1Sts & B_PCH_ACPI_PM1_STS_PWRBTN) =3D=3D > B_PCH_ACPI_PM1_STS_PWRBTN) { > + IoWrite16 (PcdGet16 (PcdPchAcpiIoPortBaseAddress) + > R_PCH_ACPI_PM1_STS, B_PCH_ACPI_PM1_STS_PWRBTN); > + IoWrite16 (PcdGet16 (PcdPchAcpiIoPortBaseAddress) + > R_PCH_ACPI_PM1_CNT, V_PCH_ACPI_PM1_CNT_S5); > + IoWrite16 (PcdGet16 (PcdPchAcpiIoPortBaseAddress) + > R_PCH_ACPI_PM1_CNT, V_PCH_ACPI_PM1_CNT_S5 + > B_PCH_ACPI_PM1_CNT_SLP_EN); > + } > +} > + > +EFI_STATUS > +EFIAPI > +TiogaPassBoardInitAfterMemoryInit ( > + VOID > + ) > +{ > + EFI_STATUS Status; > + EFI_BOOT_MODE BootMode; > + UINT16 Pm1Cnt; > + > + Status =3D PeiServicesGetBootMode (&BootMode); > + ASSERT_EFI_ERROR (Status); > + > + // > + // Check if user wants to turn off in PEI phase > + // > + if (BootMode !=3D BOOT_ON_S3_RESUME) { > + CheckPowerOffNow (); > + } else { > + Pm1Cnt =3D IoRead16 (PcdGet16 (PcdPchAcpiIoPortBaseAddress) + > R_PCH_ACPI_PM1_CNT); > + Pm1Cnt &=3D ~B_PCH_ACPI_PM1_CNT_SLP_TYP; > + IoWrite16 (PcdGet16 (PcdPchAcpiIoPortBaseAddress) + > R_PCH_ACPI_PM1_CNT, Pm1Cnt); > + } > + > + return EFI_SUCCESS; > +} > + > +EFI_STATUS > +EFIAPI > +TiogaPassBoardDebugInit ( > + VOID > + ) > +{ > + return EFI_SUCCESS; > +} > + > +EFI_BOOT_MODE > +EFIAPI > +TiogaPassBoardBootModeDetect ( > + VOID > + ) > +{ > + return BOOT_WITH_FULL_CONFIGURATION; > +} > + > diff --git > a/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardInitLib/ > UsbOC.c > b/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardInitLib > /UsbOC.c > new file mode 100644 > index 0000000000..e1661df7e3 > --- /dev/null > +++ > b/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardInitLib > /UsbOC.c > @@ -0,0 +1,46 @@ > +/** @file > + > +Copyright (c) 2018, Intel Corporation. All rights reserved.
> +Copyright (c) 2021, American Megatrends International LLC.
> +SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > +#include > + > +#include > +#include > +#include > + > +PCH_USB_OVERCURRENT_PIN > Usb20OverCurrentMappings[PCH_MAX_USB2_PORTS] =3D { > + PchUsbOverCurrentPin0, > + PchUsbOverCurrentPinSkip, > + PchUsbOverCurrentPinSkip, > + PchUsbOverCurrentPinSkip, > + PchUsbOverCurrentPinSkip, > + PchUsbOverCurrentPinSkip, > + PchUsbOverCurrentPinSkip, > + PchUsbOverCurrentPinSkip, > + PchUsbOverCurrentPinSkip, > + PchUsbOverCurrentPinSkip, > + PchUsbOverCurrentPinSkip, > + PchUsbOverCurrentPinSkip, > + PchUsbOverCurrentPinSkip, > + PchUsbOverCurrentPinSkip, > + PchUsbOverCurrentPinSkip, > + PchUsbOverCurrentPinSkip > + }; > + > +PCH_USB_OVERCURRENT_PIN > Usb30OverCurrentMappings[PCH_MAX_USB3_PORTS] =3D { > + PchUsbOverCurrentPin0, > + PchUsbOverCurrentPinSkip, > + PchUsbOverCurrentPinSkip, > + PchUsbOverCurrentPinSkip, > + PchUsbOverCurrentPinSkip, > + PchUsbOverCurrentPinSkip, > + PchUsbOverCurrentPinSkip, > + PchUsbOverCurrentPinSkip, > + PchUsbOverCurrentPinSkip, > + PchUsbOverCurrentPinSkip > + }; > + > diff --git > a/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/PeiReportFv > Lib/PeiReportFvLib.c > b/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/PeiReportFv > Lib/PeiReportFvLib.c > new file mode 100644 > index 0000000000..9d81776e22 > --- /dev/null > +++ > b/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/PeiReportFv > Lib/PeiReportFvLib.c > @@ -0,0 +1,138 @@ > +/** @file > + > +Copyright (c) 2018, Intel Corporation. All rights reserved.
> +Copyright (c) 2021, American Megatrends International LLC.
> +SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +VOID > +ReportPreMemFv ( > + VOID > + ) > +{ > + if (!PcdGetBool(PcdFspWrapperBootMode)) { > + DEBUG ((DEBUG_INFO, "Install FlashFvFspM - 0x%x, 0x%x\n", PcdGet32 > (PcdFlashFvFspMBase), PcdGet32 (PcdFlashFvFspMSize))); > + PeiServicesInstallFvInfo2Ppi ( > + &(((EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) PcdGet32 > (PcdFlashFvFspMBase))->FileSystemGuid), > + (VOID *) (UINTN) PcdGet32 (PcdFlashFvFspMBase), > + PcdGet32 (PcdFlashFvFspMSize), > + NULL, > + NULL, > + 0 > + ); > + } > + DEBUG ((DEBUG_INFO, "Install FlashFvSecurity - 0x%x, 0x%x\n", PcdGet32 > (PcdFlashFvSecurityBase), PcdGet32 (PcdFlashFvSecuritySize))); > + PeiServicesInstallFvInfo2Ppi ( > + &(((EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) PcdGet32 > (PcdFlashFvSecurityBase))->FileSystemGuid), > + (VOID *) (UINTN) PcdGet32 (PcdFlashFvSecurityBase), > + PcdGet32 (PcdFlashFvSecuritySize), > + NULL, > + NULL, > + 0 > + ); > + DEBUG ((DEBUG_INFO, "Install FlashFvAdvanced - 0x%x, 0x%x\n", > PcdGet32 (PcdFlashFvAdvancedBase), PcdGet32 > (PcdFlashFvAdvancedSize))); > + PeiServicesInstallFvInfo2Ppi ( > + &(((EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) PcdGet32 > (PcdFlashFvAdvancedBase))->FileSystemGuid), > + (VOID *) (UINTN) PcdGet32 (PcdFlashFvAdvancedBase), > + PcdGet32 (PcdFlashFvAdvancedSize), > + NULL, > + NULL, > + 0 > + ); > +} > + > +VOID > +ReportPostMemFv ( > + VOID > + ) > +{ > + EFI_STATUS Status; > + EFI_BOOT_MODE BootMode; > + > + Status =3D PeiServicesGetBootMode (&BootMode); > + ASSERT_EFI_ERROR (Status); > + > + /// > + /// Build HOB for DXE > + /// > + if (BootMode =3D=3D BOOT_IN_RECOVERY_MODE) { > + /// > + /// Prepare the recovery service > + /// > + } else { > + DEBUG ((DEBUG_INFO, "Install FlashFvPostMemory - 0x%x, 0x%x\n", > PcdGet32 (PcdFlashFvPostMemoryBase), PcdGet32 > (PcdFlashFvPostMemorySize))); > + PeiServicesInstallFvInfo2Ppi ( > + &(((EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) PcdGet32 > (PcdFlashFvPostMemoryBase))->FileSystemGuid), > + (VOID *) (UINTN) PcdGet32 (PcdFlashFvPostMemoryBase), > + PcdGet32 (PcdFlashFvPostMemorySize), > + NULL, > + NULL, > + 0 > + ); > + if (!PcdGetBool(PcdFspWrapperBootMode)) { > + DEBUG ((DEBUG_INFO, "Install FlashFvFspS - 0x%x, 0x%x\n", PcdGet32 > (PcdFlashFvFspSBase), PcdGet32 (PcdFlashFvFspSSize))); > + PeiServicesInstallFvInfo2Ppi ( > + &(((EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) PcdGet32 > (PcdFlashFvFspSBase))->FileSystemGuid), > + (VOID *) (UINTN) PcdGet32 (PcdFlashFvFspSBase), > + PcdGet32 (PcdFlashFvFspSSize), > + NULL, > + NULL, > + 0 > + ); > + DEBUG ((DEBUG_INFO, "Install FlashFvFspU - 0x%x, 0x%x\n", PcdGet32 > (PcdFlashFvFspUBase), PcdGet32 (PcdFlashFvFspUSize))); > + PeiServicesInstallFvInfo2Ppi ( > + &(((EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) PcdGet32 > (PcdFlashFvFspUBase))->FileSystemGuid), > + (VOID *) (UINTN) PcdGet32 (PcdFlashFvFspUBase), > + PcdGet32 (PcdFlashFvFspUSize), > + NULL, > + NULL, > + 0 > + ); > + } > + DEBUG ((DEBUG_INFO, "Install FlashFvUefiBoot - 0x%x, 0x%x\n", > PcdGet32 (PcdFlashFvUefiBootBase), PcdGet32 (PcdFlashFvUefiBootSize))); > + PeiServicesInstallFvInfo2Ppi ( > + &(((EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) PcdGet32 > (PcdFlashFvUefiBootBase))->FileSystemGuid), > + (VOID *) (UINTN) PcdGet32 (PcdFlashFvUefiBootBase), > + PcdGet32 (PcdFlashFvUefiBootSize), > + NULL, > + NULL, > + 0 > + ); > + DEBUG ((DEBUG_INFO, "Install FlashFvOsBoot - 0x%x, 0x%x\n", PcdGet32 > (PcdFlashFvOsBootBase), PcdGet32 (PcdFlashFvOsBootSize))); > + PeiServicesInstallFvInfo2Ppi ( > + &(((EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) PcdGet32 > (PcdFlashFvOsBootBase))->FileSystemGuid), > + (VOID *) (UINTN) PcdGet32 (PcdFlashFvOsBootBase), > + PcdGet32 (PcdFlashFvOsBootSize), > + NULL, > + NULL, > + 0 > + ); > + } > + > + // > + // Report resource HOB for flash FV > + // > + BuildResourceDescriptorHob ( > + EFI_RESOURCE_MEMORY_MAPPED_IO, > + (EFI_RESOURCE_ATTRIBUTE_PRESENT | > + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | > + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE), > + (UINTN) PcdGet32 (PcdFlashAreaBaseAddress), > + (UINTN) PcdGet32 (PcdFlashAreaSize) > + ); > + BuildMemoryAllocationHob ( > + (UINTN) PcdGet32 (PcdFlashAreaBaseAddress), > + (UINTN) PcdGet32 (PcdFlashAreaSize), > + EfiMemoryMappedIO > + ); > +} > diff --git > a/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/PeiReportFv > Lib/PeiReportFvLib.inf > b/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/PeiReportFv > Lib/PeiReportFvLib.inf > new file mode 100644 > index 0000000000..8c753e73ba > --- /dev/null > +++ > b/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/PeiReportFv > Lib/PeiReportFvLib.inf > @@ -0,0 +1,51 @@ > +## @file > +# > +# Copyright (c) 2018, Intel Corporation. All rights reserved.
> +# Copyright (c) 2021, American Megatrends International LLC.
> +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > +## > + > + > +[Defines] > + INF_VERSION =3D 0x00010017 > + BASE_NAME =3D PeiReportFvLib > + FILE_GUID =3D 44328FA5-E4DD-4A15-ABDF-C6584AC363D= 9 > + VERSION_STRING =3D 1.0 > + MODULE_TYPE =3D PEIM > + LIBRARY_CLASS =3D ReportFvLib > + > +[LibraryClasses] > + BaseMemoryLib > + DebugLib > + HobLib > + PeiServicesLib > + > +[Packages] > + MdePkg/MdePkg.dec > + MdeModulePkg/MdeModulePkg.dec > + MinPlatformPkg/MinPlatformPkg.dec > + > +[Sources] > + PeiReportFvLib.c > + > +[Pcd] > + gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode ## > CONSUMES > + gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress ## > CONSUMES > + gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize ## CONSUMES > + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase ## > CONSUMES > + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize ## > CONSUMES > + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase ## > CONSUMES > + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize ## CONSUMES > + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspUBase ## > CONSUMES > + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspUSize ## CONSUMES > + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase ## > CONSUMES > + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize ## > CONSUMES > + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootBase ## > CONSUMES > + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize ## > CONSUMES > + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootBase ## > CONSUMES > + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize ## > CONSUMES > + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityBase ## > CONSUMES > + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize ## > CONSUMES > + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase ## > CONSUMES > + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize ## > CONSUMES > diff --git > a/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/OpenBoardPkg.dsc > b/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/OpenBoardPkg.dsc > new file mode 100644 > index 0000000000..e4c8e7fbf1 > --- /dev/null > +++ > b/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/OpenBoardPkg.dsc > @@ -0,0 +1,245 @@ > +## @file > +# The main build description file for the TiogaPass board. > +# > +# Copyright (c) 2018, Intel Corporation. All rights reserved.
> +# Copyright (c) 2021, American Megatrends International LLC.
> +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > +## > + > +######################################################### > ####################### > +# > +# Defines Section - statements that will be processed to create a Makefi= le. > +# > +######################################################### > ####################### > +[Defines] > + DEFINE PLATFORM_PACKAGE =3D MinPlatformPkg > + DEFINE PLATFORM_SI_PACKAGE =3D PurleyRefreshSiliconPkg > + DEFINE PLATFORM_SI_BIN_PACKAGE =3D PurleySiliconBinPkg > + DEFINE PLATFORM_BOARD_PACKAGE =3D PurleyOpenBoardPkg > + DEFINE BOARD =3D BoardTiogaPass > + DEFINE PROJECT =3D $(PLATFORM_BOARD_PACKAGE)/$(BOAR= D) > + DEFINE PEI_ARCH =3D IA32 > + DEFINE DXE_ARCH =3D X64 > + > + PLATFORM_NAME =3D PurleyOpenBoardPkg > + PLATFORM_GUID =3D D7EAF54D-C9B9-4075-89F0-71943D= BCFA61 > + PLATFORM_VERSION =3D 0.1 > + DSC_SPECIFICATION =3D 0x00010005 > + OUTPUT_DIRECTORY =3D Build/$(PROJECT) > + SUPPORTED_ARCHITECTURES =3D IA32|X64 > + BUILD_TARGETS =3D DEBUG|RELEASE > + SKUID_IDENTIFIER =3D DEFAULT > + FLASH_DEFINITION =3D $(PROJECT)/OpenBoardPkg.fdf > + > + FIX_LOAD_TOP_MEMORY_ADDRESS =3D 0x0 > + > + DEFINE NETWORK_ISCSI_ENABLE =3D TRUE > + > + # > + # Platform On/Off features are defined here > + # > + !include $(PROJECT)/PlatformPkgConfig.dsc > + > + # > + # Include PCD configuration for this board. > + # > + !include AdvancedFeaturePkg/Include/AdvancedFeaturesPcd.dsc > + > + !include PlatformPkgPcd.dsc > + !include AdvancedFeaturePkg/Include/AdvancedFeatures.dsc > + > + > +######################################################### > ####################### > +# > +# SKU Identification section - list of all SKU IDs supported by this > +# Platform. > +# > +######################################################### > ####################### > +[SkuIds] > + 0|DEFAULT # The entry: 0|DEFAULT is reserved and always > required. > + > +[DefaultStores] > + 0|STANDARD # UEFI Standard default 0|STANDARD is reserved= . > + 1|MANUFACTURING # UEFI Manufacturing default > 1|MANUFACTURING is reserved. > + > +######################################################### > ####################### > +# > +# Includes section - other DSC file contents included for this board bui= ld. > +# > +######################################################### > ####################### > + > +####################################### > +# Library Includes > +####################################### > +!include $(PLATFORM_PACKAGE)/Include/Dsc/CoreCommonLib.dsc > +!include $(PLATFORM_PACKAGE)/Include/Dsc/CorePeiLib.dsc > +!include $(PLATFORM_PACKAGE)/Include/Dsc/CoreDxeLib.dsc > +!include $(PLATFORM_SI_PACKAGE)/SiPkgCommonLib.dsc > +!include $(PLATFORM_SI_PACKAGE)/SiPkgPeiLib.dsc > +!include $(PLATFORM_SI_PACKAGE)/SiPkgDxeLib.dsc > + > +####################################### > +# Component Includes > +####################################### > + > +[Components.$(PEI_ARCH)] > +!include $(PLATFORM_PACKAGE)/Include/Dsc/CorePeiInclude.dsc > + > +[Components.$(DXE_ARCH)] > +#TiogaPass Override START : Added Board Specific changes in core drivers > +#!include $(PLATFORM_PACKAGE)/Include/Dsc/CoreDxeInclude.dsc > +!include CoreDxeInclude.dsc > +#TiogaPass Override END > + > +####################################### > +# Build Option Includes > +####################################### > +!include $(PROJECT)/PlatformPkgBuildOption.dsc > + > +######################################################### > ####################### > +# > +# Library Class section - list of all Library Classes needed by this Pla= tform. > +# > +######################################################### > ####################### > + > +[LibraryClasses.common] > +!if gPlatformTokenSpaceGuid.PcdFastBoot =3D=3D FALSE > + > PlatformBootManagerLib|$(PLATFORM_PACKAGE)/Bds/Library/DxePlatfor > mBootManagerLib/DxePlatformBootManagerLib.inf > +!else > + > PlatformBootManagerLib|$(PLATFORM_BOARD_PACKAGE)/Override/Platfo > rm/Intel/MinPlatformPkg/Bds/Library/DxePlatformBootManagerLib/DxePlat > formBootManagerLib.inf > +!endif > + > + ReportFvLib|$(PROJECT)/Library/PeiReportFvLib/PeiReportFvLib.inf > + > TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib > Null/TestPointCheckLibNull.inf > + > + > CompressLib|$(PLATFORM_PACKAGE)/Library/CompressLib/CompressLib.in > f > + > + > PciSegmentInfoLib|$(PLATFORM_PACKAGE)/Pci/Library/PciSegmentInfoLibS > imple/PciSegmentInfoLibSimple.inf > + > AslUpdateLib|$(PLATFORM_PACKAGE)/Acpi/Library/DxeAslUpdateLib/DxeA > slUpdateLib.inf > + > + # > + # Board > + # > + > SiliconPolicyInitLib|$(PLATFORM_BOARD_PACKAGE)/Policy/Library/SiliconPo > licyInitLib/SiliconPolicyInitLib.inf > + > SiliconPolicyUpdateLib|$(PLATFORM_BOARD_PACKAGE)/Policy/Library/Silic > onPolicyUpdateLib/SiliconPolicyUpdateLib.inf > + > PlatformHookLib|$(PROJECT)/Library/BasePlatformHookLib/BasePlatformHo > okLib.inf > + > BoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/BoardInitLibNull/ > BoardInitLibNull.inf > + > +!if gIpmiFeaturePkgTokenSpaceGuid.PcdIpmiFeatureEnable =3D=3D TRUE > + > IpmiPlatformHookLib|$(PLATFORM_BOARD_PACKAGE)/Features/Ipmi/Libra > ry/IpmiPlatformHookLib/IpmiPlatformHookLib.inf > +!endif > + > +[LibraryClasses.IA32] > +!if $(TARGET) =3D=3D DEBUG > + > TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib > /PeiTestPointCheckLib.inf > +!endif > + > TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/PeiTestPoi > ntLib.inf > + > SetCacheMtrrLib|$(PLATFORM_PACKAGE)/Library/SetCacheMtrrLib/SetCac > heMtrrLib.inf > + > ReportCpuHobLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/ReportCpu > HobLib/ReportCpuHobLib.inf > +!if gIpmiFeaturePkgTokenSpaceGuid.PcdIpmiFeatureEnable =3D=3D TRUE > + > IpmiBaseLib|OutOfBandManagement/IpmiFeaturePkg/Library/PeiIpmiBaseL > ib/PeiIpmiBaseLib.inf > +!endif > + > +[LibraryClasses.X64] > + > BoardAcpiTableLib|$(PROJECT)/Library/BoardAcpiLib/DxeBoardAcpiTableLib.i > nf > +!if $(TARGET) =3D=3D DEBUG > + > TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib > /DxeTestPointCheckLib.inf > +!endif > + > TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/DxeTestPoi > ntLib.inf > + > BoardBootManagerLib|$(PLATFORM_PACKAGE)/Bds/Library/BoardBootMan > agerLibNull/BoardBootManagerLibNull.inf > + > BoardBdsHookLib|BoardModulePkg/Library/BoardBdsHookLib/BoardBdsHoo > kLib.inf > +!if gIpmiFeaturePkgTokenSpaceGuid.PcdIpmiFeatureEnable =3D=3D TRUE > + > IpmiBaseLib|OutOfBandManagement/IpmiFeaturePkg/Library/IpmiBaseLib/ > IpmiBaseLib.inf > +!endif > + > +[LibraryClasses.X64.DXE_SMM_DRIVER] > +!if $(TARGET) =3D=3D DEBUG > + > TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib > /SmmTestPointCheckLib.inf > +!endif > + > TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/SmmTestP > ointLib.inf > +!if gIpmiFeaturePkgTokenSpaceGuid.PcdIpmiFeatureEnable =3D=3D TRUE > + > IpmiBaseLib|OutOfBandManagement/IpmiFeaturePkg/Library/SmmIpmiBas > eLib/SmmIpmiBaseLib.inf > +!endif > + > +[Components.IA32] > + > + > $(PLATFORM_SI_BIN_PACKAGE)/FV/FvTempMemorySilicon/$(TARGET)/FvT > empMemorySilicon.inf > + > $(PLATFORM_SI_BIN_PACKAGE)/FV/FvPreMemorySilicon/$(TARGET)/FvPre > MemorySilicon.inf > + > $(PLATFORM_SI_BIN_PACKAGE)/FV/FvPostMemorySilicon/$(TARGET)/FvPo > stMemorySilicon.inf > + > + > $(PLATFORM_BOARD_PACKAGE)/Policy/SystemBoard/SystemBoardPei.inf > + > + $(PLATFORM_PACKAGE)/PlatformInit/ReportFv/ReportFvPei.inf > + > $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPreMem.i > nf { > + > + > BoardInitLib|$(PROJECT)/Library/BoardInitLib/PeiBoardInitPreMemLib.inf > + } > + > $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPostMem > .inf { > + > + > BoardInitLib|$(PROJECT)/Library/BoardInitLib/PeiBoardInitPostMemLib.inf > + } > + > $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMe > m.inf > + > $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPostM > em.inf > + > +[Components.X64] > + > + > $(PLATFORM_SI_BIN_PACKAGE)/FV/FvLateSilicon/$(TARGET)/FvLateSilicon.i > nf > + $(PLATFORM_SI_BIN_PACKAGE)/Microcode/Microcode.inf > + > + > $(PLATFORM_BOARD_PACKAGE)/Policy/IioUdsDataDxe/IioUdsDataDxe.inf > + > $(PLATFORM_BOARD_PACKAGE)/Policy/PlatformCpuPolicy/PlatformCpuPoli > cy.inf > + $(PLATFORM_BOARD_PACKAGE)/Pci/PciPlatform/PciPlatform.inf > + $(PLATFORM_BOARD_PACKAGE)/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf { > + > + MSFT:*_*_*_ASLCC_FLAGS =3D /D PURLEY_FLAG /D PCH_SPT > + GCC:*_*_*_ASLCC_FLAGS =3D -D PURLEY_FLAG -D PCH_SPT > + } > + > +# This is for prebuild only. No need to include in final FDF. > + $(PLATFORM_BOARD_PACKAGE)/Acpi/BoardAcpiDxe/Dsdt.inf { > + > + MSFT:*_*_*_ASLCC_FLAGS =3D /D PURLEY_FLAG /D PCH_SPT > + GCC:*_*_*_ASLCC_FLAGS =3D -D PURLEY_FLAG -D PCH_SPT > + } > + > + $(PLATFORM_PACKAGE)/Flash/SpiFvbService/SpiFvbServiceSmm.inf > + $(PLATFORM_PACKAGE)/Acpi/AcpiTables/AcpiPlatform.inf > + $(PLATFORM_PACKAGE)/Acpi/AcpiSmm/AcpiSmm.inf { > + > + > BoardAcpiEnableLib|$(PROJECT)/Library/BoardAcpiLib/SmmBoardAcpiEnable > Lib.inf > + } > + > + > $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf > + > $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitSmm/PlatformInitSmm.in > f > + > + $(PLATFORM_BOARD_PACKAGE)/Policy/S3NvramSave/S3NvramSave.inf > + BoardModulePkg/BoardBdsHookDxe/BoardBdsHookDxe.inf > + > + # > + # Shell > + # > + ShellPkg/Application/Shell/Shell.inf { > + > + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE > + > + > NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2Comma > ndsLib.inf > + > NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1Comma > ndsLib.inf > + > NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3Comma > ndsLib.inf > + > NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1Com > mandsLib.inf > + > NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1Com > mandsLib.inf > + > NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1Com > mandsLib.inf > + > NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1 > CommandsLib.inf > + > NULL|ShellPkg/Library/UefiShellNetwork2CommandsLib/UefiShellNetwork2 > CommandsLib.inf > + > ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellComma > ndLib.inf > + > HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingL > ib.inf > + > BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfg > CommandLib.inf > + ShellCEntryLib|ShellPkg/Library/UefiShellCEntryLib/UefiShellCEntryL= ib.inf > + ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf > + } > + > + MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf > + > +!if gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosFeatureEnable =3D=3D TRUE > + MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf > +!endif > diff --git > a/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/OpenBoardPkg.fdf > b/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/OpenBoardPkg.fdf > new file mode 100644 > index 0000000000..43cd8d94e1 > --- /dev/null > +++ > b/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/OpenBoardPkg.fdf > @@ -0,0 +1,600 @@ > +## @file > +# FDF file for the TiogaPass board. > +# > +# Copyright (c) 2018, Intel Corporation. All rights reserved.
> +# Copyright (c) 2021, American Megatrends International LLC.
> +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > +## > + > +[Defines] > + > +# Note: FlashNv PCD naming conventions are as follows: > +# Note: This should be 100% true of all PCD's in the > gCpPlatFlashTokenSpaceGuid space, and for > +# Others should be examined with an effort to work toward t= his > guideline. > +# PcdFlash*Base is an address, usually in the range of 0xf* of FD'= s, note > change in FDF spec > +# PcdFlash*Size is a hex count of the length of the FD or FV > +# All Fv will have the form 'PcdFlashFv', and all Fd will have the= form > 'PcdFlashFd' > +# > +# Also all values will have a PCD assigned so that they can be use= d in the > system, and > +# the FlashMap edit tool can be used to change the values here, wi= thout > effecting the code. > +# This requires all code to only use the PCD tokens to recover the= values. > + > +[FD.Platform] > +BaseAddress =3D 0xFF000000 | > gEfiPchTokenSpaceGuid.PcdFlashAreaBaseAddress > +Size =3D 0x01000000 | gEfiPchTokenSpaceGuid.PcdFlashAreaSiz= e > +ErasePolarity =3D 1 > +BlockSize =3D 0x10000 > +NumBlocks =3D 0x100 > + > +0x00000000|0x00500000 > +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase|gMinPlatform > PkgTokenSpaceGuid.PcdFlashFvAdvancedSize > +FV =3D FvAdvanced > + > +0x00500000|0x00100000 > +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityBase|gMinPlatformP > kgTokenSpaceGuid.PcdFlashFvSecuritySize > +FV =3D FvSecurity > + > +0x00600000|0x00100000 > +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootBase|gMinPlatformPk > gTokenSpaceGuid.PcdFlashFvOsBootSize > +FV =3D FvOsBoot > + > +0x00700000|0x00200000 > +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspUBase|gMinPlatformPkgT > okenSpaceGuid.PcdFlashFvFspUSize > +FV =3D FvLateSiliconCompressed > + > +0x00900000|0x00300000 > +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootBase|gMinPlatform > PkgTokenSpaceGuid.PcdFlashFvUefiBootSize > +FV =3D FvUefiBoot > + > +0x00C00000|0x0007C000 > +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfi > MdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize > +#NV_VARIABLE_STORE > +DATA =3D { > + ## This is the EFI_FIRMWARE_VOLUME_HEADER > + # ZeroVector [] > + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + # FileSystemGuid: gEfiSystemNvDataFvGuid =3D > + # { 0xFFF12B8D, 0x7696, 0x4C8B, { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B,= 0x4F, > 0x50 }} > + 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C, > + 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50, > + # FvLength: 0x100000 > + 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, > + #Signature "_FVH" #Attributes > + 0x5f, 0x46, 0x56, 0x48, 0xff, 0xfe, 0x04, 0x00, > + #HeaderLength #CheckSum #ExtHeaderOffset #Reserved #Revision > + 0x48, 0x00, 0x1A, 0x09, 0x00, 0x00, 0x00, 0x02, > + #Blockmap[0]: 16 Blocks * 0x10000 Bytes / Block > + 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, > + #Blockmap[1]: End > + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + ## This is the VARIABLE_STORE_HEADER > + !if gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable =3D=3D TRUE > + # Signature: gEfiAuthenticatedVariableGuid =3D { 0xaaf32c78, 0x947b, > 0x439a, { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 } } > + 0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43, > + 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92, > + !else > + # Signature: gEfiVariableGuid =3D { 0xddcf3616, 0x3275, 0x4164, { 0x= 98, 0xb6, > 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }} > + 0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41, > + 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d, > + !endif > + #Size: 0x7c000 > (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) - 0x48 > (size of EFI_FIRMWARE_VOLUME_HEADER) =3D 0x7BFFB8 > + # This can speed up the Variable Dispatch a bit. > + 0xB8, 0xBF, 0x07, 0x00, > + #FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: > UINT32 > + 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 > +} > + > +0x00C7C000|0x00002000 > +#NV_EVENT_LOG > + > +0x00C7E000|0x00002000 > +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|g > EfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize > +#NV_FTW_WORKING > +DATA =3D { > + # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature =3D > gEdkiiWorkingBlockSignatureGuid =3D > + # { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f,= 0x1b, > 0x95 }} > + 0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49, > + 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95, > + # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, R= eserved > + 0xE2, 0x33, 0xF2, 0x03, 0xFE, 0xFF, 0xFF, 0xFF, > + # WriteQueueSize: UINT64 > + 0xE0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 > +} > + > +0x00C80000|0x00080000 > +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfi > MdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize > +#NV_FTW_SPARE > + > + > +0x00D00000|0x00030000 > +gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeBase|gCpuUnc > oreTokenSpaceGuid.PcdFlashNvStorageMicrocodeSize > +FV =3D MICROCODE_FV > + > +0x00D30000|0x00010000 > +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase|gMinPlatf > ormPkgTokenSpaceGuid.PcdFlashFvPostMemorySize > +FV =3D FvPostMemory > + > +0x00D40000|0x00020000 > +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase|gMinPlatformPkgT > okenSpaceGuid.PcdFlashFvFspSSize > +FILE =3D > $(PLATFORM_SI_BIN_PACKAGE)/FV/FvPostMemorySilicon/$(TARGET)/FvPo > stMemorySilicon.Fv > + > +0x00D60000|0x00050000 > +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase|gMinPlatfor > mPkgTokenSpaceGuid.PcdFlashFvPreMemorySize > +FV =3D FvPreMemory > + > +0x00DB0000|0x00230000 > +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase|gMinPlatformPkg > TokenSpaceGuid.PcdFlashFvFspMSize > +FILE =3D > $(PLATFORM_SI_BIN_PACKAGE)/FV/FvPreMemorySilicon/$(TARGET)/FvPre > MemorySilicon.Fv > + > +0x00FE0000|0x00020000 > +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase|gMinPlatformPkgT > okenSpaceGuid.PcdFlashFvFspTSize > +FILE =3D > $(PLATFORM_SI_BIN_PACKAGE)/FV/FvTempMemorySilicon/$(TARGET)/FvT > empMemorySilicon.Fv > + > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase =3D > gEfiPchTokenSpaceGuid.PcdFlashAreaBaseAddress + > gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeBase > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize =3D > gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeSize > + > +SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress =3D > gEfiPchTokenSpaceGuid.PcdFlashAreaBaseAddress + > gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeBase + 0x60 > +SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =3D > gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeSize - 0x60 > + > +SET gEfiCpuTokenSpaceGuid.PcdCpuMicrocodePatchAddress =3D > gEfiPchTokenSpaceGuid.PcdFlashAreaBaseAddress + > gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeBase + 0x60 > +SET gEfiCpuTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =3D > gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeSize - 0x60 > + > +######################################################### > ####################### > +# > +# FV Section > +# > +# [FV] section is used to define what components or modules are placed > within a flash > +# device file. This section also defines order the components and modul= es > are positioned > +# within the image. The [FV] section consists of define statements, set > statements and > +# module statements. > +# > +######################################################### > ####################### > + > +[FV.FvLateSiliconCompressed] > +FvAlignment =3D 16 > +ERASE_POLARITY =3D 1 > +MEMORY_MAPPED =3D TRUE > +STICKY_WRITE =3D TRUE > +LOCK_CAP =3D TRUE > +LOCK_STATUS =3D TRUE > +WRITE_DISABLED_CAP =3D TRUE > +WRITE_ENABLED_CAP =3D TRUE > +WRITE_STATUS =3D TRUE > +WRITE_LOCK_CAP =3D TRUE > +WRITE_LOCK_STATUS =3D TRUE > +READ_DISABLED_CAP =3D TRUE > +READ_ENABLED_CAP =3D TRUE > +READ_STATUS =3D TRUE > +READ_LOCK_CAP =3D TRUE > +READ_LOCK_STATUS =3D TRUE > +FvNameGuid =3D BA793112-EA2E-47C4-9AFE-A8FCFE603D6D > + > +FILE FV_IMAGE =3D A626BB34-2455-4FCA-8DFB-FEE96DB0DC5F { > + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF > PROCESSING_REQUIRED =3D TRUE { > + SECTION FV_IMAGE =3D > $(PLATFORM_SI_BIN_PACKAGE)/FV/FvLateSilicon/$(TARGET)/FvLateSilicon. > Fv > + } > + } > + > +[FV.MICROCODE_FV] > +FvAlignment =3D 16 > +ERASE_POLARITY =3D 1 > +MEMORY_MAPPED =3D TRUE > +STICKY_WRITE =3D TRUE > +LOCK_CAP =3D TRUE > +LOCK_STATUS =3D FALSE > +WRITE_DISABLED_CAP =3D TRUE > +WRITE_ENABLED_CAP =3D TRUE > +WRITE_STATUS =3D TRUE > +WRITE_LOCK_CAP =3D TRUE > +WRITE_LOCK_STATUS =3D TRUE > +READ_DISABLED_CAP =3D TRUE > +READ_ENABLED_CAP =3D TRUE > +READ_STATUS =3D TRUE > +READ_LOCK_CAP =3D TRUE > +READ_LOCK_STATUS =3D TRUE > + > +INF RuleOverride =3D MICROCODE > $(PLATFORM_SI_BIN_PACKAGE)/Microcode/Microcode.inf > + > +[FV.FvPreMemory] > +FvAlignment =3D 16 > +FvForceRebase =3D TRUE > +ERASE_POLARITY =3D 1 > +MEMORY_MAPPED =3D TRUE > +STICKY_WRITE =3D TRUE > +LOCK_CAP =3D TRUE > +LOCK_STATUS =3D TRUE > +WRITE_DISABLED_CAP =3D TRUE > +WRITE_ENABLED_CAP =3D TRUE > +WRITE_STATUS =3D TRUE > +WRITE_LOCK_CAP =3D TRUE > +WRITE_LOCK_STATUS =3D TRUE > +READ_DISABLED_CAP =3D TRUE > +READ_ENABLED_CAP =3D TRUE > +READ_STATUS =3D TRUE > +READ_LOCK_CAP =3D TRUE > +READ_LOCK_STATUS =3D TRUE > +FvNameGuid =3D 6522280D-28F9-4131-ADC4-F40EBFA45864 > + > + ## > + # PEI Apriori file example, more PEIM module added later. > + ## > +INF MdeModulePkg/Core/Pei/PeiMain.inf > + > +!include $(PLATFORM_PACKAGE)/Include/Fdf/CorePreMemoryInclude.fdf > + > +INF > $(PLATFORM_BOARD_PACKAGE)/Policy/SystemBoard/SystemBoardPei.inf > + > +INF $(PLATFORM_PACKAGE)/PlatformInit/ReportFv/ReportFvPei.inf > +INF > $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPreMem.i > nf > +INF > $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMe > m.inf > + > +[FV.FvPostMemory] > +FvAlignment =3D 16 > +ERASE_POLARITY =3D 1 > +MEMORY_MAPPED =3D TRUE > +STICKY_WRITE =3D TRUE > +LOCK_CAP =3D TRUE > +LOCK_STATUS =3D TRUE > +WRITE_DISABLED_CAP =3D TRUE > +WRITE_ENABLED_CAP =3D TRUE > +WRITE_STATUS =3D TRUE > +WRITE_LOCK_CAP =3D TRUE > +WRITE_LOCK_STATUS =3D TRUE > +READ_DISABLED_CAP =3D TRUE > +READ_ENABLED_CAP =3D TRUE > +READ_STATUS =3D TRUE > +READ_LOCK_CAP =3D TRUE > +READ_LOCK_STATUS =3D TRUE > +FvNameGuid =3D C54E3E8D-9FF5-4D52-AF03-58018EB55F63 > + > +!include > $(PLATFORM_PACKAGE)/Include/Fdf/CorePostMemoryInclude.fdf > + > +INF > $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPostMem > .inf > +INF > $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPostM > em.inf > + > +[FV.FvUefiBootUncompact] > +BlockSize =3D 0x10000 > +FvAlignment =3D 16 > +ERASE_POLARITY =3D 1 > +MEMORY_MAPPED =3D TRUE > +STICKY_WRITE =3D TRUE > +LOCK_CAP =3D TRUE > +LOCK_STATUS =3D TRUE > +WRITE_DISABLED_CAP =3D TRUE > +WRITE_ENABLED_CAP =3D TRUE > +WRITE_STATUS =3D TRUE > +WRITE_LOCK_CAP =3D TRUE > +WRITE_LOCK_STATUS =3D TRUE > +READ_DISABLED_CAP =3D TRUE > +READ_ENABLED_CAP =3D TRUE > +READ_STATUS =3D TRUE > +READ_LOCK_CAP =3D TRUE > +READ_LOCK_STATUS =3D TRUE > +FvNameGuid =3D CDBB7B35-6833-4ed6-9AB2-57D2ACDDF6F0 > + > + ## > + # DXE Phase modules > + ## > + > + ## > + # DXE Apriori file example, more DXE module added later. > + ## > + > +#TiogaPass Override START : Added Board Specific changes in core drivers > +#!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreUefiBootInclude.fdf > +!include CoreUefiBootInclude.fdf > +#TiogaPass Override END > + > +INF PurleyOpenBoardPkg/Policy/S3NvramSave/S3NvramSave.inf > + > +INF > $(PLATFORM_BOARD_PACKAGE)/Policy/IioUdsDataDxe/IioUdsDataDxe.inf > +INF > $(PLATFORM_BOARD_PACKAGE)/Policy/PlatformCpuPolicy/PlatformCpuPoli > cy.inf > +INF $(PLATFORM_BOARD_PACKAGE)/Pci/PciPlatform/PciPlatform.inf > + > +INF > $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf > +INF BoardModulePkg/BoardBdsHookDxe/BoardBdsHookDxe.inf > +INF ShellPkg/Application/Shell/Shell.inf > + > +FILE DRIVER =3D db90bb7e-e4ba-4f07-96d6-b7076713bd2c { > + SECTION PE32 =3D edk2-non- > osi/Drivers/ASpeed/ASpeedGopBinPkg/X64/ASpeedAst2500Gop.efi > + } > + > +INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf > + > + > +[FV.FvUefiBoot] > +FvAlignment =3D 16 > +ERASE_POLARITY =3D 1 > +MEMORY_MAPPED =3D TRUE > +STICKY_WRITE =3D TRUE > +LOCK_CAP =3D TRUE > +LOCK_STATUS =3D TRUE > +WRITE_DISABLED_CAP =3D TRUE > +WRITE_ENABLED_CAP =3D TRUE > +WRITE_STATUS =3D TRUE > +WRITE_LOCK_CAP =3D TRUE > +WRITE_LOCK_STATUS =3D TRUE > +READ_DISABLED_CAP =3D TRUE > +READ_ENABLED_CAP =3D TRUE > +READ_STATUS =3D TRUE > +READ_LOCK_CAP =3D TRUE > +READ_LOCK_STATUS =3D TRUE > +FvNameGuid =3D 27A72E80-3118-4c0c-8673-AA5B4EFA9613 > + > +FILE FV_IMAGE =3D 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { > + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF > PROCESSING_REQUIRED =3D TRUE { > + SECTION FV_IMAGE =3D FvUefiBootUncompact > + } > + } > + > +[FV.FvOsBootUncompact] > +FvAlignment =3D 16 > +ERASE_POLARITY =3D 1 > +MEMORY_MAPPED =3D TRUE > +STICKY_WRITE =3D TRUE > +LOCK_CAP =3D TRUE > +LOCK_STATUS =3D TRUE > +WRITE_DISABLED_CAP =3D TRUE > +WRITE_ENABLED_CAP =3D TRUE > +WRITE_STATUS =3D TRUE > +WRITE_LOCK_CAP =3D TRUE > +WRITE_LOCK_STATUS =3D TRUE > +READ_DISABLED_CAP =3D TRUE > +READ_ENABLED_CAP =3D TRUE > +READ_STATUS =3D TRUE > +READ_LOCK_CAP =3D TRUE > +READ_LOCK_STATUS =3D TRUE > +FvNameGuid =3D 5AB52883-85DF-445B-99F7-E0C1D517A905 > + > +!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreOsBootInclude.fdf > + > +INF $(PLATFORM_PACKAGE)/Flash/SpiFvbService/SpiFvbServiceSmm.inf > +INF $(PLATFORM_PACKAGE)/Acpi/AcpiTables/AcpiPlatform.inf > +INF $(PLATFORM_PACKAGE)/Acpi/AcpiSmm/AcpiSmm.inf > + > +INF RuleOverride =3D DRIVER_ACPITABLE > $(PLATFORM_BOARD_PACKAGE)/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf > + > +INF > $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitSmm/PlatformInitSmm.in > f > + > +[FV.FvOsBoot] > +FvAlignment =3D 16 > +ERASE_POLARITY =3D 1 > +MEMORY_MAPPED =3D TRUE > +STICKY_WRITE =3D TRUE > +LOCK_CAP =3D TRUE > +LOCK_STATUS =3D TRUE > +WRITE_DISABLED_CAP =3D TRUE > +WRITE_ENABLED_CAP =3D TRUE > +WRITE_STATUS =3D TRUE > +WRITE_LOCK_CAP =3D TRUE > +WRITE_LOCK_STATUS =3D TRUE > +READ_DISABLED_CAP =3D TRUE > +READ_ENABLED_CAP =3D TRUE > +READ_STATUS =3D TRUE > +READ_LOCK_CAP =3D TRUE > +READ_LOCK_STATUS =3D TRUE > +FvNameGuid =3D 5e2363c4-3e9e-4203-b873-bb40df46c8e6 > + > +FILE FV_IMAGE =3D AC09A11F-BD9F-4C87-B656-F4868EEA89B8 { > + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF > PROCESSING_REQUIRED =3D TRUE { > + SECTION FV_IMAGE =3D FvOsBootUncompact > + } > + } > + > +[FV.FvSecurityPreMem] > +FvAlignment =3D 16 > +ERASE_POLARITY =3D 1 > +MEMORY_MAPPED =3D TRUE > +STICKY_WRITE =3D TRUE > +LOCK_CAP =3D TRUE > +LOCK_STATUS =3D TRUE > +WRITE_DISABLED_CAP =3D TRUE > +WRITE_ENABLED_CAP =3D TRUE > +WRITE_STATUS =3D TRUE > +WRITE_LOCK_CAP =3D TRUE > +WRITE_LOCK_STATUS =3D TRUE > +READ_DISABLED_CAP =3D TRUE > +READ_ENABLED_CAP =3D TRUE > +READ_STATUS =3D TRUE > +READ_LOCK_CAP =3D TRUE > +READ_LOCK_STATUS =3D TRUE > +FvNameGuid =3D A91F91A0-0CCD-4E1C-9FD8-4DAE39F348FA > + > +!include > $(PLATFORM_PACKAGE)/Include/Fdf/CoreSecurityPreMemoryInclude.fdf > + > +[FV.FvSecurityPostMem] > +FvAlignment =3D 16 > +ERASE_POLARITY =3D 1 > +MEMORY_MAPPED =3D TRUE > +STICKY_WRITE =3D TRUE > +LOCK_CAP =3D TRUE > +LOCK_STATUS =3D TRUE > +WRITE_DISABLED_CAP =3D TRUE > +WRITE_ENABLED_CAP =3D TRUE > +WRITE_STATUS =3D TRUE > +WRITE_LOCK_CAP =3D TRUE > +WRITE_LOCK_STATUS =3D TRUE > +READ_DISABLED_CAP =3D TRUE > +READ_ENABLED_CAP =3D TRUE > +READ_STATUS =3D TRUE > +READ_LOCK_CAP =3D TRUE > +READ_LOCK_STATUS =3D TRUE > +FvNameGuid =3D 04B00029-2391-44C1-97BA-3FA8A42E9D3A > + > +!include > $(PLATFORM_PACKAGE)/Include/Fdf/CoreSecurityPostMemoryInclude.fdf > + > +!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable =3D=3D TRUE > +INF $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformPei/Tcg2PlatformPei.inf > +!endif > + > +[FV.FvSecurityLate] > +FvAlignment =3D 16 > +ERASE_POLARITY =3D 1 > +MEMORY_MAPPED =3D TRUE > +STICKY_WRITE =3D TRUE > +LOCK_CAP =3D TRUE > +LOCK_STATUS =3D TRUE > +WRITE_DISABLED_CAP =3D TRUE > +WRITE_ENABLED_CAP =3D TRUE > +WRITE_STATUS =3D TRUE > +WRITE_LOCK_CAP =3D TRUE > +WRITE_LOCK_STATUS =3D TRUE > +READ_DISABLED_CAP =3D TRUE > +READ_ENABLED_CAP =3D TRUE > +READ_STATUS =3D TRUE > +READ_LOCK_CAP =3D TRUE > +READ_LOCK_STATUS =3D TRUE > +FvNameGuid =3D CCBC50ED-0902-413E-BC2C-409C906F4A80 > + > +!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreSecurityLateInclude.fdf > + > +!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable =3D=3D TRUE > +INF $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.inf > +!endif > + > +[FV.FvSecurity] > +FvAlignment =3D 16 > +ERASE_POLARITY =3D 1 > +MEMORY_MAPPED =3D TRUE > +STICKY_WRITE =3D TRUE > +LOCK_CAP =3D TRUE > +LOCK_STATUS =3D TRUE > +WRITE_DISABLED_CAP =3D TRUE > +WRITE_ENABLED_CAP =3D TRUE > +WRITE_STATUS =3D TRUE > +WRITE_LOCK_CAP =3D TRUE > +WRITE_LOCK_STATUS =3D TRUE > +READ_DISABLED_CAP =3D TRUE > +READ_ENABLED_CAP =3D TRUE > +READ_STATUS =3D TRUE > +READ_LOCK_CAP =3D TRUE > +READ_LOCK_STATUS =3D TRUE > +FvNameGuid =3D 8CBBA80C-FE21-4749-B015-6EDFC34B6BE7 > + > +FILE FV_IMAGE =3D A63B2BBF-7A02-4862-BF22-A1BA5258DD68 { > + SECTION FV_IMAGE =3D FvSecurityPreMem > + } > + > +FILE FV_IMAGE =3D 47B40638-0087-4938-97CF-B56983A1A07B { > + SECTION FV_IMAGE =3D FvSecurityPostMem > + } > + > +FILE FV_IMAGE =3D 605CBDF4-61DB-4B77-BAED-65232B8EC6D6 { > + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF > PROCESSING_REQUIRED =3D TRUE { > + SECTION FV_IMAGE =3D FvSecurityLate > + } > + } > + > +[FV.FvAdvancedPreMem] > +FvAlignment =3D 16 > +ERASE_POLARITY =3D 1 > +MEMORY_MAPPED =3D TRUE > +STICKY_WRITE =3D TRUE > +LOCK_CAP =3D TRUE > +LOCK_STATUS =3D TRUE > +WRITE_DISABLED_CAP =3D TRUE > +WRITE_ENABLED_CAP =3D TRUE > +WRITE_STATUS =3D TRUE > +WRITE_LOCK_CAP =3D TRUE > +WRITE_LOCK_STATUS =3D TRUE > +READ_DISABLED_CAP =3D TRUE > +READ_ENABLED_CAP =3D TRUE > +READ_STATUS =3D TRUE > +READ_LOCK_CAP =3D TRUE > +READ_LOCK_STATUS =3D TRUE > +FvNameGuid =3D EBC45843-B180-44D3-A485-0031A75DB16D > + > +!include AdvancedFeaturePkg/Include/PreMemory.fdf > + > +[FV.FvAdvancedUncompact] > +FvAlignment =3D 16 > +ERASE_POLARITY =3D 1 > +MEMORY_MAPPED =3D TRUE > +STICKY_WRITE =3D TRUE > +LOCK_CAP =3D TRUE > +LOCK_STATUS =3D TRUE > +WRITE_DISABLED_CAP =3D TRUE > +WRITE_ENABLED_CAP =3D TRUE > +WRITE_STATUS =3D TRUE > +WRITE_LOCK_CAP =3D TRUE > +WRITE_LOCK_STATUS =3D TRUE > +READ_DISABLED_CAP =3D TRUE > +READ_ENABLED_CAP =3D TRUE > +READ_STATUS =3D TRUE > +READ_LOCK_CAP =3D TRUE > +READ_LOCK_STATUS =3D TRUE > +FvNameGuid =3D 05411CAD-6C35-4675-B6CA-8748032144B4 > + > +!include AdvancedFeaturePkg/Include/PostMemory.fdf > + > +!if gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosFeatureEnable =3D=3D TRUE > +INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf > +!endif > + > +[FV.FvAdvanced] > +FvAlignment =3D 16 > +ERASE_POLARITY =3D 1 > +MEMORY_MAPPED =3D TRUE > +STICKY_WRITE =3D TRUE > +LOCK_CAP =3D TRUE > +LOCK_STATUS =3D TRUE > +WRITE_DISABLED_CAP =3D TRUE > +WRITE_ENABLED_CAP =3D TRUE > +WRITE_STATUS =3D TRUE > +WRITE_LOCK_CAP =3D TRUE > +WRITE_LOCK_STATUS =3D TRUE > +READ_DISABLED_CAP =3D TRUE > +READ_ENABLED_CAP =3D TRUE > +READ_STATUS =3D TRUE > +READ_LOCK_CAP =3D TRUE > +READ_LOCK_STATUS =3D TRUE > +FvNameGuid =3D 59584CB6-0740-4EE6-A335-A46B370A101A > + > +FILE FV_IMAGE =3D 0112F63C-E0EA-4CA7-BFAA-9574DB03B230 { > + SECTION FV_IMAGE =3D FvAdvancedPreMem > + } > + > +FILE FV_IMAGE =3D 07FC4960-5322-4DDC-A6A4-A17DE492DFE3 { > + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF > PROCESSING_REQUIRED =3D TRUE { > + SECTION FV_IMAGE =3D FvAdvancedUncompact > + } > + } > + > +[FV.FvDummy] > +FvAlignment =3D 16 > +FvForceRebase =3D FALSE > +ERASE_POLARITY =3D 1 > +MEMORY_MAPPED =3D TRUE > +STICKY_WRITE =3D TRUE > +LOCK_CAP =3D TRUE > +LOCK_STATUS =3D TRUE > +WRITE_DISABLED_CAP =3D TRUE > +WRITE_ENABLED_CAP =3D TRUE > +WRITE_STATUS =3D TRUE > +WRITE_LOCK_CAP =3D TRUE > +WRITE_LOCK_STATUS =3D TRUE > +READ_DISABLED_CAP =3D TRUE > +READ_ENABLED_CAP =3D TRUE > +READ_STATUS =3D TRUE > +READ_LOCK_CAP =3D TRUE > +READ_LOCK_STATUS =3D TRUE > + > +# Add dummy FV here to build the PCD in FV into PCD database. > +INF RuleOverride =3D BIN_FV > $(PLATFORM_SI_BIN_PACKAGE)/FV/FvTempMemorySilicon/$(TARGET)/FvT > empMemorySilicon.inf > +INF RuleOverride =3D BIN_FV > $(PLATFORM_SI_BIN_PACKAGE)/FV/FvPreMemorySilicon/$(TARGET)/FvPre > MemorySilicon.inf > +INF RuleOverride =3D BIN_FV > $(PLATFORM_SI_BIN_PACKAGE)/FV/FvPostMemorySilicon/$(TARGET)/FvPo > stMemorySilicon.inf > +INF RuleOverride =3D BIN_FV > $(PLATFORM_SI_BIN_PACKAGE)/FV/FvLateSilicon/$(TARGET)/FvLateSilicon.i > nf > + > + > +######################################################### > ####################### > +# > +# Rules are use with the [FV] section's module INF type to define > +# how an FFS file is created for a given INF file. The following Rule ar= e the > default > +# rules for the different module type. User can add the customized rules= to > define the > +# content of the FFS file. > +# > +######################################################### > ####################### > + > +!include $(PLATFORM_PACKAGE)/Include/Fdf/RuleInclude.fdf > diff --git > a/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/PlatformPkgBuildOp > tion.dsc > b/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/PlatformPkgBuildOp > tion.dsc > new file mode 100644 > index 0000000000..a445e3fd8e > --- /dev/null > +++ > b/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/PlatformPkgBuildOp > tion.dsc > @@ -0,0 +1,84 @@ > +## @file > +# > +# Copyright (c) 2018, Intel Corporation. All rights reserved.
> +# Copyright (c) 2021, American Megatrends International LLC.
> +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > +## > + > +[BuildOptions.Common.EDKII] > +# Append build options for EDK and EDKII drivers (=3D is Append, =3D=3D = is > Replace) > + > + DEFINE CRB_EDKII_BUILD_OPTIONS =3D -D CRB_FLAG > + DEFINE EDKII_CPU_BUILD_OPTIONS =3D -D PURLEY_FLAG > + DEFINE TRAD_BUILD_OPTION =3D -D TRAD_FLAG=3D1 > + DEFINE SUS_WELL_RESTORE_BUILD_OPTION =3D -D SUS_WELL_RESTORE=3D1 > + DEFINE PCH_BUILD_OPTION =3D -D PCH_SERVER_BIOS_FLAG=3D1 > + DEFINE SERVER_BUILD_OPTION =3D -D SERVER_BIOS_FLAG=3D1 > + DEFINE PCH_PKG_OPTIONS =3D -D PCH_SPT > + DEFINE MAX_SOCKET_OPTIONS =3D -D MAX_SOCKET=3D2 > + > + DEFINE EDKII_ALL_PPO_OPTIONS =3D $(EDKII_CPU_BUILD_OPTIONS) > + DEFINE PCH_BIOS_BUILD_OPTIONS =3D $(TRAD_BUILD_OPTION) > $(ULT_BUILD_OPTION) $(PCH_BUILD_OPTION) > $(SUS_WELL_RESTORE_BUILD_OPTION) $(SERVER_BUILD_OPTION) > + DEFINE EDKII_DSC_FEATURE_BUILD_OPTIONS =3D > $(CRB_EDKII_BUILD_OPTIONS) $(PCH_BIOS_BUILD_OPTIONS) > $(PCH_PKG_OPTIONS) $(EDKII_ALL_PPO_OPTIONS) > $(SPARING_SCRATCHPAD_OPTION) > $(TRACE_HUB_DEBUG_BUILD_OPTIONS) > $(TRACE_HUB_INIT_BUILD_OPTIONS) $(MAX_SOCKET_OPTIONS) -D > EFI_PCI_IOV_SUPPORT -D WHEA_SUPPORT -D SKX_HOST -D CLX_HOST > + > +!if $(TARGET) =3D=3D "DEBUG" > + DEFINE DEBUG_BUILD_FLAG =3D -D SERIAL_DBG_MSG=3D1 > +!else > + DEFINE DEBUG_BUILD_FLAG =3D -D MDEPKG_NDEBUG -D SILENT_MODE > +!endif > + > + DEFINE EDKII_DSC_FEATURE_BUILD_OPTIONS =3D > $(EDKII_DSC_FEATURE_BUILD_OPTIONS) $(DEBUG_BUILD_FLAG) > +# > +# PC_BUILD_END > +# > + > + > + DEFINE EDKII_DSC_FEATURE_BUILD_OPTIONS =3D > $(EDKII_DSC_FEATURE_BUILD_OPTIONS) > + > + > + *_*_*_CC_FLAGS =3D $(EDKII_DSC_FEATURE_BUILD_OPTIONS) > + *_*_*_VFRPP_FLAGS =3D $(EDKII_DSC_FEATURE_BUILD_OPTIONS) > + *_*_*_APP_FLAGS =3D $(EDKII_DSC_FEATURE_BUILD_OPTIONS) > + *_*_*_PP_FLAGS =3D $(EDKII_DSC_FEATURE_BUILD_OPTIONS) > + *_*_*_ASLPP_FLAGS =3D $(EDKII_DSC_FEATURE_BUILD_OPTIONS) > + *_*_*_ASLCC_FLAGS =3D $(EDKII_DSC_FEATURE_BUILD_OPTIONS) > + > + > +# > +# Enable source level debugging for RELEASE build > +# > +!if $(TARGET) =3D=3D "RELEASE" > + DEFINE EDKII_RELEASE_SRCDBG_ASM_BUILD_OPTIONS =3D /Zi > + DEFINE EDKII_RELEASE_SRCDBG_CC_BUILD_OPTIONS =3D /Zi /Gm > + DEFINE EDKII_RELEASE_SRCDBG_DLINK_BUILD_OPTIONS =3D /DEBUG > + > + MSFT:*_*_*_ASM_FLAGS =3D > $(EDKII_RELEASE_SRCDBG_ASM_BUILD_OPTIONS) > + MSFT:*_*_*_CC_FLAGS =3D > $(EDKII_RELEASE_SRCDBG_CC_BUILD_OPTIONS) > + MSFT:*_*_*_DLINK_FLAGS =3D > $(EDKII_RELEASE_SRCDBG_DLINK_BUILD_OPTIONS) > +!endif > + > + > +# > +# Override the existing iasl path in tools_def.template > +# > +# MSFT:*_*_*_ASL_PATH =3D=3D c:/Iasl/iasl.exe > + > +# > +# Override the VFR compile flags to speed the build time > +# > + > +*_*_*_VFR_FLAGS =3D=3D -n > + > +# Force PE/COFF sections to be aligned at 4KB boundaries to support page > level protection > +[BuildOptions.common.EDKII.DXE_SMM_DRIVER, > BuildOptions.common.EDKII.SMM_CORE] > + MSFT:*_*_*_DLINK_FLAGS =3D /ALIGN:4096 > + GCC:*_*_*_DLINK_FLAGS =3D -z common-page-size=3D0x1000 > + > +# Force PE/COFF sections to be aligned at 4KB boundaries to support > MemoryAttribute table > +[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER] > + MSFT:*_*_*_DLINK_FLAGS =3D /ALIGN:4096 > + GCC:*_*_*_DLINK_FLAGS =3D -z common-page-size=3D0x1000 > + > +[BuildOptions] > +!include NetworkPkg/NetworkBuildOptions.dsc.inc > \ No newline at end of file > diff --git > a/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/PlatformPkgConfig.d > sc > b/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/PlatformPkgConfig. > dsc > new file mode 100644 > index 0000000000..36a29c8d68 > --- /dev/null > +++ > b/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/PlatformPkgConfig. > dsc > @@ -0,0 +1,58 @@ > +## @file > +# > +# Copyright (c) 2018, Intel Corporation. All rights reserved.
> +# Copyright (c) 2021, American Megatrends International LLC.
> +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > +## > + > +# > +# TRUE is ENABLE. FALSE is DISABLE. > +# > + > +[PcdsFixedAtBuild] > + gMinPlatformPkgTokenSpaceGuid.PcdBootStage|4 > + > +[PcdsFeatureFlag] > + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE > + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE > + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE > + gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|FALSE > + gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|FALSE > + > +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 1 > + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|TRUE > +!endif > + > +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 2 > + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE > + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|TRUE > +!endif > + > +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 3 > + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE > + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|TRUE > +!endif > + > +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 4 > + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE > +!endif > + > +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 5 > + gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|TRUE > + gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|TRUE > +!endif > + > + !if $(TARGET) =3D=3D DEBUG > + gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|TRUE > + !else > + gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|FALSE > + !endif > + > + gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable|TRUE > + > + gPlatformTokenSpaceGuid.PcdFastBoot|FALSE > +!if gPlatformTokenSpaceGuid.PcdFastBoot =3D=3D TRUE > + gIpmiFeaturePkgTokenSpaceGuid.PcdIpmiFeatureEnable|FALSE > + gPlatformTokenSpaceGuid.PcdUpdateConsoleInBds|FALSE > +!endif > \ No newline at end of file > diff --git > a/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/PlatformPkgPcd.dsc > b/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/PlatformPkgPcd.dsc > new file mode 100644 > index 0000000000..e4a330b98e > --- /dev/null > +++ > b/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/PlatformPkgPcd.dsc > @@ -0,0 +1,392 @@ > +## @file > +# > +# Copyright (c) 2018, Intel Corporation. All rights reserved.
> +# Copyright (c) 2021, American Megatrends International LLC.
> +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > +## > + > +######################################################### > ####################### > +# > +# Pcd Section - list of all PCD Entries defined by this board. > +# > +######################################################### > ####################### > + > +[PcdsFixedAtBuild.common] > + ###################################### > + # Key Boot Stage and FSP configuration > + ###################################### > + # > + # Please select the Boot Stage here. > + # Stage 1 - enable debug (system deadloop after debug init) > + # Stage 2 - mem init (system deadloop after mem init) > + # Stage 3 - boot to shell only > + # Stage 4 - boot to OS > + # Stage 5 - boot to OS with security boot enabled > + # Stage 6 - boot with advanced features enabled > + # > + gMinPlatformPkgTokenSpaceGuid.PcdBootStage|4 > + > +[PcdsFeatureFlag.common] > + gPlatformTokenSpaceGuid.PcdLockCsrSsidSvidRegister|FALSE > + # Server doesn't support capsle update on Reset. > + > gEfiMdeModulePkgTokenSpaceGuid.PcdSupportUpdateCapsuleReset|FALS > E > + gEfiCpuTokenSpaceGuid.PcdCpuSmmEnableBspElection|TRUE > + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection|TRUE > + gEfiCpuTokenSpaceGuid.PcdCpuHotPlugSupport|TRUE > + gUefiCpuPkgTokenSpaceGuid.PcdCpuHotPlugSupport|TRUE > + > gEfiMdeModulePkgTokenSpaceGuid.PcdPciBusHotplugDeviceSupport|FALSE > + > +#S3 add > + gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode|TRUE > +#S3 add > + > + gEfiCpuTokenSpaceGuid.PcdCpuConroeFamilyFlag|FALSE > + gEfiCpuTokenSpaceGuid.PcdCpuCedarMillFamilyFlag|FALSE > + gEfiCpuTokenSpaceGuid.PcdCpuPrescottFamilyFlag|FALSE > + gEfiCpuTokenSpaceGuid.PcdCpuNehalemFamilyFlag|FALSE > + gEfiCpuTokenSpaceGuid.PcdCpuIvyBridgeFamilyFlag|FALSE > + gEfiCpuTokenSpaceGuid.PcdCpuSandyBridgeFamilyFlag|FALSE > + gEfiCpuTokenSpaceGuid.PcdCpuHaswellFamilyFlag|TRUE > + gEfiCpuTokenSpaceGuid.PcdCpuSkylakeFamilyFlag|TRUE > + > + gEfiCpuTokenSpaceGuid.PcdCpuGateA20MDisableFlag|FALSE > + gEfiCpuTokenSpaceGuid.PcdCpuSmmDebug|TRUE > + gEfiCpuTokenSpaceGuid.PcdCpuSelectLfpAsBspFlag|TRUE > + gEfiCpuTokenSpaceGuid.PcdCpuSocketIdReassignmentFlag|TRUE > + > + ## This PCD specified whether ACPI SDT protocol is installed. > + gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE > + > + ###################################### > + # Platform Configuration > + ###################################### > + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE > + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE > + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE > + gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable|TRUE > + gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|FALSE > + gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|FALSE > + gMinPlatformPkgTokenSpaceGuid.PcdSerialTerminalEnable|FALSE > + > +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 1 > + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|TRUE > +!endif > + > +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 2 > + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE > + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|TRUE > +!endif > + > +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 3 > + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE > + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|TRUE > +!endif > + > +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 4 > + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE > +!endif > + > +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 5 > + gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|TRUE > + gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|TRUE > +!endif > + > +!if $(TARGET) =3D=3D DEBUG > + gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|TRUE > +!else > + gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|FALSE > +!endif > + > +[PcdsFeatureFlag.X64] > + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackGuard|FALSE > + > +[PcdsFeatureFlag] > + > gEfiMdeModulePkgTokenSpaceGuid.PcdBrowerGrayOutReadOnlyMenu|TR > UE > + gNetworkFeaturePkgTokenSpaceGuid.PcdNetworkFeatureEnable|TRUE > + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosFeatureEnable|TRUE > + gIpmiFeaturePkgTokenSpaceGuid.PcdIpmiFeatureEnable|TRUE > + > +[PcdsDynamicExDefault] > +!include $(PROJECT)/StructureConfig.dsc > + > +[PcdsFixedAtBuild.X64] > + > gMinPlatformPkgTokenSpaceGuid.PcdTrustedConsoleOutputDevicePath|{0x > 02, 0x01, 0x0C, 0x00, 0xd0, 0x41, 0x03, 0x0A, 0x01, 0x00, 0x00, 0x00, 0x0= 1, > 0x01, 0x06, 0x00, 0x00, 0x01, 0x01, 0x01, 0x06, 0x00, 0x00, 0x01, 0x7F,= 0xFF, > 0x04, 0x00} > + > +[PcdsFixedAtBuild.IA32] > + > gCpuUncoreTokenSpaceGuid.PcdFlashSecCacheRegionBase|0x00FFA00000 > + gCpuUncoreTokenSpaceGuid.PcdFlashSecCacheRegionSize|0x0000600000 > + > +[PcdsFixedAtBuild.common] > + > gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationC > hange|TRUE > +!if $(TARGET) =3D=3D "RELEASE" > + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0 > + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x03 > +!else > + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F > + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07 > +!endif > +!if $(TARGET) =3D=3D RELEASE > + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE > +!else > + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE > +!endif > + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07 > + > gEfiMdeModulePkgTokenSpaceGuid.PcdLoadModuleAtFixAddressEnable|0 > + gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x0 > +#S3 modified > + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x10000 > + gEfiMdeModulePkgTokenSpaceGuid.PcdShadowPeimOnS3Boot|TRUE > +#S3 modified > + > + gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x0 > + gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x0 > + gEfiMdePkgTokenSpaceGuid.PcdFSBClock|133333333 > + > gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreMaxPeiStackSize|0x100000 > + > gEfiMdeModulePkgTokenSpaceGuid.PcdMaxSizeNonPopulateCapsule|0x17 > 00000 > + > + gEfiCpuTokenSpaceGuid.PcdCpuIEDRamSize|0x400000 > + gEfiCpuTokenSpaceGuid.PcdCpuSmmApSyncTimeout|10000 > + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|10000 > + gEfiCpuTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|512 > + gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|512 > + gEfiCpuTokenSpaceGuid.PcdPlatformType|2 > + gEfiCpuTokenSpaceGuid.PcdPlatformCpuMaxCoreFrequency|4000 > + gEfiCpuTokenSpaceGuid.PcdPlatformCpuMaxFsbFrequency|1066 > + gEfiCpuTokenSpaceGuid.PcdCpuSmmStackSize|0x10000 > + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x10000 > + > + ## Specifies delay value in microseconds after sending out an INIT IPI= . > + # @Prompt Configure delay value after send an INIT IPI > + gUefiCpuPkgTokenSpaceGuid.PcdCpuInitIpiDelayInMicroSeconds|10 > + > + ## Specifies max supported number of Logical Processors. > + # @Prompt Configure max supported number of Logical Processorss > + gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|512 > + gUefiCpuPkgTokenSpaceGuid.PcdCpuApStackSize|0x1000 > +!if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable =3D=3D TRUE > + gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x1 > +!endif > + > + gPlatformTokenSpaceGuid.PcdBusStack|0x06 > + gPlatformTokenSpaceGuid.PcdUboDev|0x08 > + gPlatformTokenSpaceGuid.PcdUboFunc|0x02 > + gPlatformTokenSpaceGuid.PcdUboCpuBusNo0|0xCC > + > + gEfiCpuTokenSpaceGuid.PcdCpuIEDEnabled|TRUE > + > + ## Defines the ACPI register set base address. > + # The invalid 0xFFFF is as its default value. It must be configured t= o the real > value. > + # @Prompt ACPI Timer IO Port Address > + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddress | > 0x0500 > + > + ## Defines the PCI Bus Number of the PCI device that contains the BAR > and Enable for ACPI hardware registers. > + # @Prompt ACPI Hardware PCI Bus Number > + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBusNumber | 0x00 > + > + > gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision|0x000000 > 02 > + > gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorId|0x4C544E49 > + > gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision|0x2009 > 1013 > + > + ## Defines the PCI Device Number of the PCI device that contains the B= AR > and Enable for ACPI hardware registers. > + # The invalid 0xFF is as its default value. It must be configured to = the real > value. > + # @Prompt ACPI Hardware PCI Device Number > + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciDeviceNumber | 0x1F > + > + ## Defines the PCI Function Number of the PCI device that contains the > BAR and Enable for ACPI hardware registers. > + # The invalid 0xFF is as its default value. It must be configured to = the real > value. > + # @Prompt ACPI Hardware PCI Function Number > + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciFunctionNumber | 0x02 > + > + ## Defines the PCI Register Offset of the PCI device that contains the > Enable for ACPI hardware registers. > + # The invalid 0xFFFF is as its default value. It must be configured t= o the real > value. > + # @Prompt ACPI Hardware PCI Register Offset > + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciEnableRegisterOffset > |0x0044 > + > + ## Defines the bit mask that must be set to enable the APIC hardware > register BAR. > + # @Prompt ACPI Hardware PCI Bar Enable BitMask > + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoBarEnableMask | 0x80 > + > + ## Defines the PCI Register Offset of the PCI device that contains the= BAR > for ACPI hardware registers. > + # The invalid 0xFFFF is as its default value. It must be configured t= o the real > value. > + # @Prompt ACPI Hardware PCI Bar Register Offset > + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBarRegisterOffset > |0x0040 > + > + ## Defines the offset to the 32-bit Timer Value register that resides = within > the ACPI BAR. > + # @Prompt Offset to 32-bit Timer register in ACPI BAR > + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiPm1TmrOffset |0x0008 > + > + ## Defines the bit mask to retrieve ACPI IO Port Base Address > + # @Prompt ACPI IO Port Base Address Mask > + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddressMask > |0xFFFC > + > + # Indicates the max nested level > + gEfiCpRcPkgTokenSpaceGuid.PcdMaxNestedLevel|0x00000010 > + > + gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuSocketCount|$(MAX_SOCKET) > + > gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|$(MAX_SOCKET > ) > + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|28 > + > + > gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationC > hange|FALSE > + > + > gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiReclaimMemorySize|0 > x70 > + > gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiNvsMemorySize|0x80 > + > gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x1 > 470 > + > gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize|0xA0 > + > gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0x80 > + > + # > + # The PCDs are used to control the Windows SMM Security Mitigations > Table - Protection Flags > + # > + # BIT0: If set, expresses that for all synchronous SMM entries,SMM wil= l > validate that input and output buffers lie entirely within the expected f= ixed > memory regions. > + # BIT1: If set, expresses that for all synchronous SMM entries, SMM wi= ll > validate that input and output pointers embedded within the fixed > communication buffer only refer to address ranges \ > + # that lie entirely within the expected fixed memory regions. > + # BIT2: Firmware setting this bit is an indication that it will not al= low > reconfiguration of system resources via non-architectural mechanisms. > + # BIT3-31: Reserved > + # > + gMinPlatformPkgTokenSpaceGuid.PcdWsmtProtectionFlags|0x07 > + > +[PcdsFixedAtBuild.X64] > + gPcAtChipsetPkgTokenSpaceGuid.PcdMinimalValidYear|2015 > + gPcAtChipsetPkgTokenSpaceGuid.PcdMaximalValidYear|2099 > + # Change PcdBootManagerMenuFile to UiApp > +## > + > + gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, > 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0= x66, > 0x23, 0x31 } > + > + gEfiCpuTokenSpaceGuid.PcdCpuSmmCodeAccessCheckEnable |TRUE > + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmCodeAccessCheckEnable |TRUE > + > + gMinPlatformPkgTokenSpaceGuid.PcdFadtPreferredPmProfile|0x04 > + gMinPlatformPkgTokenSpaceGuid.PcdFadtIaPcBootArch|0x0000 > + gMinPlatformPkgTokenSpaceGuid.PcdFadtFlags|0x000004A5 > + > + gMinPlatformPkgTokenSpaceGuid.PcdAcpiEnableSwSmi|0xA0 > + gMinPlatformPkgTokenSpaceGuid.PcdAcpiDisableSwSmi|0xA1 > + > + gMinPlatformPkgTokenSpaceGuid.PcdLocalApicAddress|0xFEE00000 > + gMinPlatformPkgTokenSpaceGuid.PcdIoApicAddress|0xFEC00000 > + gMinPlatformPkgTokenSpaceGuid.PcdIoApicId|0x08 > + > + gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicCount|32 > + gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicIdBase|0x09 > + gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicAddressBase|0xFEC01000 > + gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicInterruptBase|24 > + > + gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1AEventBlockAddress|0x500 > + gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1BEventBlockAddress|0 > + > gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1AControlBlockAddress|0x504 > + gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1BControlBlockAddress|0 > + > gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm2ControlBlockAddress|0x550 > + gMinPlatformPkgTokenSpaceGuid.PcdAcpiPmTimerBlockAddress|0x508 > + gMinPlatformPkgTokenSpaceGuid.PcdAcpiGpe0BlockAddress|0x580 > + gMinPlatformPkgTokenSpaceGuid.PcdAcpiGpe1BlockAddress|0 > + > +[PcdsPatchableInModule.common] > + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000042 > + > +!if gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable =3D=3D TRUE > + > gEfiMdeModulePkgTokenSpaceGuid.PcdSmiHandlerProfilePropertyMask|0x > 1 > +!endif > + > + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x80000000 > + > gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000 > + gPcAtChipsetPkgTokenSpaceGuid.PcdHpetBaseAddress|0xFED00000 > + > + gMinPlatformPkgTokenSpaceGuid.PcdPciReservedIobase |0x1000 > + gMinPlatformPkgTokenSpaceGuid.PcdPciReservedIoLimit |0xFFFF > + gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemBase > |0x90000000 > + gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemLimit > |0xFBFFFFFF > + gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBBase > |0x380000000000 > + gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBLimit > |0x3803FFFFFFFF > + > + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|800 > + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|600 > + > + gEfiCpuTokenSpaceGuid.PcdCpuSmmUseDelayIndication|FALSE > + gEfiCpuTokenSpaceGuid.PcdCpuSmmUseBlockIndication|FALSE > + gEfiCpuTokenSpaceGuid.PcdCpuSmmUseSmmEnableIndication|FALSE > + gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable|TRUE > + > + gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress|0xFF800000 > + gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize|0x01400000 > + > +[PcdsDynamicExDefault.common.DEFAULT] > + > gEfiCpuTokenSpaceGuid.PcdCpuProcessorFeatureUserConfiguration|0x002C > F6CF > + gEfiCpuTokenSpaceGuid.PcdCpuProcessorFeatureUserConfigurationEx1|0 > + > gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|30000 > + gEfiCpuTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|200000 > + gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport|TRUE > + > + gUefiCpuPkgTokenSpaceGuid.PcdCpuS3DataAddress|0 > + > + gEfiPchTokenSpaceGuid.PcdWakeOnRTCS5|FALSE > + gEfiPchTokenSpaceGuid.PcdRtcWakeupTimeHour|0 > + gEfiPchTokenSpaceGuid.PcdRtcWakeupTimeMinute|0 > + gEfiPchTokenSpaceGuid.PcdRtcWakeupTimeSecond|0 > + > + gOemSkuTokenSpaceGuid.PcdOemSkuUplinkPortIndex|0x5 > + > +[PcdsDynamicExHii.common.DEFAULT] > +!if gPlatformTokenSpaceGuid.PcdFastBoot =3D=3D FALSE > + > gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlo > balVariableGuid|0x0|3 # Variable: L"Timeout" > +!else > + > gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlo > balVariableGuid|0x0|0 # Variable: L"Timeout" > +!endif > + > gEfiMdePkgTokenSpaceGuid.PcdHardwareErrorRecordLevel|L"HwErrRecSup > port"|gEfiGlobalVariableGuid|0x0|1 # Variable: L"HwErrRecSupport" > + > + > +[PcdsDynamicExDefault] > + > + gOemSkuTokenSpaceGuid.PcdForceTo1SConfigMode|FALSE > + > +## *** PURLEY_PPO *** - Added in 8th segment in PcdPcieMmcfgTablePtr > to fix size assert in PcieAddressLib.c > +## | = MMCFG Table Header > | Segment 0 = | Segment 1 > | Segment 2 = | Segment 3 > | Segment 4 = | Segment 5 > | Segment 6 = | Segment 7 > | Segment 8 > + gEfiCpRcPkgTokenSpaceGuid.PcdPcieMmcfgTablePtr|{0x0, 0x0, 0x0, 0x0, > 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0= , 0x0, > 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0= , 0x0, > 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0= , 0x0, > 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0= , 0x0, > 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x= 0, 0x0, > 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0= , 0x0, > 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0= , 0x0, > 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0= , 0x0, > 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0= , 0x0, > 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0} > + > + gEfiCpuTokenSpaceGuid.PcdCpuEnergyPolicy|0 > + gEfiCpuTokenSpaceGuid.PcdCpuAcpiLvl2Addr|0 > + gEfiCpuTokenSpaceGuid.PcdCpuPackageCStateLimit|0 > + gEfiCpuTokenSpaceGuid.PcdCpuCoreCStateValue|0 > + gEfiCpuTokenSpaceGuid.PcdCpuClockModulationDutyCycle|0 > + gEfiCpuTokenSpaceGuid.PcdCpuHwCoordination|TRUE > + gEfiCpuTokenSpaceGuid.PcdCpuDcuMode|0 > + gEfiCpuTokenSpaceGuid.PcdCpuTurboOverride|0x0 > + gEfiCpuTokenSpaceGuid.PcdCpuProcessorMsrLockCtrl|0 > + gEfiCpuTokenSpaceGuid.PcdCpuIioLlcWaysBitMask|0x0 > + gEfiCpuTokenSpaceGuid.PcdCpuExpandedIioLlcWaysBitMask|0x0 > + gEfiCpuTokenSpaceGuid.PcdCpuRemoteWaysBitMask|0x0 > + gEfiCpuTokenSpaceGuid.PcdPchTraceHubEn|0x0 > + gEfiCpuTokenSpaceGuid.PcdCpuQlruCfgBitMask|0x0 > + gEfiCpuTokenSpaceGuid.PcdSbspSelection|0xFF > +# > gEfiCpuTokenSpaceGuid.PcdCpuSocketId|{0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0, > 0x1,0x0,0x0,0x0,0x1,0x0,0x0,0x0,0x2,0x0,0x0,0x0,0x2,0x0,0x0,0x0,0x3,0x0,0= x > 0,0x0,0x3,0x0,0x0,0x0} > + gEfiCpuTokenSpaceGuid.PcdCpuPmStructAddr|0x0 > + gEfiCpuTokenSpaceGuid.PcdCpuRRQCountThreshold|0x0 > + > + gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|TRUE > + gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport|TRUE > + gEfiMdeModulePkgTokenSpaceGuid.PcdMrIovSupport|FALSE > + gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSystemPageSize|0x1F > + > + > gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L""|VOID*| > 36 > + > + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId|{0x49, 0x4E, > 0x54, 0x45, 0x4C, 0x20} > + > gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId|0x2046573 > 030363253 > + > + gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicEnable|0x0 > + > +[PcdsDynamicExDefault.X64] > + > + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200 > + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|8 > + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|1 > + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits|1 > + gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|0 > + > + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|31 > + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|100 > + > + > gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution|80 > 0 > + > gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution|600 > + > + gUefiCpuPkgTokenSpaceGuid.PcdCpuHotPlugDataAddress|0 > diff --git > a/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/StructureConfig.dsc > b/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/StructureConfig.dsc > new file mode 100644 > index 0000000000..19a5e5b340 > --- /dev/null > +++ > b/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/StructureConfig.dsc > @@ -0,0 +1,6236 @@ > +## @file > +# > +# Copyright (c) 2018, Intel Corporation. All rights reserved.
> +# Copyright (c) 2021, American Megatrends International LLC.
> +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > +## > + > +#[PcdsDynamicEx.common.DEFAULT.MANUFACTURING] > +# gOemSkuTokenSpaceGuid.PcdSetupData|L"Setup"|ec87d643-eba4- > 4bb5-a1e5-3f3e36b20da9|0x00 > +# gOemSkuTokenSpaceGuid.PcdSetupData.serialDebugMsgLvl|0x1 > +# gOemSkuTokenSpaceGuid.PcdSetupData.TagecMem|0x1 > +# > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData|L"PchRcConfiguratio > n"|d19a26a3-17f1-48c3-8a1e-11eb0a7f6e4e|0x00 > +# gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchHdAudio|0x0 > +# > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData|L"SocketIioConfig"|dd84 > 017e-7f52-48f9-b16e-50ed9e0dbe27|0x00 > +# > gOemSkuTokenSpaceGuid.PcdSocketCommonRcConfigData|L"SocketComm > onRcConfig"|4402ca38-808f-4279-bcec-5baf8d59092f|0x00 > +# > gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData|L"SocketMpLinkCon > fig"|2b9b22de-2ad4-4abc-957d-5f18c504a05c|0x00 > +# > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData|L"SocketMemoryC > onfig"|98cf19ed-4109-4681-b79d-9196757c7824|0x00 > +# > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData|L"Sock > etPowerManagementConfig"|A1047342-BDBA-4DAE-A67A- > 40979B65C7F8|0x00 > +# > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Procho > tLock|0x1 > +# > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PkgCst > EntryValCtl|0x0 > +# > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.TurboP > owerLimitLock|0x1 > +# > gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData|L"SocketPro > cessorCoreConfig"|07013588-C789-4E12-A7C3-88FAFAE79F7C|0x00 > +# > gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.ProcessorVm > xEnable|0x0 > +# > gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.ProcessorMs > rLockControl|0x0 > + > +#[PcdsDynamicEx.common.DEFAULT.STANDARD] > + #gOemSkuTokenSpaceGuid.PcdSetupData|L"Setup"|ec87d643-eba4- > 4bb5-a1e5-3f3e36b20da9|0x00 > + gOemSkuTokenSpaceGuid.PcdSetupData|{0x0} > + gOemSkuTokenSpaceGuid.PcdSetupData.CloudProfile|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.Use1GPageTable|0x1 > + #gOemSkuTokenSpaceGuid.PcdSetupData.ResetOnMemMapChange|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.FanPwmOffset|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.WakeOnLanSupport|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.ValidationBreakpointType|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.bsdBreakpoint|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.ForceSetup|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.BiosGuardEnabled|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.RtoPopulateBGDirectory|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.EnableAntiFlashWearout|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.SkipXmlComprs|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.DfxAdvDebugJumper|0x2 > + gOemSkuTokenSpaceGuid.PcdSetupData.serialDebugMsgLvl|0x4 > + gOemSkuTokenSpaceGuid.PcdSetupData.serialDebugTrace|0x0 > + > gOemSkuTokenSpaceGuid.PcdSetupData.serialDebugMsgLvlTrainResults|0x > 0 > + gOemSkuTokenSpaceGuid.PcdSetupData.VideoSelect|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.Ps2PortSwap|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.Numlock|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.WakeOnLanS5|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.BootNetwork|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.ARIEnable|0x1 > + gOemSkuTokenSpaceGuid.PcdSetupData.SRIOVEnable|0x1 > + gOemSkuTokenSpaceGuid.PcdSetupData.SystemPageSize|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.MRIOVEnable|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.WakeOnRTCS4S5|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.RTCWakeupTimeHour|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.RTCWakeupTimeMinute|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.RTCWakeupTimeSecond|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.LegacyPxeRom|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.EfiNetworkSupport|0x1 > + gOemSkuTokenSpaceGuid.PcdSetupData.LomDisableByGpio|0x1 > + gOemSkuTokenSpaceGuid.PcdSetupData.ReserveMem|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.ReserveStartAddr|0x100000 > + gOemSkuTokenSpaceGuid.PcdSetupData.TagecMem|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.ValidationResetType|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.ValidationCountOuter|0x1f4 > + gOemSkuTokenSpaceGuid.PcdSetupData.ValidationCountInner|0x1f4 > + gOemSkuTokenSpaceGuid.PcdSetupData.ValidationStopOnError|0x1 > + gOemSkuTokenSpaceGuid.PcdSetupData.ValidationBootWhenDone|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.ValidationSkxPciError|0x1 > + gOemSkuTokenSpaceGuid.PcdSetupData.ValidationSkxPciLinkError|0x1 > + > gOemSkuTokenSpaceGuid.PcdSetupData.ValidationSkxPciLinkRecoveryCoun > tError|0x1 > + > gOemSkuTokenSpaceGuid.PcdSetupData.ValidationSkxPciLinkRecoveryCoun > tThreshold|0x4 > + gOemSkuTokenSpaceGuid.PcdSetupData.ValidationPchPciError|0x1 > + gOemSkuTokenSpaceGuid.PcdSetupData.ValidationKtiError|0x1 > + gOemSkuTokenSpaceGuid.PcdSetupData.XhciWakeOnUsbEnabled|0x1 > + gOemSkuTokenSpaceGuid.PcdSetupData.UsbLegacySupport|0x1 > + gOemSkuTokenSpaceGuid.PcdSetupData.UsbEmul6064|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.UsbMassResetDelay|0x1 > + gOemSkuTokenSpaceGuid.PcdSetupData.UsbNonBoot|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.UsbEmu1|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.UsbEmu2|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.UsbEmu3|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.UsbEmu4|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.UsbEmu5|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.UsbEmu6|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.UsbEmu7|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.UsbEmu8|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.UsbEmu9|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.UsbEmu10|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.UsbEmu11|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.UsbEmu12|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.UsbEmu13|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.UsbEmu14|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.UsbEmu15|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.UsbEmu16|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.PcieClockGating|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.GbePciePortNum|0x1 > + gOemSkuTokenSpaceGuid.PcdSetupData.RamDebugInterface|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.TraceHubDebugInterface|0x1 > + gOemSkuTokenSpaceGuid.PcdSetupData.SystemErrorEn|0x1 > + gOemSkuTokenSpaceGuid.PcdSetupData.PoisonEn|0x1 > + gOemSkuTokenSpaceGuid.PcdSetupData.ViralEn|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.ClearViralStatus|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.CloakingEn|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.UboxToPcuMcaEn|0x1 > + gOemSkuTokenSpaceGuid.PcdSetupData.CaterrGpioSmiEn|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.FatalErrSpinLoopEn|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.EmcaEn|0x1 > + gOemSkuTokenSpaceGuid.PcdSetupData.LmceEn|0x1 > + gOemSkuTokenSpaceGuid.PcdSetupData.EmcaIgnOptin|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.EmcaCsmiEn|0x2 > + gOemSkuTokenSpaceGuid.PcdSetupData.EmcaMsmiEn|0x2 > + gOemSkuTokenSpaceGuid.PcdSetupData.ElogCorrErrEn|0x1 > + gOemSkuTokenSpaceGuid.PcdSetupData.ElogMemErrEn|0x1 > + gOemSkuTokenSpaceGuid.PcdSetupData.ElogProcErrEn|0x1 > + gOemSkuTokenSpaceGuid.PcdSetupData.WheaSupportEn|0x1 > + gOemSkuTokenSpaceGuid.PcdSetupData.WheaLogMemoryEn|0x1 > + gOemSkuTokenSpaceGuid.PcdSetupData.WheaLogProcEn|0x1 > + gOemSkuTokenSpaceGuid.PcdSetupData.WheaLogPciEn|0x1 > + gOemSkuTokenSpaceGuid.PcdSetupData.McaBankErrInjEn|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.WheaErrorInjSupportEn|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.WheaErrInjEn|0x1 > + gOemSkuTokenSpaceGuid.PcdSetupData.WheaPcieErrInjEn|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.PcieErrInjActionTable|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.MeSegErrorInjEn|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.ParityCheckEn|0x0 > + > gOemSkuTokenSpaceGuid.PcdSetupData.McBankWarmBootClearError|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.KTIFailoverSmiEn|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.MemErrEn|0x1 > + gOemSkuTokenSpaceGuid.PcdSetupData.CorrMemErrEn|0x1 > + gOemSkuTokenSpaceGuid.PcdSetupData.LeakyBktHiLeakyBktLo|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.SpareIntSelect|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.FnvErrorEn|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.FnvErrorLowPrioritySignal|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.FnvErrorHighPrioritySignal|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.IioErrorEn|0x1 > + gOemSkuTokenSpaceGuid.PcdSetupData.IoMcaEn|0x1 > + gOemSkuTokenSpaceGuid.PcdSetupData.IioErrorPinEn|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.IioErrRegistersClearEn|0x1 > + gOemSkuTokenSpaceGuid.PcdSetupData.LerEn|0x0 > + > gOemSkuTokenSpaceGuid.PcdSetupData.DisableMAerrorLoggingDueToLER| > 0x1 > + gOemSkuTokenSpaceGuid.PcdSetupData.IioIrpErrorEn|0x1 > + gOemSkuTokenSpaceGuid.PcdSetupData.irpp0_parityError|0x1 > + gOemSkuTokenSpaceGuid.PcdSetupData.irpp0_qtOverflow|0x1 > + gOemSkuTokenSpaceGuid.PcdSetupData.irpp0_unexprsp|0x1 > + gOemSkuTokenSpaceGuid.PcdSetupData.irpp0_csraccunaligned|0x1 > + gOemSkuTokenSpaceGuid.PcdSetupData.irpp0_unceccCs0|0x1 > + gOemSkuTokenSpaceGuid.PcdSetupData.irpp0_unceccCs1|0x1 > + gOemSkuTokenSpaceGuid.PcdSetupData.irpp0_rcvdpoison|0x1 > + gOemSkuTokenSpaceGuid.PcdSetupData.irpp0_crreccCs0|0x1 > + gOemSkuTokenSpaceGuid.PcdSetupData.irpp0_crreccCs1|0x1 > + gOemSkuTokenSpaceGuid.PcdSetupData.IioMiscErrorEn|0x1 > + gOemSkuTokenSpaceGuid.PcdSetupData.IioVtdErrorEn|0x1 > + gOemSkuTokenSpaceGuid.PcdSetupData.IioDmaErrorEn|0x1 > + gOemSkuTokenSpaceGuid.PcdSetupData.IioDmiErrorEn|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.PcieErrEn|0x1 > + gOemSkuTokenSpaceGuid.PcdSetupData.IioPcieAddCorrErrorEn|0x1 > + gOemSkuTokenSpaceGuid.PcdSetupData.IioPcieAddUnCorrEn|0x1 > + gOemSkuTokenSpaceGuid.PcdSetupData.IioPcieAerSpecCompEn|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.PcieCorrErrEn|0x1 > + gOemSkuTokenSpaceGuid.PcdSetupData.PcieUncorrErrEn|0x1 > + gOemSkuTokenSpaceGuid.PcdSetupData.PcieFatalErrEn|0x1 > + gOemSkuTokenSpaceGuid.PcdSetupData.PcieCorErrCntr|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.PcieCorErrMaskBitMap|0x3f > + gOemSkuTokenSpaceGuid.PcdSetupData.PcieCorErrThres|0x1 > + gOemSkuTokenSpaceGuid.PcdSetupData.PcieAerCorrErrEn|0x1 > + gOemSkuTokenSpaceGuid.PcdSetupData.PcieAerAdNfatErrEn|0x1 > + gOemSkuTokenSpaceGuid.PcdSetupData.PcieAerNfatErrEn|0x1 > + gOemSkuTokenSpaceGuid.PcdSetupData.PcieAerFatErrEn|0x1 > + gOemSkuTokenSpaceGuid.PcdSetupData.SerrPropEn|0x1 > + gOemSkuTokenSpaceGuid.PcdSetupData.PerrPropEn|0x1 > + gOemSkuTokenSpaceGuid.PcdSetupData.OsSigOnSerrEn|0x1 > + gOemSkuTokenSpaceGuid.PcdSetupData.OsSigOnPerrEn|0x1 > + gOemSkuTokenSpaceGuid.PcdSetupData.ConsoleRedirection|0x1 > + gOemSkuTokenSpaceGuid.PcdSetupData.FlowControl|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.BaudRate|0x5 > + gOemSkuTokenSpaceGuid.PcdSetupData.TerminalType|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.Parity|0x1 > + gOemSkuTokenSpaceGuid.PcdSetupData.DataBits|0x8 > + gOemSkuTokenSpaceGuid.PcdSetupData.StopBits|0x1 > + gOemSkuTokenSpaceGuid.PcdSetupData.TerminalResolution|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.LegacyOsRedirection|0x1 > + gOemSkuTokenSpaceGuid.PcdSetupData.BootAllOptions|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.OverclockingSupport|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.FilterPll|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.CoreMaxOcRatio|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.CoreVoltageMode|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.CoreVoltageOverride|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.CoreExtraTurboVoltage|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.CoreVoltageOffset|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.CoreVoltageOffsetPrefix|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.ClrMaxOcRatio|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.ClrVoltageMode|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.ClrVoltageOverride|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.ClrExtraTurboVoltage|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.ClrVoltageOffset|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.ClrVoltageOffsetPrefix|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.UncoreVoltageOffset|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.UncoreVoltageOffsetPrefix|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.IoaVoltageOffset|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.IoaVoltageOffsetPrefix|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.IodVoltageOffset|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.IodVoltageOffsetPrefix|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.VccIoVoltage|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.SvidEnable|0x1 > + gOemSkuTokenSpaceGuid.PcdSetupData.SvidVoltageOverride|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.CpuVccInVoltage|0x167 > + gOemSkuTokenSpaceGuid.PcdSetupData.FivrFaultsEnable|0x1 > + gOemSkuTokenSpaceGuid.PcdSetupData.FivrEfficiencyEnable|0x1 > + gOemSkuTokenSpaceGuid.PcdSetupData.SerialBaudRate|0x1c200 > + gOemSkuTokenSpaceGuid.PcdSetupData.UefiOptimizedBootToggle|0x1 > + > gOemSkuTokenSpaceGuid.PcdSetupData.EfiWindowsInt10Workaround|0x0 > + gOemSkuTokenSpaceGuid.PcdSetupData.SetShellFirst|0x1 > + gOemSkuTokenSpaceGuid.PcdSetupData.UsbStackSupport|0x1 > + gOemSkuTokenSpaceGuid.PcdSetupData.XmlCliSupport|0x1 > + gOemSkuTokenSpaceGuid.PcdSetupData.ReportAlertSPA|1 > + gOemSkuTokenSpaceGuid.PcdSetupData.NgnHostAlertPatrolScrubUNC|1 > + gOemSkuTokenSpaceGuid.PcdSetupData.DcpmmUncPoison|1 > + gOemSkuTokenSpaceGuid.PcdSetupData.UCErrChkForVariableSrv|1 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData|{0} > + > #gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData|L"PchRcConfigurati > on"|d19a26a3-17f1-48c3-8a1e-11eb0a7f6e4e|0x00 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.FirmwareConfigurati > on|0x0 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchDciEn|0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchDciAutoDetect|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.BoardCapability|0x1 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.DeepSxMode|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.Gp27WakeFromDee > pSx|0x0 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchSmbus|0x1 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchSerm|0x0 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchDisplay|0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPciClockRun|0x1 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchSirqMode|0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.EnableClockSpreadSp > ec|0x1 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.StateAfterG3|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.IchPort80Route|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchCrossThrottling|0 > x1 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchCrid|0x0 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PciePllSsc|0xff > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.UsbPrecondition|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchUsbManualMode > |0x0 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.Btcg|0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.Usb3PinsTermination > |0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.EnableUsb3Pin[0]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.EnableUsb3Pin[1]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.EnableUsb3Pin[2]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.EnableUsb3Pin[3]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.EnableUsb3Pin[4]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.EnableUsb3Pin[5]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.EnableUsb3Pin[6]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.EnableUsb3Pin[7]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.EnableUsb3Pin[8]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.EnableUsb3Pin[9]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchUsbPerPortCtl|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchUsbHsPort[0]|0x > 1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchUsbHsPort[1]|0x > 1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchUsbHsPort[2]|0x > 1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchUsbHsPort[3]|0x > 1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchUsbHsPort[4]|0x > 1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchUsbHsPort[5]|0x > 1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchUsbHsPort[6]|0x > 1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchUsbHsPort[7]|0x > 1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchUsbHsPort[8]|0x > 1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchUsbHsPort[9]|0x > 1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchUsbHsPort[10]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchUsbHsPort[11]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchUsbHsPort[12]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchUsbHsPort[13]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchUsbSsPort[0]|0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchUsbSsPort[1]|0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchUsbSsPort[2]|0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchUsbSsPort[3]|0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchUsbSsPort[4]|0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchUsbSsPort[5]|0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchUsbSsPort[6]|0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchUsbSsPort[7]|0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchUsbSsPort[8]|0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchUsbSsPort[9]|0x1 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.XhciIdleL1|0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.XhciDisMSICapability > |0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.XhciOcMapEnabled| > 0x1 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchHdAudio|0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchHdAudioCodecSel > ect|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchHdAudioPme|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.RtoHdaVcType|0x0 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchSata|0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataInterfaceMode| > 0x0 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataTestMode|0x0 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataSalp|0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataAlternateId|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataRaidLoadEfiDrive > r|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.RstPcieStorageRema > p[0]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.RstPcieStorageRema > pPort[0]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.RstPcieStorageRema > p[1]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.RstPcieStorageRema > pPort[1]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.RstPcieStorageRema > p[2]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.RstPcieStorageRema > pPort[2]|0x0 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataPort[0]|0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataHotPlug[0]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataExternal[0]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataMechanicalSw[0] > |0x1 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataSpinUp[0]|0x0 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataType[0]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataTopology[0]|0x0 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataPort[1]|0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataHotPlug[1]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataExternal[1]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataMechanicalSw[1] > |0x1 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataSpinUp[1]|0x0 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataType[1]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataTopology[1]|0x0 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataPort[2]|0x1 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PxDevSlp[2]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataHotPlug[2]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataExternal[2]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataMechanicalSw[2] > |0x1 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataSpinUp[2]|0x0 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataType[2]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataTopology[2]|0x0 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataPort[3]|0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataHotPlug[3]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataExternal[3]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataMechanicalSw[3] > |0x1 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataSpinUp[3]|0x0 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataType[3]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataTopology[3]|0x0 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataPort[4]|0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataHotPlug[4]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataExternal[4]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataMechanicalSw[4] > |0x1 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataSpinUp[4]|0x0 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataType[4]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataTopology[4]|0x0 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataPort[5]|0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataHotPlug[5]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataMechanicalSw[5] > |0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataExternal[5]|0x0 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataSpinUp[5]|0x0 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataType[5]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataTopology[5]|0x0 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataPort[6]|0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataHotPlug[6]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataMechanicalSw[6] > |0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataExternal[6]|0x0 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataSpinUp[6]|0x0 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataType[6]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataTopology[6]|0x0 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataPort[7]|0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataHotPlug[7]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataMechanicalSw[7] > |0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataExternal[7]|0x0 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataSpinUp[7]|0x0 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataType[7]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataTopology[7]|0x0 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataHddlk|0x1 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataLedl|0x1 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataRaidR0|0x1 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataRaidR1|0x1 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataRaidR10|0x1 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataRaidR5|0x1 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataRaidIrrt|0x1 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataRaidOub|0x1 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataRaidIooe|0x1 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataRaidSrt|0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataRaidOromDelay| > 0x0 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchsSata|0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataInterfaceMode > |0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataTestMode|0x0 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataSalp|0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataAlternateId|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataRaidLoadEfiDriv > er|0x0 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataPort[0]|0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataHotPlug[0]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataExternal[0]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataSpinUp[0]|0x0 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataType[0]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataTopology[0]|0x > 0 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataPort[1]|0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataHotPlug[1]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataExternal[1]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataSpinUp[1]|0x0 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataType[1]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataTopology[1]|0x > 0 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataPort[2]|0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataHotPlug[2]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataExternal[2]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataSpinUp[2]|0x0 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataType[2]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataTopology[2]|0x > 0 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataPort[3]|0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataHotPlug[3]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataExternal[3]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataSpinUp[3]|0x0 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataType[3]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataTopology[3]|0x > 0 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataPort[4]|0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataHotPlug[4]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataExternal[4]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataSpinUp[4]|0x0 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataType[4]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataTopology[4]|0x > 0 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataPort[5]|0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataHotPlug[5]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataExternal[5]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataSpinUp[5]|0x0 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataType[5]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataTopology[5]|0x > 0 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataHddlk|0x1 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataLedl|0x1 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataRaidR0|0x1 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataRaidR1|0x1 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataRaidR10|0x1 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataRaidR5|0x1 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataRaidIrrt|0x1 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataRaidOub|0x1 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataRaidIooe|0x1 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataRaidSrt|0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataRaidOromDelay > |0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchWakeOnLan|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchSlpLanLowDc|0x1 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchLanK1Off|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PciDelayOptimization > Ecr|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieComplianceTest > Mode|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieGlobalAspm| > 0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieUX16Complet > ionTimeout|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieUX8Completi > onTimeout|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieUX16MaxPayl > oadSize|0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieUX8MaxPayl > oadSize|0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieDmiExtSync|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieDmiStopAndScre > amEnable|0x0 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.XTpmLen|0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSBDE|0 > x0 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieSBDEPort|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortFunctio > nSwapping|0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMaxRea > dRequestSize|0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCm[0]|0x6 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCp[0]|0x6 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCm[1]|0x6 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCp[1]|0x6 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCm[2]|0x6 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCp[2]|0x6 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCm[3]|0x6 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCp[3]|0x6 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCm[4]|0x6 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCp[4]|0x6 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCm[5]|0x6 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCp[5]|0x6 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCm[6]|0x6 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCp[6]|0x6 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCm[7]|0x6 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCp[7]|0x6 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCm[8]|0x6 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCp[8]|0x6 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCm[9]|0x6 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCp[9]|0x6 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCm[10]|0x6 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCp[10]|0x6 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCm[11]|0x6 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCp[11]|0x6 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCm[12]|0x6 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCp[12]|0x6 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCm[13]|0x6 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCp[13]|0x6 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCm[14]|0x6 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCp[14]|0x6 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCm[15]|0x6 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCp[15]|0x6 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCm[16]|0x6 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCp[16]|0x6 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCm[17]|0x6 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCp[17]|0x6 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCm[18]|0x6 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCp[18]|0x6 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCm[19]|0x6 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCp[19]|0x6 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieSwEqOverride|0 > x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieSwEqCoeffCm[0] > |0x6 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieSwEqCoeffCp[0] > |0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieSwEqCoeffCm[1] > |0x4 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieSwEqCoeffCp[1] > |0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieSwEqCoeffCm[2] > |0x8 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieSwEqCoeffCp[2] > |0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieSwEqCoeffCm[3] > |0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieSwEqCoeffCp[3] > |0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieSwEqCoeffCm[4] > |0xa > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieSwEqCoeffCp[4] > |0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEn[0]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAspm[0 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortL1SubSt > ates[0]|0x3 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEqPh3M > ethod[0]|0x4 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortACS[0]| > 0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortURE[0]| > 0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortFEE[0]| > 0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortNFE[0]| > 0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCEE[0]| > 0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSFE[0]| > 0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSNE[0]| > 0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSCE[0]| > 0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortPMCE[0 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortHPE[0]| > 0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAER[0]| > 0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSpeed[0 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMSIE[0] > |0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieTopology[0]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMaxPay > LoadSize[0]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortComple > tionTimeout[0]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[0]| > 0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatenc > yOverrideMode[0]|0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatenc > yOverrideValue[0]|0x3c > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatenc > yOverrideMultiplier[0]|0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLat > encyOverrideMode[0]|0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLat > encyOverrideValue[0]|0x3c > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLat > encyOverrideMultiplier[0]|0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrConfigLock > [0]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEn[1]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAspm[1 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortL1SubSt > ates[1]|0x3 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEqPh3M > ethod[1]|0x4 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortACS[1]| > 0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortURE[1]| > 0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortFEE[1]| > 0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortNFE[1]| > 0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCEE[1]| > 0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSFE[1]| > 0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSNE[1]| > 0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSCE[1]| > 0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortPMCE[1 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortHPE[1]| > 0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAER[1]| > 0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSpeed[1 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMSIE[1] > |0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieTopology[1]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMaxPay > LoadSize[1]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortComple > tionTimeout[1]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[1]| > 0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatenc > yOverrideMode[1]|0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatenc > yOverrideValue[1]|0x3c > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatenc > yOverrideMultiplier[1]|0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLat > encyOverrideMode[1]|0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLat > encyOverrideValue[1]|0x3c > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLat > encyOverrideMultiplier[1]|0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrConfigLock > [1]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEn[2]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAspm[2 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortL1SubSt > ates[2]|0x3 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEqPh3M > ethod[2]|0x4 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortACS[2]| > 0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortURE[2]| > 0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortFEE[2]| > 0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortNFE[2]| > 0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCEE[2]| > 0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSFE[2]| > 0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSNE[2]| > 0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSCE[2]| > 0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortPMCE[2 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortHPE[2]| > 0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAER[2]| > 0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSpeed[2 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMSIE[2] > |0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieTopology[2]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMaxPay > LoadSize[2]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortComple > tionTimeout[2]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[2]| > 0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatenc > yOverrideMode[2]|0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatenc > yOverrideValue[2]|0x3c > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatenc > yOverrideMultiplier[2]|0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLat > encyOverrideMode[2]|0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLat > encyOverrideValue[2]|0x3c > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLat > encyOverrideMultiplier[2]|0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrConfigLock > [2]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEn[3]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAspm[3 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortL1SubSt > ates[3]|0x3 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEqPh3M > ethod[3]|0x4 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortACS[3]| > 0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortURE[3]| > 0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortFEE[3]| > 0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortNFE[3]| > 0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCEE[3]| > 0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSFE[3]| > 0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSNE[3]| > 0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSCE[3]| > 0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortPMCE[3 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortHPE[3]| > 0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAER[3]| > 0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSpeed[3 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMSIE[3] > |0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieTopology[3]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMaxPay > LoadSize[3]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortComple > tionTimeout[3]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[3]| > 0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatenc > yOverrideMode[3]|0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatenc > yOverrideValue[3]|0x3c > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatenc > yOverrideMultiplier[3]|0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLat > encyOverrideMode[3]|0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLat > encyOverrideValue[3]|0x3c > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLat > encyOverrideMultiplier[3]|0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrConfigLock > [3]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEn[4]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAspm[4 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortL1SubSt > ates[4]|0x3 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEqPh3M > ethod[4]|0x4 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortACS[4]| > 0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortURE[4]| > 0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortFEE[4]| > 0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortNFE[4]| > 0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCEE[4]| > 0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSFE[4]| > 0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSNE[4]| > 0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSCE[4]| > 0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortPMCE[4 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortHPE[4]| > 0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAER[4]| > 0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSpeed[4 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMSIE[4] > |0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieTopology[4]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMaxPay > LoadSize[4]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortComple > tionTimeout[4]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[4]| > 0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatenc > yOverrideMode[4]|0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatenc > yOverrideValue[4]|0x3c > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatenc > yOverrideMultiplier[4]|0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLat > encyOverrideMode[4]|0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLat > encyOverrideValue[4]|0x3c > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLat > encyOverrideMultiplier[4]|0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrConfigLock > [4]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEn[5]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAspm[5 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortL1SubSt > ates[5]|0x3 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEqPh3M > ethod[5]|0x4 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortACS[5]| > 0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortURE[5]| > 0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortFEE[5]| > 0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortNFE[5]| > 0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCEE[5]| > 0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSFE[5]| > 0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSNE[5]| > 0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSCE[5]| > 0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortPMCE[5 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortHPE[5]| > 0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAER[5]| > 0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSpeed[5 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMSIE[5] > |0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieTopology[5]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMaxPay > LoadSize[5]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortComple > tionTimeout[5]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[5]| > 0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatenc > yOverrideMode[5]|0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatenc > yOverrideValue[5]|0x3c > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatenc > yOverrideMultiplier[5]|0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLat > encyOverrideMode[5]|0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLat > encyOverrideValue[5]|0x3c > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLat > encyOverrideMultiplier[5]|0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrConfigLock > [5]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEn[6]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAspm[6 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortL1SubSt > ates[6]|0x3 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEqPh3M > ethod[6]|0x4 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortACS[6]| > 0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortURE[6]| > 0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortFEE[6]| > 0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortNFE[6]| > 0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCEE[6]| > 0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSFE[6]| > 0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSNE[6]| > 0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSCE[6]| > 0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortPMCE[6 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortHPE[6]| > 0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAER[6]| > 0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSpeed[6 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMSIE[6] > |0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieTopology[6]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMaxPay > LoadSize[6]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortComple > tionTimeout[6]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[6]| > 0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatenc > yOverrideMode[6]|0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatenc > yOverrideValue[6]|0x3c > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatenc > yOverrideMultiplier[6]|0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLat > encyOverrideMode[6]|0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLat > encyOverrideValue[6]|0x3c > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLat > encyOverrideMultiplier[6]|0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrConfigLock > [6]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEn[7]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAspm[7 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortL1SubSt > ates[7]|0x3 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEqPh3M > ethod[7]|0x4 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortACS[7]| > 0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortURE[7]| > 0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortFEE[7]| > 0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortNFE[7]| > 0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCEE[7]| > 0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSFE[7]| > 0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSNE[7]| > 0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSCE[7]| > 0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortPMCE[7 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortHPE[7]| > 0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAER[7]| > 0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSpeed[7 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMSIE[7] > |0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieTopology[7]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMaxPay > LoadSize[7]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortComple > tionTimeout[7]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[7]| > 0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatenc > yOverrideMode[7]|0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatenc > yOverrideValue[7]|0x3c > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatenc > yOverrideMultiplier[7]|0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLat > encyOverrideMode[7]|0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLat > encyOverrideValue[7]|0x3c > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLat > encyOverrideMultiplier[7]|0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrConfigLock > [7]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEn[8]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAspm[8 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortL1SubSt > ates[8]|0x3 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEqPh3M > ethod[8]|0x4 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortACS[8]| > 0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortURE[8]| > 0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortFEE[8]| > 0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortNFE[8]| > 0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCEE[8]| > 0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSFE[8]| > 0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSNE[8]| > 0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSCE[8]| > 0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortPMCE[8 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortHPE[8]| > 0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAER[8]| > 0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSpeed[8 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMSIE[8] > |0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieTopology[8]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMaxPay > LoadSize[8]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortComple > tionTimeout[8]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[8]| > 0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatenc > yOverrideMode[8]|0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatenc > yOverrideValue[8]|0x3c > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatenc > yOverrideMultiplier[8]|0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLat > encyOverrideMode[8]|0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLat > encyOverrideValue[8]|0x3c > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLat > encyOverrideMultiplier[8]|0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrConfigLock > [8]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEn[9]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAspm[9 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortL1SubSt > ates[9]|0x3 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEqPh3M > ethod[9]|0x4 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortACS[9]| > 0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortURE[9]| > 0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortFEE[9]| > 0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortNFE[9]| > 0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCEE[9]| > 0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSFE[9]| > 0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSNE[9]| > 0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSCE[9]| > 0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortPMCE[9 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortHPE[9]| > 0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAER[9]| > 0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSpeed[9 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMSIE[9] > |0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieTopology[9]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMaxPay > LoadSize[9]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortComple > tionTimeout[9]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[9]| > 0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatenc > yOverrideMode[9]|0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatenc > yOverrideValue[9]|0x3c > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatenc > yOverrideMultiplier[9]|0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLat > encyOverrideMode[9]|0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLat > encyOverrideValue[9]|0x3c > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLat > encyOverrideMultiplier[9]|0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrConfigLock > [9]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEn[10]| > 0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAspm[1 > 0]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortL1SubSt > ates[10]|0x3 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEqPh3M > ethod[10]|0x4 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortACS[10] > |0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortURE[10] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortFEE[10] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortNFE[10] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCEE[10] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSFE[10] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSNE[10] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSCE[10] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortPMCE[1 > 0]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortHPE[10] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAER[10] > |0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSpeed[1 > 0]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMSIE[10 > ]|0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieTopology[10]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMaxPay > LoadSize[10]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortComple > tionTimeout[10]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[10] > |0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatenc > yOverrideMode[10]|0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatenc > yOverrideValue[10]|0x3c > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatenc > yOverrideMultiplier[10]|0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLat > encyOverrideMode[10]|0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLat > encyOverrideValue[10]|0x3c > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLat > encyOverrideMultiplier[10]|0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrConfigLock > [10]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEn[11]| > 0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAspm[1 > 1]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortL1SubSt > ates[11]|0x3 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEqPh3M > ethod[11]|0x4 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortACS[11] > |0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortURE[11] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortFEE[11] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortNFE[11] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCEE[11] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSFE[11] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSNE[11] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSCE[11] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortPMCE[1 > 1]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortHPE[11] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAER[11] > |0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSpeed[1 > 1]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMSIE[11 > ]|0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieTopology[11]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMaxPay > LoadSize[11]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortComple > tionTimeout[11]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[11] > |0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatenc > yOverrideMode[11]|0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatenc > yOverrideValue[11]|0x3c > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatenc > yOverrideMultiplier[11]|0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLat > encyOverrideMode[11]|0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLat > encyOverrideValue[11]|0x3c > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLat > encyOverrideMultiplier[11]|0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrConfigLock > [11]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEn[12]| > 0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAspm[1 > 2]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortL1SubSt > ates[12]|0x3 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEqPh3M > ethod[12]|0x4 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortACS[12] > |0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortURE[12] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortFEE[12] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortNFE[12] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCEE[12] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSFE[12] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSNE[12] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSCE[12] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortPMCE[1 > 2]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortHPE[12] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAER[12] > |0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSpeed[1 > 2]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMSIE[12 > ]|0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieTopology[12]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMaxPay > LoadSize[12]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortComple > tionTimeout[12]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[12] > |0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatenc > yOverrideMode[12]|0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatenc > yOverrideValue[12]|0x3c > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatenc > yOverrideMultiplier[12]|0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLat > encyOverrideMode[12]|0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLat > encyOverrideValue[12]|0x3c > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLat > encyOverrideMultiplier[12]|0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrConfigLock > [12]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEn[13]| > 0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAspm[1 > 3]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortL1SubSt > ates[13]|0x3 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEqPh3M > ethod[13]|0x4 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortACS[13] > |0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortURE[13] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortFEE[13] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortNFE[13] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCEE[13] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSFE[13] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSNE[13] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSCE[13] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortPMCE[1 > 3]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortHPE[13] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAER[13] > |0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSpeed[1 > 3]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMSIE[13 > ]|0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieTopology[13]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMaxPay > LoadSize[13]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortComple > tionTimeout[13]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[13] > |0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatenc > yOverrideMode[13]|0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatenc > yOverrideValue[13]|0x3c > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatenc > yOverrideMultiplier[13]|0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLat > encyOverrideMode[13]|0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLat > encyOverrideValue[13]|0x3c > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLat > encyOverrideMultiplier[13]|0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrConfigLock > [13]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEn[14]| > 0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAspm[1 > 4]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortL1SubSt > ates[14]|0x3 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEqPh3M > ethod[14]|0x4 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortACS[14] > |0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortURE[14] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortFEE[14] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortNFE[14] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCEE[14] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSFE[14] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSNE[14] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSCE[14] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortPMCE[1 > 4]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortHPE[14] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAER[14] > |0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSpeed[1 > 4]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMSIE[14 > ]|0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieTopology[14]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMaxPay > LoadSize[14]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortComple > tionTimeout[14]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[14] > |0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatenc > yOverrideMode[14]|0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatenc > yOverrideValue[14]|0x3c > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatenc > yOverrideMultiplier[14]|0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLat > encyOverrideMode[14]|0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLat > encyOverrideValue[14]|0x3c > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLat > encyOverrideMultiplier[14]|0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrConfigLock > [14]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEn[15]| > 0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAspm[1 > 5]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortL1SubSt > ates[15]|0x3 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEqPh3M > ethod[15]|0x4 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortACS[15] > |0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortURE[15] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortFEE[15] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortNFE[15] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCEE[15] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSFE[15] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSNE[15] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSCE[15] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortPMCE[1 > 5]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortHPE[15] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAER[15] > |0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSpeed[1 > 5]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMSIE[15 > ]|0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieTopology[15]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMaxPay > LoadSize[15]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortComple > tionTimeout[15]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[15] > |0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatenc > yOverrideMode[15]|0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatenc > yOverrideValue[15]|0x3c > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatenc > yOverrideMultiplier[15]|0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLat > encyOverrideMode[15]|0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLat > encyOverrideValue[15]|0x3c > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLat > encyOverrideMultiplier[15]|0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrConfigLock > [15]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEn[16]| > 0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAspm[1 > 6]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortL1SubSt > ates[16]|0x3 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEqPh3M > ethod[16]|0x4 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortACS[16] > |0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortURE[16] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortFEE[16] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortNFE[16] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCEE[16] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSFE[16] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSNE[16] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSCE[16] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortPMCE[1 > 6]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortHPE[16] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAER[16] > |0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSpeed[1 > 6]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMSIE[16 > ]|0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieTopology[16]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMaxPay > LoadSize[16]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortComple > tionTimeout[16]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[16] > |0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatenc > yOverrideMode[16]|0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatenc > yOverrideValue[16]|0x3c > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatenc > yOverrideMultiplier[16]|0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLat > encyOverrideMode[16]|0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLat > encyOverrideValue[16]|0x3c > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLat > encyOverrideMultiplier[16]|0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrConfigLock > [16]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEn[17]| > 0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAspm[1 > 7]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortL1SubSt > ates[17]|0x3 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEqPh3M > ethod[17]|0x4 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortACS[17] > |0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortURE[17] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortFEE[17] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortNFE[17] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCEE[17] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSFE[17] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSNE[17] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSCE[17] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortPMCE[1 > 7]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortHPE[17] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAER[17] > |0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSpeed[1 > 7]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMSIE[17 > ]|0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieTopology[17]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMaxPay > LoadSize[17]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortComple > tionTimeout[17]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[17] > |0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatenc > yOverrideMode[17]|0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatenc > yOverrideValue[17]|0x3c > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatenc > yOverrideMultiplier[17]|0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLat > encyOverrideMode[17]|0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLat > encyOverrideValue[17]|0x3c > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLat > encyOverrideMultiplier[17]|0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrConfigLock > [17]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEn[18]| > 0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAspm[1 > 8]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortL1SubSt > ates[18]|0x3 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEqPh3M > ethod[18]|0x4 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortACS[18] > |0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortURE[18] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortFEE[18] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortNFE[18] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCEE[18] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSFE[18] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSNE[18] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSCE[18] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortPMCE[1 > 8]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortHPE[18] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSpeed[1 > 8]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMSIE[18 > ]|0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieTopology[18]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMaxPay > LoadSize[18]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortComple > tionTimeout[18]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[18] > |0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatenc > yOverrideMode[18]|0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatenc > yOverrideValue[18]|0x3c > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatenc > yOverrideMultiplier[18]|0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLat > encyOverrideMode[18]|0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLat > encyOverrideValue[18]|0x3c > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLat > encyOverrideMultiplier[18]|0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrConfigLock > [18]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEn[19]| > 0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAspm[1 > 9]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortL1SubSt > ates[19]|0x3 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEqPh3M > ethod[19]|0x4 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortACS[19] > |0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortURE[19] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortFEE[19] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortNFE[19] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCEE[19] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSFE[19] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSNE[19] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSCE[19] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortPMCE[1 > 9]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortHPE[19] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSpeed[1 > 9]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMSIE[19 > ]|0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieTopology[19]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMaxPay > LoadSize[19]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortComple > tionTimeout[19]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[19] > |0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatenc > yOverrideMode[19]|0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatenc > yOverrideValue[19]|0x3c > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatenc > yOverrideMultiplier[19]|0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLat > encyOverrideMode[19]|0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLat > encyOverrideValue[19]|0x3c > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLat > encyOverrideMultiplier[19]|0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrConfigLock > [19]|0x0 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchSmmBwp|0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.ThermalDeviceEnabl > e|0x3 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.ThermalDeviceEnabl > e|0x3 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.TraceHubEnableMod > e|0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.MemRegion0BufferSi > ze|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.MemRegion1BufferSi > ze|0x0 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.Dwr_Enable|0x0 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.Dwr_Stall|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.DwrEn_PMCGBL|0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.DwrEn_CPUTHRM|0 > x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.DwrEn_PCHTHRM|0x > 0 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.DwrEn_PBO|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.DwrEn_MEPBO|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.DwrEn_MEWDT|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.DwrEn_MEGBL|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.DwrEn_CTWDT|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.DwrEn_PMCWDT|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.DwrEn_ME_UERR|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.DwrEn_SYSPWR|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.DwrEn_OCWDT|0x0 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.DwrEn_IEPBO|0x0 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.DwrEn_IEWDT|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.DwrEn_IEGBLN|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.DwrEn_IE_UERRN|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.DwrEn_ACRU_ERR_2 > H_EN|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.DwrPmcEn_HOST_RE > SET_TIMEOUT|0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.DwrPmcEn_SX_ENTR > Y_TIMEOUT|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.DwrPmcEn_HOST_RS > T_PROM|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.DwrPmcEn_HSMB_ > MSG|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.DwrPmcEn_IE_MTP_ > TIMEOUT|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.DwrPmcEn_MTP_TI > MEOUT|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.DwrPmcEn_ESPI_ERR > OR_DETECT|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchP2sbDevReveal|0 > x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchP2sbUnlock|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.TestDmiAspmCtrl|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PmcReadDisable|0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.TestSmbusSpdWrite > Disable|0x1 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchAllUnLock|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchTraceHubHide|0x > 1 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchRtcLock|0x1 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchBiosLock|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchGbeFlashLockDo > wn|0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchThermalUnlock|0 > x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.FlashLockDown|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchEvaMrom0HookE > nable|0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchEvaMrom1HookE > nable|0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.TestMctpBroadcastC > ycle|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.DmiLinkDownHangBy > pass|0x0 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchAdrEn|0x0 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.AdrTimerEn|0x0 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.AdrTimerVal|0x4 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.AdrMultiplierVal|0x6 > 3 > + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.AdrGpioSel|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchSataLtrEnable|0x > 1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchSataLtrOverride| > 0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchSataSnoopLatenc > yOverrideValue|0x28 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchSataSnoopLatenc > yOverrideMultiplier|0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchSataLtrConfigLock > |0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchSSataLtrEnable|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchSSataLtrOverride > |0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchSSataSnoopLaten > cyOverrideValue|0x28 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchSSataSnoopLaten > cyOverrideMultiplier|0x2 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchSSataLtrConfigLoc > k|0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[0]| > 0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieForceLtrOver > ride[0]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[1]| > 0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieForceLtrOver > ride[1]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[2]| > 0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieForceLtrOver > ride[2]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[3]| > 0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieForceLtrOver > ride[3]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[4]| > 0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieForceLtrOver > ride[4]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[5]| > 0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieForceLtrOver > ride[5]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[6]| > 0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieForceLtrOver > ride[6]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[7]| > 0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieForceLtrOver > ride[7]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[8]| > 0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieForceLtrOver > ride[8]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[9]| > 0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieForceLtrOver > ride[9]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[10] > |0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieForceLtrOver > ride[10]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[11] > |0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieForceLtrOver > ride[11]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[12] > |0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieForceLtrOver > ride[12]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[13] > |0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieForceLtrOver > ride[13]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[14] > |0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieForceLtrOver > ride[14]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[15] > |0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieForceLtrOver > ride[15]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[16] > |0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieForceLtrOver > ride[16]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[17] > |0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieForceLtrOver > ride[17]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[18] > |0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieForceLtrOver > ride[18]|0x0 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[19] > |0x1 > + > gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieForceLtrOver > ride[19]|0x0 > + > #gOemSkuTokenSpaceGuid.PcdSocketIioConfigData|L"SocketIioConfig"|dd8 > 4017e-7f52-48f9-b16e-50ed9e0dbe27|0x00 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData|{0x0} > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Pci64BitResourceAllocati > on|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieBiosTrainEnable|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieHotPlugEnable|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAcpiHotPlugEnable|0 > x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MultiCastEnable|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.McastBaseAddrRegion|0 > x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.McastIndexPosition|0xc > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.McastNumGroup|0x8 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[0]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[1]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[2]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[3]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[4]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[5]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[6]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[7]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[8]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[9]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[10]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[11]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[12]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[13]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[14]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[15]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[16]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[17]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[18]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[19]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[20]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[21]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[22]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[23]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[24]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[25]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[26]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[27]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[28]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[29]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[30]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[31]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[32]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[33]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[34]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[35]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[36]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[37]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[38]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[39]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[40]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[41]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[42]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[43]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[44]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[45]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[46]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[47]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[48]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[49]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[50]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[51]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[52]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[53]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[54]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[55]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[56]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[57]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[58]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[59]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[60]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[61]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[62]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[63]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[64]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[65]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[66]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[67]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[68]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[69]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[70]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[71]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[72]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[73]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[74]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[75]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[76]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[77]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[78]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[79]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[80]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[81]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[82]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[83]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NoSnoopRdCfg|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NoSnoopWrCfg|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MaxReadCompCombSize > |0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ProblematicPort|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DmiAllocatingFlow|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAllocatingFlow|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HaltOnDmiDegraded|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RxClockWA|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.GlobalPme2AckTOCtrl|0x > 0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MctpEn|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PCUF6Hide|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EN1K|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DualCvIoFlow|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.CoherentReadPart|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.CoherentReadFull|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.CompletionTimeoutGlob > al|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.CompletionTimeoutGlob > alValue|0x9 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieGlobalAspm|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.StopAndScream|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SnoopResponseHoldOff| > 0xf > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PCIe_LTR|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieExtendedTagField|0x > 1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PCIe_AtomicOpReq|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxReadRequestSiz > e|0x7 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieRelaxedOrdering|0x > 1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ConfigIOU0[0]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ConfigIOU1[0]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ConfigIOU2[0]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ConfigMCP0[0]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ConfigMCP1[0]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.CompletionTimeout[0]|0 > x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.CompletionTimeoutValu > e[0]|0x9 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RpCorrectableErrorEsc[0] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RpUncorrectableNonFata > lErrorEsc[0]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RpUncorrectableFatalErr > orEsc[0]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ConfigIOU0[1]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ConfigIOU1[1]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ConfigIOU2[1]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ConfigMCP0[1]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ConfigMCP1[1]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.CompletionTimeout[1]|0 > x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.CompletionTimeoutValu > e[1]|0x9 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RpCorrectableErrorEsc[1] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RpUncorrectableNonFata > lErrorEsc[1]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RpUncorrectableFatalErr > orEsc[1]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DevPresIoApicIio[0]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DevPresIoApicIio[1]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DevPresIoApicIio[2]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DevPresIoApicIio[3]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DevPresIoApicIio[4]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DevPresIoApicIio[5]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DevPresIoApicIio[6]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DevPresIoApicIio[7]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DevPresIoApicIio[8]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DevPresIoApicIio[9]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DevPresIoApicIio[10]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DevPresIoApicIio[11]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DevPresIoApicIio[12]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DevPresIoApicIio[13]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DevPresIoApicIio[14]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DevPresIoApicIio[15]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DevPresIoApicIio[16]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DevPresIoApicIio[17]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DevPresIoApicIio[18]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DevPresIoApicIio[19]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DevPresIoApicIio[20]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DevPresIoApicIio[21]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DevPresIoApicIio[22]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DevPresIoApicIio[23]|0x > 0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VTdSupport|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InterruptRemap|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PassThroughDma|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ATS|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IioPresent[0]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IioPresent[1]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PostedInterrupt|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.CoherencySupport|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDEnabled[0]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[0]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[1]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[2]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[3]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarSz[0]|0x19 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarAttr[0]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarAttr[0]|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBarSz1[0]|0x1 > 9 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar1Attr[0]|0x > 1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBarSz2[0]|0x1 > 4 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar2Attr[0]|0x > 1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDEnabled[1]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[4]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[5]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[6]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[7]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarSz[1]|0x19 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarAttr[1]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarAttr[1]|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBarSz1[1]|0x1 > 9 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar1Attr[1]|0x > 1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBarSz2[1]|0x1 > 4 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar2Attr[1]|0x > 1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar2Attr[1]|0x > 1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDEnabled[2]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[8]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[9]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[10]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[11]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarSz[2]|0x19 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarAttr[2]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarAttr[2]|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBarSz1[2]|0x1 > 9 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar1Attr[2]|0x > 1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBarSz2[2]|0x1 > 4 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar2Attr[2]|0x > 1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar2Attr[2]|0x > 1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDEnabled[3]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[12]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[13]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[14]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[15]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarSz[3]|0x19 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarAttr[3]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarAttr[3]|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBarSz1[3]|0x1 > 9 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar1Attr[3]|0x > 1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBarSz2[3]|0x1 > 4 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar2Attr[3]|0x > 1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar2Attr[3]|0x > 1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDEnabled[4]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[16]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[17]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[18]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[19]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarSz[4]|0x19 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarAttr[4]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarAttr[4]|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBarSz1[4]|0x1 > 9 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar1Attr[4]|0x > 1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBarSz2[4]|0x1 > 4 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar2Attr[4]|0x > 1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar2Attr[4]|0x > 1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDEnabled[5]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[20]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[21]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[22]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[23]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarSz[5]|0x19 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarAttr[5]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarAttr[5]|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBarSz1[5]|0x1 > 9 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar1Attr[5]|0x > 1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBarSz2[5]|0x1 > 4 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar2Attr[5]|0x > 1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar2Attr[5]|0x > 1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDEnabled[6]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[24]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[25]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[26]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[27]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarSz[6]|0x19 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarAttr[6]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarAttr[6]|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBarSz1[6]|0x1 > 9 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar1Attr[6]|0x > 1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBarSz2[6]|0x1 > 4 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar2Attr[6]|0x > 1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar2Attr[6]|0x > 1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDEnabled[7]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[28]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[29]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[30]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[31]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarSz[7]|0x19 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarAttr[7]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarAttr[7]|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBarSz1[7]|0x1 > 9 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar1Attr[7]|0x > 1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBarSz2[7]|0x1 > 4 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar2Attr[7]|0x > 1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar2Attr[7]|0x > 1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDEnabled[8]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[32]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[33]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[34]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[35]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarSz[8]|0x19 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarAttr[8]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarAttr[8]|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBarSz1[8]|0x1 > 9 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar1Attr[8]|0x > 1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBarSz2[8]|0x1 > 4 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar2Attr[8]|0x > 1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar2Attr[8]|0x > 1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDEnabled[9]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[36]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[37]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[38]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[39]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarSz[9]|0x19 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarAttr[9]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarAttr[9]|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBarSz1[9]|0x1 > 9 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar1Attr[9]|0x > 1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBarSz2[9]|0x1 > 4 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar2Attr[9]|0x > 1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar2Attr[9]|0x > 1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDEnabled[10]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[40]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[41]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[42]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[43]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarSz[10]|0x19 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarAttr[10]|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarAttr[10]|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBarSz1[10]|0x > 19 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar1Attr[10]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBarSz2[10]|0x > 14 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar2Attr[10]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar2Attr[10]|0 > x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDEnabled[11]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[44]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[45]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[46]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[47]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarSz[11]|0x19 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarAttr[11]|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarAttr[11]|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBarSz1[11]|0x > 19 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar1Attr[11]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBarSz2[11]|0x > 14 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar2Attr[11]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar2Attr[11]|0 > x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAICEnabled[0]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAICEnabled[1]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAICEnabled[2]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAICEnabled[3]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAICEnabled[4]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAICEnabled[5]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAICEnabled[6]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAICEnabled[7]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAICEnabled[8]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAICEnabled[9]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAICEnabled[10]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAICEnabled[11]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieSlotOprom1|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieSlotOprom2|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieSlotOprom3|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieSlotOprom4|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieSlotOprom5|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieSlotOprom6|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieSlotOprom7|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieSlotOprom8|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisableTPH|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PrioritizeTPH|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.CbRelaxedOrdering|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[0]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[0]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[1]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[1]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[2]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[2]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[3]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[3]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[4]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[4]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[5]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[5]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[6]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[6]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[7]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[7]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[8]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[8]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[9]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[9]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[10]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[10]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[11]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[11]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[12]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[12]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[13]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[13]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[14]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[14]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[15]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[15]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[16]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[16]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[17]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[17]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[18]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[18]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[19]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[19]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[20]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[20]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[21]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[21]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[22]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[22]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[23]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[23]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[24]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[24]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[25]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[25]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[26]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[26]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[27]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[27]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[28]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[28]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[29]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[29]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[30]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[30]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[31]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[31]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoEnable|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoLtssmLogger|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoLtssmLoggerStop|0x9 > 9 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoLtssmLoggerSpeed|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoLtssmLoggerMask|0x > ff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoJitterLogger|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[0 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[2 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[3 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[4 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[5 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[6 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[7 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[8 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[9 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 0]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 1]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 2]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 3]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 4]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 5]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 6]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 7]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 8]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 9]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[2 > 0]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[2 > 1]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[2 > 2]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[2 > 3]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[2 > 4]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[2 > 5]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[2 > 6]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[2 > 7]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[2 > 8]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[2 > 9]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[3 > 0]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[3 > 1]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[3 > 2]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[3 > 3]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[3 > 4]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[3 > 5]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[3 > 6]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[3 > 7]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[3 > 8]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[3 > 9]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[4 > 0]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[4 > 1]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[4 > 2]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[4 > 3]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[4 > 4]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[4 > 5]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[4 > 6]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[4 > 7]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[4 > 8]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[4 > 9]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[5 > 0]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[5 > 1]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[5 > 2]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[5 > 3]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[5 > 4]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[5 > 5]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[5 > 6]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[5 > 7]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[5 > 8]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[5 > 9]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[6 > 0]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[6 > 1]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[6 > 2]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[6 > 3]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[6 > 4]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[6 > 5]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[6 > 6]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[6 > 7]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[6 > 8]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[6 > 9]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[7 > 0]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[7 > 1]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[7 > 2]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[7 > 3]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[7 > 4]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[7 > 5]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[7 > 6]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[7 > 7]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[7 > 8]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[7 > 9]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[8 > 0]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[8 > 1]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[8 > 2]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[8 > 3]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[8 > 4]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[8 > 5]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[8 > 6]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[8 > 7]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[8 > 8]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[8 > 9]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[9 > 0]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[9 > 1]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[9 > 2]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[9 > 3]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[9 > 4]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[9 > 5]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[9 > 6]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[9 > 7]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[9 > 8]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[9 > 9]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 00]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 01]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 02]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 03]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 04]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 05]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 06]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 07]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 08]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 09]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 10]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 11]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 12]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 13]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 14]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 15]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 16]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 17]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 18]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 19]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 20]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 21]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 22]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 23]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 24]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 25]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 26]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 27]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 28]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 29]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 30]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 31]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 32]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 33]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 34]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 35]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 36]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 37]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 38]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 39]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 40]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 41]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 42]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 43]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 44]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 45]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 46]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 47]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 48]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 49]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 50]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 51]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 52]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 53]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 54]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 55]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 56]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 57]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 58]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 59]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 60]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 61]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 62]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 63]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 64]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 65]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 66]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 67]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 68]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 69]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 70]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 71]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 72]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 73]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 74]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 75]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 76]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 77]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 78]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 79]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 80]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 81]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 82]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 83]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 84]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 85]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 86]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 87]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 88]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 89]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 90]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1 > 91]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[ > 0]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pre > cursor[0]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cur > sor[0]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pos > tcursor[0]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pre > cursor[0]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cur > sor[0]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pos > tcursor[0]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[0]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[0]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[0]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[0]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[0] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[ > 1]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pre > cursor[1]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cur > sor[1]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pos > tcursor[1]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pre > cursor[1]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cur > sor[1]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pos > tcursor[1]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[1]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[1]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[1]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[1]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[1] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[ > 2]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pre > cursor[2]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cur > sor[2]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pos > tcursor[2]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pre > cursor[2]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cur > sor[2]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pos > tcursor[2]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[2]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[2]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[2]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[2]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[2] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[ > 3]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pre > cursor[3]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cur > sor[3]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pos > tcursor[3]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pre > cursor[3]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cur > sor[3]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pos > tcursor[3]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[3]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[3]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[3]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[3]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[3] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[ > 4]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pre > cursor[4]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cur > sor[4]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pos > tcursor[4]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pre > cursor[4]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cur > sor[4]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pos > tcursor[4]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[4]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[4]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[4]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[4]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[4] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[ > 5]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pre > cursor[5]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cur > sor[5]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pos > tcursor[5]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pre > cursor[5]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cur > sor[5]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pos > tcursor[5]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[5]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[5]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[5]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[5]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[5] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[ > 6]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pre > cursor[6]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cur > sor[6]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pos > tcursor[6]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pre > cursor[6]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cur > sor[6]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pos > tcursor[6]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[6]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[6]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[6]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[6]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[6] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[ > 7]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pre > cursor[7]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cur > sor[7]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pos > tcursor[7]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pre > cursor[7]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cur > sor[7]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pos > tcursor[7]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[7]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[7]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[7]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[7]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[7] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[ > 8]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pre > cursor[8]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cur > sor[8]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pos > tcursor[8]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pre > cursor[8]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cur > sor[8]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pos > tcursor[8]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[8]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[8]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[8]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[8]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[8] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[ > 9]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pre > cursor[9]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cur > sor[9]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pos > tcursor[9]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pre > cursor[9]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cur > sor[9]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pos > tcursor[9]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[9]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[9]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[9]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[9]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[9] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[ > 10]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pre > cursor[10]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cur > sor[10]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pos > tcursor[10]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pre > cursor[10]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cur > sor[10]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pos > tcursor[10]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[10]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[10]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[10]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[10]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[10 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[ > 11]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pre > cursor[11]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cur > sor[11]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pos > tcursor[11]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pre > cursor[11]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cur > sor[11]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pos > tcursor[11]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[11]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[11]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[11]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[11]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[11 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[ > 12]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pre > cursor[12]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cur > sor[12]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pos > tcursor[12]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pre > cursor[12]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cur > sor[12]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pos > tcursor[12]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[12]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[12]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[12]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[12]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[12 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[ > 13]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pre > cursor[13]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cur > sor[13]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pos > tcursor[13]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pre > cursor[13]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cur > sor[13]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pos > tcursor[13]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[13]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[13]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[13]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[13]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[13 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[ > 14]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pre > cursor[14]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cur > sor[14]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pos > tcursor[14]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pre > cursor[14]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cur > sor[14]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pos > tcursor[14]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[14]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[14]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[14]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[14]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[14 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[ > 15]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pre > cursor[15]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cur > sor[15]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pos > tcursor[15]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pre > cursor[15]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cur > sor[15]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pos > tcursor[15]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[15]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[15]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[15]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[15]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[15 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[ > 16]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pre > cursor[16]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cur > sor[16]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pos > tcursor[16]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pre > cursor[16]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cur > sor[16]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pos > tcursor[16]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[16]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[16]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[16]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[16]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[16 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[ > 17]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pre > cursor[17]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cur > sor[17]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pos > tcursor[17]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pre > cursor[17]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cur > sor[17]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pos > tcursor[17]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[17]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[17]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[17]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[17]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[17 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[ > 18]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pre > cursor[18]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cur > sor[18]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pos > tcursor[18]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pre > cursor[18]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cur > sor[18]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pos > tcursor[18]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[18]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[18]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[18]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[18]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[18 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[ > 19]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pre > cursor[19]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cur > sor[19]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pos > tcursor[19]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pre > cursor[19]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cur > sor[19]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pos > tcursor[19]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[19]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[19]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[19]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[19]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[19 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[ > 20]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pre > cursor[20]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cur > sor[20]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pos > tcursor[20]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pre > cursor[20]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cur > sor[20]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pos > tcursor[20]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[20]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[20]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[20]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[20]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[20 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[ > 21]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pre > cursor[21]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cur > sor[21]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pos > tcursor[21]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pre > cursor[21]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cur > sor[21]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pos > tcursor[21]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[21]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[21]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[21]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[21]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[21 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[ > 22]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pre > cursor[22]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cur > sor[22]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pos > tcursor[22]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pre > cursor[22]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cur > sor[22]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pos > tcursor[22]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[22]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[22]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[22]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[22]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[22 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[ > 23]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pre > cursor[23]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cur > sor[23]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pos > tcursor[23]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pre > cursor[23]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cur > sor[23]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pos > tcursor[23]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[23]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[23]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[23]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[23]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[23 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[ > 24]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pre > cursor[24]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cur > sor[24]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pos > tcursor[24]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pre > cursor[24]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cur > sor[24]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pos > tcursor[24]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[24]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[24]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[24]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[24]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[24 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[ > 25]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pre > cursor[25]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cur > sor[25]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pos > tcursor[25]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pre > cursor[25]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cur > sor[25]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pos > tcursor[25]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[25]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[25]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[25]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[25]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[25 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[ > 26]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pre > cursor[26]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cur > sor[26]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pos > tcursor[26]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pre > cursor[26]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cur > sor[26]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pos > tcursor[26]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[26]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[26]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[26]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[26]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[26 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[ > 27]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pre > cursor[27]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cur > sor[27]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pos > tcursor[27]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pre > cursor[27]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cur > sor[27]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pos > tcursor[27]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[27]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[27]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[27]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[27]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[27 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[ > 28]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pre > cursor[28]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cur > sor[28]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pos > tcursor[28]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pre > cursor[28]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cur > sor[28]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pos > tcursor[28]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[28]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[28]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[28]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[28]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[28 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[ > 29]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pre > cursor[29]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cur > sor[29]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pos > tcursor[29]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pre > cursor[29]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cur > sor[29]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pos > tcursor[29]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[29]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[29]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[29]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[29]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[29 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[ > 30]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pre > cursor[30]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cur > sor[30]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pos > tcursor[30]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pre > cursor[30]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cur > sor[30]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pos > tcursor[30]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[30]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[30]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[30]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[30]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[30 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[ > 31]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pre > cursor[31]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cur > sor[31]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pos > tcursor[31]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pre > cursor[31]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cur > sor[31]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pos > tcursor[31]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[31]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[31]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[31]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[31]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[31 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[ > 32]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pre > cursor[32]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cur > sor[32]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pos > tcursor[32]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pre > cursor[32]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cur > sor[32]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pos > tcursor[32]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[32]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[32]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[32]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[32]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[32 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[ > 33]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pre > cursor[33]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cur > sor[33]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pos > tcursor[33]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pre > cursor[33]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cur > sor[33]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pos > tcursor[33]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[33]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[33]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[33]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[33]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[33 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[ > 34]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pre > cursor[34]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cur > sor[34]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pos > tcursor[34]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pre > cursor[34]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cur > sor[34]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pos > tcursor[34]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[34]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[34]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[34]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[34]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[34 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[ > 35]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pre > cursor[35]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cur > sor[35]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pos > tcursor[35]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pre > cursor[35]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cur > sor[35]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pos > tcursor[35]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[35]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[35]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[35]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[35]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[35 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[ > 36]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pre > cursor[36]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cur > sor[36]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pos > tcursor[36]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pre > cursor[36]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cur > sor[36]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pos > tcursor[36]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[36]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[36]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[36]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[36]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[36 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[ > 37]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pre > cursor[37]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cur > sor[37]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pos > tcursor[37]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pre > cursor[37]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cur > sor[37]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pos > tcursor[37]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[37]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[37]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[37]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[37]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[37 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[ > 38]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pre > cursor[38]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cur > sor[38]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pos > tcursor[38]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pre > cursor[38]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cur > sor[38]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pos > tcursor[38]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[38]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[38]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[38]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[38]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[38 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[ > 39]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pre > cursor[39]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cur > sor[39]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pos > tcursor[39]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pre > cursor[39]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cur > sor[39]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pos > tcursor[39]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[39]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[39]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[39]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[39]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[39 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[ > 40]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pre > cursor[40]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cur > sor[40]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pos > tcursor[40]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pre > cursor[40]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cur > sor[40]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pos > tcursor[40]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[40]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[40]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[40]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[40]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[40 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[ > 41]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pre > cursor[41]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cur > sor[41]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pos > tcursor[41]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pre > cursor[41]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cur > sor[41]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pos > tcursor[41]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[41]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[41]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[41]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[41]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[41 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[ > 42]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pre > cursor[42]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cur > sor[42]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pos > tcursor[42]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pre > cursor[42]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cur > sor[42]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pos > tcursor[42]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[42]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[42]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[42]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[42]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[42 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[ > 43]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pre > cursor[43]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cur > sor[43]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pos > tcursor[43]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pre > cursor[43]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cur > sor[43]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pos > tcursor[43]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[43]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[43]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[43]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[43]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[43 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[ > 44]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pre > cursor[44]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cur > sor[44]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pos > tcursor[44]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pre > cursor[44]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cur > sor[44]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pos > tcursor[44]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[44]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[44]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[44]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[44]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[44 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[ > 45]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pre > cursor[45]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cur > sor[45]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pos > tcursor[45]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pre > cursor[45]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cur > sor[45]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pos > tcursor[45]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[45]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[45]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[45]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[45]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[45 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[ > 46]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pre > cursor[46]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cur > sor[46]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pos > tcursor[46]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pre > cursor[46]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cur > sor[46]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pos > tcursor[46]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[46]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[46]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[46]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[46]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[46 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[ > 47]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pre > cursor[47]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cur > sor[47]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pos > tcursor[47]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pre > cursor[47]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cur > sor[47]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pos > tcursor[47]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[47]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[47]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[47]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[47]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[47 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[ > 48]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pre > cursor[48]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cur > sor[48]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pos > tcursor[48]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pre > cursor[48]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cur > sor[48]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pos > tcursor[48]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[48]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[48]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[48]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[48]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[48 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[ > 49]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pre > cursor[49]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cur > sor[49]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pos > tcursor[49]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pre > cursor[49]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cur > sor[49]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pos > tcursor[49]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[49]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[49]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[49]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[49]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[49 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[ > 50]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pre > cursor[50]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cur > sor[50]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pos > tcursor[50]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pre > cursor[50]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cur > sor[50]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pos > tcursor[50]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[50]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[50]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[50]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[50]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[50 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[ > 51]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pre > cursor[51]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cur > sor[51]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pos > tcursor[51]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pre > cursor[51]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cur > sor[51]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pos > tcursor[51]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[51]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[51]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[51]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[51]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[51 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[ > 52]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pre > cursor[52]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cur > sor[52]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pos > tcursor[52]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pre > cursor[52]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cur > sor[52]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pos > tcursor[52]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[52]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[52]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[52]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[52]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[52 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[ > 53]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pre > cursor[53]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cur > sor[53]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pos > tcursor[53]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pre > cursor[53]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cur > sor[53]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pos > tcursor[53]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[53]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[53]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[53]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[53]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[53 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[ > 54]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pre > cursor[54]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cur > sor[54]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pos > tcursor[54]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pre > cursor[54]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cur > sor[54]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pos > tcursor[54]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[54]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[54]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[54]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[54]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[54 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[ > 55]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pre > cursor[55]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cur > sor[55]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pos > tcursor[55]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pre > cursor[55]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cur > sor[55]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pos > tcursor[55]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[55]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[55]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[55]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[55]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[55 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[ > 56]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pre > cursor[56]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cur > sor[56]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pos > tcursor[56]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pre > cursor[56]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cur > sor[56]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pos > tcursor[56]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[56]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[56]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[56]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[56]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[56 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[ > 57]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pre > cursor[57]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cur > sor[57]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pos > tcursor[57]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pre > cursor[57]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cur > sor[57]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pos > tcursor[57]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[57]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[57]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[57]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[57]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[57 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[ > 58]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pre > cursor[58]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cur > sor[58]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pos > tcursor[58]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pre > cursor[58]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cur > sor[58]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pos > tcursor[58]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[58]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[58]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[58]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[58]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[58 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[ > 59]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pre > cursor[59]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cur > sor[59]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pos > tcursor[59]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pre > cursor[59]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cur > sor[59]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pos > tcursor[59]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[59]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[59]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[59]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[59]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[59 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[ > 60]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pre > cursor[60]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cur > sor[60]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pos > tcursor[60]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pre > cursor[60]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cur > sor[60]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pos > tcursor[60]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[60]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[60]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[60]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[60]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[60 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[ > 61]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pre > cursor[61]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cur > sor[61]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pos > tcursor[61]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pre > cursor[61]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cur > sor[61]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pos > tcursor[61]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[61]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[61]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[61]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[61]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[61 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[ > 62]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pre > cursor[62]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cur > sor[62]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pos > tcursor[62]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pre > cursor[62]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cur > sor[62]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pos > tcursor[62]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[62]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[62]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[62]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[62]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[62 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[ > 63]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pre > cursor[63]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cur > sor[63]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pos > tcursor[63]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pre > cursor[63]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cur > sor[63]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pos > tcursor[63]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[63]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[63]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[63]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[63]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[63 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[ > 64]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pre > cursor[64]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cur > sor[64]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pos > tcursor[64]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pre > cursor[64]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cur > sor[64]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pos > tcursor[64]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[64]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[64]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[64]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[64]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[64 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[ > 65]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pre > cursor[65]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cur > sor[65]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pos > tcursor[65]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pre > cursor[65]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cur > sor[65]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pos > tcursor[65]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[65]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[65]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[65]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[65]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[65 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[ > 66]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pre > cursor[66]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cur > sor[66]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pos > tcursor[66]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pre > cursor[66]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cur > sor[66]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pos > tcursor[66]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[66]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[66]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[66]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[66]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[66 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[ > 67]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pre > cursor[67]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cur > sor[67]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pos > tcursor[67]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pre > cursor[67]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cur > sor[67]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pos > tcursor[67]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[67]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[67]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[67]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[67]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[67 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[ > 68]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pre > cursor[68]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cur > sor[68]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pos > tcursor[68]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pre > cursor[68]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cur > sor[68]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pos > tcursor[68]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[68]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[68]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[68]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[68]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[68 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[ > 69]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pre > cursor[69]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cur > sor[69]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pos > tcursor[69]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pre > cursor[69]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cur > sor[69]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pos > tcursor[69]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[69]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[69]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[69]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[69]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[69 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[ > 70]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pre > cursor[70]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cur > sor[70]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pos > tcursor[70]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pre > cursor[70]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cur > sor[70]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pos > tcursor[70]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[70]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[70]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[70]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[70]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[70 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[ > 71]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pre > cursor[71]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cur > sor[71]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pos > tcursor[71]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pre > cursor[71]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cur > sor[71]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pos > tcursor[71]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[71]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[71]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[71]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[71]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[71 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[ > 72]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pre > cursor[72]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cur > sor[72]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pos > tcursor[72]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pre > cursor[72]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cur > sor[72]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pos > tcursor[72]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[72]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[72]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[72]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[72]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[72 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[ > 73]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pre > cursor[73]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cur > sor[73]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pos > tcursor[73]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pre > cursor[73]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cur > sor[73]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pos > tcursor[73]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[73]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[73]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[73]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[73]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[73 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[ > 74]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pre > cursor[74]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cur > sor[74]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pos > tcursor[74]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pre > cursor[74]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cur > sor[74]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pos > tcursor[74]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[74]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[74]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[74]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[74]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[74 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[ > 75]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pre > cursor[75]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cur > sor[75]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pos > tcursor[75]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pre > cursor[75]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cur > sor[75]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pos > tcursor[75]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[75]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[75]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[75]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[75]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[75 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[ > 76]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pre > cursor[76]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cur > sor[76]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pos > tcursor[76]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pre > cursor[76]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cur > sor[76]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pos > tcursor[76]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[76]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[76]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[76]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[76]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[76 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[ > 77]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pre > cursor[77]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cur > sor[77]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pos > tcursor[77]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pre > cursor[77]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cur > sor[77]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pos > tcursor[77]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[77]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[77]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[77]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[77]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[77 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[ > 78]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pre > cursor[78]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cur > sor[78]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pos > tcursor[78]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pre > cursor[78]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cur > sor[78]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pos > tcursor[78]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[78]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[78]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[78]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[78]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[78 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[ > 79]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pre > cursor[79]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cur > sor[79]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pos > tcursor[79]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pre > cursor[79]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cur > sor[79]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pos > tcursor[79]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[79]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[79]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[79]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[79]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[79 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[ > 80]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pre > cursor[80]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cur > sor[80]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pos > tcursor[80]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pre > cursor[80]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cur > sor[80]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pos > tcursor[80]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[80]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[80]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[80]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[80]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[80 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[ > 81]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pre > cursor[81]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cur > sor[81]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pos > tcursor[81]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pre > cursor[81]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cur > sor[81]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pos > tcursor[81]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[81]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[81]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[81]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[81]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[81 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[ > 82]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pre > cursor[82]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cur > sor[82]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pos > tcursor[82]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pre > cursor[82]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cur > sor[82]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pos > tcursor[82]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[82]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[82]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[82]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[82]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[82 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[ > 83]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pre > cursor[83]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cur > sor[83]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Pos > tcursor[83]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pre > cursor[83]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cur > sor[83]|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Pos > tcursor[83]|0xb > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[83]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[83]|0xff > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[83]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[83]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[83 > ]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[0]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[0 > ]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[0]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[0]|0x > 1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[0]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[0]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[0]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[0]|0x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[0]|0x4 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[0]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[0]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[0]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[0]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[0]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[0]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[0]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[0]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[0]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[0]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[0]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[0]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedReques > ts[0]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[0]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[0]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[0]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[0]|0x6 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[1]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[1]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[1]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[1]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[1]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[1 > ]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[1]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[1]|0x > 1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[1]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[1]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[1]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[1]|0x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[1]|0x4 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[1]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[1]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[1]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[1]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[1]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[1]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[1]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[1]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[1]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[1]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[1]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[1]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[1]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[1]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedReques > ts[1]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[1]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[1]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[1]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[1]|0x6 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbPpd[0]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeOverride[0]|0 > x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbSplitBar[0]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar23[0]|0x1 > 6 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar4[0]|0xc > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar5[0]|0xc > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar45[0]|0x1 > 6 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar23[0]|0x1 > 6 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar4[0]|0xc > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar5[0]|0xc > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar45[0]|0x1 > 6 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbSBar01Prefetch[0]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbXlinkCtlOverride[0]|0 > x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[1]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[2]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[2]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[2]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[2]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[2]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[2 > ]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[2]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[2]|0x > 1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[2]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[2]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[2]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[2]|0x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[2]|0x4 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[2]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[2]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[2]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[2]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[2]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[2]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[2]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[2]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[2]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[2]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[2]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[2]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[2]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[2]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedReques > ts[2]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[2]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[2]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[2]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[2]|0x6 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[2]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[3]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[3]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[3]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[3]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[3]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[3 > ]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[3]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[3]|0x > 1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[3]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[3]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[3]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[3]|0x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[3]|0x4 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[3]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[3]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[3]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[3]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[3]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[3]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[3]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[3]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[3]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[3]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[3]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[3]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[3]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[3]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedReques > ts[3]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[3]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[3]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[3]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[3]|0x6 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[3]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[4]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[4]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[4]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[4]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[4]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[4 > ]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[4]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[4]|0x > 1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[4]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[4]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[4]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[4]|0x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[4]|0x4 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[4]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[4]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[4]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[4]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[4]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[4]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[4]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[4]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[4]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[4]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[4]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[4]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[4]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[4]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedReques > ts[4]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[4]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[4]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[4]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[4]|0x6 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[4]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[5]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[5]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[5]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[5]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[5]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[5 > ]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[5]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[5]|0x > 1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[5]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[5]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[5]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[5]|0x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[5]|0x4 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[5]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[5]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[5]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[5]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[5]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[5]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[5]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[5]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[5]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[5]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[5]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[5]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[5]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[5]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedReques > ts[5]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[5]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[5]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[5]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[5]|0x6 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbPpd[1]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeOverride[1]|0 > x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbSplitBar[1]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar23[1]|0x1 > 6 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar4[1]|0xc > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar5[1]|0xc > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar45[1]|0x1 > 6 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar23[1]|0x1 > 6 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar4[1]|0xc > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar5[1]|0xc > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar45[1]|0x1 > 6 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbSBar01Prefetch[1]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbXlinkCtlOverride[1]|0 > x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[5]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[6]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[6]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[6]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[6]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[6]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[6 > ]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[6]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[6]|0x > 1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[6]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[6]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[6]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[6]|0x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[6]|0x4 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[6]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[6]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[6]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[6]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[6]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[6]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[6]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[6]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[6]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[6]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[6]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[6]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[6]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[6]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedReques > ts[6]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[6]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[6]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[6]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[6]|0x6 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[6]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[7]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[7]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[7]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[7]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[7]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[7 > ]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[7]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[7]|0x > 1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[7]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[7]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[7]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[7]|0x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[7]|0x4 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[7]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[7]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[7]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[7]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[7]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[7]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[7]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[7]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[7]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[7]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[7]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[7]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[7]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[7]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedReques > ts[7]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[7]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[7]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[7]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[7]|0x6 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[7]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[8]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[8]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[8]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[8]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[8]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[8 > ]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[8]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[8]|0x > 1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[8]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[8]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[8]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[8]|0x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[8]|0x4 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[8]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[8]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[8]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[8]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[8]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[8]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[8]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[8]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[8]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[8]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[8]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[8]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[8]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[8]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedReques > ts[8]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[8]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[8]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[8]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[8]|0x6 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[8]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[9]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[9]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[9]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[9]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[9]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[9 > ]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[9]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[9]|0x > 1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[9]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[9]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[9]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[9]|0x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[9]|0x4 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[9]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[9]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[9]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[9]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[9]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[9]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[9]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[9]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[9]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[9]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[9]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[9]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[9]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[9]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedReques > ts[9]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[9]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[9]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[9]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[9]|0x6 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbPpd[2]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeOverride[2]|0 > x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbSplitBar[2]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar23[2]|0x1 > 6 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar4[2]|0xc > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar5[2]|0xc > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar45[2]|0x1 > 6 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar23[2]|0x1 > 6 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar4[2]|0xc > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar5[2]|0xc > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar45[2]|0x1 > 6 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbSBar01Prefetch[2]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbXlinkCtlOverride[2]|0 > x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[9]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[10]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[10]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[10]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[10]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[10]|0 > x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[1 > 0]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[10]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[10]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[10]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[10]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[10]|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[10]|0x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[10]|0x4 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[10]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[10]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[10]|0x > 0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[10]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[10]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[10]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[10]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[10]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[10]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[10]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[10]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[10]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[10]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[10]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedReques > ts[10]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[10]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[10]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[10]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[10]|0x6 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[10]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[11]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[11]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[11]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[11]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[11]|0 > x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[1 > 1]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[11]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[11]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[11]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[11]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[11]|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[11]|0x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[11]|0x4 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[11]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[11]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[11]|0x > 0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[11]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[11]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[11]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[11]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[11]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[11]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[11]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[11]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[11]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[11]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[11]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedReques > ts[11]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[11]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[11]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[11]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[11]|0x6 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[11]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[12]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[12]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[12]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[12]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[12]|0 > x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[1 > 2]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[12]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[12]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[12]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[12]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[12]|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[12]|0x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[12]|0x4 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[12]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[12]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[12]|0x > 0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[12]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[12]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[12]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[12]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[12]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[12]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[12]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[12]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[12]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[12]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[12]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedReques > ts[12]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[12]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[12]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[12]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[12]|0x6 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[12]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[13]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[13]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[13]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[13]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[13]|0 > x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[1 > 3]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[13]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[13]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[13]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[13]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[13]|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[13]|0x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[13]|0x4 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[13]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[13]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[13]|0x > 0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[13]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[13]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[13]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[13]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[13]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[13]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[13]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[13]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[13]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[13]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[13]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedReques > ts[13]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[13]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[13]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[13]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[13]|0x6 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[13]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[14]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[14]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[14]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[14]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[14]|0 > x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[1 > 4]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[14]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[14]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[14]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[14]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[14]|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[14]|0x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[14]|0x4 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[14]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[14]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[14]|0x > 0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[14]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[14]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[14]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[14]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[14]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[14]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[14]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[14]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[14]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[14]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[14]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedReques > ts[14]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[14]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[14]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[14]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[14]|0x6 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[14]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[15]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[15]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[15]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[15]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[15]|0 > x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[1 > 5]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[15]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[15]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[15]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[15]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[15]|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[15]|0x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[15]|0x4 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[15]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[15]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[15]|0x > 0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[15]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[15]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[15]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[15]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[15]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[15]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[15]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[15]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[15]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[15]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[15]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedReques > ts[15]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[15]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[15]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[15]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[15]|0x6 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[15]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[16]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[16]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[16]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[16]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[16]|0 > x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[1 > 6]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[16]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[16]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[16]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[16]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[16]|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[16]|0x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[16]|0x4 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[16]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[16]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[16]|0x > 0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[16]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[16]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[16]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[16]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[16]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[16]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[16]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[16]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[16]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[16]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[16]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedReques > ts[16]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[16]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[16]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[16]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[16]|0x6 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[16]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[17]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[17]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[17]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[17]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[17]|0 > x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[1 > 7]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[17]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[17]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[17]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[17]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[17]|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[17]|0x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[17]|0x4 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[17]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[17]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[17]|0x > 0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[17]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[17]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[17]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[17]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[17]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[17]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[17]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[17]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[17]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[17]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[17]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedReques > ts[17]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[17]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[17]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[17]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[17]|0x6 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[17]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[18]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[18]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[18]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[18]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[18]|0 > x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[1 > 8]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[18]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[18]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[18]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[18]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[18]|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[18]|0x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[18]|0x4 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[18]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[18]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[18]|0x > 0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[18]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[18]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[18]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[18]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[18]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[18]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[18]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[18]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[18]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[18]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[18]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedReques > ts[18]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[18]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[18]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[18]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[18]|0x6 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[18]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[19]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[19]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[19]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[19]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[19]|0 > x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[1 > 9]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[19]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[19]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[19]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[19]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[19]|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[19]|0x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[19]|0x4 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[19]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[19]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[19]|0x > 0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[19]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[19]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[19]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[19]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[19]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[19]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[19]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[19]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[19]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[19]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[19]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedReques > ts[19]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[19]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[19]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[19]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[19]|0x6 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[19]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[20]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[20]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[20]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[20]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[20]|0 > x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[2 > 0]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[20]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[20]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[20]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[20]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[20]|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[20]|0x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[20]|0x4 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[20]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[20]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[20]|0x > 0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[20]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[20]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[20]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[20]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[20]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[20]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[20]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[20]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[20]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[20]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[20]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedReques > ts[20]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[20]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[20]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[20]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[20]|0x6 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[20]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[21]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[21]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[21]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[21]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[21]|0 > x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[2 > 1]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[21]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[21]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[21]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[21]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[21]|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[21]|0x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[21]|0x4 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[21]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[21]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[21]|0x > 0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[21]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[21]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[21]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[21]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[21]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[21]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[21]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[21]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[21]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[21]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[21]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedReques > ts[21]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[21]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[21]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[21]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[21]|0x6 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[21]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[22]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[22]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[22]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[22]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[22]|0 > x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[2 > 2]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[22]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[22]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[22]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[22]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[22]|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[22]|0x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[22]|0x4 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[22]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[22]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[22]|0x > 0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[22]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[22]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[22]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[22]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[22]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[22]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[22]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[22]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[22]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[22]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[22]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedReques > ts[22]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[22]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[22]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[22]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[22]|0x6 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbPpd[3]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeOverride[3]|0 > x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbSplitBar[3]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar23[3]|0x1 > 6 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar4[3]|0xc > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar5[3]|0xc > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar45[3]|0x1 > 6 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar23[3]|0x1 > 6 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar4[3]|0xc > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar5[3]|0xc > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar45[3]|0x1 > 6 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbSBar01Prefetch[3]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbXlinkCtlOverride[3]|0 > x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[22]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[23]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[23]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[23]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[23]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[23]|0 > x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[2 > 3]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[23]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[23]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[23]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[23]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[23]|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[23]|0x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[23]|0x4 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[23]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[23]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[23]|0x > 0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[23]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[23]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[23]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[23]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[23]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[23]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[23]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[23]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[23]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[23]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[23]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedReques > ts[23]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[23]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[23]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[23]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[23]|0x6 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[23]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[24]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[24]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[24]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[24]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[24]|0 > x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[2 > 4]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[24]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[24]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[24]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[24]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[24]|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[24]|0x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[24]|0x4 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[24]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[24]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[24]|0x > 0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[24]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[24]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[24]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[24]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[24]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[24]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[24]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[24]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[24]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[24]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[24]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedReques > ts[24]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[24]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[24]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[24]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[24]|0x6 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[24]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[25]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[25]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[25]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[25]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[25]|0 > x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[2 > 5]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[25]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[25]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[25]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[25]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[25]|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[25]|0x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[25]|0x4 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[25]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[25]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[25]|0x > 0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[25]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[25]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[25]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[25]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[25]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[25]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[25]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[25]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[25]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[25]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[25]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedReques > ts[25]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[25]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[25]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[25]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[25]|0x6 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[25]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[26]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[26]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[26]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[26]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[26]|0 > x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[2 > 6]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[26]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[26]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[26]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[26]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[26]|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[26]|0x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[26]|0x4 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[26]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[26]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[26]|0x > 0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[26]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[26]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[26]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[26]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[26]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[26]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[26]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[26]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[26]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[26]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[26]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedReques > ts[26]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[26]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[26]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[26]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[26]|0x6 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbPpd[4]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeOverride[4]|0 > x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbSplitBar[4]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar23[4]|0x1 > 6 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar4[4]|0xc > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar5[4]|0xc > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar45[4]|0x1 > 6 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar23[4]|0x1 > 6 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar4[4]|0xc > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar5[4]|0xc > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar45[4]|0x1 > 6 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbSBar01Prefetch[4]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbXlinkCtlOverride[4]|0 > x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[26]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[27]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[27]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[27]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[27]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[27]|0 > x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[2 > 7]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[27]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[27]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[27]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[27]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[27]|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[27]|0x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[27]|0x4 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[27]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[27]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[27]|0x > 0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[27]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[27]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[27]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[27]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[27]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[27]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[27]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[27]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[27]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[27]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[27]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedReques > ts[27]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[27]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[27]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[27]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[27]|0x6 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[27]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[28]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[28]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[28]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[28]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[28]|0 > x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[2 > 8]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[28]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[28]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[28]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[28]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[28]|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[28]|0x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[28]|0x4 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[28]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[28]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[28]|0x > 0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[28]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[28]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[28]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[28]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[28]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[28]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[28]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[28]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[28]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[28]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[28]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedReques > ts[28]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[28]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[28]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[28]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[28]|0x6 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[28]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[29]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[29]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[29]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[29]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[29]|0 > x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[2 > 9]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[29]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[29]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[29]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[29]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[29]|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[29]|0x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[29]|0x4 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[29]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[29]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[29]|0x > 0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[29]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[29]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[29]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[29]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[29]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[29]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[29]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[29]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[29]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[29]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[29]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedReques > ts[29]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[29]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[29]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[29]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[29]|0x6 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[29]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[30]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[30]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[30]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[30]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[30]|0 > x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[3 > 0]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[30]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[30]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[30]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[30]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[30]|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[30]|0x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[30]|0x4 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[30]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[30]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[30]|0x > 0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[30]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[30]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[30]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[30]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[30]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[30]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[30]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[30]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[30]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[30]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[30]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedReques > ts[30]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[30]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[30]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[30]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[30]|0x6 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbPpd[5]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeOverride[5]|0 > x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbSplitBar[5]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar23[5]|0x1 > 6 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar4[5]|0xc > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar5[5]|0xc > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar45[5]|0x1 > 6 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar23[5]|0x1 > 6 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar4[5]|0xc > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar5[5]|0xc > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar45[5]|0x1 > 6 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbSBar01Prefetch[5]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbXlinkCtlOverride[5]|0 > x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[30]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[31]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[31]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[31]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[31]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[31]|0 > x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[3 > 1]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[31]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[31]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[31]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[31]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[31]|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[31]|0x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[31]|0x4 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[31]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[31]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[31]|0x > 0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[31]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[31]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[31]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[31]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[31]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[31]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[31]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[31]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[31]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[31]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[31]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedReques > ts[31]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[31]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[31]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[31]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[31]|0x6 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[31]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[32]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[32]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[32]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[32]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[32]|0 > x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[3 > 2]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[32]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[32]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[32]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[32]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[32]|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[32]|0x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[32]|0x4 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[32]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[32]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[32]|0x > 0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[32]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[32]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[32]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[32]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[32]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[32]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[32]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[32]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[32]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[32]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[32]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedReques > ts[32]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[32]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[32]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[32]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[32]|0x6 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[32]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[33]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[33]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[33]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[33]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[33]|0 > x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[3 > 3]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[33]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[33]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[33]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[33]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[33]|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[33]|0x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[33]|0x4 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[33]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[33]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[33]|0x > 0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[33]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[33]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[33]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[33]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[33]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[33]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[33]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[33]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[33]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[33]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[33]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedReques > ts[33]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[33]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[33]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[33]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[33]|0x6 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[33]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[34]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[34]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[34]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[34]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[34]|0 > x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[3 > 4]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[34]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[34]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[34]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[34]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[34]|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[34]|0x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[34]|0x4 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[34]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[34]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[34]|0x > 0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[34]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[34]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[34]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[34]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[34]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[34]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[34]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[34]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[34]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[34]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[34]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedReques > ts[34]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[34]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[34]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[34]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[34]|0x6 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[34]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[35]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[35]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[35]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[35]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[35]|0 > x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[3 > 5]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[35]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[35]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[35]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[35]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[35]|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[35]|0x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[35]|0x4 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[35]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[35]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[35]|0x > 0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[35]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[35]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[35]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[35]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[35]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[35]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[35]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[35]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[35]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[35]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[35]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedReques > ts[35]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[35]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[35]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[35]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[35]|0x6 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[35]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[36]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[36]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[36]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[36]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[36]|0 > x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[3 > 6]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[36]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[36]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[36]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[36]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[36]|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[36]|0x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[36]|0x4 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[36]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[36]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[36]|0x > 0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[36]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[36]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[36]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[36]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[36]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[36]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[36]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[36]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[36]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[36]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[36]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedReques > ts[36]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[36]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[36]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[36]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[36]|0x6 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[36]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[37]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[37]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[37]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[37]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[37]|0 > x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[3 > 7]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[37]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[37]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[37]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[37]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[37]|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[37]|0x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[37]|0x4 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[37]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[37]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[37]|0x > 0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[37]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[37]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[37]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[37]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[37]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[37]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[37]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[37]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[37]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[37]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[37]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedReques > ts[37]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[37]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[37]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[37]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[37]|0x6 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[37]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[38]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[38]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[38]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[38]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[38]|0 > x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[3 > 8]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[38]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[38]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[38]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[38]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[38]|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[38]|0x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[38]|0x4 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[38]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[38]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[38]|0x > 0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[38]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[38]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[38]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[38]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[38]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[38]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[38]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[38]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[38]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[38]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[38]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedReques > ts[38]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[38]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[38]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[38]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[38]|0x6 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[38]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[39]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[39]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[39]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[39]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[39]|0 > x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[3 > 9]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[39]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[39]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[39]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[39]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[39]|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[39]|0x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[39]|0x4 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[39]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[39]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[39]|0x > 0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[39]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[39]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[39]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[39]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[39]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[39]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[39]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[39]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[39]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[39]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[39]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedReques > ts[39]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[39]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[39]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[39]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[39]|0x6 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[39]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[40]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[40]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[40]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[40]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[40]|0 > x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[4 > 0]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[40]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[40]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[40]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[40]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[40]|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[40]|0x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[40]|0x4 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[40]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[40]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[40]|0x > 0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[40]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[40]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[40]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[40]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[40]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[40]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[40]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[40]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[40]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[40]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[40]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedReques > ts[40]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[40]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[40]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[40]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[40]|0x6 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[40]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[41]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[41]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[41]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[41]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[41]|0 > x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[4 > 1]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[41]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[41]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[41]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[41]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[41]|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[41]|0x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[41]|0x4 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[41]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[41]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[41]|0x > 0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[41]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[41]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[41]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[41]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[41]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[41]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[41]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[41]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[41]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[41]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[41]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedReques > ts[41]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[41]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[41]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[41]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[41]|0x6 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[41]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[42]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[42]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[42]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[42]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[42]|0 > x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[4 > 2]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[42]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[42]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[42]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[42]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[42]|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[42]|0x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[42]|0x4 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[42]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[42]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[42]|0x > 0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[42]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[42]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[42]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[42]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[42]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[42]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[42]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[42]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[42]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[42]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[42]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedReques > ts[42]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[42]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[42]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[42]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[42]|0x6 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[42]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[43]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[43]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[43]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[43]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[43]|0 > x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[4 > 3]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[43]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[43]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[43]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[43]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[43]|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[43]|0x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[43]|0x4 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[43]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[43]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[43]|0x > 0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[43]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[43]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[43]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[43]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[43]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[43]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[43]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[43]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[43]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[43]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[43]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedReques > ts[43]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[43]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[43]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[43]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[43]|0x6 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbPpd[6]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeOverride[6]|0 > x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbSplitBar[6]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar23[6]|0x1 > 6 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar4[6]|0xc > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar5[6]|0xc > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar45[6]|0x1 > 6 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar23[6]|0x1 > 6 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar4[6]|0xc > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar5[6]|0xc > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar45[6]|0x1 > 6 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbSBar01Prefetch[6]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbXlinkCtlOverride[6]|0 > x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[43]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[44]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[44]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[44]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[44]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[44]|0 > x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[4 > 4]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[44]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[44]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[44]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[44]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[44]|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[44]|0x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[44]|0x4 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[44]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[44]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[44]|0x > 0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[44]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[44]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[44]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[44]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[44]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[44]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[44]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[44]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[44]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[44]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[44]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedReques > ts[44]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[44]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[44]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[44]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[44]|0x6 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[44]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[45]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[45]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[45]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[45]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[45]|0 > x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[4 > 5]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[45]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[45]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[45]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[45]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[45]|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[45]|0x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[45]|0x4 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[45]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[45]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[45]|0x > 0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[45]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[45]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[45]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[45]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[45]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[45]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[45]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[45]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[45]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[45]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[45]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedReques > ts[45]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[45]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[45]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[45]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[45]|0x6 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[45]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[46]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[46]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[46]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[46]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[46]|0 > x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[4 > 6]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[46]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[46]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[46]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[46]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[46]|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[46]|0x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[46]|0x4 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[46]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[46]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[46]|0x > 0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[46]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[46]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[46]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[46]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[46]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[46]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[46]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[46]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[46]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[46]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[46]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedReques > ts[46]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[46]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[46]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[46]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[46]|0x6 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[46]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[47]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[47]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[47]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[47]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[47]|0 > x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[4 > 7]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[47]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[47]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[47]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[47]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[47]|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[47]|0x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[47]|0x4 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[47]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[47]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[47]|0x > 0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[47]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[47]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[47]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[47]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[47]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[47]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[47]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[47]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[47]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[47]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[47]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedReques > ts[47]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[47]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[47]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[47]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[47]|0x6 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbPpd[7]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeOverride[7]|0 > x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbSplitBar[7]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar23[7]|0x1 > 6 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar4[7]|0xc > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar5[7]|0xc > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar45[7]|0x1 > 6 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar23[7]|0x1 > 6 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar4[7]|0xc > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar5[7]|0xc > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar45[7]|0x1 > 6 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbSBar01Prefetch[7]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbXlinkCtlOverride[7]|0 > x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[47]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[48]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[48]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[48]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[48]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[48]|0 > x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[4 > 8]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[48]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[48]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[48]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[48]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[48]|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[48]|0x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[48]|0x4 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[48]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[48]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[48]|0x > 0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[48]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[48]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[48]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[48]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[48]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[48]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[48]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[48]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[48]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[48]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[48]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedReques > ts[48]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[48]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[48]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[48]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[48]|0x6 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[48]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[49]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[49]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[49]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[49]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[49]|0 > x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[4 > 9]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[49]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[49]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[49]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[49]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[49]|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[49]|0x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[49]|0x4 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[49]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[49]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[49]|0x > 0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[49]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[49]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[49]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[49]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[49]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[49]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[49]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[49]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[49]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[49]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[49]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedReques > ts[49]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[49]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[49]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[49]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[49]|0x6 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[49]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[50]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[50]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[50]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[50]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[50]|0 > x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[5 > 0]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[50]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[50]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[50]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[50]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[50]|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[50]|0x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[50]|0x4 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[50]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[50]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[50]|0x > 0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[50]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[50]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[50]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[50]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[50]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[50]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[50]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[50]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[50]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[50]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[50]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedReques > ts[50]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[50]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[50]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[50]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[50]|0x6 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[50]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[51]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[51]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[51]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[51]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[51]|0 > x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[5 > 1]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[51]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[51]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[51]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[51]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[51]|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[51]|0x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[51]|0x4 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[51]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[51]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[51]|0x > 0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[51]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[51]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[51]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[51]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[51]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[51]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[51]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[51]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[51]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[51]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[51]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedReques > ts[51]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[51]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[51]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[51]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[51]|0x6 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbPpd[8]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeOverride[8]|0 > x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbSplitBar[8]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar23[8]|0x1 > 6 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar4[8]|0xc > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar5[8]|0xc > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar45[8]|0x1 > 6 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar23[8]|0x1 > 6 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar4[8]|0xc > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar5[8]|0xc > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar45[8]|0x1 > 6 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbSBar01Prefetch[8]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbXlinkCtlOverride[8]|0 > x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[51]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[52]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[52]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[52]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[52]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[52]|0 > x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[5 > 2]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[52]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[52]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[52]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[52]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[52]|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[52]|0x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[52]|0x4 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[52]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[52]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[52]|0x > 0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[52]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[52]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[52]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[52]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[52]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[52]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[52]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[52]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[52]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[52]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[52]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedReques > ts[52]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[52]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[52]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[52]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[52]|0x6 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[52]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[53]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[53]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[53]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[53]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[53]|0 > x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[5 > 3]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[53]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[53]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[53]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[53]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[53]|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[53]|0x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[53]|0x4 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[53]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[53]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[53]|0x > 0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[53]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[53]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[53]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[53]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[53]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[53]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[53]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[53]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[53]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[53]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[53]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedReques > ts[53]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[53]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[53]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[53]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[53]|0x6 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[53]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[54]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[54]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[54]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[54]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[54]|0 > x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[5 > 4]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[54]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[54]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[54]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[54]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[54]|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[54]|0x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[54]|0x4 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[54]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[54]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[54]|0x > 0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[54]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[54]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[54]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[54]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[54]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[54]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[54]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[54]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[54]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[54]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[54]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedReques > ts[54]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[54]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[54]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[54]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[54]|0x6 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[54]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[55]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[55]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[55]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[55]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[55]|0 > x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[5 > 5]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[55]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[55]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[55]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[55]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[55]|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[55]|0x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[55]|0x4 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[55]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[55]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[55]|0x > 0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[55]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[55]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[55]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[55]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[55]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[55]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[55]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[55]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[55]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[55]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[55]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedReques > ts[55]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[55]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[55]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[55]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[55]|0x6 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[55]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[56]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[56]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[56]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[56]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[56]|0 > x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[5 > 6]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[56]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[56]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[56]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[56]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[56]|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[56]|0x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[56]|0x4 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[56]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[56]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[56]|0x > 0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[56]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[56]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[56]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[56]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[56]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[56]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[56]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[56]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[56]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[56]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[56]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedReques > ts[56]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[56]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[56]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[56]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[56]|0x6 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[56]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[57]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[57]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[57]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[57]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[57]|0 > x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[5 > 7]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[57]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[57]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[57]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[57]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[57]|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[57]|0x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[57]|0x4 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[57]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[57]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[57]|0x > 0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[57]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[57]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[57]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[57]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[57]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[57]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[57]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[57]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[57]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[57]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[57]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedReques > ts[57]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[57]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[57]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[57]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[57]|0x6 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[57]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[58]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[58]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[58]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[58]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[58]|0 > x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[5 > 8]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[58]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[58]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[58]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[58]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[58]|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[58]|0x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[58]|0x4 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[58]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[58]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[58]|0x > 0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[58]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[58]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[58]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[58]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[58]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[58]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[58]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[58]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[58]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[58]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[58]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedReques > ts[58]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[58]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[58]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[58]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[58]|0x6 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[58]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[59]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[59]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[59]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[59]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[59]|0 > x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[5 > 9]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[59]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[59]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[59]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[59]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[59]|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[59]|0x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[59]|0x4 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[59]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[59]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[59]|0x > 0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[59]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[59]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[59]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[59]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[59]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[59]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[59]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[59]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[59]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[59]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[59]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedReques > ts[59]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[59]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[59]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[59]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[59]|0x6 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[59]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[60]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[60]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[60]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[60]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[60]|0 > x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[6 > 0]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[60]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[60]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[60]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[60]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[60]|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[60]|0x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[60]|0x4 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[60]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[60]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[60]|0x > 0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[60]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[60]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[60]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[60]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[60]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[60]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[60]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[60]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[60]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[60]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[60]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedReques > ts[60]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[60]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[60]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[60]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[60]|0x6 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[60]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[61]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[61]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[61]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[61]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[61]|0 > x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[6 > 1]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[61]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[61]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[61]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[61]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[61]|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[61]|0x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[61]|0x4 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[61]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[61]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[61]|0x > 0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[61]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[61]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[61]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[61]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[61]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[61]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[61]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[61]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[61]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[61]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[61]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedReques > ts[61]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[61]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[61]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[61]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[61]|0x6 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[61]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[62]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[62]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[62]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[62]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[62]|0 > x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[6 > 2]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[62]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[62]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[62]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[62]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[62]|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[62]|0x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[62]|0x4 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[62]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[62]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[62]|0x > 0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[62]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[62]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[62]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[62]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[62]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[62]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[62]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[62]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[62]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[62]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[62]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedReques > ts[62]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[62]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[62]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[62]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[62]|0x6 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[62]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[63]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[63]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[63]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[63]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[63]|0 > x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[6 > 3]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[63]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[63]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[63]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[63]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[63]|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[63]|0x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[63]|0x4 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[63]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[63]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[63]|0x > 0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[63]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[63]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[63]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[63]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[63]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[63]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[63]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[63]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[63]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[63]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[63]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedReques > ts[63]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[63]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[63]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[63]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[63]|0x6 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[63]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[64]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[64]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[64]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[64]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[64]|0 > x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[6 > 4]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[64]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[64]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[64]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[64]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[64]|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[64]|0x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[64]|0x4 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[64]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[64]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[64]|0x > 0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[64]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[64]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[64]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[64]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[64]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[64]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[64]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[64]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[64]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[64]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[64]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedReques > ts[64]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[64]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[64]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[64]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[64]|0x6 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbPpd[9]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeOverride[9]|0 > x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbSplitBar[9]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar23[9]|0x1 > 6 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar4[9]|0xc > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar5[9]|0xc > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar45[9]|0x1 > 6 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar23[9]|0x1 > 6 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar4[9]|0xc > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar5[9]|0xc > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar45[9]|0x1 > 6 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbSBar01Prefetch[9]|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbXlinkCtlOverride[9]|0 > x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[64]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[65]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[65]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[65]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[65]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[65]|0 > x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[6 > 5]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[65]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[65]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[65]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[65]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[65]|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[65]|0x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[65]|0x4 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[65]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[65]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[65]|0x > 0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[65]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[65]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[65]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[65]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[65]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[65]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[65]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[65]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[65]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[65]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[65]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedReques > ts[65]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[65]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[65]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[65]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[65]|0x6 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[65]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[66]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[66]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[66]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[66]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[66]|0 > x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[6 > 6]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[66]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[66]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[66]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[66]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[66]|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[66]|0x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[66]|0x4 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[66]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[66]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[66]|0x > 0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[66]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[66]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[66]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[66]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[66]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[66]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[66]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[66]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[66]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[66]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[66]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedReques > ts[66]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[66]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[66]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[66]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[66]|0x6 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[66]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[67]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[67]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[67]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[67]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[67]|0 > x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[6 > 7]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[67]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[67]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[67]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[67]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[67]|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[67]|0x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[67]|0x4 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[67]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[67]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[67]|0x > 0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[67]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[67]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[67]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[67]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[67]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[67]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[67]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[67]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[67]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[67]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[67]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedReques > ts[67]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[67]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[67]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[67]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[67]|0x6 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[67]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[68]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[68]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[68]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[68]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[68]|0 > x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[6 > 8]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[68]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[68]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[68]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[68]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[68]|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[68]|0x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[68]|0x4 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[68]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[68]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[68]|0x > 0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[68]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[68]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[68]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[68]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[68]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[68]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[68]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[68]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[68]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[68]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[68]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedReques > ts[68]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[68]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[68]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[68]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[68]|0x6 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbPpd[10]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeOverride[10]| > 0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbSplitBar[10]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar23[10]|0x > 16 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar4[10]|0xc > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar5[10]|0xc > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar45[10]|0x > 16 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar23[10]|0x > 16 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar4[10]|0xc > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar5[10]|0xc > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar45[10]|0x > 16 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbSBar01Prefetch[10]|0 > x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbXlinkCtlOverride[10]| > 0x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[68]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[69]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[69]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[69]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[69]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[69]|0 > x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[6 > 9]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[69]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[69]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[69]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[69]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[69]|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[69]|0x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[69]|0x4 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[69]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[69]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[69]|0x > 0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[69]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[69]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[69]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[69]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[69]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[69]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[69]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[69]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[69]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[69]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[69]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedReques > ts[69]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[69]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[69]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[69]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[69]|0x6 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[69]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[70]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[70]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[70]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[70]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[70]|0 > x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[7 > 0]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[70]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[70]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[70]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[70]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[70]|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[70]|0x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[70]|0x4 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[70]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[70]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[70]|0x > 0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[70]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[70]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[70]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[70]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[70]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[70]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[70]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[70]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[70]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[70]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[70]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedReques > ts[70]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[70]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[70]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[70]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[70]|0x6 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[70]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[71]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[71]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[71]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[71]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[71]|0 > x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[7 > 1]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[71]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[71]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[71]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[71]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[71]|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[71]|0x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[71]|0x4 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[71]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[71]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[71]|0x > 0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[71]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[71]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[71]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[71]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[71]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[71]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[71]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[71]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[71]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[71]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[71]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedReques > ts[71]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[71]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[71]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[71]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[71]|0x6 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[71]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[72]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[72]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[72]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[72]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[72]|0 > x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[7 > 2]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[72]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[72]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[72]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[72]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[72]|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[72]|0x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[72]|0x4 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[72]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[72]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[72]|0x > 0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[72]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[72]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[72]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[72]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[72]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[72]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[72]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[72]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[72]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[72]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[72]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedReques > ts[72]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[72]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[72]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[72]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[72]|0x6 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbPpd[11]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeOverride[11]| > 0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbSplitBar[11]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar23[11]|0x > 16 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar4[11]|0xc > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar5[11]|0xc > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar45[11]|0x > 16 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar23[11]|0x > 16 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar4[11]|0xc > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar5[11]|0xc > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar45[11]|0x > 16 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbSBar01Prefetch[11]|0 > x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbXlinkCtlOverride[11]| > 0x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[72]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[73]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[73]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[73]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[73]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[73]|0 > x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[7 > 3]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[73]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[73]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[73]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[73]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[73]|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[73]|0x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[73]|0x4 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[73]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[73]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[73]|0x > 0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[73]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[73]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[73]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[73]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[73]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[73]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[73]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[73]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[73]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[73]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[73]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedReques > ts[73]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[73]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[73]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[73]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[73]|0x6 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[73]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[74]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[74]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[74]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[74]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[74]|0 > x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[7 > 4]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[74]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[74]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[74]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[74]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[74]|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[74]|0x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[74]|0x4 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[74]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[74]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[74]|0x > 0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[74]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[74]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[74]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[74]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[74]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[74]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[74]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[74]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[74]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[74]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[74]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedReques > ts[74]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[74]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[74]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[74]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[74]|0x6 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[74]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[75]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[75]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[75]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[75]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[75]|0 > x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[7 > 5]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[75]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[75]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[75]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[75]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[75]|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[75]|0x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[75]|0x4 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[75]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[75]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[75]|0x > 0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[75]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[75]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[75]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[75]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[75]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[75]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[75]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[75]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[75]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[75]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[75]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedReques > ts[75]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[75]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[75]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[75]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[75]|0x6 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[75]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[76]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[76]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[76]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[76]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[76]|0 > x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[7 > 6]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[76]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[76]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[76]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[76]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[76]|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[76]|0x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[76]|0x4 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[76]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[76]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[76]|0x > 0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[76]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[76]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[76]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[76]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[76]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[76]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[76]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[76]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[76]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[76]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[76]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedReques > ts[76]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[76]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[76]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[76]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[76]|0x6 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[76]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[77]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[77]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[77]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[77]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[77]|0 > x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[7 > 7]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[77]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[77]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[77]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[77]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[77]|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[77]|0x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[77]|0x4 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[77]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[77]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[77]|0x > 0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[77]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[77]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[77]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[77]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[77]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[77]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[77]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[77]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[77]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[77]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[77]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedReques > ts[77]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[77]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[77]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[77]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[77]|0x6 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[77]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[78]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[78]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[78]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[78]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[78]|0 > x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[7 > 8]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[78]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[78]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[78]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[78]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[78]|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[78]|0x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[78]|0x4 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[78]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[78]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[78]|0x > 0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[78]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[78]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[78]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[78]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[78]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[78]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[78]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[78]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[78]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[78]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[78]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedReques > ts[78]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[78]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[78]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[78]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[78]|0x6 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[78]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[79]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[79]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[79]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[79]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[79]|0 > x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[7 > 9]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[79]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[79]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[79]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[79]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[79]|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[79]|0x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[79]|0x4 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[79]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[79]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[79]|0x > 0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[79]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[79]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[79]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[79]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[79]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[79]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[79]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[79]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[79]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[79]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[79]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedReques > ts[79]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[79]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[79]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[79]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[79]|0x6 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[79]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[80]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[80]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[80]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[80]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[80]|0 > x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[8 > 0]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[80]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[80]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[80]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[80]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[80]|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[80]|0x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[80]|0x4 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[80]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[80]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[80]|0x > 0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[80]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[80]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[80]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[80]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[80]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[80]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[80]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[80]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[80]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[80]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[80]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedReques > ts[80]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[80]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[80]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[80]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[80]|0x6 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[80]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[81]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[81]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[81]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[81]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[81]|0 > x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[8 > 1]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[81]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[81]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[81]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[81]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[81]|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[81]|0x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[81]|0x4 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[81]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[81]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[81]|0x > 0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[81]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[81]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[81]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[81]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[81]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[81]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[81]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[81]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[81]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[81]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[81]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedReques > ts[81]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[81]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[81]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[81]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[81]|0x6 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[81]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[82]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[82]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[82]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[82]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[82]|0 > x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[8 > 2]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[82]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[82]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[82]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[82]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[82]|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[82]|0x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[82]|0x4 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[82]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[82]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[82]|0x > 0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[82]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[82]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[82]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[82]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[82]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[82]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[82]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[82]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[82]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[82]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[82]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedReques > ts[82]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[82]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[82]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[82]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[82]|0x6 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[82]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[83]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[83]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[83]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[83]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[83]|0 > x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[8 > 3]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[83]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[83]|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[83]|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[83]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[83]|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[83]|0x3 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[83]|0x4 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[83]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[83]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[83]|0x > 0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[83]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[83]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[83]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[83]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[83]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[83]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[83]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[83]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[83]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[83]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[83]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedReques > ts[83]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[83]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[83]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[83]|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[83]|0x6 > + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[83]|0x0 > + > #gOemSkuTokenSpaceGuid.PcdSocketCommonRcConfigData|L"SocketCom > monRcConfig"|4402ca38-808f-4279-bcec-5baf8d59092f|0x00 > + gOemSkuTokenSpaceGuid.PcdSocketCommonRcConfigData|{0x0} > + > gOemSkuTokenSpaceGuid.PcdSocketCommonRcConfigData.MmcfgBase|0x3 > + > gOemSkuTokenSpaceGuid.PcdSocketCommonRcConfigData.MmcfgSize|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketCommonRcConfigData.MmiohBase|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketCommonRcConfigData.MmiohSize|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketCommonRcConfigData.IsocEn|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketCommonRcConfigData.NumaEn|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketCommonRcConfigData.LockStep|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketCommonRcConfigData.MirrorMode|0x > 0 > + > #gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData|L"SocketMpLinkCo > nfig"|2b9b22de-2ad4-4abc-957d-5f18c504a05c|0x00 > + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData|{0} > + > gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.DegradePrecedence > |0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.QpiLinkSpeedMode > |0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.QpiLinkSpeed|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.KtiLinkL0pEn|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.KtiLinkL1En|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.KtiFailoverEn|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.IoDcMode|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.DirectoryModeEn|0 > x1 > + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.SncEn|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.XptPrefetchEn|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.KtiPrefetchEn|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.RdCurForXptPrefetc > hEn|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.KtiLinkVnaOverride| > 0x7f > + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.KtiCrcMode|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.KtiLbEn|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.LegacyVgaSoc|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.LegacyVgaStack|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.MmioP2pDis|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.QpiCpuSktHotPlugE > n|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.KtiCpuSktHotPlugTo > pology|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.KtiSkuMismatchChe > ck|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.DebugPrintLevel|0x > f > + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.IrqThreshold|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.BusRatio[0]|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.BusRatio[1]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.Cpu0P0KtiPortDisabl > e|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.Cpu0P0KtiLinkVnaO > verride|0x7f > + > gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.Cpu0P0KtiLinkSpeed > |0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.Cpu0P1KtiPortDisabl > e|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.Cpu0P1KtiLinkVnaO > verride|0x7f > + > gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.Cpu0P1KtiLinkSpeed > |0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.Cpu0P2KtiPortDisabl > e|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.Cpu0P2KtiLinkVnaO > verride|0x7f > + > gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.Cpu0P2KtiLinkSpeed > |0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.Cpu1P0KtiPortDisabl > e|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.Cpu1P0KtiLinkVnaO > verride|0x7f > + > gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.Cpu1P0KtiLinkSpeed > |0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.Cpu1P1KtiPortDisabl > e|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.Cpu1P1KtiLinkVnaO > verride|0x7f > + > gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.Cpu1P1KtiLinkSpeed > |0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.Cpu1P2KtiPortDisabl > e|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.Cpu1P2KtiLinkVnaO > verride|0x7f > + > gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.Cpu1P2KtiLinkSpeed > |0x2 > + > #gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData|L"SocketMemory > Config"|98cf19ed-4109-4681-b79d-9196757c7824|0x00 > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData|{0x0} > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.Srat|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.SratMemoryHotPl > ug|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.SratCpuHotPlug|0x > 0 > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.EnforcePOR|0x3 > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.pprType|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.pprErrInjTest|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.DdrFreqLimit|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.imcBclk|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.promoteMrcWarni > ngs|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.promoteWarnings > |0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.haltOnMemErr|0x > 1 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.MultiThreaded|0x > 1 > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.EccSupport|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.spdCrcCheck|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.logParsing|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.lrdimmModuleDel > ay|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.HwMemTest|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.MemTestLoops|0x > 1 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.DdrMemoryType| > 0x2 > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.RankMargin|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.EnableBacksideRM > T|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.EnableBacksideCM > DRMT|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.rmtPatternLength| > 0x7fff > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.rmtPatternLengthE > xt|0x7fff > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.perbitmargin|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.AttemptFastBoot| > 0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.AttemptFastBootC > old|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.MemTestOnFastB > oot|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.RmtOnColdFastBo > ot|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.bdatEn|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.ScrambleEnDDRT| > 0x2 > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.ScrambleEn|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.allowCorrectableEr > ror|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.WrCRC|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.dimmIsolation|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.WritePreamble|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.ReadPreamble|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.ScrambleSeedLow > |0xa02b > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.ScrambleSeedHigh > |0xd395 > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.ADREn|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.Reserved_12|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.check_pm_sts|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.check_platform_d > etect|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.CustomRefreshRat > eEn|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.CustomRefreshRat > e|0x14 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.mcBgfThreshold|0 > x0 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.dllResetTestLoops > |0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.oppReadInWmm| > 0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.normOppInterval| > 0x400 > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.caParity|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.smbSpeed|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.mrcRepeatTest|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.memFlowsExt|0xff > ffffff > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.memFlows|0xfffff > fff > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.rankMaskEn|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.Blockgnt2cmd1cyc > |0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.Disddrtopprd|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck0ch0|0xff > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck0ch1|0xff > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck0ch2|0xff > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck0ch3|0xff > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck0ch4|0xff > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck0ch5|0xff > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck1ch0|0xff > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck1ch1|0xff > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck1ch2|0xff > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck1ch3|0xff > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck1ch4|0xff > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck1ch5|0xff > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck2ch0|0xff > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck2ch1|0xff > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck2ch2|0xff > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck2ch3|0xff > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck2ch4|0xff > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck2ch5|0xff > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck3ch0|0xff > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck3ch1|0xff > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck3ch2|0xff > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck3ch3|0xff > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck3ch4|0xff > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck3ch5|0xff > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.PagePolicy|0x3 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.DutyCycleTraining| > 0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.readVrefCenter|0 > x2 > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.eyeDiagram|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.turnaroundOpt|0x > 2 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.oneRankTimingMo > de|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.pda|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.wrVrefCenter|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.thermalthrottlings > upport|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.thermalmemtrip|0 > x0 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.memhotSupport|0 > x0 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.CkeProgramming| > 0x0 > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.Reserved6|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.PkgcSrefEn|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.CkeIdleTimer|0x14 > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.ApdEn|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.PpdEn|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.DdrtCkeEn|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.OppSrefEn|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.DdrtSrefEn|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.MdllOffEn|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.CkMode|0x2 > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.XMPMode|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.XMPMode|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.XMPMode|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.Vdd|0x4b0 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.commandTiming|0 > x0 > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.tREFI|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.tCAS|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.tRP|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.tRCD|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.tRAS|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.tWR|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.tRFC|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.tRRD|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.tRTP|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.tWTR|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.tFAW|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.tRC|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.tCWL|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.volMemMode|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.memInterleaveGra > n1LM|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.ImcInterleaving|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.ChannelInterleavin > g|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.RankInterleaving|0 > x0 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.SocketInterleaveB > elow4GB|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.Reserved_1|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.Reserved_7|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.Reserved_2|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.Reserved_3|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.Reserved_4|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.Reserved_5|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.FastGoConfig|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.setSecureEraseAll > DIMMs|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.setSecureEraseSkt > Ch[0]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.setSecureEraseSkt > Ch[1]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.setSecureEraseSkt > Ch[2]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.setSecureEraseSkt > Ch[3]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.setSecureEraseSkt > Ch[4]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.setSecureEraseSkt > Ch[5]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.setSecureEraseSkt > Ch[6]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.setSecureEraseSkt > Ch[7]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.setSecureEraseSkt > Ch[8]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.setSecureEraseSkt > Ch[9]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.setSecureEraseSkt > Ch[10]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.setSecureEraseSkt > Ch[11]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.setSecureEraseSkt > Ch[12]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.setSecureEraseSkt > Ch[13]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.setSecureEraseSkt > Ch[14]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.setSecureEraseSkt > Ch[15]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.setSecureEraseSkt > Ch[16]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.setSecureEraseSkt > Ch[17]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.setSecureEraseSkt > Ch[18]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.setSecureEraseSkt > Ch[19]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.setSecureEraseSkt > Ch[20]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.setSecureEraseSkt > Ch[21]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.setSecureEraseSkt > Ch[22]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.setSecureEraseSkt > Ch[23]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.partialmirrorsad0| > 0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.partialmirror|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.partialmirrorsize[0] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.partialmirrorsize[1] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.partialmirrorsize[2] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.partialmirrorsize[3] > |0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.PartialMirrorUefi|0 > x0 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.PartialMirrorUefiP > ercent|0x0 > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.RankSparing|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.multiSparingRanks > |0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.DemandScrubMod > e|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.spareErrTh|0x7fff > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.leakyBktLo|0x28 > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.leakyBktHi|0x29 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.SddcPlusOneEn|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.SddcPlusOneEn|0x > 0 > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.ADDDCEn|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.AdddcErrInjEn|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.DieSparing|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.Reserved1|0x80 > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.PatrolScrub|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.PatrolScrubDuratio > n|0x18 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.PatrolScrubAddrM > ode|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.Reserved_11|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.RtoMaxNodeInterl > eave|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.RtoHighAddressSta > rtBitPosition|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.RtoLowMemChan > nel|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.RtoCfgMask2LM|0 > x0 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.Reserved_13|0x1 > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.mdllSden|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.BwLimitTfOvrd|0x > 0 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.DramRaplExtende > dRange|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.CmsEnableDramP > m|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.AdvMemTestRetry > AfterRepair|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.AdvMemTestCond > ition|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.AdvMemTestCond > Vdd|1260 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.AdvMemTestCond > Twr|10 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.AdvMemTestCond > Trefi|15600 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.AdvMemTestCond > Pause|100000 > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.Reserved10|2 > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.Reserved11|2 > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.Reserved12|2 > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.Reserved13|2 > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.Reserved14|2 > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.Reserved15|16 > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.Reserved16|2 > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.Reserved17|2 > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.Reserved18|2 > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.Reserved19|1 > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.Reserved20|1 > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.Reserved21|1 > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.Reserved22|1 > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.Reserved23|1 > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.Reserved24|1 > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.Reserved25|1 > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.Reserved26|1 > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.Reserved27|1 > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.Reserved28|9 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.eraseArmNVDIM > MS|1 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.restoreNVDIMMS| > 1 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.interNVDIMMS|1 > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.OffsetTxDq|100 > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.OffsetRxDq|100 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.OffsetTxVref|100 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.OffsetRxVref|100 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.OffsetCmdAll|100 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.OffsetCmdVref|10 > 0 > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.OffsetCtlAll|100 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.turnaroundOptDdr > t|2 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.NgnEccExitCorr|2 > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.NgnArsPublish|2 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.NgnAveragePower > |15000 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.NgnThrottleTemp| > 2 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.AppDirectMemory > Hole|1 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.LatchSystemShutd > ownState|1 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.EliminateDirectoryI > nFarMemory|1 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.NvmdimmPowerC > yclePolicy|1 > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.Reserved29|1 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.Force1ChWayFM| > 1 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.NvmMediaStatusE > xception|1 > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck4ch0|0xFF > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck4ch1|0xFF > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck4ch2|0xFF > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck4ch3|0xFF > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck4ch4|0xFF > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck4ch5|0xFF > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck5ch0|0xFF > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck5ch1|0xFF > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck5ch2|0xFF > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck5ch3|0xFF > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck5ch4|0xFF > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck5ch5|0xFF > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck6ch0|0xFF > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck6ch1|0xFF > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck6ch2|0xFF > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck6ch3|0xFF > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck6ch4|0xFF > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck6ch5|0xFF > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck7ch0|0xFF > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck7ch1|0xFF > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck7ch2|0xFF > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck7ch3|0xFF > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck7ch4|0xFF > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck7ch5|0xFF > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.Reserved33|1 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.LsxImplementatio > n|1 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.NvdimmSmbusMa > xAccessTime|350 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.NvdimmSmbusRel > easeDelay|150 > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.Reserved35|2 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.AdvMemTestCond > ition|1 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.AdvMemTestCond > Vdd|1260 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.AdvMemTestCond > Twr|10 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.AdvMemTestCond > Trefi|15600 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.AdvMemTestCond > Pause|100000 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.OffsetRecEn|100 > + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.RcvenAve|2 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.allowCorrectableM > emTestError|2 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.PatrolErrorDowngr > adeEn|1 > + > gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.AdvMemTestRetry > AfterRepair|1 > + > #gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData|L"Soc > ketPowerManagementConfig"|A1047342-BDBA-4DAE-A67A- > 40979B65C7F8|0x00 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData|{0x0} > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.SPTWo > rkaround|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.AcpiS3E > nable|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.AcpiS4E > nable|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Process > orHWPMEnable|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Process > orHWPMInterrupt|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Process > orEPPEnable|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Process > orEppProfile|0x55 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Process > orAPSrocketing|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Process > orScalability|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Process > orRaplPrioritization|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.WFRW > AEnable|0x2 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.UFSDis > able|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Process > orEistEnable|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.ConfigT > DPLevel|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PState > Domain|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Process > orEistPsdFunc|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Process > orSinglePCTLEn|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Process > orSPD|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.BootPS > tate|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.EETurb > oDisable|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Turbo > Mode|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Enable > Xe|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Overclo > ckingLock|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.TurboR > atioLimitRatio[0]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.TurboR > atioLimitCores[0]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.TurboR > atioLimitRatio[1]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.TurboR > atioLimitCores[1]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.TurboR > atioLimitRatio[2]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.TurboR > atioLimitCores[2]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.TurboR > atioLimitRatio[3]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.TurboR > atioLimitCores[3]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.TurboR > atioLimitRatio[4]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.TurboR > atioLimitCores[4]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.TurboR > atioLimitRatio[5]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.TurboR > atioLimitCores[5]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.TurboR > atioLimitRatio[6]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.TurboR > atioLimitCores[6]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.TurboR > atioLimitRatio[7]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.TurboR > atioLimitCores[7]|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.LOT26U > nusedVrPowerDownEnable|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Process > orAutonomousCstateEnable|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.C6Enab > le|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Process > orC1eEnable|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.OSCx|0 > x0 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Packag > eCState|0xff > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.C2C3TT > |0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Dynami > cL1|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PkgCLa > tNeg|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.LTRSwI > nput|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.CStateL > atencyCtrlValid[0]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.CStateL > atencyCtrlMultiplier[0]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.CStateL > atencyCtrlValue[0]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.CStateL > atencyCtrlValid[1]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.CStateL > atencyCtrlMultiplier[1]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.CStateL > atencyCtrlValue[1]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.CStateL > atencyCtrlValid[2]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.CStateL > atencyCtrlMultiplier[2]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.CStateL > atencyCtrlValue[2]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.TStateE > nable|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.OnDieT > hermalThrottling|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Procho > tLock|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Enable > ProcHot|0x3 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Enable > ThermalMonitor|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Procho > tResponseRatio|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.TCCActi > vationOffset|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.SAPMC > ontrol|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PwrPer > fTuning|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Process > orOutofBandAlternateEPB|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.AltEngP > erfBIAS|0x7 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PwrPer > fSwitch|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.WorkLd > Config|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.EngAvg > TimeWdw1|0x17 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.P0TtlTi > meLow1|0x23 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.P0TtlTi > meHigh1|0x3a > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Current > Config|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Current > Limit|0x438 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PpcccL > ock|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PkgCst > EntryValCtl|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.SnpLat > Vld|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.SnpLat > Ovrd|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.SnpLat > Mult|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.SnpLat > Val|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.NonSn > pLatVld|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.NonSn > pLatOvrd|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.NonSn > pLatMult|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.NonSn > pLatVal|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.UncrPe > rfPlmtOvrdEn|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.EetOve > rrideEn|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.IoBwPl > mtOvrdEn|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.IomAp > mOvrdEn|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.QpiAp > mOvrdEn|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PerfPli > mitDifferential|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PerfPLi > mitClipC|0x1f > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PerfPL > mtThshld|0xf > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PerfPLi > mitEn|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.FastRa > plDutyCycle|0x40 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.TurboP > owerLimitLock|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PowerL > imit1En|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PowerL > imit1Power|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PowerL > imit1Time|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PowerL > imit2En|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PowerL > imit2Power|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PowerL > imit2Time|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PmaxO > ffset|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Kti0In[0 > ]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Kti1In[0 > ]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Kti2In[0 > ]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PcieIio0 > In[0]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PcieIio1 > In[0]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PcieIio2 > In[0]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PcieIio3 > In[0]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PcieIio4 > In[0]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PcieIio5 > In[0]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Kti0In[1 > ]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Kti1In[1 > ]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Kti2In[1 > ]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PcieIio0 > In[1]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PcieIio1 > In[1]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PcieIio2 > In[1]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PcieIio3 > In[1]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PcieIio4 > In[1]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PcieIio5 > In[1]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Iio0Pkg > cClkGateDis[0]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Iio1Pkg > cClkGateDis[0]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Iio2Pkg > cClkGateDis[0]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Kti01Pk > gcClkGateDis[0]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Kti23Pk > gcClkGateDis[0]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Mc1Pk > gcClkGateDis[0]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Mc0Pk > gcClkGateDis[0]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Kti01pll > OffEna[0]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Kti23pll > OffEna[0]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.P0pllOf > fEna[0]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.P1pllOf > fEna[0]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.P2pllOf > fEna[0]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Mc0pll > OffEna[0]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Mc1pll > OffEna[0]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.SetvidD > ecayDisable[0]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.SapmCt > lLock[0]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Iio0Pkg > cClkGateDis[1]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Iio1Pkg > cClkGateDis[1]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Iio2Pkg > cClkGateDis[1]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Kti01Pk > gcClkGateDis[1]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Kti23Pk > gcClkGateDis[1]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Mc1Pk > gcClkGateDis[1]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Mc0Pk > gcClkGateDis[1]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Kti01pll > OffEna[1]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Kti23pll > OffEna[1]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.P0pllOf > fEna[1]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.P1pllOf > fEna[1]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.P2pllOf > fEna[1]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Mc0pll > OffEna[1]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Mc1pll > OffEna[1]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.SetvidD > ecayDisable[1]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.SapmCt > lLock[1]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Process > orConfigurePbf|1 > + > gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.AvxIccp > Level|1 > + > #gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData|L"SocketPr > ocessorCoreConfig"|07013588-C789-4E12-A7C3-88FAFAE79F7C|0x00 > + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData|{0x0} > + > gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.PchTraceHub > En|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.ProcessorHy > perThreadingDisable|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.IedSize|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.IedTraceSize > |0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.TsegSize|0x5 > + > gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.AllowMixedP > owerOnCpuRatio|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.CheckCpuBis > t|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.ThreeStrikeTi > mer|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.FastStringEn > able|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.MachineChe > ckEnable|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.CpuidMaxVal > ue|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.ExecuteDisa > bleBit|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.ProcessorLts > xEnable|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.ProcessorVm > xEnable|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.ProcessorSm > xEnable|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.LockChipset| > 0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.BiosAcmErro > rReset|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.ProcessorMs > rLockControl|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.PpinControl| > 0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.DebugInterf > ace|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.MlcStreamer > PrefetcherEnable|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.MlcSpatialPr > efetcherEnable|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.DCUStreame > rPrefetcherEnable|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.DCUIPPrefet > cherEnable|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.DCUModeSe > lection|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.BspSelection > |0xff > + > gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.Reserved2|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.ProcessorX2 > apic|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.ForceX2ApicI > ds|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.AesEnable|0 > x1 > + > gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.ForcePhysica > lModeEnable|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.ProcessorVir > tualWireMode|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.PCIeDownStr > eamPECIWrite|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.PeciInTrustC > ontrolBit|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.IioLlcWaysM > ask|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.ExpandedIio > LlcWaysMask|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.RemoteWay > sMask|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.QlruCfgMask > _Hi|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.QlruCfgMask > _Lo|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.TargetedSmi > |0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.eSmmSaveSt > ate|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.SmbusErrorR > ecovery|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.CoreDisable > Mask[0]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.IotEn[0]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.OclaMinWay > [0]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.OclaMaxTorE > ntry[0]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.CoreDisable > Mask[1]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.IotEn[1]|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.OclaMinWay > [1]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.OclaMaxTorE > ntry[1]|0x1 > + > gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.ProcessorFle > xibleRatioOverrideEnable|0x0 > + > gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.ProcessorFle > xibleRatio|0x17 > + > gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.MonitorMwa > itEnabled|2 > + > diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/__init__.py > b/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/__init__.py > new file mode 100644 > index 0000000000..e69de29bb2 > diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/bld.bat > b/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/bld.bat > new file mode 100644 > index 0000000000..5c4dbf064c > --- /dev/null > +++ b/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/bld.bat > @@ -0,0 +1,139 @@ > +@REM @file > +@REM > +@REM Copyright (c) 2018, Intel Corporation. All rights reserved.
> +@REM Copyright (c) 2021, American Megatrends International LLC.
> +@REM SPDX-License-Identifier: BSD-2-Clause-Patent > +@REM > + > +@echo off > + > +REM Run setlocal to take a snapshot of the environment variables. endlo= cal > is called to restore the environment. > +setlocal > +set SCRIPT_ERROR=3D0 > + > +REM ---- Do NOT use :: for comments Inside of code blocks() ---- > + > +::******************************************************** > ************** > +:: Initial Setup > +::******************************************************** > ************** > + > +:parseCmdLine > +if "%1"=3D=3D"" goto :argumentCheck > + > +if /I "%1"=3D=3D"debug" set TARGET=3DDEBUG > +if /I "%1"=3D=3D"release" set TARGET=3DRELEASE > + > +if /I "%1"=3D=3D"clean" ( > + set BUILD_TYPE=3Dcleantree > + call :cleantree > + goto :EOF > +) > + > +shift > +GOTO :parseCmdLine > + > +:argumentCheck: > + > +if /I "%TARGET%" =3D=3D "" ( > + echo Info: debug/release argument is empty, use DEBUG as default > + set TARGET=3DDEBUG > +) > + > +REM Art to notify which board you're working on > +echo. > +type logo.txt > +echo. > + > +:: > +:: Build configuration > +:: > +set BUILD_REPORT_FLAGS=3D > +set BUILD_CMD_LINE=3D > +set BUILD_LOG=3D%WORKSPACE%\Build\build.log > +set BUILD_REPORT=3D%WORKSPACE%\Build\BuildReport.txt > + > +del %BUILD_LOG% *.efi *.log 2>NUL > + > +echo -------------------------------------------------------------------= ------------------ > ------- > +echo. > +echo Purley Build Start > +echo. > +echo -------------------------------------------------------------------= ------------------ > ------- > + > + > +:doPreBuild > +echo. > +echo -------------------------------------------------------------------= - > +echo. > +echo Prebuild Start > +echo. > +echo -------------------------------------------------------------------= - > +call prebuild.bat > +if %SCRIPT_ERROR% NEQ 0 EXIT /b %ERRORLEVEL% > + > +echo -------------------------------------------------------------------= - > +echo. > +echo Prebuild End > +echo. > +echo -------------------------------------------------------------------= - > +if %ERRORLEVEL% NEQ 0 EXIT /b %ERRORLEVEL% > +timeout 1 > + > +:buildBios > +set BUILD_CMD_LINE=3D%BUILD_CMD_LINE% -D > MAX_SOCKET=3D%MAX_SOCKET% -y %BUILD_REPORT% > +echo -------------------------------------------------------------------= - > +echo. > +echo Build Start > +echo. > +echo -------------------------------------------------------------------= - > +echo. > +echo build %BUILD_CMD_LINE% --log=3D%BUILD_LOG% > %BUILD_REPORT_FLAGS% > +call build %BUILD_CMD_LINE% --log=3D%BUILD_LOG% > %BUILD_REPORT_FLAGS% > +echo -------------------------------------------------------------------= - > +echo. > +echo Build End > +echo. > +echo -------------------------------------------------------------------= - > +if %ERRORLEVEL% NEQ 0 EXIT /b %ERRORLEVEL% > +timeout 1 > + > +:postBuild > + > +echo -------------------------------------------------------------------= - > +echo. > +echo PostBuild Start > +echo. > +echo -------------------------------------------------------------------= - > +echo. > +call postbuild.bat > +if %ERRORLEVEL% NEQ 0 EXIT /b %ERRORLEVEL% > +timeout 1 > +echo -------------------------------------------------------------------= - > +echo. > +echo PostBuild End > +echo. > +echo -------------------------------------------------------------------= - > + > +echo %date% %time% > +echo. > + > +echo -------------------------------------------------------------------= ------------------ > ------- > +echo. > +echo Purley Build End > +echo. > +echo -------------------------------------------------------------------= ------------------ > ------- > + > +:done > +endlocal & EXIT /b %SCRIPT_ERROR% > + > +::-------------------------------------------------------- > +::-- Function section starts below here > +::-------------------------------------------------------- > +:cleantree > +choice /t 3 /d y /m "Confirm: clean tree of intermediate files created i= n tree > during build" > +if %ERRORLEVEL% EQU 2 goto :EOF > +goto :EOF > + > + > +:ErrorHandler: > +echo Error handler > \ No newline at end of file > diff --git > a/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/build_board.py > b/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/build_board.py > new file mode 100644 > index 0000000000..2a1f063b9d > --- /dev/null > +++ b/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/build_board.py > @@ -0,0 +1,195 @@ > +# @ build_board.py > +# This adds additional functions to the build_bios.py > +# > +# Copyright (c) 2018, Intel Corporation. All rights reserved.
> +# Copyright (c) 2021, American Megatrends International LLC.
> +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > + > +""" > +This module serves as an additional build steps for the Tioga Pass board > +""" > + > +import os > +import sys > + > + > +def pre_build_ex(config, functions): > + """Additional Pre BIOS build function > + > + :param config: The environment variables to be used in the build pro= cess > + :type config: Dictionary > + :param functions: A dictionary of function pointers > + :type functions: Dictionary > + :returns: nothing > + """ > + print("Info: re-generating PlatformOffset header files") > + > + execute_script =3D functions.get("execute_script") > + > + command =3D ["build", "-D", "MAX_SOCKET=3D" + config.get("MAX_SOCKET= ", > "1"), > + "-m", > + os.path.join(config["PLATFORM_BOARD_PACKAGE"], > + "Acpi", "BoardAcpiDxe", "Dsdt.inf"), > + "-y", > + config.get("PRE_BUILD_REPORT", > + os.path.join(config["WORKSPACE"], > + "preBuildReport.txt")), > + "--log=3D" + config.get("PRE_BUILD_LOG", > + os.path.join(config["WORKSPACE"], > + "prebuild.log"))] > + > + _, _, _, code =3D execute_script(command, config) > + if code !=3D 0: > + print(" ".join(command)) > + print("Error re-generating PlatformOffset header files") > + sys.exit(1) > + > + config["AML_FILTER"] =3D "\"PSYS\" .MCTL\" .FIX[0-9,A-Z]\"" > + print("AML_FILTER=3D ", config.get("AML_FILTER")) > + > + # build the command with arguments > + command =3D ["python", > + os.path.join(config["MIN_PACKAGE_TOOLS"], > + "AmlGenOffset", > + "AmlGenOffset.py"), > + "-d", "--aml_filter", config["AML_FILTER"], > + "-o", os.path.join(config["WORKSPACE_PLATFORM"], > + config["PLATFORM_BOARD_PACKAGE"], > + "Acpi", "BoardAcpiDxe", > + "AmlOffsetTable.c"), > + os.path.join(config["BUILD_X64"], > + "PurleyOpenBoardPkg", > + "Acpi", > + "BoardAcpiDxe", > + "DSDT", > + "OUTPUT", > + "Dsdt", "WFPPlatform.offset.h")] > + > + # execute the command > + _, _, _, code =3D execute_script(command, config) > + if code !=3D 0: > + print(" ".join(command)) > + print("Error re-generating PlatformOffset header files") > + sys.exit(1) > + > + print("GenOffset done") > + return config > + > + > +def build_ex(config, functions): > + """Additional BIOS build function > + > + :param config: The environment variables to be used in > + the build process > + :type config: Dictionary > + :param functions: A dictionary of function pointers > + :type functions: Dictionary > + :returns: config dictionary > + :rtype: Dictionary > + """ > + print("build_ex") > + return None > + > + > +def post_build_ex(config, functions): > + """Additional Post BIOS build function > + > + :param config: The environment variables to be used in the post > + build process > + :type config: Dictionary > + :param functions: A dictionary of function pointers > + :type functions: Dictionary > + :returns: config dictionary > + :rtype: Dictionary > + """ > + print("post_build_ex") > + > + execute_script =3D functions.get("execute_script") > + > + if not execute_script: > + print("post_build_ex Error") > + sys.exit(1) > + > + common_patch_command =3D [os.path.join(config["PYTHON_HOME"], > "python"), > + os.path.join(config["MIN_PACKAGE_TOOLS"], > + "PatchFv", "PatchBinFv.py"), > + config["TARGET"], > + os.path.join(config["WORKSPACE_SILICON_BIN"]= , > + "PurleySiliconBinPkg", "FV"), > + os.path.join(config["WORKSPACE"], > + "BuildReport.log")] > + > + fvs_to_patch =3D ["FvTempMemorySilicon", > + "FvPreMemorySilicon", > + "FvPostMemorySilicon", > + "FvLateSilicon"] > + for fv in fvs_to_patch: > + patch_command =3D common_patch_command + [fv] > + _, _, _, code =3D execute_script(patch_command, config) > + if code !=3D 0: > + print(" ".join(patch_command)) > + print("Patch Error!") > + sys.exit(1) > + > + common_rebase_command =3D [os.path.join(config["PYTHON_HOME"], > "python"), > + os.path.join(config["MIN_PACKAGE_TOOLS"], > + "PatchFv", "RebaseBinFv.py"), > + config["TARGET"], > + os.path.join(config["WORKSPACE_SILICON_BIN"= ], > + "PurleySiliconBinPkg", "FV"), > + os.path.join(config["WORKSPACE"], > + "BuildReport.log")] > + > + rebase_command =3D common_rebase_command +\ > + ["FvPreMemorySilicon", > + "gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase"] > + > + _, _, _, code =3D execute_script(rebase_command, config) > + if code !=3D 0: > + print(" ".join(rebase_command)) > + print("Patch Error!") > + sys.exit(1) > + > + rebase_command =3D common_rebase_command +\ > + ["FvPostMemorySilicon", > + "gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase"] > + > + _, _, _, code =3D execute_script(rebase_command, config) > + if code !=3D 0: > + print(" ".join(rebase_command)) > + print("Patch Error!") > + sys.exit(1) > + > + common_patchbfv_command =3D [os.path.join(config["PYTHON_HOME"], > "python"), > + os.path.join(config["MIN_PACKAGE_TOOLS"], > + "PatchFv", "PatchBfv.py"), > + os.path.join(config["BUILD_DIR_PATH"], > + "FV", "PLATFORM.fd"), > + os.path.join(config["WORKSPACE"], > + "BuildReport.log")] > + > + patchbfv_command =3D common_patchbfv_command +\ > + ["gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase"] > + > + _, _, _, code =3D execute_script(patchbfv_command, config) > + if code !=3D 0: > + print(" ".join(patchbfv_command)) > + print("Patch Error!") > + sys.exit(1) > + > + return None > + > + > +def clean_ex(config, functions): > + """Additional clean function > + > + :param config: The environment variables to be used in the build pro= cess > + :type config: Dictionary > + :param functions: A dictionary of function pointers > + :type functions: Dictionary > + :returns: config dictionary > + :rtype: Dictionary > + """ > + print("clean_ex") > + return None > diff --git > a/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/build_config.cfg > b/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/build_config.cfg > new file mode 100644 > index 0000000000..227a1162f1 > --- /dev/null > +++ b/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/build_config.cfg > @@ -0,0 +1,34 @@ > +# @ build_config.cfg > +# This is the main/default build configuration file > +# > +# Copyright (c) 2018, Intel Corporation. All rights reserved.
> +# Copyright (c) 2021, American Megatrends International LLC.
> +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > + > + > +[CONFIG] > +WORKSPACE_PLATFORM_BIN =3D > +WORKSPACE_FSP_BIN =3D > +EDK_SETUP_OPTION =3D > +openssl_path =3D > +PLATFORM_BOARD_PACKAGE =3D PurleyOpenBoardPkg > +PROJECT =3D PurleyOpenBoardPkg/BoardTiogaPass > +BOARD =3D BoardTiogaPass > +FLASH_MAP_FDF =3D PurleyOpenBoardPkg/Include/Fdf/FlashMapInclude.fdf > +PROJECT_DSC =3D PurleyOpenBoardPkg/BoardTiogaPass/OpenBoardPkg.dsc > +BOARD_PKG_PCD_DSC =3D > PurleyOpenBoardPkg/BoardTiogaPass/PlatformPkgPcd.dsc > +ADDITIONAL_SCRIPTS =3D > PurleyOpenBoardPkg/BoardTiogaPass/build_board.py > +PRE_BUILD_LOG =3D prebuild.log > +PRE_BUILD_REPORT =3D prebuildReport.log > +PrepRELEASE =3D DEBUG > +SILENT_MODE =3D FALSE > +EXT_CONFIG_CLEAR =3D > +CapsuleBuild =3D FALSE > +EXT_BUILD_FLAGS =3D > +CAPSULE_BUILD =3D 0 > +TARGET =3D DEBUG > +TARGET_SHORT =3D D > +PERFORMANCE_BUILD =3D FALSE > +FSP_WRAPPER_BUILD =3D FALSE > +MAX_SOCKET =3D 2 > diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/logo.txt > b/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/logo.txt > new file mode 100644 > index 0000000000..a6c208f49a > --- /dev/null > +++ b/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/logo.txt > @@ -0,0 +1,10 @@ > + > + _________ ___ ________ ________ ________ ________ > ________ ________ ________ > +|\___ ___\ |\ \ |\ __ \ |\ ___ \ |\ __ \ |\ __ = \ |\ __ \ |\ > ____\ |\ ____\ > +\|___ \ \_| \ \ \ \ \ \|\ \ \ \ \\|\__\ \ \ \|\ \ \ \ \|\ = \ \ \ \|\ \ \ \ > \___|_ \ \ \___|_ > + \ \ \ \ \ \ \ \ \\\ \ \ \ \ _____ \ \ __ \ \ \ __= __\ \ \ __ \ \ > \_____ \ \ \_____ \ > + \ \ \ \ \ \ \ \ \\\ \ \ \ \\___ \ \ \ \\\ \ \ \ \_= __| \ \ \\\ \ > \|____|\ \ \|____|\ \ > + \ \__\ \ \__\ \ \_______\ \ \ \\_\\ \ \ \__\\\__\ \ \__\= \ > \__\\\__\ ____\_\ \ ____\_\ \ > + \|__| \|__| \|_______| \ \________\ \|__| \|__| \|__| > \|__| \|__| |\_________\ |\_________\ > + \|________| = \|_________| > \|_________| > + > diff --git > a/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/postbuild.bat > b/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/postbuild.bat > new file mode 100644 > index 0000000000..c158be23b1 > --- /dev/null > +++ b/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/postbuild.bat > @@ -0,0 +1,96 @@ > +@REM @file > +@REM > +@REM Copyright (c) 2018, Intel Corporation. All rights reserved.
> +@REM Copyright (c) 2021, American Megatrends International LLC.
> +@REM SPDX-License-Identifier: BSD-2-Clause-Patent > +@REM > + > +@set SCRIPT_ERROR=3D0 > + > +set /a postbuildstep=3D0 > + > +@echo. > +@echo BoardPostBuild.%postbuildstep% python PatchBinFv.py > +@set /a postbuildstep=3D%postbuildstep%+1 > +echo python %WORKSPACE%\edk2- > platforms\Platform\Intel\MinPlatformPkg\Tools\PatchFv\PatchBinFv.py > %TARGET% %WORKSPACE%\edk2-non- > osi\Silicon\Intel\PurleySiliconBinPkg\FV > %WORKSPACE%\Build\BuildReport.txt FvTempMemorySilicon > +call %PYTHON_HOME%\python.exe %WORKSPACE%\edk2- > platforms\Platform\Intel\MinPlatformPkg\Tools\PatchFv\PatchBinFv.py > %TARGET% %WORKSPACE%\edk2-non- > osi\Silicon\Intel\PurleySiliconBinPkg\FV > %WORKSPACE%\Build\BuildReport.txt FvTempMemorySilicon > +if %ERRORLEVEL% NEQ 0 ( > + set SCRIPT_ERROR=3D1 > + echo PatchBinFv Error. Exit > + goto :EOF > +) > +echo python %WORKSPACE%\edk2- > platforms\Platform\Intel\MinPlatformPkg\Tools\PatchFv\PatchBinFv.py > %TARGET% %WORKSPACE%\edk2-non- > osi\Silicon\Intel\PurleySiliconBinPkg\FV > %WORKSPACE%\Build\BuildReport.txt FvPreMemorySilicon > +call %PYTHON_HOME%\python.exe %WORKSPACE%\edk2- > platforms\Platform\Intel\MinPlatformPkg\Tools\PatchFv\PatchBinFv.py > %TARGET% %WORKSPACE%\edk2-non- > osi\Silicon\Intel\PurleySiliconBinPkg\FV > %WORKSPACE%\Build\BuildReport.txt FvPreMemorySilicon > +if %ERRORLEVEL% NEQ 0 ( > + set SCRIPT_ERROR=3D1 > + echo PatchBinFv Error. Exit > + goto :EOF > +) > +echo python %WORKSPACE%\edk2- > platforms\Platform\Intel\MinPlatformPkg\Tools\PatchFv\PatchBinFv.py > %TARGET% %WORKSPACE%\edk2-non- > osi\Silicon\Intel\PurleySiliconBinPkg\FV > %WORKSPACE%\Build\BuildReport.txt FvPostMemorySilicon > +call %PYTHON_HOME%\python.exe %WORKSPACE%\edk2- > platforms\Platform\Intel\MinPlatformPkg\Tools\PatchFv\PatchBinFv.py > %TARGET% %WORKSPACE%\edk2-non- > osi\Silicon\Intel\PurleySiliconBinPkg\FV > %WORKSPACE%\Build\BuildReport.txt FvPostMemorySilicon > +if %ERRORLEVEL% NEQ 0 ( > + set SCRIPT_ERROR=3D1 > + echo PatchBinFv Error. Exit > + goto :EOF > +) > +echo python %WORKSPACE%\edk2- > platforms\Platform\Intel\MinPlatformPkg\Tools\PatchFv\PatchBinFv.py > %TARGET% %WORKSPACE%\edk2-non- > osi\Silicon\Intel\PurleySiliconBinPkg\FV > %WORKSPACE%\Build\BuildReport.txt FvLateSilicon > +call %PYTHON_HOME%\python.exe %WORKSPACE%\edk2- > platforms\Platform\Intel\MinPlatformPkg\Tools\PatchFv\PatchBinFv.py > %TARGET% %WORKSPACE%\edk2-non- > osi\Silicon\Intel\PurleySiliconBinPkg\FV > %WORKSPACE%\Build\BuildReport.txt FvLateSilicon > +if %ERRORLEVEL% NEQ 0 ( > + set SCRIPT_ERROR=3D1 > + echo PatchBinFv Error. Exit > + goto :EOF > +) > + > +@echo. > +@echo BoardPostBuild.%postbuildstep% python RebaseBinFv.py > +@set /a postbuildstep=3D%postbuildstep%+1 > +echo python %WORKSPACE%\edk2- > platforms\Platform\Intel\MinPlatformPkg\Tools\PatchFv\RebaseBinFv.py > %TARGET% %WORKSPACE%\edk2-non- > osi\Silicon\Intel\PurleySiliconBinPkg\FV > %WORKSPACE%\Build\BuildReport.txt FvPreMemorySilicon > gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase > +call %PYTHON_HOME%\python.exe %WORKSPACE%\edk2- > platforms\Platform\Intel\MinPlatformPkg\Tools\PatchFv\RebaseBinFv.py > %TARGET% %WORKSPACE%\edk2-non- > osi\Silicon\Intel\PurleySiliconBinPkg\FV > %WORKSPACE%\Build\BuildReport.txt FvPreMemorySilicon > gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase > +if %ERRORLEVEL% NEQ 0 ( > + set SCRIPT_ERROR=3D1 > + echo RebaseBinFv Error. Exit > + goto :EOF > +) > + > +echo python %WORKSPACE%\edk2- > platforms\Platform\Intel\MinPlatformPkg\Tools\PatchFv\RebaseBinFv.py > %TARGET% %WORKSPACE%\edk2-non- > osi\Silicon\Intel\PurleySiliconBinPkg\FV > %WORKSPACE%\Build\BuildReport.txt FvPostMemorySilicon > gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase > +call %PYTHON_HOME%\python.exe %WORKSPACE%\edk2- > platforms\Platform\Intel\MinPlatformPkg\Tools\PatchFv\RebaseBinFv.py > %TARGET% %WORKSPACE%\edk2-non- > osi\Silicon\Intel\PurleySiliconBinPkg\FV > %WORKSPACE%\Build\BuildReport.txt FvPostMemorySilicon > gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase > +if %ERRORLEVEL% NEQ 0 ( > + set SCRIPT_ERROR=3D1 > + echo RebaseBinFv Error. Exit > + goto :EOF > +) > + > +@echo. > +@echo BoardPostBuild.%postbuildstep% re-generate FDS > +@set /a postbuildstep=3D%postbuildstep%+1 > +echo build fds > +@REM call build fds > +if %ERRORLEVEL% NEQ 0 ( > + set SCRIPT_ERROR=3D1 > + echo gen FDS Error. Exit > + goto :EOF > +) > + > +@echo. > +@echo BoardPostBuild.%postbuildstep% python PatchBfv.py > +@set /a postbuildstep=3D%postbuildstep%+1 > +echo python %WORKSPACE%\edk2- > platforms\Platform\Intel\MinPlatformPkg\Tools\PatchFv\PatchBfv.py > %WORKSPACE%\Build\%BOARD_PKG%\%BOARD_NAME%\%TARGET%_%T > OOL_CHAIN_TAG%\FV\PLATFORM.fd %WORKSPACE%\Build\BuildReport.txt > gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase > +call %PYTHON_HOME%\python.exe %WORKSPACE%\edk2- > platforms\Platform\Intel\MinPlatformPkg\Tools\PatchFv\PatchBfv.py > %WORKSPACE%\Build\%BOARD_PKG%\%BOARD_NAME%\%TARGET%_%T > OOL_CHAIN_TAG%\FV\PLATFORM.fd %WORKSPACE%\Build\BuildReport.txt > gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase > +if %ERRORLEVEL% NEQ 0 ( > + set SCRIPT_ERROR=3D1 > + echo PatchBfv Error. Exit > + goto :EOF > +) > + > +:_done > + > +@echo. > +@cd %WORKSPACE% > +@if "%SCRIPT_ERROR%" =3D=3D "0" ( > + @echo PostBuild SUCCEEDED. > +) else ( > + @echo PostBuild FAILED. > + Pause 0 > +) > + > +EXIT /B %SCRIPT_ERROR% > diff --git > a/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/prebuild.bat > b/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/prebuild.bat > new file mode 100644 > index 0000000000..f0ea157482 > --- /dev/null > +++ b/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/prebuild.bat > @@ -0,0 +1,213 @@ > +@REM @file > +@REM > +@REM Copyright (c) 2018, Intel Corporation. All rights reserved.
> +@REM Copyright (c) 2021, American Megatrends International LLC.
> +@REM SPDX-License-Identifier: BSD-2-Clause-Patent > +@REM > + > +@set SCRIPT_ERROR=3D0 > + > +set /a prebuildstep=3D0 > + > +call :check_BuildTools > +if %SCRIPT_ERROR% NEQ 0 GOTO :done > + > +call :setBuildEnv > +if %SCRIPT_ERROR% NEQ 0 GOTO :done > + > +call :createTargetTxt > +if %SCRIPT_ERROR% NEQ 0 GOTO :done > + > +call :genPlatformOffsetHeaderFile > +if %SCRIPT_ERROR% NEQ 0 GOTO :done > + > +:prebuildFinish > +echo. > +echo ACTIVE_PLATFORM =3D %WORKSPACE%\edk2- > platforms\Platform\Intel\%BOARD_PKG%\%BOARD_NAME%\OpenBoardPk > g.dsc > +echo EDK_TOOLS_PATH =3D %EDK_TOOLS_PATH% > +echo TARGET =3D %TARGET% > +echo TARGET_ARCH =3D IA32 X64 > +echo TOOL_CHAIN_TAG =3D %TOOL_CHAIN_TAG% > +echo WORKSPACE =3D %WORKSPACE% > +echo PACKAGES_PATH =3D %PACKAGES_PATH% > +echo MAX_CONCURRENT_THREAD_NUMBER =3D > %BUILD_MAX_CON_THREAD_NUM% > +echo. > +echo Build Path =3D %OUTPUT_DIR% > +echo. > + > +REM Remove environment variable because it's no longer needed. > +set BUILD_MAX_CON_THREAD_NUM=3D > + > +:done > +REM Use done label to exit batch file and run any final steps; GOTO :EOF > immediately exits. > +EXIT /B %SCRIPT_ERROR% > + > +::-------------------------------------------------------- > +::-- Function section starts below here > +::-------------------------------------------------------- > + > +:cleanup_check_VSTools > +set COMPILER_VERSION_STRING=3D > +del cloutput.txt > nul > +REM cleanup_check_VSTools is called below. When a label is called, 'GOTO > :EOF' is used to return to caller. > +GOTO :EOF > + > +:check_BuildTools > +echo PreBuild.%prebuildstep% check_BuildTools > +echo ..VSTools > +set /a prebuildstep=3D%prebuildstep%+1 > +set TOOL_CHAIN_TAG=3D > +@if not defined TOOL_CHAIN_TAG ( > + echo. > + echo Prebuild: TOOL_CHAIN_TAG is not set before > + echo. > + > + @if defined VS140COMNTOOLS ( > + echo. > + echo Set the VS2015 environment. > + echo. > + set CL_SEL=3DVS2015 > + if /I "%VS140COMNTOOLS%" =3D=3D "C:\Program Files\Microsoft Visual S= tudio > 14.0\Common7\Tools\" ( > + set TOOL_CHAIN_TAG=3DVS2015 > + ) else ( > + set TOOL_CHAIN_TAG=3DVS2015x86 > + ) > + if /I "%PROCESSOR_ARCHITECTURE%" =3D=3D "AMD64" ( > + set CL_CMDLINE=3D"%VS140COMNTOOLS:~0,-14%VC\bin\amd64\cl.exe" > + ) else ( > + set CL_CMDLINE=3D"%VS140COMNTOOLS:~0,-14%VC\bin\cl.exe" > + ) > + ) else if defined VS120COMNTOOLS ( > + echo. > + echo Set the VS2013 environment. > + echo. > + set CL_SEL=3DVS2013 > + if /I "%VS120COMNTOOLS%" =3D=3D "C:\Program Files\Microsoft Visual S= tudio > 12.0\Common7\Tools\" ( > + set TOOL_CHAIN_TAG=3DVS2013 > + ) else ( > + set TOOL_CHAIN_TAG=3DVS2013x86 > + ) > + if /I "%PROCESSOR_ARCHITECTURE%" =3D=3D "AMD64" ( > + set CL_CMDLINE=3D"%VS120COMNTOOLS:~0,-14%VC\bin\amd64\cl.exe" > + ) else ( > + set CL_CMDLINE=3D"%VS120COMNTOOLS:~0,-14%VC\bin\cl.exe" > + ) > + ) else ( > + echo. > + echo !!! ERROR !!! VS2015 or VS2013 not installed correctly. !!! > + echo. > + goto :ErrorExit > + ) > +) > + > +echo ..iASL > +set CHECK_PATH_IASL=3D%IASL_PREFIX% > +if not exist %CHECK_PATH_IASL%\iasl.exe ( > + echo. > + echo !!! ERROR !!! Could not find iASL compiler at > %CHECK_PATH_IASL%\iasl.exe. !!! > + echo. > + set SCRIPT_ERROR=3D1 > +) > +set CHECK_PATH_IASL=3D > + > +echo ..NASM > +set CHECK_PATH_NASM=3Dc:\NASM > +if not exist %CHECK_PATH_NASM%\nasm.exe ( > + echo. > + echo !!! ERROR !!! Could not find NASM compiler at > %CHECK_PATH_NASM%\nasm.exe. !!! > + echo. > + set SCRIPT_ERROR=3D1 > +) > +set CHECK_PATH_NASM=3D > + > +echo ..Python > +set CHECK_PATH_PYTHON=3Dc:\Python27 > +if not exist %CHECK_PATH_PYTHON%\python.exe ( > + echo. > + echo !!! ERROR !!! Could not find Python at > %CHECK_PATH_PYTHON%\python.exe. !!! > + echo. > + set SCRIPT_ERROR=3D1 > +) > +set CHECK_PATH_PYTHON=3D > +set PYTHON_HOME=3DC:\Python27 > + > +GOTO :EOF > + > +:setBuildEnv > +echo PreBuild.%prebuildstep% SetBuildEnv > +set /a prebuildstep=3D%prebuildstep%+1 > + > +@set BOARD_PKG=3DPurleyOpenBoardPkg > +@set BOARD_NAME=3DBoardTiogaPass > +@set MAX_SOCKET=3D2 > + > +echo. > +echo BOARD_NAME=3D%BOARD_NAME% > +echo BOARD_PKG=3D%BOARD_PKG% > +echo MAX_SOCKET=3D%MAX_SOCKET% > +echo TARGET=3D%TARGET% > + > +@set > OUTPUT_DIR=3D%WORKSPACE%\Build\%BOARD_PKG%\%BOARD_NAME%\% > TARGET%_%TOOL_CHAIN_TAG% > + > +if not exist %OUTPUT_DIR% mkdir %OUTPUT_DIR% > +GOTO :EOF > + > +:createTargetTxt > +echo PreBuild.%prebuildstep% CreateTargetTxt > +set /a prebuildstep=3D%prebuildstep%+1 > +set /a BUILD_MAX_CON_THREAD_NUM =3D %NUMBER_OF_PROCESSORS%- > 1 > +@REM set /a BUILD_MAX_CON_THREAD_NUM =3D 1 > +findstr /V "ACTIVE_PLATFORM TARGET TARGET_ARCH TOOL_CHAIN_TAG > BUILD_RULE_CONF MAX_CONCURRENT_THREAD_NUMBER" > %WORKSPACE%\Conf\target.txt > %OUTPUT_DIR%\target.txt 2>NUL > +echo ACTIVE_PLATFORM =3D %WORKSPACE%/edk2- > platforms/Platform/Intel/%BOARD_PKG%/%BOARD_NAME%/OpenBoardPk > g.dsc >> %OUTPUT_DIR%\target.txt > +echo TARGET =3D %TARGET% >> > %OUTPUT_DIR%\target.txt > +echo TARGET_ARCH =3D IA32 X64 >> > %OUTPUT_DIR%\target.txt > +echo TOOL_CHAIN_TAG =3D %TOOL_CHAIN_TAG% >> > %OUTPUT_DIR%\target.txt > +echo BUILD_RULE_CONF =3D Conf/build_rule.txt >> > %OUTPUT_DIR%\target.txt > +echo MAX_CONCURRENT_THREAD_NUMBER =3D > %BUILD_MAX_CON_THREAD_NUM% >> %OUTPUT_DIR%\target.txt > +if exist %WORKSPACE%\Conf\target.txt ( > + del /f %WORKSPACE%\Conf\target.txt > +) > +move /Y %OUTPUT_DIR%\target.txt %WORKSPACE%\Conf\ > nul > +if not exist %OUTPUT_DIR%\X64 mkdir %OUTPUT_DIR%\X64 > +GOTO :EOF > + > + > +:genPlatformOffsetHeaderFile > +echo. > +echo PreBuild.%prebuildstep% GenPlatformOffsetHeaderFile > +set /a prebuildstep=3D%prebuildstep%+1 > + > +echo Info: re-generating PlatformOffset header files > + > +set PRE_BUILD_CMD_LINE=3D%BUILD_CMD_LINE% -D > MAX_SOCKET=3D%MAX_SOCKET% > +set PRE_BUILD_LOG=3D%WORKSPACE%\Build\prebuild.log > +set PRE_BUILD_REPORT=3D%WORKSPACE%\Build\preBuildReport.txt > + > +echo build %PRE_BUILD_CMD_LINE% -m > %BOARD_PKG%\Acpi\BoardAcpiDxe\Dsdt.inf -y %PRE_BUILD_REPORT% -- > log=3D%PRE_BUILD_LOG% > +call build %PRE_BUILD_CMD_LINE% -m > %BOARD_PKG%\Acpi\BoardAcpiDxe\Dsdt.inf -y %PRE_BUILD_REPORT% -- > log=3D%PRE_BUILD_LOG% > +if %ERRORLEVEL% NEQ 0 EXIT /b %ERRORLEVEL% > + > +@REM PSYS =3D=3D FIX0 > +@REM MCTL =3D=3D FIX8 > +set AML_FILTER=3D"\"PSYS\" .MCTL\" .FIX[0-9,A-Z]\"" > +echo AML_FILTER=3D%AML_FILTER% > +call %PYTHON_HOME%\python.exe %WORKSPACE%\edk2- > platforms\Platform\Intel\MinPlatformPkg\Tools\AmlGenOffset\AmlGenOff > set.py -d --aml_filter %AML_FILTER% -o %WORKSPACE%\edk2- > platforms\Platform\Intel\%BOARD_PKG%\Acpi\BoardAcpiDxe\AmlOffsetTa > ble.c > %OUTPUT_DIR%\X64\PurleyOpenBoardPkg\Acpi\BoardAcpiDxe\DSDT\OUT > PUT\Dsdt\WFPPlatform.offset.h > +@REM Create copyright header for AML offset file > +( > + echo /** @file > + echo Copyright ^(c^) 2018 - 2019, Intel Corporation. All rights > reserved.^ > + echo Copyright ^(c^) 2021, American Megatrends International > LLC.^ > + echo SPDX-License-Identifier: BSD-2-Clause-Patent > + echo. > + echo **/ > + echo. > +)> %OUTPUT_DIR%\TempCopyright.txt > +@REM Concatenate copyright and AmlOffsetTable, then delete temporary > files > +copy /Y "%OUTPUT_DIR%\TempCopyright.txt" + "%WORKSPACE%\edk2- > platforms\Platform\Intel\%BOARD_PKG%\Acpi\BoardAcpiDxe\AmlOffsetTa > ble.c" "%OUTPUT_DIR%\AmlOffsetTable.c" > nul > +copy /Y "%OUTPUT_DIR%\AmlOffsetTable.c" "%WORKSPACE%\edk2- > platforms\Platform\Intel\%BOARD_PKG%\Acpi\BoardAcpiDxe\AmlOffsetTa > ble.c" > nul > +del /f %OUTPUT_DIR%\TempCopyright.txt > nul > +del /f %OUTPUT_DIR%\AmlOffsetTable.c > nul > +echo. > +echo GenOffset done > + > +GOTO :EOF > \ No newline at end of file > diff --git > a/Platform/Intel/PurleyOpenBoardPkg/Features/Ipmi/Library/IpmiLibKcs/Ip > miLibKcs.inf > b/Platform/Intel/PurleyOpenBoardPkg/Features/Ipmi/Library/IpmiLibKcs/Ip > miLibKcs.inf > index 239e115ad4..f56631fe9e 100644 > --- > a/Platform/Intel/PurleyOpenBoardPkg/Features/Ipmi/Library/IpmiLibKcs/Ip > miLibKcs.inf > +++ > b/Platform/Intel/PurleyOpenBoardPkg/Features/Ipmi/Library/IpmiLibKcs/Ip > miLibKcs.inf > @@ -1,8 +1,8 @@ > ## @file >=20 > # Component description file for IPMI KCS Library. >=20 > # >=20 > -# Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.
>=20 > -# >=20 > +# Copyright (c) 2018, Intel Corporation. All rights reserved.
>=20 > +# Copyright (c) 2021, American Megatrends International LLC.
>=20 > # SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > # >=20 > ## >=20 > @@ -13,7 +13,7 @@ > FILE_GUID =3D 9879DB3A-C2CD-4615-ACDA-95C1B2EC00B= 3 >=20 > MODULE_TYPE =3D UEFI_DRIVER >=20 > VERSION_STRING =3D 1.0 >=20 > - LIBRARY_CLASS =3D IpmiLib >=20 > + LIBRARY_CLASS =3D IpmiBaseLib >=20 >=20 >=20 > [sources] >=20 > IpmiLibKcs.c >=20 > @@ -22,7 +22,7 @@ > [Packages] >=20 > MdePkg/MdePkg.dec >=20 > MdeModulePkg/MdeModulePkg.dec >=20 > - AdvancedFeaturePkg/AdvancedFeaturePkg.dec >=20 > + OutOfBandManagement/IpmiFeaturePkg/IpmiFeaturePkg.dec >=20 > PurleyOpenBoardPkg/OpenBoardPkg.dec >=20 >=20 >=20 > [LibraryClasses] >=20 > @@ -37,4 +37,4 @@ > [Pcd] >=20 > gEfiIpmiPkgTokenSpaceGuid.PcdIpmiKcsTimeoutPeriod >=20 > gEfiIpmiPkgTokenSpaceGuid.PcdIpmiBmcSlaveAddress >=20 > - gAdvancedFeaturePkgTokenSpaceGuid.PcdIpmiIoBaseAddress > \ No newline at end of file > + gIpmiFeaturePkgTokenSpaceGuid.PcdIpmiIoBaseAddress > \ No newline at end of file > diff --git > a/Platform/Intel/PurleyOpenBoardPkg/Features/Ipmi/Library/IpmiPlatform > HookLib/IpmiPlatformHookLib.inf > b/Platform/Intel/PurleyOpenBoardPkg/Features/Ipmi/Library/IpmiPlatform > HookLib/IpmiPlatformHookLib.inf > index 94ab840a02..2bfddce611 100644 > --- > a/Platform/Intel/PurleyOpenBoardPkg/Features/Ipmi/Library/IpmiPlatform > HookLib/IpmiPlatformHookLib.inf > +++ > b/Platform/Intel/PurleyOpenBoardPkg/Features/Ipmi/Library/IpmiPlatform > HookLib/IpmiPlatformHookLib.inf > @@ -1,8 +1,8 @@ > ## @file >=20 > # Component description file for IPMI platform hook Library. >=20 > # >=20 > -# Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.
>=20 > -# >=20 > +# Copyright (c) 2018, Intel Corporation. All rights reserved.
>=20 > +# Copyright (c) 2021, American Megatrends International LLC.
>=20 > # SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > # >=20 > ## >=20 > @@ -20,7 +20,7 @@ >=20 >=20 > [Packages] >=20 > MdePkg/MdePkg.dec >=20 > - AdvancedFeaturePkg/AdvancedFeaturePkg.dec >=20 > + OutOfBandManagement/IpmiFeaturePkg/IpmiFeaturePkg.dec >=20 > PurleyRefreshSiliconPkg/SiPkg.dec >=20 >=20 >=20 > [LibraryClasses] >=20 > diff --git > a/Platform/Intel/PurleyOpenBoardPkg/Include/Guid/PchRcVariable.h > b/Platform/Intel/PurleyOpenBoardPkg/Include/Guid/PchRcVariable.h > index 79b7429052..916562e3b2 100644 > --- a/Platform/Intel/PurleyOpenBoardPkg/Include/Guid/PchRcVariable.h > +++ b/Platform/Intel/PurleyOpenBoardPkg/Include/Guid/PchRcVariable.h > @@ -1,6 +1,7 @@ > /** @file >=20 >=20 >=20 > Copyright (c) 2018, Intel Corporation. All rights reserved.
>=20 > +Copyright (c) 2021, American Megatrends International LLC.
>=20 > SPDX-License-Identifier: BSD-2-Clause-Patent >=20 >=20 >=20 > **/ >=20 > @@ -20,6 +21,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent > typedef struct { >=20 >=20 >=20 > UINT8 BiosGuard; >=20 > + UINT8 Reserved1; >=20 > UINT8 Dwr_Enable; >=20 > UINT8 Dwr_Stall; >=20 > UINT8 Dwr_BmcRootPort; >=20 > @@ -387,6 +389,10 @@ typedef struct { > UINT8 AdrMultiplierVal; >=20 > UINT8 AdrGpioSel; >=20 > UINT8 AdrHostPartitionReset; >=20 > + UINT8 AdrSysPwrOk; >=20 > + UINT8 AdrOverClockingWdt; >=20 > + UINT8 AdrCpuThermalWdt; >=20 > + UINT8 AdrPmcParityError; >=20 >=20 >=20 > // >=20 > // Audio DSP Configuration >=20 > diff --git > a/Platform/Intel/PurleyOpenBoardPkg/Include/Guid/SetupVariable.h > b/Platform/Intel/PurleyOpenBoardPkg/Include/Guid/SetupVariable.h > index f8ea067b50..ed6077b4ee 100644 > --- a/Platform/Intel/PurleyOpenBoardPkg/Include/Guid/SetupVariable.h > +++ b/Platform/Intel/PurleyOpenBoardPkg/Include/Guid/SetupVariable.h > @@ -1,6 +1,7 @@ > /** @file >=20 >=20 >=20 > Copyright (c) 2018, Intel Corporation. All rights reserved.
>=20 > +Copyright (c) 2021, American Megatrends International LLC.
>=20 > SPDX-License-Identifier: BSD-2-Clause-Patent >=20 >=20 >=20 > **/ >=20 > @@ -42,6 +43,13 @@ typedef struct { > UINT8 TpmState; >=20 > UINT8 MorState; >=20 >=20 >=20 > + // >=20 > + // XmlCli >=20 > + // >=20 > + UINT8 XmlCliSupport; >=20 > + UINT8 SkipXmlComprs; >=20 > + UINT8 PublishSetupPgPtr; >=20 > + >=20 > // >=20 > // Breakpoints >=20 > // >=20 > @@ -493,7 +501,6 @@ typedef struct { > UINT8 BClkOverride; >=20 > UINT8 BclkAdjustable; >=20 > UINT8 DmiPegRatio; >=20 > - UINT8 SkipXmlComprs; >=20 > UINT8 DfxAdvDebugJumper; >=20 > UINT8 DfxAltPostCode; >=20 >=20 >=20 > @@ -519,6 +526,12 @@ typedef struct { > // PC_SIO_END >=20 > // >=20 > UINT8 RsaSupport; >=20 > + UINT8 FnvErrorMailbox; // 0 - DDRT, 1 - SMBUS >=20 > + UINT8 ReportAlertSPA; // Include SPA when reporting DDR= T alert. > Only to disable for MCE recovery test. >=20 > + UINT8 AEPErrorInjEn; >=20 > + UINT8 NgnHostAlertPatrolScrubUNC; // Signal DDRT interrupt upon > receiving Uncorrectable Error for NGN Patrol Scrub >=20 > + UINT8 DcpmmUncPoison; >=20 > + UINT8 UCErrChkForVariableSrv; >=20 >=20 >=20 > } SYSTEM_CONFIGURATION; >=20 >=20 >=20 > diff --git a/Platform/Intel/PurleyOpenBoardPkg/OpenBoardPkg.dec > b/Platform/Intel/PurleyOpenBoardPkg/OpenBoardPkg.dec > index 96dd6b5b48..4dcec5430b 100644 > --- a/Platform/Intel/PurleyOpenBoardPkg/OpenBoardPkg.dec > +++ b/Platform/Intel/PurleyOpenBoardPkg/OpenBoardPkg.dec > @@ -6,6 +6,7 @@ > # for the build infrastructure. >=20 > # >=20 > # Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.
>=20 > +# Copyright (c) 2021, American Megatrends International LLC.
>=20 > # >=20 > # SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > # >=20 > diff --git a/Platform/Intel/build.cfg b/Platform/Intel/build.cfg > index ede542f9f5..e3baf9a11d 100644 > --- a/Platform/Intel/build.cfg > +++ b/Platform/Intel/build.cfg > @@ -2,6 +2,7 @@ > # This is the main/default build configuration file >=20 > # >=20 > # Copyright (c) 2019 - 2020, Intel Corporation. All rights reserved.
>=20 > +# Copyright (c) 2021, American Megatrends International LLC.
>=20 > # SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > # >=20 >=20 >=20 > @@ -62,3 +63,4 @@ UpXtreme =3D > WhiskeylakeOpenBoardPkg/UpXtreme/build_config.cfg > WhiskeylakeURvp =3D > WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/build_config.cfg >=20 > CometlakeURvp =3D > CometlakeOpenBoardPkg/CometlakeURvp/build_config.cfg >=20 > TigerlakeURvp =3D TigerlakeOpenBoardPkg/TigerlakeURvp/build_config.cfg >=20 > +BoardTiogaPass =3D PurleyOpenBoardPkg/BoardTiogaPass/build_config.cfg >=20 > diff --git a/Platform/Intel/build_bios.py b/Platform/Intel/build_bios.py > index 8f855f63eb..b55f315f6a 100644 > --- a/Platform/Intel/build_bios.py > +++ b/Platform/Intel/build_bios.py > @@ -4,6 +4,7 @@ > # imported functions from board directory >=20 > # >=20 > # Copyright (c) 2019 - 2020, Intel Corporation. All rights reserved.
>=20 > +# Copyright (c) 2021, American Megatrends International LLC.
>=20 > # SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > # >=20 >=20 >=20 > @@ -130,7 +131,7 @@ def pre_build(build_config, build_type=3D"DEBUG", > silent=3DFalse, toolchain=3DNone): > config["PACKAGES_PATH"] +=3D os.pathsep + filepath >=20 > config["PACKAGES_PATH"] +=3D os.pathsep + > config["WORKSPACE_DRIVERS"] >=20 > config["PACKAGES_PATH"] +=3D os.pathsep + \ >=20 > - os.path.join(config["WORKSPACE"], "FSP") >=20 > + os.path.join(config["WORKSPACE"], config["WORKSPACE_FSP_BIN"]) >=20 > config["PACKAGES_PATH"] +=3D os.pathsep + \ >=20 > os.path.join(config["WORKSPACE"], "edk2") >=20 > config["PACKAGES_PATH"] +=3D os.pathsep + > os.path.join(config["WORKSPACE"]) >=20 > -- > 2.25.0.windows.1 >=20 >=20 > Please consider the environment before printing this email. >=20 > The information contained in this message may be confidential and > proprietary to American Megatrends (AMI). This communication is intended > to be read only by the individual or entity to whom it is addressed or by= their > designee. If the reader of this message is not the intended recipient, yo= u are > on notice that any distribution of this message, in any form, is strictly > prohibited. Please promptly notify the sender by reply e-mail or by > telephone at 770-246-8600, and then delete or destroy all copies of the > transmission.