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X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR11MB1329 Return-Path: nathaniel.l.desimone@intel.com X-OriginatorOrg: intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Nate DeSimone > -----Original Message----- > From: Luo, Heng > Sent: Sunday, January 31, 2021 5:37 PM > To: devel@edk2.groups.io > Cc: Chaganty, Rangasai V ; Desimone, > Nathaniel L > Subject: [PATCH 18/40] TigerlakeSiliconPkg/IpBlock: Add Graphics > component >=20 > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3171 >=20 > Adds the following files: > * IpBlock/Graphics/AcpiTables > * IpBlock/Graphics/IncludePrivate > * IpBlock/Graphics/LibraryPrivate >=20 > Cc: Sai Chaganty > Cc: Nate DeSimone > Signed-off-by: Heng Luo > --- > Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/AcpiTables/Igfx.asl > | 1955 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/AcpiTables/IgfxCommon.= a > sl | 480 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/AcpiTables/IgfxDsm.as= l > | 398 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/AcpiTables/IgfxOpGbda.= as > l | 127 > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/AcpiTables/IgfxOpRn.a= sl > | 314 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/AcpiTables/IgfxOpSbcb.= asl > | 261 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > + > Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/AcpiTables/IgfxSsdt.a= sl > | 73 +++++++++++++++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/AcpiTables/IgfxSsdt.i= nf > | 23 +++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/IncludePrivate/Library= /Dx > eGraphicsInitLib.h | 53 ++++++++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/IncludePrivate/Library= /Dx > eGraphicsPolicyLib.h | 71 ++++++++++++++++++++++++++++= ++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/IncludePrivate/Library= /Dx > eIgdOpRegionInitLib.h | 177 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeGrap= hic > sInitLib/DxeGraphicsInitLib.c | 135 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeGrap= hic > sInitLib/DxeGraphicsInitLib.inf | 45 +++++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeGrap= hic > sPolicyLib/DxeGraphicsPolicyLib.c | 118 > +++++++++++++++++++++++++++++++++++++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeGrap= hic > sPolicyLib/DxeGraphicsPolicyLib.inf | 37 +++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeIgdO= pR > egionInitLib/DxeIgdOpRegionInit.c | 541 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeIgdO= pR > egionInitLib/DxeIgdOpRegionInitLib.inf | 49 ++++++++++++++++++++++ > 17 files changed, 4857 insertions(+) >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/AcpiTables/Igfx.asl > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/AcpiTables/Igfx.asl > new file mode 100644 > index 0000000000..d00a1d8f58 > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/AcpiTables/Igfx.= asl > @@ -0,0 +1,1955 @@ > +/** @file >=20 > + This file contains the IGD OpRegion/Software ACPI Reference >=20 > + Code. >=20 > + It defines the methods to enable/disable output switching, >=20 > + store display switching and LCD brightness BIOS control >=20 > + and return valid addresses for all display device encoders >=20 > + present in the system, etc. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +External(\PLD1, MethodObj) >=20 > +External(\PLD2, MethodObj) >=20 > +External(\ECST, MethodObj) >=20 > +External(\PBCL, MethodObj) >=20 > +External(HDOS, MethodObj) >=20 > +External(\ECON, IntObj) >=20 > +External(\PNHM, IntObj) >=20 > +External(OSYS, IntObj) >=20 > +External(CPSC) >=20 > +External(\GUAM, MethodObj) >=20 > +External(DSEN) >=20 > +External(S0ID) >=20 > + >=20 > +// >=20 > +// Default Physical Location of Device >=20 > +// >=20 > +Name (DPLD, Package (0x1) { >=20 > + ToPLD ( >=20 > + PLD_Revision =3D 0x2, >=20 > + PLD_IgnoreColor =3D 0x1, >=20 > + PLD_Red =3D 0x0, >=20 > + PLD_Green =3D 0x0, >=20 > + PLD_Blue =3D 0x0, >=20 > + PLD_Width =3D 0x320, //800 mm >=20 > + PLD_Height =3D 0x7D0, //2000 mm >=20 > + PLD_UserVisible =3D 0x1, //Set if the device connect= ion point can be > seen by the user without disassembly. >=20 > + PLD_Dock =3D 0x0, // Set if the device connec= tion point resides > in a docking station or port replicator. >=20 > + PLD_Lid =3D 0x0, // Set if this device conne= ction point resides on > the lid of laptop system. >=20 > + PLD_Panel =3D "TOP", // Describes which p= anel surface of the > systems housing the device connection point resides on. >=20 > + PLD_VerticalPosition =3D "CENTER", // Vertical Position= on the panel > where the device connection point resides. >=20 > + PLD_HorizontalPosition =3D "RIGHT", // Horizontal Positi= on on the > panel where the device connection point resides. >=20 > + PLD_Shape =3D "VERTICALRECTANGLE", >=20 > + PLD_GroupOrientation =3D 0x0, // if Set, indicates vertic= al grouping, > otherwise horizontal is assumed. >=20 > + PLD_GroupToken =3D 0x0, // Unique numerical value i= dentifying a > group. >=20 > + PLD_GroupPosition =3D 0x0, // Identifies this device c= onnection > points position in the group (i.e. 1st, 2nd) >=20 > + PLD_Bay =3D 0x0, // Set if describing a devi= ce in a bay or if device > connection point is a bay. >=20 > + PLD_Ejectable =3D 0x0, // Set if the device is eje= ctable. Indicates > ejectability in the absence of _EJx objects >=20 > + PLD_EjectRequired =3D 0x0, // OSPM Ejection required: = Set if OSPM > needs to be involved with ejection process. User-operated physical > hardware ejection is not possible. >=20 > + PLD_CabinetNumber =3D 0x0, // For single cabinet syste= m, this field > is always 0. >=20 > + PLD_CardCageNumber =3D 0x0, // For single card cage sys= tem, this > field is always 0. >=20 > + PLD_Reference =3D 0x0, // if Set, this _PLD define= s a reference > shape that is used to help orient the user with respect to the other shap= es > when rendering _PLDs. >=20 > + PLD_Rotation =3D 0x0, // 0 - 0deg, 1 - 45deg, 2 -= 90deg, 3 - 135deg, > 4 - 180deg, 5 - 225deg, 6 - 270deg, 7 - 315deg >=20 > + PLD_Order =3D 0x3, // Identifies the drawing o= rder of the > connection point described by a _PLD >=20 > + PLD_VerticalOffset =3D 0x0, >=20 > + PLD_HorizontalOffset =3D 0x0 >=20 > + ) >=20 > + } // Package >=20 > +) //DPLD >=20 > + >=20 > +// Enable/Disable Output Switching. In WIN2K/WINXP, _DOS =3D 0 will >=20 > +// get called during initialization to prepare for an ACPI Display >=20 > +// Switch Event. During an ACPI Display Switch, the OS will call >=20 > +// _DOS =3D 2 immediately after a Notify=3D0x80 to temporarily disable >=20 > +// all Display Switching. After ACPI Display Switching is complete, >=20 > +// the OS will call _DOS =3D 0 to re-enable ACPI Display Switching. >=20 > +Method(_DOS,1) >=20 > +{ >=20 > + // >=20 > + // Store Display Switching and LCD brightness BIOS control bit >=20 > + // >=20 > + Store(And(Arg0,7),DSEN) >=20 > + >=20 > + If(LEqual(And(Arg0, 0x3), 0)) // If _DOS[1:0]=3D0 >=20 > + { >=20 > + If(CondRefOf(HDOS)) >=20 > + { >=20 > + HDOS() >=20 > + } >=20 > + } >=20 > +} >=20 > + >=20 > +// >=20 > +// Enumerate the Display Environment. This method will return >=20 > +// valid addresses for all display device encoders present in the >=20 > +// system. The Miniport Driver will reject the addresses for every >=20 > +// encoder that does not have an attached display device. After >=20 > +// enumeration is complete, the OS will call the _DGS methods >=20 > +// during a display switch only for the addresses accepted by the >=20 > +// Miniport Driver. For hot-insertion and removal of display >=20 > +// devices, a re-enumeration notification will be required so the >=20 > +// address of the newly present display device will be accepted by >=20 > +// the Miniport Driver. >=20 > +// >=20 > +Method(_DOD,0) >=20 > +{ >=20 > + // >=20 > + // Two LFP devices are supporte by default >=20 > + // >=20 > + Store(2, NDID) >=20 > + If(LNotEqual(DIDL, Zero)) >=20 > + { >=20 > + Store(SDDL(DIDL),DID1) >=20 > + } >=20 > + If(LNotEqual(DDL2, Zero)) >=20 > + { >=20 > + Store(SDDL(DDL2),DID2) >=20 > + } >=20 > + If(LNotEqual(DDL3, Zero)) >=20 > + { >=20 > + Store(SDDL(DDL3),DID3) >=20 > + } >=20 > + If(LNotEqual(DDL4, Zero)) >=20 > + { >=20 > + Store(SDDL(DDL4),DID4) >=20 > + } >=20 > + If(LNotEqual(DDL5, Zero)) >=20 > + { >=20 > + Store(SDDL(DDL5),DID5) >=20 > + } >=20 > + If(LNotEqual(DDL6, Zero)) >=20 > + { >=20 > + Store(SDDL(DDL6),DID6) >=20 > + } >=20 > + If(LNotEqual(DDL7, Zero)) >=20 > + { >=20 > + Store(SDDL(DDL7),DID7) >=20 > + } >=20 > + If(LNotEqual(DDL8, Zero)) >=20 > + { >=20 > + Store(SDDL(DDL8),DID8) >=20 > + } >=20 > + If(LNotEqual(DDL9, Zero)) >=20 > + { >=20 > + Store(SDDL(DDL9),DID9) >=20 > + } >=20 > + If(LNotEqual(DD10, Zero)) >=20 > + { >=20 > + Store(SDDL(DD10),DIDA) >=20 > + } >=20 > + If(LNotEqual(DD11, Zero)) >=20 > + { >=20 > + Store(SDDL(DD11),DIDB) >=20 > + } >=20 > + If(LNotEqual(DD12, Zero)) >=20 > + { >=20 > + Store(SDDL(DD12),DIDC) >=20 > + } >=20 > + If(LNotEqual(DD13, Zero)) >=20 > + { >=20 > + Store(SDDL(DD13),DIDD) >=20 > + } >=20 > + If(LNotEqual(DD14, Zero)) >=20 > + { >=20 > + Store(SDDL(DD14),DIDE) >=20 > + } >=20 > + If(LNotEqual(DD15, Zero)) >=20 > + { >=20 > + Store(SDDL(DD15),DIDF) >=20 > + } >=20 > + >=20 > + // >=20 > + // Enumerate the encoders. Note that for >=20 > + // current silicon, the maximum number of encoders >=20 > + // possible is 15. >=20 > + // >=20 > + If(LEqual(NDID,1)) >=20 > + { >=20 > + Name(TMP1,Package() { >=20 > + 0xFFFFFFFF}) >=20 > + If (LEqual(IPTP,1)) { >=20 > + // >=20 > + // IGFX need report IPUA as GFX0 child >=20 > + // >=20 > + Store(0x00023480,Index(TMP1,0)) >=20 > + } Else { >=20 > + Store(Or(0x10000,DID1),Index(TMP1,0)) >=20 > + } >=20 > + Return(TMP1) >=20 > + } >=20 > + >=20 > + If(LEqual(NDID,2)) >=20 > + { >=20 > + Name(TMP2,Package() { >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF}) >=20 > + Store(Or(0x10000,DID1),Index(TMP2,0)) >=20 > + If (LEqual(IPTP,1)) { >=20 > + // >=20 > + // IGFX need report IPUA as GFX0 child >=20 > + // >=20 > + Store(0x00023480,Index(TMP2,1)) >=20 > + } Else { >=20 > + Store(Or(0x10000,DID2),Index(TMP2,1)) >=20 > + } >=20 > + Return(TMP2) >=20 > + } >=20 > + >=20 > + If(LEqual(NDID,3)) >=20 > + { >=20 > + Name(TMP3,Package() { >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF}) >=20 > + Store(Or(0x10000,DID1),Index(TMP3,0)) >=20 > + Store(Or(0x10000,DID2),Index(TMP3,1)) >=20 > + If (LEqual(IPTP,1)) { >=20 > + // >=20 > + // IGFX need report IPUA as GFX0 child >=20 > + // >=20 > + Store(0x00023480,Index(TMP3,2)) >=20 > + } Else { >=20 > + Store(Or(0x10000,DID3),Index(TMP3,2)) >=20 > + } >=20 > + Return(TMP3) >=20 > + } >=20 > + >=20 > + If(LEqual(NDID,4)) >=20 > + { >=20 > + Name(TMP4,Package() { >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF}) >=20 > + Store(Or(0x10000,DID1),Index(TMP4,0)) >=20 > + Store(Or(0x10000,DID2),Index(TMP4,1)) >=20 > + Store(Or(0x10000,DID3),Index(TMP4,2)) >=20 > + If (LEqual(IPTP,1)) { >=20 > + // >=20 > + // IGFX need report IPUA as GFX0 child >=20 > + // >=20 > + Store(0x00023480,Index(TMP4,3)) >=20 > + } Else { >=20 > + Store(Or(0x10000,DID4),Index(TMP4,3)) >=20 > + } >=20 > + Return(TMP4) >=20 > + } >=20 > + >=20 > + If(LEqual(NDID,5)) >=20 > + { >=20 > + Name(TMP5,Package() { >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF}) >=20 > + Store(Or(0x10000,DID1),Index(TMP5,0)) >=20 > + Store(Or(0x10000,DID2),Index(TMP5,1)) >=20 > + Store(Or(0x10000,DID3),Index(TMP5,2)) >=20 > + Store(Or(0x10000,DID4),Index(TMP5,3)) >=20 > + If (LEqual(IPTP,1)) { >=20 > + // >=20 > + // IGFX need report IPUA as GFX0 child >=20 > + // >=20 > + Store(0x00023480,Index(TMP5,4)) >=20 > + } Else { >=20 > + Store(Or(0x10000,DID5),Index(TMP5,4)) >=20 > + } >=20 > + Return(TMP5) >=20 > + } >=20 > + >=20 > + If(LEqual(NDID,6)) >=20 > + { >=20 > + Name(TMP6,Package() { >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF}) >=20 > + Store(Or(0x10000,DID1),Index(TMP6,0)) >=20 > + Store(Or(0x10000,DID2),Index(TMP6,1)) >=20 > + Store(Or(0x10000,DID3),Index(TMP6,2)) >=20 > + Store(Or(0x10000,DID4),Index(TMP6,3)) >=20 > + Store(Or(0x10000,DID5),Index(TMP6,4)) >=20 > + If (LEqual(IPTP,1)) { >=20 > + // >=20 > + // IGFX need report IPUA as GFX0 child >=20 > + // >=20 > + Store(0x00023480,Index(TMP6,5)) >=20 > + } Else { >=20 > + Store(Or(0x10000,DID6),Index(TMP6,5)) >=20 > + } >=20 > + Return(TMP6) >=20 > + } >=20 > + >=20 > + If(LEqual(NDID,7)) >=20 > + { >=20 > + Name(TMP7,Package() { >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF}) >=20 > + Store(Or(0x10000,DID1),Index(TMP7,0)) >=20 > + Store(Or(0x10000,DID2),Index(TMP7,1)) >=20 > + Store(Or(0x10000,DID3),Index(TMP7,2)) >=20 > + Store(Or(0x10000,DID4),Index(TMP7,3)) >=20 > + Store(Or(0x10000,DID5),Index(TMP7,4)) >=20 > + Store(Or(0x10000,DID6),Index(TMP7,5)) >=20 > + If (LEqual(IPTP,1)) { >=20 > + // >=20 > + // IGFX need report IPUA as GFX0 child >=20 > + // >=20 > + Store(0x00023480,Index(TMP7,6)) >=20 > + } Else { >=20 > + Store(Or(0x10000,DID7),Index(TMP7,6)) >=20 > + } >=20 > + Return(TMP7) >=20 > + } >=20 > + >=20 > + If(LEqual(NDID,8)) >=20 > + { >=20 > + Name(TMP8,Package() { >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF}) >=20 > + Store(Or(0x10000,DID1),Index(TMP8,0)) >=20 > + Store(Or(0x10000,DID2),Index(TMP8,1)) >=20 > + Store(Or(0x10000,DID3),Index(TMP8,2)) >=20 > + Store(Or(0x10000,DID4),Index(TMP8,3)) >=20 > + Store(Or(0x10000,DID5),Index(TMP8,4)) >=20 > + Store(Or(0x10000,DID6),Index(TMP8,5)) >=20 > + Store(Or(0x10000,DID7),Index(TMP8,6)) >=20 > + If (LEqual(IPTP,1)) { >=20 > + // >=20 > + // IGFX need report IPUA as GFX0 child >=20 > + // >=20 > + Store(0x00023480,Index(TMP8,7)) >=20 > + } Else { >=20 > + Store(Or(0x10000,DID8),Index(TMP8,7)) >=20 > + } >=20 > + Return(TMP8) >=20 > + } >=20 > + >=20 > + If(LEqual(NDID,9)) >=20 > + { >=20 > + Name(TMP9,Package() { >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF}) >=20 > + Store(Or(0x10000,DID1),Index(TMP9,0)) >=20 > + Store(Or(0x10000,DID2),Index(TMP9,1)) >=20 > + Store(Or(0x10000,DID3),Index(TMP9,2)) >=20 > + Store(Or(0x10000,DID4),Index(TMP9,3)) >=20 > + Store(Or(0x10000,DID5),Index(TMP9,4)) >=20 > + Store(Or(0x10000,DID6),Index(TMP9,5)) >=20 > + Store(Or(0x10000,DID7),Index(TMP9,6)) >=20 > + Store(Or(0x10000,DID8),Index(TMP9,7)) >=20 > + If (LEqual(IPTP,1)) { >=20 > + // >=20 > + // IGFX need report IPUA as GFX0 child >=20 > + // >=20 > + Store(0x00023480,Index(TMP9,8)) >=20 > + } Else { >=20 > + Store(Or(0x10000,DID9),Index(TMP9,8)) >=20 > + } >=20 > + Return(TMP9) >=20 > + } >=20 > + >=20 > + If(LEqual(NDID,0x0A)) >=20 > + { >=20 > + Name(TMPA,Package() { >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF}) >=20 > + Store(Or(0x10000,DID1),Index(TMPA,0)) >=20 > + Store(Or(0x10000,DID2),Index(TMPA,1)) >=20 > + Store(Or(0x10000,DID3),Index(TMPA,2)) >=20 > + Store(Or(0x10000,DID4),Index(TMPA,3)) >=20 > + Store(Or(0x10000,DID5),Index(TMPA,4)) >=20 > + Store(Or(0x10000,DID6),Index(TMPA,5)) >=20 > + Store(Or(0x10000,DID7),Index(TMPA,6)) >=20 > + Store(Or(0x10000,DID8),Index(TMPA,7)) >=20 > + Store(Or(0x10000,DID9),Index(TMPA,8)) >=20 > + If (LEqual(IPTP,1)) { >=20 > + // >=20 > + // IGFX need report IPUA as GFX0 child >=20 > + // >=20 > + Store(0x00023480,Index(TMPA,9)) >=20 > + } Else { >=20 > + Store(Or(0x10000,DIDA),Index(TMPA,9)) >=20 > + } >=20 > + Return(TMPA) >=20 > + } >=20 > + >=20 > + If(LEqual(NDID,0x0B)) >=20 > + { >=20 > + Name(TMPB,Package() { >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF}) >=20 > + Store(Or(0x10000,DID1),Index(TMPB,0)) >=20 > + Store(Or(0x10000,DID2),Index(TMPB,1)) >=20 > + Store(Or(0x10000,DID3),Index(TMPB,2)) >=20 > + Store(Or(0x10000,DID4),Index(TMPB,3)) >=20 > + Store(Or(0x10000,DID5),Index(TMPB,4)) >=20 > + Store(Or(0x10000,DID6),Index(TMPB,5)) >=20 > + Store(Or(0x10000,DID7),Index(TMPB,6)) >=20 > + Store(Or(0x10000,DID8),Index(TMPB,7)) >=20 > + Store(Or(0x10000,DID9),Index(TMPB,8)) >=20 > + Store(Or(0x10000,DIDA),Index(TMPB,9)) >=20 > + If (LEqual(IPTP,1)) { >=20 > + // >=20 > + // IGFX need report IPUA as GFX0 child >=20 > + // >=20 > + Store(0x00023480,Index(TMPB,10)) >=20 > + } Else { >=20 > + Store(Or(0x10000,DIDB),Index(TMPB,10)) >=20 > + } >=20 > + Return(TMPB) >=20 > + } >=20 > + >=20 > + If(LEqual(NDID,0x0C)) >=20 > + { >=20 > + Name(TMPC,Package() { >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF}) >=20 > + Store(Or(0x10000,DID1),Index(TMPC,0)) >=20 > + Store(Or(0x10000,DID2),Index(TMPC,1)) >=20 > + Store(Or(0x10000,DID3),Index(TMPC,2)) >=20 > + Store(Or(0x10000,DID4),Index(TMPC,3)) >=20 > + Store(Or(0x10000,DID5),Index(TMPC,4)) >=20 > + Store(Or(0x10000,DID6),Index(TMPC,5)) >=20 > + Store(Or(0x10000,DID7),Index(TMPC,6)) >=20 > + Store(Or(0x10000,DID8),Index(TMPC,7)) >=20 > + Store(Or(0x10000,DID9),Index(TMPC,8)) >=20 > + Store(Or(0x10000,DIDA),Index(TMPC,9)) >=20 > + Store(Or(0x10000,DIDB),Index(TMPC,10)) >=20 > + If (LEqual(IPTP,1)) { >=20 > + // >=20 > + // IGFX need report IPUA as GFX0 child >=20 > + // >=20 > + Store(0x00023480,Index(TMPC,11)) >=20 > + } Else { >=20 > + Store(Or(0x10000,DIDC),Index(TMPC,11)) >=20 > + } >=20 > + Return(TMPC) >=20 > + } >=20 > + >=20 > + If(LEqual(NDID,0x0D)) >=20 > + { >=20 > + Name(TMPD,Package() { >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF}) >=20 > + Store(Or(0x10000,DID1),Index(TMPD,0)) >=20 > + Store(Or(0x10000,DID2),Index(TMPD,1)) >=20 > + Store(Or(0x10000,DID3),Index(TMPD,2)) >=20 > + Store(Or(0x10000,DID4),Index(TMPD,3)) >=20 > + Store(Or(0x10000,DID5),Index(TMPD,4)) >=20 > + Store(Or(0x10000,DID6),Index(TMPD,5)) >=20 > + Store(Or(0x10000,DID7),Index(TMPD,6)) >=20 > + Store(Or(0x10000,DID8),Index(TMPD,7)) >=20 > + Store(Or(0x10000,DID9),Index(TMPD,8)) >=20 > + Store(Or(0x10000,DIDA),Index(TMPD,9)) >=20 > + Store(Or(0x10000,DIDB),Index(TMPD,10)) >=20 > + Store(Or(0x10000,DIDC),Index(TMPD,11)) >=20 > + If (LEqual(IPTP,1)) { >=20 > + // >=20 > + // IGFX need report IPUA as GFX0 child >=20 > + // >=20 > + Store(0x00023480,Index(TMPD,12)) >=20 > + } Else { >=20 > + Store(Or(0x10000,DIDD),Index(TMPD,12)) >=20 > + } >=20 > + Return(TMPD) >=20 > + } >=20 > + >=20 > + If(LEqual(NDID,0x0E)) >=20 > + { >=20 > + Name(TMPE,Package() { >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF}) >=20 > + Store(Or(0x10000,DID1),Index(TMPE,0)) >=20 > + Store(Or(0x10000,DID2),Index(TMPE,1)) >=20 > + Store(Or(0x10000,DID3),Index(TMPE,2)) >=20 > + Store(Or(0x10000,DID4),Index(TMPE,3)) >=20 > + Store(Or(0x10000,DID5),Index(TMPE,4)) >=20 > + Store(Or(0x10000,DID6),Index(TMPE,5)) >=20 > + Store(Or(0x10000,DID7),Index(TMPE,6)) >=20 > + Store(Or(0x10000,DID8),Index(TMPE,7)) >=20 > + Store(Or(0x10000,DID9),Index(TMPE,8)) >=20 > + Store(Or(0x10000,DIDA),Index(TMPE,9)) >=20 > + Store(Or(0x10000,DIDB),Index(TMPE,10)) >=20 > + Store(Or(0x10000,DIDC),Index(TMPE,11)) >=20 > + Store(Or(0x10000,DIDD),Index(TMPE,12)) >=20 > + If (LEqual(IPTP,1)) { >=20 > + // >=20 > + // IGFX need report IPUA as GFX0 child >=20 > + // >=20 > + Store(0x00023480,Index(TMPE,13)) >=20 > + } Else { >=20 > + Store(Or(0x10000,DIDE),Index(TMPE,13)) >=20 > + } >=20 > + Return(TMPE) >=20 > + } >=20 > + >=20 > + If(LEqual(NDID,0x0F)) >=20 > + { >=20 > + Name(TMPF,Package() { >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF}) >=20 > + Store(Or(0x10000,DID1),Index(TMPF,0)) >=20 > + Store(Or(0x10000,DID2),Index(TMPF,1)) >=20 > + Store(Or(0x10000,DID3),Index(TMPF,2)) >=20 > + Store(Or(0x10000,DID4),Index(TMPF,3)) >=20 > + Store(Or(0x10000,DID5),Index(TMPF,4)) >=20 > + Store(Or(0x10000,DID6),Index(TMPF,5)) >=20 > + Store(Or(0x10000,DID7),Index(TMPF,6)) >=20 > + Store(Or(0x10000,DID8),Index(TMPF,7)) >=20 > + Store(Or(0x10000,DID9),Index(TMPF,8)) >=20 > + Store(Or(0x10000,DIDA),Index(TMPF,9)) >=20 > + Store(Or(0x10000,DIDB),Index(TMPF,10)) >=20 > + Store(Or(0x10000,DIDC),Index(TMPF,11)) >=20 > + Store(Or(0x10000,DIDD),Index(TMPF,12)) >=20 > + Store(Or(0x10000,DIDE),Index(TMPF,13)) >=20 > + If (LEqual(IPTP,1)) { >=20 > + // >=20 > + // IGFX need report IPUA as GFX0 child >=20 > + // >=20 > + Store(0x00023480,Index(TMPF,14)) >=20 > + } Else { >=20 > + Store(Or(0x10000,DIDF),Index(TMPF,14)) >=20 > + } >=20 > + Return(TMPF) >=20 > + } >=20 > + >=20 > + If(LEqual(NDID,0x10)) >=20 > + { >=20 > + Name(TMPG,Package() { >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF, >=20 > + 0xFFFFFFFF}) >=20 > + Store(Or(0x10000,DID1),Index(TMPG,0)) >=20 > + Store(Or(0x10000,DID2),Index(TMPG,1)) >=20 > + Store(Or(0x10000,DID3),Index(TMPG,2)) >=20 > + Store(Or(0x10000,DID4),Index(TMPG,3)) >=20 > + Store(Or(0x10000,DID5),Index(TMPG,4)) >=20 > + Store(Or(0x10000,DID6),Index(TMPG,5)) >=20 > + Store(Or(0x10000,DID7),Index(TMPG,6)) >=20 > + Store(Or(0x10000,DID8),Index(TMPG,7)) >=20 > + Store(Or(0x10000,DID9),Index(TMPG,8)) >=20 > + Store(Or(0x10000,DIDA),Index(TMPG,9)) >=20 > + Store(Or(0x10000,DIDB),Index(TMPG,10)) >=20 > + Store(Or(0x10000,DIDC),Index(TMPG,11)) >=20 > + Store(Or(0x10000,DIDD),Index(TMPG,12)) >=20 > + Store(Or(0x10000,DIDE),Index(TMPG,13)) >=20 > + Store(Or(0x10000,DIDF),Index(TMPG,14)) >=20 > + // >=20 > + // IGFX need report IPUA as GFX0 child >=20 > + // NDID can only be 0x10 if IPU is enabled >=20 > + // >=20 > + Store(0x00023480,Index(TMPG,15)) >=20 > + Return(TMPG) >=20 > + } >=20 > + >=20 > + // >=20 > + // If nothing else, return Unknown LFP. >=20 > + // (Prevents compiler warning.) >=20 > + // >=20 > + Return(Package() {0x00000400}) >=20 > +} >=20 > + >=20 > +Device(DD01) >=20 > +{ >=20 > + // >=20 > + // Return Unique ID. >=20 > + // >=20 > + Method(_ADR,0,Serialized) >=20 > + { >=20 > + If(LEqual(And(0x0F00,DID1),0x400)) >=20 > + { >=20 > + Store(0x1, EDPV) >=20 > + Store(NXD1, NXDX) >=20 > + Store(DID1, DIDX) >=20 > + Return(1) >=20 > + } >=20 > + If(LEqual(DID1,0)) >=20 > + { >=20 > + Return(1) >=20 > + } >=20 > + Else >=20 > + { >=20 > + Return(And(0xFFFF,DID1)) >=20 > + } >=20 > + } >=20 > + >=20 > + // >=20 > + // Return the Current Status. >=20 > + // >=20 > + Method(_DCS,0) >=20 > + { >=20 > + Return(CDDS(DID1)) >=20 > + } >=20 > + >=20 > + // >=20 > + // Query Graphics State (active or inactive). >=20 > + // >=20 > + Method(_DGS,0) >=20 > + { >=20 > + If(LAnd(LEqual(And(HGMD,0x7F),0x01),CondRefOf(SNXD))) >=20 > + { >=20 > + Return (NXD1) >=20 > + } >=20 > + Return(NDDS(DID1)) >=20 > + } >=20 > + >=20 > + // >=20 > + // Device Set State. >=20 > + // >=20 > + Method(_DSS,1) >=20 > + { >=20 > + DSST(Arg0) >=20 > + } >=20 > +} >=20 > + >=20 > +Device(DD02) >=20 > +{ >=20 > + // >=20 > + // Return Unique ID. >=20 > + // >=20 > + Method(_ADR,0,Serialized) >=20 > + { >=20 > + If(LEqual(And(0x0F00,DID2),0x400)) >=20 > + { >=20 > + If(LEqual(And(0xF,DID2),0x1)) >=20 > + { >=20 > + Store(0x2, EDPV) >=20 > + Store(NXD2, NXDY) >=20 > + Store(DID2, DIDY) >=20 > + Return(2) >=20 > + } >=20 > + Store(0x2, EDPV) >=20 > + Store(NXD2, NXDX) >=20 > + Store(DID2, DIDX) >=20 > + Return(2) >=20 > + } >=20 > + If(LEqual(DID2,0)) >=20 > + { >=20 > + Return(2) >=20 > + } >=20 > + Else >=20 > + { >=20 > + Return(And(0xFFFF,DID2)) >=20 > + } >=20 > + } >=20 > + >=20 > + // >=20 > + // Return the Current Status. >=20 > + // >=20 > + Method(_DCS,0) >=20 > + { >=20 > + If(LEqual(LIDS,0)) >=20 > + { >=20 > + Return(0x0) >=20 > + } >=20 > + Return(CDDS(DID2)) >=20 > + } >=20 > + >=20 > + // >=20 > + // Query Graphics State (active or inactive). >=20 > + // >=20 > + Method(_DGS,0) >=20 > + { >=20 > + // >=20 > + // Return the Next State. >=20 > + // >=20 > + If(LAnd(LEqual(And(HGMD,0x7F),0x01),CondRefOf(SNXD))) >=20 > + { >=20 > + Return (NXD2) >=20 > + } >=20 > + Return(NDDS(DID2)) >=20 > + } >=20 > + >=20 > + // >=20 > + // Device Set State. >=20 > + // >=20 > + Method(_DSS,1) >=20 > + { >=20 > + DSST(Arg0) >=20 > + } >=20 > +} >=20 > + >=20 > +Device(DD03) >=20 > +{ >=20 > + // >=20 > + // Return Unique ID. >=20 > + // >=20 > + Method(_ADR,0,Serialized) >=20 > + { >=20 > + If(LEqual(And(0x0F00,DID3),0x400)) >=20 > + { >=20 > + Store(0x3, EDPV) >=20 > + Store(NXD3, NXDX) >=20 > + Store(DID3, DIDX) >=20 > + Return(3) >=20 > + } >=20 > + If(LEqual(DID3,0)) >=20 > + { >=20 > + Return(3) >=20 > + } >=20 > + Else >=20 > + { >=20 > + Return(And(0xFFFF,DID3)) >=20 > + } >=20 > + } >=20 > + >=20 > + // >=20 > + // Return the Current Status. >=20 > + // >=20 > + Method(_DCS,0) >=20 > + { >=20 > + If(LEqual(DID3,0)) >=20 > + { >=20 > + Return(0x0B) >=20 > + } >=20 > + Else >=20 > + { >=20 > + Return(CDDS(DID3)) >=20 > + } >=20 > + } >=20 > + >=20 > + // >=20 > + // Query Graphics State (active or inactive). >=20 > + // >=20 > + Method(_DGS,0) >=20 > + { >=20 > + If(LAnd(LEqual(And(HGMD,0x7F),0x01),CondRefOf(SNXD))) >=20 > + { >=20 > + Return (NXD3) >=20 > + } >=20 > + Return(NDDS(DID3)) >=20 > + } >=20 > + >=20 > + // >=20 > + // Device Set State. >=20 > + // >=20 > + Method(_DSS,1) >=20 > + { >=20 > + DSST(Arg0) >=20 > + } >=20 > +} >=20 > + >=20 > +Device(DD04) >=20 > +{ >=20 > + // >=20 > + // Return Unique ID. >=20 > + // >=20 > + Method(_ADR,0,Serialized) >=20 > + { >=20 > + If(LEqual(And(0x0F00,DID4),0x400)) >=20 > + { >=20 > + Store(0x4, EDPV) >=20 > + Store(NXD4, NXDX) >=20 > + Store(DID4, DIDX) >=20 > + Return(4) >=20 > + } >=20 > + If(LEqual(DID4,0)) >=20 > + { >=20 > + Return(4) >=20 > + } >=20 > + Else >=20 > + { >=20 > + Return(And(0xFFFF,DID4)) >=20 > + } >=20 > + } >=20 > + >=20 > + // >=20 > + // Return the Current Status. >=20 > + // >=20 > + Method(_DCS,0) >=20 > + { >=20 > + If(LEqual(DID4,0)) >=20 > + { >=20 > + Return(0x0B) >=20 > + } >=20 > + Else >=20 > + { >=20 > + Return(CDDS(DID4)) >=20 > + } >=20 > + } >=20 > + >=20 > + // >=20 > + // Query Graphics State (active or inactive). >=20 > + // >=20 > + Method(_DGS,0) >=20 > + { >=20 > + If(LAnd(LEqual(And(HGMD,0x7F),0x01),CondRefOf(SNXD))) >=20 > + { >=20 > + Return (NXD4) >=20 > + } >=20 > + Return(NDDS(DID4)) >=20 > + } >=20 > + >=20 > + // >=20 > + // Device Set State. (See table above.) >=20 > + // >=20 > + Method(_DSS,1) >=20 > + { >=20 > + DSST(Arg0) >=20 > + } >=20 > +} >=20 > + >=20 > +Device(DD05) >=20 > +{ >=20 > + // >=20 > + // Return Unique ID. >=20 > + // >=20 > + Method(_ADR,0,Serialized) >=20 > + { >=20 > + If(LEqual(And(0x0F00,DID5),0x400)) >=20 > + { >=20 > + Store(0x5, EDPV) >=20 > + Store(NXD5, NXDX) >=20 > + Store(DID5, DIDX) >=20 > + Return(5) >=20 > + } >=20 > + If(LEqual(DID5,0)) >=20 > + { >=20 > + Return(5) >=20 > + } >=20 > + Else >=20 > + { >=20 > + Return(And(0xFFFF,DID5)) >=20 > + } >=20 > + } >=20 > + >=20 > + // >=20 > + // Return the Current Status. >=20 > + // >=20 > + Method(_DCS,0) >=20 > + { >=20 > + If(LEqual(DID5,0)) >=20 > + { >=20 > + Return(0x0B) >=20 > + } >=20 > + Else >=20 > + { >=20 > + Return(CDDS(DID5)) >=20 > + } >=20 > + } >=20 > + >=20 > + // >=20 > + // Query Graphics State (active or inactive). >=20 > + // >=20 > + Method(_DGS,0) >=20 > + { >=20 > + If(LAnd(LEqual(And(HGMD,0x7F),0x01),CondRefOf(SNXD))) >=20 > + { >=20 > + Return (NXD5) >=20 > + } >=20 > + Return(NDDS(DID5)) >=20 > + } >=20 > + >=20 > + // >=20 > + // Device Set State. >=20 > + // >=20 > + Method(_DSS,1) >=20 > + { >=20 > + DSST(Arg0) >=20 > + } >=20 > +} >=20 > + >=20 > +Device(DD06) >=20 > +{ >=20 > + // >=20 > + // Return Unique ID. >=20 > + // >=20 > + Method(_ADR,0,Serialized) >=20 > + { >=20 > + If(LEqual(And(0x0F00,DID6),0x400)) >=20 > + { >=20 > + Store(0x6, EDPV) >=20 > + Store(NXD6, NXDX) >=20 > + Store(DID6, DIDX) >=20 > + Return(6) >=20 > + } >=20 > + If(LEqual(DID6,0)) >=20 > + { >=20 > + Return(6) >=20 > + } >=20 > + Else >=20 > + { >=20 > + Return(And(0xFFFF,DID6)) >=20 > + } >=20 > + } >=20 > + >=20 > + // >=20 > + // Return the Current Status. >=20 > + // >=20 > + Method(_DCS,0) >=20 > + { >=20 > + If(LEqual(DID6,0)) >=20 > + { >=20 > + Return(0x0B) >=20 > + } >=20 > + Else >=20 > + { >=20 > + Return(CDDS(DID6)) >=20 > + } >=20 > + } >=20 > + >=20 > + // >=20 > + // Query Graphics State (active or inactive). >=20 > + // >=20 > + Method(_DGS,0) >=20 > + { >=20 > + If(LAnd(LEqual(And(HGMD,0x7F),0x01),CondRefOf(SNXD))) >=20 > + { >=20 > + Return (NXD6) >=20 > + } >=20 > + Return(NDDS(DID6)) >=20 > + } >=20 > + >=20 > + // >=20 > + // Device Set State. >=20 > + // >=20 > + Method(_DSS,1) >=20 > + { >=20 > + DSST(Arg0) >=20 > + } >=20 > +} >=20 > + >=20 > +Device(DD07) >=20 > +{ >=20 > + // >=20 > + // Return Unique ID. >=20 > + // >=20 > + Method(_ADR,0,Serialized) >=20 > + { >=20 > + If(LEqual(And(0x0F00,DID7),0x400)) >=20 > + { >=20 > + Store(0x7, EDPV) >=20 > + Store(NXD7, NXDX) >=20 > + Store(DID7, DIDX) >=20 > + Return(7) >=20 > + } >=20 > + If(LEqual(DID7,0)) >=20 > + { >=20 > + Return(7) >=20 > + } >=20 > + Else >=20 > + { >=20 > + Return(And(0xFFFF,DID7)) >=20 > + } >=20 > + } >=20 > + >=20 > + // >=20 > + // Return the Current Status. >=20 > + // >=20 > + Method(_DCS,0) >=20 > + { >=20 > + If(LEqual(DID7,0)) >=20 > + { >=20 > + Return(0x0B) >=20 > + } >=20 > + Else >=20 > + { >=20 > + Return(CDDS(DID7)) >=20 > + } >=20 > + } >=20 > + >=20 > + // >=20 > + // Query Graphics State (active or inactive). >=20 > + // >=20 > + Method(_DGS,0) >=20 > + { >=20 > + If(LAnd(LEqual(And(HGMD,0x7F),0x01),CondRefOf(SNXD))) >=20 > + { >=20 > + Return (NXD7) >=20 > + } >=20 > + Return(NDDS(DID7)) >=20 > + } >=20 > + >=20 > + // >=20 > + // Device Set State. >=20 > + // >=20 > + Method(_DSS,1) >=20 > + { >=20 > + DSST(Arg0) >=20 > + } >=20 > +} >=20 > + >=20 > +Device(DD08) >=20 > +{ >=20 > + // >=20 > + // Return Unique ID. >=20 > + // >=20 > + Method(_ADR,0,Serialized) >=20 > + { >=20 > + If(LEqual(And(0x0F00,DID8),0x400)) >=20 > + { >=20 > + Store(0x8, EDPV) >=20 > + Store(NXD8, NXDX) >=20 > + Store(DID8, DIDX) >=20 > + Return(8) >=20 > + } >=20 > + If(LEqual(DID8,0)) >=20 > + { >=20 > + Return(8) >=20 > + } >=20 > + Else >=20 > + { >=20 > + Return(And(0xFFFF,DID8)) >=20 > + } >=20 > + } >=20 > + >=20 > + // >=20 > + // Return the Current Status. >=20 > + // >=20 > + Method(_DCS,0) >=20 > + { >=20 > + If(LEqual(DID8,0)) >=20 > + { >=20 > + Return(0x0B) >=20 > + } >=20 > + Else >=20 > + { >=20 > + Return(CDDS(DID8)) >=20 > + } >=20 > + } >=20 > + >=20 > + // >=20 > + // Query Graphics State (active or inactive). >=20 > + // >=20 > + Method(_DGS,0) >=20 > + { >=20 > + If(LAnd(LEqual(And(HGMD,0x7F),0x01),CondRefOf(SNXD))) >=20 > + { >=20 > + Return (NXD8) >=20 > + } >=20 > + Return(NDDS(DID8)) >=20 > + } >=20 > + >=20 > + // >=20 > + // Device Set State. >=20 > + // >=20 > + Method(_DSS,1) >=20 > + { >=20 > + DSST(Arg0) >=20 > + } >=20 > +} >=20 > + >=20 > +Device(DD09) >=20 > +{ >=20 > + // >=20 > + // Return Unique ID. >=20 > + // >=20 > + Method(_ADR,0,Serialized) >=20 > + { >=20 > + If(LEqual(And(0x0F00,DID9),0x400)) >=20 > + { >=20 > + Store(0x9, EDPV) >=20 > + Store(NXD8, NXDX) >=20 > + Store(DID9, DIDX) >=20 > + Return(9) >=20 > + } >=20 > + If(LEqual(DID9,0)) >=20 > + { >=20 > + Return(9) >=20 > + } >=20 > + Else >=20 > + { >=20 > + Return(And(0xFFFF,DID9)) >=20 > + } >=20 > + } >=20 > + >=20 > + // >=20 > + // Return the Current Status. >=20 > + // >=20 > + Method(_DCS,0) >=20 > + { >=20 > + If(LEqual(DID9,0)) >=20 > + { >=20 > + Return(0x0B) >=20 > + } >=20 > + Else >=20 > + { >=20 > + Return(CDDS(DID9)) >=20 > + } >=20 > + } >=20 > + >=20 > + // >=20 > + // Query Graphics State (active or inactive). >=20 > + // >=20 > + Method(_DGS,0) >=20 > + { >=20 > + If(LAnd(LEqual(And(HGMD,0x7F),0x01),CondRefOf(SNXD))) >=20 > + { >=20 > + Return (NXD8) >=20 > + } >=20 > + Return(NDDS(DID9)) >=20 > + } >=20 > + >=20 > + // >=20 > + // Device Set State. >=20 > + // >=20 > + Method(_DSS,1) >=20 > + { >=20 > + DSST(Arg0) >=20 > + } >=20 > +} >=20 > + >=20 > +Device(DD0A) >=20 > +{ >=20 > + // >=20 > + // Return Unique ID. >=20 > + // >=20 > + Method(_ADR,0,Serialized) >=20 > + { >=20 > + If(LEqual(And(0x0F00,DIDA),0x400)) >=20 > + { >=20 > + Store(0xA, EDPV) >=20 > + Store(NXD8, NXDX) >=20 > + Store(DIDA, DIDX) >=20 > + Return(0x0A) >=20 > + } >=20 > + If(LEqual(DIDA,0)) >=20 > + { >=20 > + Return(0x0A) >=20 > + } >=20 > + Else >=20 > + { >=20 > + Return(And(0xFFFF,DIDA)) >=20 > + } >=20 > + } >=20 > + >=20 > + // >=20 > + // Return the Current Status. >=20 > + // >=20 > + Method(_DCS,0) >=20 > + { >=20 > + If(LEqual(DIDA,0)) >=20 > + { >=20 > + Return(0x0B) >=20 > + } >=20 > + Else >=20 > + { >=20 > + Return(CDDS(DIDA)) >=20 > + } >=20 > + } >=20 > + >=20 > + // >=20 > + // Query Graphics State (active or inactive). >=20 > + // >=20 > + Method(_DGS,0) >=20 > + { >=20 > + If(LAnd(LEqual(And(HGMD,0x7F),0x01),CondRefOf(SNXD))) >=20 > + { >=20 > + Return (NXD8) >=20 > + } >=20 > + Return(NDDS(DIDA)) >=20 > + } >=20 > + >=20 > + // >=20 > + // Device Set State. >=20 > + // >=20 > + Method(_DSS,1) >=20 > + { >=20 > + DSST(Arg0) >=20 > + } >=20 > +} >=20 > + >=20 > +Device(DD0B) >=20 > +{ >=20 > + // >=20 > + // Return Unique ID. >=20 > + // >=20 > + Method(_ADR,0,Serialized) >=20 > + { >=20 > + If(LEqual(And(0x0F00,DIDB),0x400)) >=20 > + { >=20 > + Store(0xB, EDPV) >=20 > + Store(NXD8, NXDX) >=20 > + Store(DIDB, DIDX) >=20 > + Return(0X0B) >=20 > + } >=20 > + If(LEqual(DIDB,0)) >=20 > + { >=20 > + Return(0x0B) >=20 > + } >=20 > + Else >=20 > + { >=20 > + Return(And(0xFFFF,DIDB)) >=20 > + } >=20 > + } >=20 > + >=20 > + // >=20 > + // Return the Current Status. >=20 > + // >=20 > + Method(_DCS,0) >=20 > + { >=20 > + If(LEqual(DIDB,0)) >=20 > + { >=20 > + Return(0x0B) >=20 > + } >=20 > + Else >=20 > + { >=20 > + Return(CDDS(DIDB)) >=20 > + } >=20 > + } >=20 > + >=20 > + // >=20 > + // Query Graphics State (active or inactive). >=20 > + // >=20 > + Method(_DGS,0) >=20 > + { >=20 > + If(LAnd(LEqual(And(HGMD,0x7F),0x01),CondRefOf(SNXD))) >=20 > + { >=20 > + Return (NXD8) >=20 > + } >=20 > + Return(NDDS(DIDB)) >=20 > + } >=20 > + >=20 > + // >=20 > + // Device Set State. >=20 > + // >=20 > + Method(_DSS,1) >=20 > + { >=20 > + DSST(Arg0) >=20 > + } >=20 > +} >=20 > + >=20 > +Device(DD0C) >=20 > +{ >=20 > + // >=20 > + // Return Unique ID. >=20 > + // >=20 > + Method(_ADR,0,Serialized) >=20 > + { >=20 > + If(LEqual(And(0x0F00,DIDC),0x400)) >=20 > + { >=20 > + Store(0xC, EDPV) >=20 > + Store(NXD8, NXDX) >=20 > + Store(DIDC, DIDX) >=20 > + Return(0X0C) >=20 > + } >=20 > + If(LEqual(DIDC,0)) >=20 > + { >=20 > + Return(0x0C) >=20 > + } >=20 > + Else >=20 > + { >=20 > + Return(And(0xFFFF,DIDC)) >=20 > + } >=20 > + } >=20 > + >=20 > + // >=20 > + // Return the Current Status. >=20 > + // >=20 > + Method(_DCS,0) >=20 > + { >=20 > + If(LEqual(DIDC,0)) >=20 > + { >=20 > + Return(0x0C) >=20 > + } >=20 > + Else >=20 > + { >=20 > + Return(CDDS(DIDC)) >=20 > + } >=20 > + } >=20 > + >=20 > + // >=20 > + // Query Graphics State (active or inactive). >=20 > + // >=20 > + Method(_DGS,0) >=20 > + { >=20 > + If(LAnd(LEqual(And(HGMD,0x7F),0x01),CondRefOf(SNXD))) >=20 > + { >=20 > + Return (NXD8) >=20 > + } >=20 > + Return(NDDS(DIDC)) >=20 > + } >=20 > + >=20 > + // >=20 > + // Device Set State. >=20 > + // >=20 > + Method(_DSS,1) >=20 > + { >=20 > + DSST(Arg0) >=20 > + } >=20 > +} >=20 > + >=20 > +Device(DD0D) >=20 > +{ >=20 > + // >=20 > + // Return Unique ID. >=20 > + // >=20 > + Method(_ADR,0,Serialized) >=20 > + { >=20 > + If(LEqual(And(0x0F00,DIDD),0x400)) >=20 > + { >=20 > + Store(0xD, EDPV) >=20 > + Store(NXD8, NXDX) >=20 > + Store(DIDD, DIDX) >=20 > + Return(0X0D) >=20 > + } >=20 > + If(LEqual(DIDD,0)) >=20 > + { >=20 > + Return(0x0D) >=20 > + } >=20 > + Else >=20 > + { >=20 > + Return(And(0xFFFF,DIDD)) >=20 > + } >=20 > + } >=20 > + >=20 > + // >=20 > + // Return the Current Status. >=20 > + // >=20 > + Method(_DCS,0) >=20 > + { >=20 > + If(LEqual(DIDD,0)) >=20 > + { >=20 > + Return(0x0D) >=20 > + } >=20 > + Else >=20 > + { >=20 > + Return(CDDS(DIDD)) >=20 > + } >=20 > + } >=20 > + >=20 > + // >=20 > + // Query Graphics State (active or inactive). >=20 > + // >=20 > + Method(_DGS,0) >=20 > + { >=20 > + If(LAnd(LEqual(And(HGMD,0x7F),0x01),CondRefOf(SNXD))) >=20 > + { >=20 > + Return (NXD8) >=20 > + } >=20 > + Return(NDDS(DIDD)) >=20 > + } >=20 > + >=20 > + // >=20 > + // Device Set State. >=20 > + // >=20 > + Method(_DSS,1) >=20 > + { >=20 > + DSST(Arg0) >=20 > + } >=20 > +} >=20 > + >=20 > +Device(DD0E) >=20 > +{ >=20 > + // >=20 > + // Return Unique ID. >=20 > + // >=20 > + Method(_ADR,0,Serialized) >=20 > + { >=20 > + If(LEqual(And(0x0F00,DIDE),0x400)) >=20 > + { >=20 > + Store(0xE, EDPV) >=20 > + Store(NXD8, NXDX) >=20 > + Store(DIDE, DIDX) >=20 > + Return(0X0E) >=20 > + } >=20 > + If(LEqual(DIDE,0)) >=20 > + { >=20 > + Return(0x0E) >=20 > + } >=20 > + Else >=20 > + { >=20 > + Return(And(0xFFFF,DIDE)) >=20 > + } >=20 > + } >=20 > + >=20 > + // >=20 > + // Return the Current Status. >=20 > + // >=20 > + Method(_DCS,0) >=20 > + { >=20 > + If(LEqual(DIDE,0)) >=20 > + { >=20 > + Return(0x0E) >=20 > + } >=20 > + Else >=20 > + { >=20 > + Return(CDDS(DIDE)) >=20 > + } >=20 > + } >=20 > + >=20 > + // >=20 > + // Query Graphics State (active or inactive). >=20 > + // >=20 > + Method(_DGS,0) >=20 > + { >=20 > + If(LAnd(LEqual(And(HGMD,0x7F),0x01),CondRefOf(SNXD))) >=20 > + { >=20 > + Return (NXD8) >=20 > + } >=20 > + Return(NDDS(DIDE)) >=20 > + } >=20 > + >=20 > + // >=20 > + // Device Set State. >=20 > + // >=20 > + Method(_DSS,1) >=20 > + { >=20 > + DSST(Arg0) >=20 > + } >=20 > +} >=20 > + >=20 > +Device(DD0F) >=20 > +{ >=20 > + // >=20 > + // Return Unique ID. >=20 > + // >=20 > + Method(_ADR,0,Serialized) >=20 > + { >=20 > + If(LEqual(And(0x0F00,DIDF),0x400)) >=20 > + { >=20 > + Store(0xF, EDPV) >=20 > + Store(NXD8, NXDX) >=20 > + Store(DIDF, DIDX) >=20 > + Return(0X0F) >=20 > + } >=20 > + If(LEqual(DIDF,0)) >=20 > + { >=20 > + Return(0x0F) >=20 > + } >=20 > + Else >=20 > + { >=20 > + Return(And(0xFFFF,DIDF)) >=20 > + } >=20 > + } >=20 > + >=20 > + // >=20 > + // Return the Current Status. >=20 > + // >=20 > + Method(_DCS,0) >=20 > + { >=20 > + If(LEqual(DIDC,0)) >=20 > + { >=20 > + Return(0x0F) >=20 > + } >=20 > + Else >=20 > + { >=20 > + Return(CDDS(DIDF)) >=20 > + } >=20 > + } >=20 > + >=20 > + // >=20 > + // Query Graphics State (active or inactive). >=20 > + // >=20 > + Method(_DGS,0) >=20 > + { >=20 > + If(LAnd(LEqual(And(HGMD,0x7F),0x01),CondRefOf(SNXD))) >=20 > + { >=20 > + Return (NXD8) >=20 > + } >=20 > + Return(NDDS(DIDF)) >=20 > + } >=20 > + >=20 > + // >=20 > + // Device Set State. >=20 > + // >=20 > + Method(_DSS,1) >=20 > + { >=20 > + DSST(Arg0) >=20 > + } >=20 > +} >=20 > + >=20 > +// >=20 > +//Device for eDP >=20 > +// >=20 > +Device(DD1F) >=20 > +{ >=20 > + // >=20 > + // Return Unique ID. >=20 > + // >=20 > + Method(_ADR,0,Serialized) >=20 > + { >=20 > + If(LEqual(EDPV, 0x0)) >=20 > + { >=20 > + Return(0x1F) >=20 > + } >=20 > + Else >=20 > + { >=20 > + Return(And(0xFFFF,DIDX)) >=20 > + } >=20 > + } >=20 > + >=20 > + // >=20 > + // Return the Current Status. >=20 > + // >=20 > + Method(_DCS,0) >=20 > + { >=20 > + If(LEqual(EDPV, 0x0)) >=20 > + { >=20 > + Return(0x00) >=20 > + } >=20 > + Else >=20 > + { >=20 > + Return(CDDS(DIDX)) >=20 > + } >=20 > + } >=20 > + >=20 > + // >=20 > + // Query Graphics State (active or inactive). >=20 > + // >=20 > + Method(_DGS,0) >=20 > + { >=20 > + If(LAnd(LEqual(And(HGMD,0x7F),0x01),CondRefOf(SNXD))) >=20 > + { >=20 > + Return (NXDX) >=20 > + } >=20 > + Return(NDDS(DIDX)) >=20 > + } >=20 > + >=20 > + // >=20 > + // Device Set State. >=20 > + // >=20 > + Method(_DSS,1) >=20 > + { >=20 > + DSST(Arg0) >=20 > + } >=20 > + >=20 > + // >=20 > + // Query List of Brightness Control Levels Supported. >=20 > + // >=20 > + Method(_BCL,0) >=20 > + { >=20 > + // >=20 > + // List of supported brightness levels in the following sequence. >=20 > + // Level when machine has full power. >=20 > + // Level when machine is on batteries. >=20 > + // Other supported levels. >=20 > + // >=20 > + If(CondRefOf(\PBCL)) { >=20 > + Return (PBCL()) >=20 > + } Else { >=20 > + Return(Package(){80, 50, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12,= 13, 14, 15, 16, > 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 3= 5, 36, 37, 38, > 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 5= 7, 58, 59, 60, > 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 7= 9, 80, 81, 82, > 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100}) >=20 > + } >=20 > + } >=20 > + >=20 > + // >=20 > + // Set the Brightness Level. >=20 > + // >=20 > + Method (_BCM,1) >=20 > + { >=20 > + // >=20 > + // Set the requested level if it is between 0 and 100%. >=20 > + // >=20 > + If(LAnd(LGreaterEqual(Arg0,0),LLessEqual(Arg0,100))) >=20 > + { >=20 > + \_SB.PC00.GFX0.AINT(1, Arg0) >=20 > + Store(Arg0,BRTL) // Store Brightness Level. >=20 > + } >=20 > + } >=20 > + >=20 > + // >=20 > + // Brightness Query Current level. >=20 > + // >=20 > + Method (_BQC,0) >=20 > + { >=20 > + Return(BRTL) >=20 > + } >=20 > + >=20 > + // >=20 > + // Physical Location of Device >=20 > + // >=20 > + Method (_PLD,0) >=20 > + { >=20 > + If(CondRefOf(\PLD1)) { >=20 > + Return (PLD1()) >=20 > + } Else { >=20 > + Return (DPLD) >=20 > + } >=20 > + } >=20 > +} >=20 > + >=20 > +// >=20 > +// Second Display >=20 > +// >=20 > +Device(DD2F) >=20 > +{ >=20 > + // >=20 > + // Return Unique ID. >=20 > + // >=20 > + Method(_ADR,0,Serialized) >=20 > + { >=20 > + If(LEqual(EDPV, 0x0)) >=20 > + { >=20 > + Return(0x1F) >=20 > + } >=20 > + If(LEqual(EDPV, 0x1)) >=20 > + { >=20 > + Return(0x1F) >=20 > + } >=20 > + Else >=20 > + { >=20 > + Return(And(0xFFFF,DIDY)) >=20 > + } >=20 > + } >=20 > + >=20 > + // >=20 > + // Return the Current Status. >=20 > + // >=20 > + Method(_DCS,0) >=20 > + { >=20 > + If(LEqual(EDPV, 0x0)) >=20 > + { >=20 > + Return(0x00) >=20 > + } >=20 > + If(LEqual(EDPV, 0x1)) >=20 > + { >=20 > + Return(0x0) >=20 > + } >=20 > + Else >=20 > + { >=20 > + Return(CDDS(DIDY)) >=20 > + } >=20 > + } >=20 > + >=20 > + // >=20 > + // Query Graphics State (active or inactive). >=20 > + // >=20 > + Method(_DGS,0) >=20 > + { >=20 > + If(LAnd(LEqual(And(HGMD,0x7F),0x01),CondRefOf(SNXD))) >=20 > + { >=20 > + Return (NXDY) >=20 > + } >=20 > + Return(NDDS(DIDY)) >=20 > + } >=20 > + >=20 > + // >=20 > + // Device Set State. >=20 > + // >=20 > + Method(_DSS,1) >=20 > + { >=20 > + DSST(Arg0) >=20 > + } >=20 > + >=20 > + // >=20 > + // Query List of Brightness Control Levels Supported. >=20 > + // >=20 > + Method(_BCL,0) >=20 > + { >=20 > + // >=20 > + // List of supported brightness levels in the following sequence. >=20 > + // Level when machine has full power. >=20 > + // Level when machine is on batteries. >=20 > + // Other supported levels. >=20 > + // >=20 > + If(CondRefOf(\PBCL)) { >=20 > + Return (PBCL()) >=20 > + } Else { >=20 > + Return(Package(){80, 50, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12,= 13, 14, 15, 16, > 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 3= 5, 36, 37, 38, > 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 5= 7, 58, 59, 60, > 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 7= 9, 80, 81, 82, > 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100}) >=20 > + } >=20 > + } >=20 > + >=20 > + // >=20 > + // Set the Brightness Level. >=20 > + // >=20 > + Method (_BCM,1) >=20 > + { >=20 > + // >=20 > + // Set the requested level if it is between 0 and 100%. >=20 > + // >=20 > + If(LAnd(LGreaterEqual(Arg0,0),LLessEqual(Arg0,100))) >=20 > + { >=20 > + \_SB.PC00.GFX0.AINT(1, Arg0) >=20 > + Store(Arg0,BRTL) // Store Brightness Level. >=20 > + } >=20 > + } >=20 > + >=20 > + // >=20 > + // Brightness Query Current level. >=20 > + // >=20 > + Method (_BQC,0) >=20 > + { >=20 > + Return(BRTL) >=20 > + } >=20 > + >=20 > + Method (_PLD,0) >=20 > + { >=20 > + If(CondRefOf(\PLD2)) { >=20 > + Return (PLD2()) >=20 > + } Else { >=20 > + Return (DPLD) >=20 > + } >=20 > + } >=20 > +} >=20 > + >=20 > +Method(SDDL,1) >=20 > +{ >=20 > + Increment(NDID) >=20 > + Store(And(Arg0,0xF0F),Local0) >=20 > + Or(0x80000000,Local0, Local1) >=20 > + If(LEqual(DIDL,Local0)) >=20 > + { >=20 > + Return(Local1) >=20 > + } >=20 > + If(LEqual(DDL2,Local0)) >=20 > + { >=20 > + Return(Local1) >=20 > + } >=20 > + If(LEqual(DDL3,Local0)) >=20 > + { >=20 > + Return(Local1) >=20 > + } >=20 > + If(LEqual(DDL4,Local0)) >=20 > + { >=20 > + Return(Local1) >=20 > + } >=20 > + If(LEqual(DDL5,Local0)) >=20 > + { >=20 > + Return(Local1) >=20 > + } >=20 > + If(LEqual(DDL6,Local0)) >=20 > + { >=20 > + Return(Local1) >=20 > + } >=20 > + If(LEqual(DDL7,Local0)) >=20 > + { >=20 > + Return(Local1) >=20 > + } >=20 > + If(LEqual(DDL8,Local0)) >=20 > + { >=20 > + Return(Local1) >=20 > + } >=20 > + If(LEqual(DDL9,Local0)) >=20 > + { >=20 > + Return(Local1) >=20 > + } >=20 > + If(LEqual(DD10,Local0)) >=20 > + { >=20 > + Return(Local1) >=20 > + } >=20 > + If(LEqual(DD11,Local0)) >=20 > + { >=20 > + Return(Local1) >=20 > + } >=20 > + If(LEqual(DD12,Local0)) >=20 > + { >=20 > + Return(Local1) >=20 > + } >=20 > + If(LEqual(DD13,Local0)) >=20 > + { >=20 > + Return(Local1) >=20 > + } >=20 > + If(LEqual(DD14,Local0)) >=20 > + { >=20 > + Return(Local1) >=20 > + } >=20 > + If(LEqual(DD15,Local0)) >=20 > + { >=20 > + Return(Local1) >=20 > + } >=20 > + Return(0) >=20 > +} >=20 > + >=20 > +Method(CDDS,1) >=20 > +{ >=20 > + Store(And(Arg0,0xF0F),Local0) >=20 > + >=20 > + If(LEqual(0, Local0)) >=20 > + { >=20 > + Return(0x1D) >=20 > + } >=20 > + If(LEqual(CADL, Local0)) >=20 > + { >=20 > + Return(0x1F) >=20 > + } >=20 > + If(LEqual(CAL2, Local0)) >=20 > + { >=20 > + Return(0x1F) >=20 > + } >=20 > + If(LEqual(CAL3, Local0)) >=20 > + { >=20 > + Return(0x1F) >=20 > + } >=20 > + If(LEqual(CAL4, Local0)) >=20 > + { >=20 > + Return(0x1F) >=20 > + } >=20 > + If(LEqual(CAL5, Local0)) >=20 > + { >=20 > + Return(0x1F) >=20 > + } >=20 > + If(LEqual(CAL6, Local0)) >=20 > + { >=20 > + Return(0x1F) >=20 > + } >=20 > + If(LEqual(CAL7, Local0)) >=20 > + { >=20 > + Return(0x1F) >=20 > + } >=20 > + If(LEqual(CAL8, Local0)) >=20 > + { >=20 > + Return(0x1F) >=20 > + } >=20 > + Return(0x1D) >=20 > +} >=20 > + >=20 > +Method(NDDS,1) >=20 > +{ >=20 > + Store(And(Arg0,0xF0F),Local0) >=20 > + >=20 > + If(LEqual(0, Local0)) >=20 > + { >=20 > + Return(0) >=20 > + } >=20 > + If(LEqual(NADL, Local0)) >=20 > + { >=20 > + Return(1) >=20 > + } >=20 > + If(LEqual(NDL2, Local0)) >=20 > + { >=20 > + Return(1) >=20 > + } >=20 > + If(LEqual(NDL3, Local0)) >=20 > + { >=20 > + Return(1) >=20 > + } >=20 > + If(LEqual(NDL4, Local0)) >=20 > + { >=20 > + Return(1) >=20 > + } >=20 > + If(LEqual(NDL5, Local0)) >=20 > + { >=20 > + Return(1) >=20 > + } >=20 > + If(LEqual(NDL6, Local0)) >=20 > + { >=20 > + Return(1) >=20 > + } >=20 > + If(LEqual(NDL7, Local0)) >=20 > + { >=20 > + Return(1) >=20 > + } >=20 > + If(LEqual(NDL8, Local0)) >=20 > + { >=20 > + Return(1) >=20 > + } >=20 > + Return(0) >=20 > +} >=20 > + >=20 > +// >=20 > +// Device Set State Table >=20 > +// BIT31 BIT30 Execution >=20 > +// 0 0 Don't implement. >=20 > +// 0 1 Cache change. Nothing to Implement. >=20 > +// 1 0 Don't Implement. >=20 > +// 1 1 Display Switch Complete. Implement. >=20 > +// >=20 > +Method(DSST,1) >=20 > +{ >=20 > + If(LEqual(And(Arg0,0xC0000000),0xC0000000)) >=20 > + { >=20 > + // >=20 > + // State change was performed by the >=20 > + // Video Drivers. Simply update the >=20 > + // New State. >=20 > + // >=20 > + Store(NSTE,CSTE) >=20 > + } >=20 > +} >=20 > + >=20 > +// >=20 > +// Include IGD OpRegion/Software SCI interrupt handler/DSM which is used > by >=20 > +// the graphics drivers to request data from system BIOS. >=20 > +// >=20 > +include ("IgfxOpRn.asl") >=20 > +include ("IgfxDsm.asl") >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/AcpiTables/IgfxCommo > n.asl > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/AcpiTables/IgfxCommo > n.asl > new file mode 100644 > index 0000000000..7325b9fdea > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/AcpiTables/IgfxCommo > n.asl > @@ -0,0 +1,480 @@ > +/** @file >=20 > + IGD OpRegion/Software SCI Reference Code. >=20 > + This file contains ASL code with the purpose of handling events >=20 > + i.e. hotkeys and other system interrupts. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +// >=20 > +// Notes: >=20 > +// 1. The following routines are to be called from the appropriate event >=20 > +// handlers. >=20 > +// 2. This code cannot comprehend the exact implementation in the OEM's > BIOS. >=20 > +// Therefore, an OEM must call these methods from the existing event >=20 > +// handler infrastructure. Details on when/why to call each method i= s >=20 > +// included in the method header under the "usage" section. >=20 > +// >=20 > + >=20 > +/********************************************************* > ***************; >=20 > +;* ACPI Notification Methods >=20 > +;********************************************************* > ***************/ >=20 > + >=20 > + >=20 > +/********************************************************* > ***************; >=20 > +;* >=20 > +;* Name: PDRD >=20 > +;* >=20 > +;* Description: Check if the graphics driver is ready to process >=20 > +;* notifications and video extensions. >=20 > +;* >=20 > +;* Usage: This method is to be called prior to performing any >=20 > +;* notifications or handling video extensions. >=20 > +;* Ex: If (PDRD()) {Return (FAIL)} >=20 > +;* >=20 > +;* Input: None >=20 > +;* >=20 > +;* Output: None >=20 > +;* >=20 > +;* References: DRDY (Driver ready status), ASLP (Driver recommended >=20 > +;* sleep timeout value). >=20 > +;* >=20 > +;********************************************************* > ***************/ >=20 > + >=20 > +External(HNOT, MethodObj) >=20 > + >=20 > +Method(PDRD) >=20 > +{ >=20 > + // >=20 > + // If DRDY is clear, the driver is not ready. If the return value is >=20 > + // !=3D0, do not perform any notifications or video extension handling= . >=20 > + // >=20 > + Return(LNot(DRDY)) >=20 > +} >=20 > + >=20 > +/********************************************************* > ***************; >=20 > +;* >=20 > +;* Name: PSTS >=20 > +;* >=20 > +;* Description: Check if the graphics driver has completed the previous >=20 > +;* "notify" command. >=20 > +;* >=20 > +;* Usage: This method is called before every "notify" command. A >=20 > +;* "notify" should only be set if the driver has completed = the >=20 > +;* previous command. Else, ignore the event and exit the p= arent >=20 > +;* method. >=20 > +;* Ex: If (PSTS()) {Return (FAIL)} >=20 > +;* >=20 > +;* Input: None >=20 > +;* >=20 > +;* Output: None >=20 > +;* >=20 > +;* References: CSTS (Notification status), ASLP (Driver recommended sle= ep >=20 > +;* timeout value). >=20 > +;* >=20 > +;********************************************************* > ***************/ >=20 > + >=20 > +Method(PSTS) >=20 > +{ >=20 > + If(LGreater(CSTS, 2)) >=20 > + { >=20 > + // >=20 > + // Sleep for ASLP milliseconds if the status is not "success, >=20 > + // failure, or pending" >=20 > + // >=20 > + Sleep(ASLP) >=20 > + } >=20 > + >=20 > + Return(LEqual(CSTS, 3)) // Return True if still Dispatched >=20 > +} >=20 > + >=20 > +/********************************************************* > ***************; >=20 > +;* >=20 > +;* Name: GNOT >=20 > +;* >=20 > +;* Description: Call the appropriate methods to query the graphics drive= r >=20 > +;* status. If all methods return success, do a notificatio= n of >=20 > +;* the graphics device. >=20 > +;* >=20 > +;* Usage: This method is to be called when a graphics device >=20 > +;* notification is required (display switch hotkey, etc). >=20 > +;* >=20 > +;* Input: Arg0 =3D Current event type: >=20 > +;* 1 =3D display switch >=20 > +;* 2 =3D lid >=20 > +;* 3 =3D dock >=20 > +;* Arg1 =3D Notification type: >=20 > +;* 0 =3D Re-enumeration >=20 > +;* 0x80 =3D Display switch >=20 > +;* >=20 > +;* Output: Returns 0 =3D success, 1 =3D failure >=20 > +;* >=20 > +;* References: PDRD and PSTS methods. OSYS (OS version) >=20 > +;* >=20 > +;********************************************************* > ***************/ >=20 > + >=20 > +Method(GNOT, 2) >=20 > +{ >=20 > + // >=20 > + // Check for 1. Driver loaded, 2. Driver ready. >=20 > + // If any of these cases is not met, skip this event and return failur= e. >=20 > + // >=20 > + If(PDRD()) >=20 > + { >=20 > + Return(0x1) // Return failure if driver not loaded. >=20 > + } >=20 > + >=20 > + Store(Arg0, CEVT) // Set up the current event value >=20 > + Store(3, CSTS) // CSTS=3DBIOS dispatched an event >=20 > + >=20 > + If(LAnd(LEqual(CHPD, 0), LEqual(Arg1, 0))) // Do not re-enum if driver > supports hotplug >=20 > + { >=20 > + // >=20 > + // Re-enumerate the Graphics Device for non-XP operating systems. >=20 > + // >=20 > + Notify(\_SB.PC00.GFX0, Arg1) >=20 > + } >=20 > + >=20 > + If(CondRefOf(HNOT)) >=20 > + { >=20 > + HNOT(Arg0) //Notification handler for Hybrid graphics >=20 > + } >=20 > + Else >=20 > + { >=20 > + Notify(\_SB.PC00.GFX0,0x80) >=20 > + } >=20 > + >=20 > + Return(0x0) // Return success >=20 > +} >=20 > + >=20 > +/********************************************************* > ***************; >=20 > +;* >=20 > +;* Name: GHDS >=20 > +;* >=20 > +;* Description: Handle a hotkey display switching event (performs a >=20 > +;* Notify(GFX0, 0). >=20 > +;* >=20 > +;* Usage: This method must be called when a hotkey event occurs an= d > the >=20 > +;* purpose of that hotkey is to do a display switch. >=20 > +;* >=20 > +;* Input: Arg0 =3D Toggle table number. >=20 > +;* >=20 > +;* Output: Returns 0 =3D success, 1 =3D failure. >=20 > +;* CEVT and TIDX are indirect outputs. >=20 > +;* >=20 > +;* References: TIDX, GNOT >=20 > +;* >=20 > +;********************************************************* > ***************/ >=20 > + >=20 > +Method(GHDS, 1) >=20 > +{ >=20 > + Store(Arg0, TIDX) // Store the table number >=20 > + // >=20 > + // Call GNOT for CEVT =3D 1 =3D hotkey, notify value =3D 0 >=20 > + // >=20 > + Return(GNOT(1, 0)) // Return stats from GNOT >=20 > +} >=20 > + >=20 > +/********************************************************* > ***************; >=20 > +;* >=20 > +;* Name: GLID >=20 > +;* >=20 > +;* Description: Handle a lid event (performs the Notify(GFX0, 0), but no= t the >=20 > +;* lid notify). >=20 > +;* >=20 > +;* Usage: This method must be called when a lid event occurs. A >=20 > +;* Notify(LID0, 0x80) must follow the call to this method. >=20 > +;* >=20 > +;* Input: Arg0 =3D Lid state: >=20 > +;* 0 =3D All closed >=20 > +;* 1 =3D internal LFP lid open >=20 > +;* 2 =3D external lid open >=20 > +;* 3 =3D both external and internal open >=20 > +;* >=20 > +;* Output: Returns 0=3Dsuccess, 1=3Dfailure. >=20 > +;* CLID and CEVT are indirect outputs. >=20 > +;* >=20 > +;* References: CLID, GNOT >=20 > +;* >=20 > +;********************************************************* > ***************/ >=20 > + >=20 > +Method(GLID, 1) >=20 > +{ >=20 > + >=20 > + If (LEqual(Arg0,1)) >=20 > + { >=20 > + Store(3,CLID) >=20 > + } >=20 > + Else >=20 > + { >=20 > + Store(Arg0, CLID) >=20 > + } >=20 > + // >=20 > + //Store(Arg0, CLID) // Store the current lid state >=20 > + // Call GNOT for CEVT=3D2=3DLid, notify value =3D 0 >=20 > + // >=20 > + if (GNOT(2, 0)) { >=20 > + Or (CLID, 0x80000000, CLID) >=20 > + Return (1) // Return Fail >=20 > + } >=20 > + >=20 > + Return (0) // Return Pass >=20 > +} >=20 > + >=20 > +/********************************************************* > ***************; >=20 > +;* >=20 > +;* Name: GDCK >=20 > +;* >=20 > +;* Description: Handle a docking event by updating the current docking > status >=20 > +;* and doing a notification. >=20 > +;* >=20 > +;* Usage: This method must be called when a docking event occurs. >=20 > +;* >=20 > +;* Input: Arg0 =3D Docking state: >=20 > +;* 0 =3D Undocked >=20 > +;* 1 =3D Docked >=20 > +;* >=20 > +;* Output: Returns 0=3Dsuccess, 1=3Dfailure. >=20 > +;* CDCK and CEVT are indirect outputs. >=20 > +;* >=20 > +;* References: CDCK, GNOT >=20 > +;* >=20 > +;********************************************************* > ***************/ >=20 > + >=20 > +Method(GDCK, 1) >=20 > +{ >=20 > + Store(Arg0, CDCK) // Store the current dock state >=20 > + // >=20 > + // Call GNOT for CEVT=3D4=3DDock, notify value =3D 0 >=20 > + // >=20 > + Return(GNOT(4, 0)) // Return stats from GNOT >=20 > +} >=20 > + >=20 > +/********************************************************* > ***************; >=20 > +;* ASLE Interrupt Methods >=20 > +;********************************************************* > ***************/ >=20 > + >=20 > +/********************************************************* > ***************; >=20 > +;* >=20 > +;* Name: PARD >=20 > +;* >=20 > +;* Description: Check if the driver is ready to handle ASLE interrupts >=20 > +;* generate by the system BIOS. >=20 > +;* >=20 > +;* Usage: This method must be called before generating each ASLE >=20 > +;* interrupt. >=20 > +;* >=20 > +;* Input: None >=20 > +;* >=20 > +;* Output: Returns 0 =3D success, 1 =3D failure. >=20 > +;* >=20 > +;* References: ARDY (Driver readiness), ASLP (Driver recommended sleep >=20 > +;* timeout value) >=20 > +;* >=20 > +;********************************************************* > ***************/ >=20 > + >=20 > +Method(PARD) >=20 > +{ >=20 > + If(LNot(ARDY)) >=20 > + { >=20 > + // >=20 > + // Sleep for ASLP milliseconds if the driver is not ready. >=20 > + // >=20 > + Sleep(ASLP) >=20 > + } >=20 > + // >=20 > + // If ARDY is clear, the driver is not ready. If the return value is >=20 > + // !=3D0, do not generate the ASLE interrupt. >=20 > + // >=20 > + Return(LNot(ARDY)) >=20 > +} >=20 > + >=20 > +// >=20 > +// Intel Ultrabook Event Handler. Arg0 represents the Ultrabook Event B= it # > to pass >=20 > +// to the Intel Graphics Driver. Note that this is a serialized method, > meaning >=20 > +// sumultaneous events are not allowed. >=20 > +// >=20 > +Method(IUEH,1,Serialized) >=20 > +{ >=20 > + And(IUER,0xC0,IUER) // Clear all button events on entry. >=20 > + XOr(IUER,Shiftleft(1,Arg0),IUER) // Toggle status. >=20 > + >=20 > + If(LLessEqual(Arg0,4)) // Button Event? >=20 > + { >=20 > + Return(AINT(5,0)) // Generate event and return status. >=20 > + >=20 > + } >=20 > + Else // Indicator Event. >=20 > + { >=20 > + Return(AINT(Arg0,0)) // Generate event and return status. >=20 > + } >=20 > +} >=20 > + >=20 > +/********************************************************* > ***************; >=20 > +;* >=20 > +;* Name: AINT >=20 > +;* >=20 > +;* Description: Call the appropriate methods to generate an ASLE interru= pt. >=20 > +;* This process includes ensuring the graphics driver is re= ady >=20 > +;* to process the interrupt, ensuring the driver supports t= he >=20 > +;* interrupt of interest, and passing information about the= event >=20 > +;* to the graphics driver. >=20 > +;* >=20 > +;* Usage: This method must called to generate an ASLE interrupt. >=20 > +;* >=20 > +;* Input: Arg0 =3D ASLE command function code: >=20 > +;* 0 =3D Set ALS illuminance >=20 > +;* 1 =3D Set backlight brightness >=20 > +;* 2 =3D Do Panel Fitting >=20 > +;* 4 =3D Reserved >=20 > +;* 5 =3D Button Indicator Event >=20 > +;* 6 =3D Convertible Indicator Event >=20 > +;* 7 =3D Docking Indicator Event >=20 > +;* Arg1 =3D If Arg0 =3D 0, current ALS reading: >=20 > +;* 0 =3D Reading below sensor range >=20 > +;* 1-0xFFFE =3D Current sensor reading >=20 > +;* 0xFFFF =3D Reading above sensor range >=20 > +;* Arg1 =3D If Arg0 =3D 1, requested backlight percentage >=20 > +;* >=20 > +;* Output: Returns 0 =3D success, 1 =3D failure >=20 > +;* >=20 > +;* References: PARD method. >=20 > +;* >=20 > +;********************************************************* > ***************/ >=20 > + >=20 > +Method(AINT, 2) >=20 > +{ >=20 > + // >=20 > + // Return failure if the requested feature is not supported by the >=20 > + // driver. >=20 > + // >=20 > + If(LNot(And(TCHE, ShiftLeft(1, Arg0)))) >=20 > + { >=20 > + Return(0x1) >=20 > + } >=20 > + // >=20 > + // Return failure if the driver is not ready to handle an ASLE >=20 > + // interrupt. >=20 > + // >=20 > + If(PARD()) >=20 > + { >=20 > + Return(0x1) >=20 > + } >=20 > + // >=20 > + // Handle Intel Ultrabook Events. >=20 > + // >=20 > + If(LAnd(LGreaterEqual(Arg0,5),LLessEqual(Arg0,7))) >=20 > + { >=20 > + Store(ShiftLeft(1,Arg0), ASLC) // Set Ultrbook Event [6:4]. >=20 > + Store(0x01, ASLE) // Generate ASLE interrupt >=20 > + >=20 > + Store(0,Local2) // Use Local2 as a timeout counter. Intialize to ze= ro. >=20 > + >=20 > + While(LAnd(LLess(Local2,250),LNotEqual(ASLC,0))) // Wait 1 second or > until Driver ACKs a success. >=20 > + { >=20 > + Sleep(4) // Delay 4 ms. >=20 > + Increment(Local2) // Increment Timeout. >=20 > + } >=20 > + >=20 > + Return(0) // Return success >=20 > + } >=20 > + // >=20 > + // Evaluate the first argument (Panel fitting, backlight brightness, o= r ALS). >=20 > + // >=20 > + If(LEqual(Arg0, 2)) // Arg0 =3D 2, so request a panel fitting = mode change. >=20 > + { >=20 > + If(CPFM) // If current mode field is non-zero use i= t. >=20 > + { >=20 > + And(CPFM, 0x0F, Local0) // Create variables without reserved >=20 > + And(EPFM, 0x0F, Local1) // or valid bits. >=20 > + >=20 > + If(LEqual(Local0, 1)) // If current mode is centered, >=20 > + { >=20 > + If(And(Local1, 6)) // and if stretched is enabled, >=20 > + { >=20 > + Store(6, PFIT) // request stretched. >=20 > + } >=20 > + Else // Otherwise, >=20 > + { >=20 > + If(And(Local1, 8)) // if aspect ratio is enabled, >=20 > + { >=20 > + Store(8, PFIT) // request aspect ratio. >=20 > + } >=20 > + Else // Only centered mode is enabled >=20 > + { >=20 > + Store(1, PFIT) // so request centered. (No change.) >=20 > + } >=20 > + } >=20 > + } >=20 > + If(LEqual(Local0, 6)) // If current mode is stretched, >=20 > + { >=20 > + If(And(Local1, 8)) // and if aspect ratio is enabled, >=20 > + { >=20 > + Store(8, PFIT) // request aspect ratio. >=20 > + } >=20 > + Else // Otherwise, >=20 > + { >=20 > + If(And(Local1, 1)) // if centered is enabled, >=20 > + { >=20 > + Store(1, PFIT) // request centered. >=20 > + } >=20 > + Else // Only stretched mode is enabled >=20 > + { >=20 > + Store(6, PFIT) // so request stretched. (No change.) >=20 > + } >=20 > + } >=20 > + } >=20 > + If(LEqual(Local0, 8)) // If current mode is aspect ratio, >=20 > + { >=20 > + If(And(Local1, 1)) // and if centered is enabled, >=20 > + { >=20 > + Store(1, PFIT) // request centered. >=20 > + } >=20 > + Else // Otherwise, >=20 > + { >=20 > + If(And(Local1, 6)) // if stretched is enabled, >=20 > + { >=20 > + Store(6, PFIT) // request stretched. >=20 > + } >=20 > + Else // Only aspect ratio mode is enabled >=20 > + { >=20 > + Store(8, PFIT) // so request aspect ratio. (No change.) >=20 > + } >=20 > + } >=20 > + } >=20 > + } >=20 > + // >=20 > + // The following code for panel fitting (within the Else condition) = is > retained for backward compatiblity. >=20 > + // >=20 > + Else // If CFPM field is zero use PFIT and togg= le the >=20 > + { >=20 > + Xor(PFIT,7,PFIT) // mode setting between stretched and cent= ered > only. >=20 > + } >=20 > + Or(PFIT,0x80000000,PFIT) // Set the valid bit for all cases. >=20 > + Store(4, ASLC) // Store "Panel fitting event" to ASLC[31:= 1] >=20 > + } >=20 > + Else >=20 > + { >=20 > + If(LEqual(Arg0, 1)) // Arg0=3D1, so set the backlight brightness. >=20 > + { >=20 > + Store(Divide(Multiply(Arg1, 255), 100), BCLP) // Convert from perc= ent to > 0-255. >=20 > + Or(BCLP, 0x80000000, BCLP) // Set the valid bit. >=20 > + Store(2, ASLC) // Store "Backlight control event" to ASLC[31:1] >=20 > + } >=20 > + Else >=20 > + { >=20 > + If(LEqual(Arg0, 0)) // Arg0=3D0, so set the ALS illuminace >=20 > + { >=20 > + Store(Arg1, ALSI) >=20 > + Store(1, ASLC) // Store "ALS event" to ASLC[31:1] >=20 > + } >=20 > + Else >=20 > + { >=20 > + Return(0x1) // Unsupported function >=20 > + } >=20 > + } >=20 > + } >=20 > + >=20 > + Store(0x01, ASLE) // Generate ASLE interrupt >=20 > + Return(0x0) // Return success >=20 > +} >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/AcpiTables/IgfxDsm.a= sl > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/AcpiTables/IgfxDsm.a= sl > new file mode 100644 > index 0000000000..ecd87e8c1f > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/AcpiTables/IgfxDsm.a= sl > @@ -0,0 +1,398 @@ > +/** @file >=20 > + IGD OpRegion/_DSM Reference Code. >=20 > + This file contains Get BIOS Data and Callback functions for >=20 > + the Integrated Graphics Device (IGD) OpRegion/DSM mechanism >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +External(\_SB.PC00.IMMC, MethodObj) >=20 > +External(\_SB.PC00.IMMD, MethodObj) >=20 > + >=20 > +// >=20 > +// _DSM Device Specific Method >=20 > +// >=20 > +// Arg0: UUID Unique function identifier >=20 > +// Arg1: Integer Revision Level >=20 > +// Arg2: Integer Function Index (1 =3D Return Supported Functions) >=20 > +// Arg3: Additional Inputs/Package Parameters Bits [31:0] input as {Byte= 0, > Byte1, Byte2, Byte3} to BIOS which is passed as 32 bit DWORD by Driver >=20 > +// >=20 > +Method (_DSM, 4, Serialized, 0, UnknownObj, {BuffObj, IntObj, IntObj, > PkgObj}) { >=20 > + >=20 > + If (LEqual(Arg0, ToUUID ("3E5B41C6-EB1D-4260-9D15-C71FBADAE414"))) { >=20 > + // >=20 > + // _DSM Definition for Igd functions >=20 > + // Arguments: >=20 > + // Arg0: UUID: 3E5B41C6-EB1D-4260-9D15-C71FBADAE414 >=20 > + // Arg1: Revision ID: 1 >=20 > + // Arg2: Function Index: 16 >=20 > + // Arg3: Additional Inputs Bits[31:0] Arg3 {Byte0, Byte1, Byte2, Byt= e3} >=20 > + // >=20 > + // Return: >=20 > + // Success for simple notification, Opregion update for some routine= s and > a Package for AKSV >=20 > + // >=20 > + If (Lor(LEqual(Arg2,18),LEqual(Arg2,19))) { >=20 > + CreateDwordField(Arg3, 0x0, DDIN) >=20 > + CreateDwordField(Arg3, 0x4, BUF1) >=20 > + // >=20 > + // OPTS is return buffer from IOM mailbox - >=20 > + // Byte[0] is Status field. >=20 > + // BYTE[1] is HDP Count. >=20 > + // >=20 > + Name(OPTS, Buffer(4){0,0,0,0}) >=20 > + CreateByteField(OPTS, 0x00, CMST) // Command Status field >=20 > + // Success - 0 >=20 > + // Fail - 1 >=20 > + CreateByteField(OPTS, 0x01, RTB1) // Return Buffer 1 >=20 > + >=20 > + // >=20 > + // Gfx Empty Dongle Buffer is data for return DSM fun# >=20 > + // with below buffer format >=20 > + // Byte[0-3] is Data field. >=20 > + // Byte[4] is Status field. >=20 > + // >=20 > + Name(GEDB, Buffer(5){0,0,0,0,0}) >=20 > + CreateDwordField(GEDB, 0x00, GEDF) // Gfx Empty Dongle Data Field >=20 > + CreateByteField(GEDB, 0x04, GESF) // Gfx Empty Dongle Status Fiel= d >=20 > + // Success - 0 >=20 > + // Fail - None 0 >=20 > + } >=20 > + >=20 > + // >=20 > + // Switch by function index >=20 > + // >=20 > + Switch(ToInteger(Arg2)) { >=20 > + // >=20 > + // Function Index: 0 >=20 > + // Standard query - A bitmask of functions supported >=20 > + // >=20 > + // Return: A bitmask of functions supported >=20 > + // >=20 > + Case (0) >=20 > + { >=20 > + If (LEqual(Arg1, 1)) { // test Arg1 for Revision ID: 1 >=20 > + Store("iGfx Supported Functions Bitmap ", Debug) >=20 > + >=20 > + Return(0xDE7FF) >=20 > + } >=20 > + } >=20 > + >=20 > + // >=20 > + // Function Index: 1 >=20 > + // Adapter Power State Notification >=20 > + // Arg3 Bits [7:0]: Adapter Power State bits [7:0] from Driver 00h= =3D D0; > 01h =3D D1; 02h =3D D2; 04h =3D D3 (Cold/Hot); 08h =3D D4 (Hibernate Noti= fication) >=20 > + // Return: Success >=20 > + // >=20 > + Case(1) { >=20 > + If (LEqual(Arg1, 1)) { // test Arg1 for Revision ID: 1 >=20 > + Store(" Adapter Power State Notification ", Debug) >=20 > + >=20 > + // >=20 > + // Handle Low Power S0 Idle Capability if enabled >=20 > + // >=20 > + If(LAnd(LEqual(S0ID, 1),LLess(OSYS, 2015))) { >=20 > + // >=20 > + // Call GUAM to trigger CS Entry >=20 > + // If Adapter Power State Notification =3D D1 (Arg3[0]=3D0= x01) >=20 > + // >=20 > + If (LEqual (And(DerefOf (Index (Arg3,0)), 0xFF), 0x01)) { >=20 > + // GUAM - Global User Absent Mode Notification Method >=20 > + \GUAM(One) // 0x01 - Power State Standby (CS Entry) >=20 > + } >=20 > + Store(And(DerefOf (Index (Arg3,1)), 0xFF), Local0) >=20 > + // >=20 > + // Call GUAM >=20 > + // If Display Turn ON Notification (Arg3 [1] =3D=3D 0) for C= S Exit >=20 > + // >=20 > + If (LEqual (Local0, 0)) { >=20 > + // GUAM - Global User Absent Mode Notification Method >=20 > + \GUAM(0) >=20 > + } >=20 > + } >=20 > + >=20 > + // Upon notification from driver that the Adapter Power State = =3D D0, >=20 > + // check if previous lid event failed. If it did, retry the l= id >=20 > + // event here. >=20 > + If(LEqual(DerefOf (Index (Arg3,0)), 0)) { >=20 > + Store(CLID, Local0) >=20 > + If(And(0x80000000,Local0)) { >=20 > + And(CLID, 0x0000000F, CLID) >=20 > + GLID(CLID) >=20 > + } >=20 > + } >=20 > + Return(0x01) >=20 > + } >=20 > + } >=20 > + // >=20 > + // Function Index: 2 >=20 > + // Display Power State Notification >=20 > + // Arg3: Display Power State Bits [15:8] >=20 > + // 00h =3D On >=20 > + // 01h =3D Standby >=20 > + // 02h =3D Suspend >=20 > + // 04h =3D Off >=20 > + // 08h =3D Reduced On >=20 > + // Return: Success >=20 > + // >=20 > + Case(2) { >=20 > + if (LEqual(Arg1, 1)) { // test Arg1 for Revision ID: 1 >=20 > + >=20 > + Store("Display Power State Notification ", Debug) >=20 > + Return(0x01) >=20 > + } >=20 > + } >=20 > + >=20 > + // >=20 > + // Function Index: 3 >=20 > + // BIOS POST Completion Notification >=20 > + // Return: Success >=20 > + // >=20 > + Case(3) { >=20 > + if (LEqual(Arg1, 1)) { // test Arg1 for Revision ID: 1 >=20 > + Store("BIOS POST Completion Notification ", Debug) >=20 > + Return(0x01) // Not supported, but no failure >=20 > + } >=20 > + } >=20 > + >=20 > + // >=20 > + // Function Index: 4 >=20 > + // Pre-Hires Set Mode >=20 > + // Return: Success >=20 > + // >=20 > + Case(4) { >=20 > + if (LEqual(Arg1, 1)){ // test Arg1 for Revision ID: 1 >=20 > + Store("Pre-Hires Set Mode ", Debug) >=20 > + Return(0x01) // Not supported, but no failure >=20 > + } >=20 > + } >=20 > + >=20 > + // >=20 > + // Function Index: 5 >=20 > + // Post-Hires Set Mode >=20 > + // Return: Success >=20 > + // >=20 > + Case(5) { >=20 > + if (LEqual(Arg1, 1)){ // test Arg1 for Revision ID: 1 >=20 > + Store("Post-Hires Set Mode ", Debug) >=20 > + Return(0x01) // Not supported, but no failure >=20 > + } >=20 > + } >=20 > + >=20 > + // >=20 > + // Function Index: 6 >=20 > + // SetDisplayDeviceNotification (Display Switch) >=20 > + // Return: Success >=20 > + // >=20 > + Case(6) { >=20 > + if (LEqual(Arg1, 1)){ // test Arg1 for Revision ID: 1 >=20 > + Store("SetDisplayDeviceNotification", Debug) >=20 > + Return(0x01) // Not supported, but no failure >=20 > + } >=20 > + } >=20 > + >=20 > + // >=20 > + // Function Index: 7 >=20 > + // SetBootDevicePreference >=20 > + // Return: Success >=20 > + // >=20 > + Case(7) { >=20 > + if (LEqual(Arg1, 1)){ // test Arg1 for Revision ID: 1 >=20 > + // An OEM may elect to implement this method. In that c= ase, >=20 > + // the input values must be saved into non-volatile storage fo= r >=20 > + // parsing during the next boot. The following Sample code is= Intel >=20 > + // validated implementation. >=20 > + >=20 > + Store("SetBootDevicePreference ", Debug) >=20 > + And(DerefOf (Index (Arg3,0)), 0xFF, IBTT) // Save the boot dis= play to > NVS >=20 > + Return(0x01) >=20 > + } >=20 > + } >=20 > + >=20 > + // >=20 > + // Function Index: 8 >=20 > + // SetPanelPreference >=20 > + // Return: Success >=20 > + // >=20 > + Case(8) { >=20 > + if (LEqual(Arg1, 1)){ // test Arg1 for Revision ID: 1 >=20 > + // An OEM may elect to implement this method. In that case, >=20 > + // the input values must be saved into non-volatile storage fo= r >=20 > + // parsing during the next boot. The following Sample code is= Intel >=20 > + // validated implementation. >=20 > + >=20 > + Store("SetPanelPreference ", Debug) >=20 > + >=20 > + // Set the panel-related NVRAM variables based the input from = the > driver. >=20 > + And(DerefOf (Index (Arg3,0)), 0xFF, IPSC) >=20 > + >=20 > + // Change panel type if a change is requested by the driver (C= hange if >=20 > + // panel type input is non-zero). Zero=3DNo change requested. >=20 > + If(And(DerefOf (Index (Arg3,1)), 0xFF)) { >=20 > + And(DerefOf (Index (Arg3,1)), 0xFF, IPAT) >=20 > + Decrement(IPAT) // 0 =3D no change, so fit to CMOS map >=20 > + } >=20 > + And(ShiftRight(DerefOf (Index (Arg3,2)), 4), 0x7, IBIA) >=20 > + Return(0x01) // Success >=20 > + } >=20 > + } >=20 > + >=20 > + // >=20 > + // Function Index: 9 >=20 > + // FullScreenDOS >=20 > + // Return: Success >=20 > + // >=20 > + Case(9) { >=20 > + if (LEqual(Arg1, 1)){ // test Arg1 for Revision ID: 1 >=20 > + Store("FullScreenDOS ", Debug) >=20 > + Return(0x01) // Not supported, but no failure >=20 > + } >=20 > + } >=20 > + >=20 > + // >=20 > + // Function Index: 10 >=20 > + // APM Complete >=20 > + // Return: Adjusted Lid State >=20 > + // >=20 > + Case(10) { >=20 > + if (LEqual(Arg1, 1)) { // test Arg1 for Revision ID: 1 >=20 > + >=20 > + Store("APM Complete ", Debug) >=20 > + Store(ShiftLeft(LIDS, 8), Local0) // Report the lid state >=20 > + Add(Local0, 0x100, Local0) // Adjust the lid state, 0 = =3D Unknown >=20 > + Return(Local0) >=20 > + } >=20 > + } >=20 > + >=20 > + // >=20 > + // >=20 > + // Function Index: 13 >=20 > + // GetBootDisplayPreference >=20 > + // Arg3 Bits [30:16] : Boot Device Ports >=20 > + // Arg3 Bits [7:0] : Boot Device Type >=20 > + // Return: Boot device port and Boot device type from saved > configuration >=20 > + // >=20 > + Case(13) { >=20 > + if (LEqual(Arg1, 1)){ // test Arg1 for Revision ID: 1 >=20 > + >=20 > + Store("GetBootDisplayPreference ", Debug) >=20 > + Or(ShiftLeft(DerefOf (Index (Arg3,3)), 24), ShiftLeft(DerefOf = (Index > (Arg3,2)), 16), Local0) // Combine Arg3 Bits [31:16] >=20 > + And(Local0, 0xEFFF0000, Local0) >=20 > + And(Local0, ShiftLeft(DeRefOf(Index(DBTB, IBTT)), 16), Local0) >=20 > + Or(IBTT, Local0, Local0) // Arg3 Bits [7:0] =3D Boot device ty= pe >=20 > + Return(Local0) >=20 > + } >=20 > + } >=20 > + >=20 > + // >=20 > + // Function Index: 14 >=20 > + // GetPanelDetails >=20 > + // Return: Different Panel Settings >=20 > + // >=20 > + Case(14) { >=20 > + if (LEqual(Arg1, 1)){ // test Arg1 for Revision ID: 1 >=20 > + Store("GetPanelDetails ", Debug) >=20 > + >=20 > + // Report the scaling setting >=20 > + // Bits [7:0] - Panel Scaling >=20 > + // Bits contain the panel scaling user setting from CMOS >=20 > + // 00h =3D On: Auto >=20 > + // 01h =3D On: Force Scaling >=20 > + // 02h =3D Off >=20 > + // 03h =3D Maintain Aspect Ratio >=20 > + >=20 > + Store(IPSC, Local0) >=20 > + Or(Local0, ShiftLeft(IPAT, 8), Local0) >=20 > + >=20 > + // Adjust panel type, 0 =3D VBT default >=20 > + // Bits [15:8] - Panel Type >=20 > + // Bits contain the panel type user setting from CMOS >=20 > + // 00h =3D Not Valid, use default Panel Type & Timings from VB= T >=20 > + // 01h - 0Fh =3D Panel Number >=20 > + >=20 > + Add(Local0, 0x100, Local0) >=20 > + >=20 > + // Report the lid state and Adjust it >=20 > + // Bits [16] - Lid State >=20 > + // Bits contain the current panel lid state >=20 > + // 0 =3D Lid Open >=20 > + // 1 =3D Lid Closed >=20 > + >=20 > + Or(Local0, ShiftLeft(LIDS, 16), Local0) >=20 > + Add(Local0, 0x10000, Local0) >=20 > + >=20 > + // Report the BIA setting >=20 > + // Bits [22:20] - Backlight Image Adaptation (BIA) Control >=20 > + // Bits contain the backlight image adaptation control user set= ting from > CMOS >=20 > + // 000 =3D VBT Default >=20 > + // 001 =3D BIA Disabled (BLC may still be enabled) >=20 > + // 010 - 110 =3D BIA Enabled at Aggressiveness Level [1 - 5] >=20 > + >=20 > + Or(Local0, ShiftLeft(IBIA, 20), Local0) >=20 > + Return(Local0) >=20 > + } >=20 > + } >=20 > + >=20 > + // >=20 > + // Function Index: 15 >=20 > + // GetInternalGraphics >=20 > + // Return: Different Internal Grahics Settings >=20 > + // >=20 > + >=20 > + Case(15) { >=20 > + if (LEqual(Arg1, 1)){ // test Arg1 for Revision ID: 1 >=20 > + Store("GetInternalGraphics ", Debug) >=20 > + >=20 > + Store(GIVD, Local0) // Local0[0] - VGA= mode(1=3DVGA) >=20 > + Xor(Local0, 1, Local0) // Invert the VGA mode = polarity >=20 > + >=20 > + Or(Local0, ShiftLeft(GMFN, 1), Local0) // Local0[1] - # I= GD PCI > functions-1 >=20 > + // Local0[3:2] - Res= erved >=20 > + // Local0[4] - IGD= D3 support(0=3Dcold) >=20 > + // Local0[10:5] - Res= erved >=20 > + Or(Local0, ShiftLeft(3, 11), Local0) // Local0[12:11] - DVM= T version > (11b =3D 5.0) >=20 > + >=20 > + // >=20 > + // Report DVMT 5.0 Total Graphics memory size. >=20 > + // >=20 > + Or(Local0, ShiftLeft(IDMS, 17), Local0) // Bits 20:17 are for = Gfx total > memory size >=20 > + >=20 > + // If the "Set Internal Graphics" call is supported, the modif= ied >=20 > + // settings flag must be programmed per the specification. Th= is means >=20 > + // that the flag must be set to indicate that system BIOS requ= ests >=20 > + // these settings. Once "Set Internal Graphics" is called, th= e >=20 > + // modified settings flag must be cleared on all subsequent c= alls to >=20 > + // this function. >=20 > + >=20 > + // Report the graphics frequency based on B0:D2:F0:RF0h[12]. = Must >=20 > + // take into account the current VCO. >=20 > + >=20 > + Or(ShiftLeft(DeRefOf(Index(DeRefOf(Index(CDCT, HVCO)), CDVL)), > 21),Local0, Local0) >=20 > + Return(Local0) >=20 > + } >=20 > + } >=20 > + >=20 > + // >=20 > + // Function Index: 16 >=20 > + // GetAKSV >=20 > + // Retrun: 5 bytes of AKSV >=20 > + // >=20 > + Case(16) { >=20 > + if (LEqual(Arg1, 1)) { // test Arg1 for Revision ID: 1 >=20 > + >=20 > + Store("GetAKSV ", Debug) >=20 > + Name (KSVP, Package() >=20 > + { >=20 > + 0x80000000, >=20 > + 0x8000 >=20 > + }) >=20 > + Store(KSV0, Index(KSVP,0)) // First four bytes of AKSV >=20 > + Store(KSV1, Index(KSVP,1)) // Fifth byte of AKSV >=20 > + Return(KSVP) // Success >=20 > + } >=20 > + } >=20 > + } // End of switch(Arg2) >=20 > + } // End of if (ToUUID("3E5B41C6-EB1D-4260-9D15-C71FBADAE414D")) >=20 > + >=20 > + Return (Buffer () {0x00}) >=20 > +} // End of _DSM >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/AcpiTables/IgfxOpGbd= a. > asl > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/AcpiTables/IgfxOpGbd= a > .asl > new file mode 100644 > index 0000000000..2b5f2393b0 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/AcpiTables/IgfxOpGbd= a > .asl > @@ -0,0 +1,127 @@ > +/** @file >=20 > + IGD OpRegion/Software SCI Reference Code. >=20 > + This file contains Get BIOS Data Area funciton support for >=20 > + the Integrated Graphics Device (IGD) OpRegion/Software SCI mechanism >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +Method (GBDA, 0, Serialized) >=20 > +{ >=20 > + // >=20 > + // Supported calls: Sub-function 0 >=20 > + // >=20 > + If (LEqual(GESF, 0)) >=20 > + { >=20 > + // >=20 > + // Reference code is set to Intel's validated implementation. >=20 > + // >=20 > + Store(0x0000659, PARM) >=20 > + Store(Zero, GESF) // Clear the exit parameter >=20 > + Return(SUCC) // Success >=20 > + } >=20 > + // >=20 > + // Requested callbacks: Sub-function 1 >=20 > + // >=20 > + If (LEqual(GESF, 1)) >=20 > + { >=20 > + // >=20 > + // Call back functions are where the driver calls the >=20 > + // system BIOS at function indicated event. >=20 > + // >=20 > + Store(0x300482, PARM) >=20 > + If(LEqual(S0ID, One)){ >=20 > + Or(PARM, 0x100, PARM) //Request Fn 8 callback in CS systems >=20 > + } >=20 > + Store(Zero, GESF) // Clear the exit parameter >=20 > + Return(SUCC) // Success >=20 > + } >=20 > + // >=20 > + // Get Boot display Preferences: Sub-function 4 >=20 > + // >=20 > + If (LEqual(GESF, 4)) >=20 > + { >=20 > + // >=20 > + // Get Boot Display Preferences function. >=20 > + // >=20 > + And(PARM, 0xEFFF0000, PARM) // PARM[30:16] =3D Boot device ports >=20 > + And(PARM, ShiftLeft(DeRefOf(Index(DBTB, IBTT)), 16), PARM) >=20 > + Or(IBTT, PARM, PARM) // PARM[7:0] =3D Boot device type >=20 > + Store(Zero, GESF) // Clear the exit parameter >=20 > + Return(SUCC) // Success >=20 > + } >=20 > + // >=20 > + // Panel details: Sub-function 5 >=20 > + // >=20 > + If (LEqual(GESF, 5)) >=20 > + { >=20 > + // >=20 > + // Get Panel Details function. >=20 > + // >=20 > + Store(IPSC, PARM) // Report the scaling setting >=20 > + Or(PARM, ShiftLeft(IPAT, 8), PARM) >=20 > + Add(PARM, 0x100, PARM) // Adjust panel type, 0 =3D VBT default >=20 > + Or(PARM, ShiftLeft(LIDS, 16), PARM) // Report the lid state >=20 > + Add(PARM, 0x10000, PARM) // Adjust the lid state, 0 =3D Unknown >=20 > + Or(PARM, ShiftLeft(IBIA, 20), PARM) // Report the BIA setting >=20 > + Store(Zero, GESF) >=20 > + Return(SUCC) >=20 > + } >=20 > + // >=20 > + // Internal graphics: Sub-function 7 >=20 > + // >=20 > + If (LEqual(GESF, 7)) >=20 > + { >=20 > + Store(GIVD, PARM) // PARM[0] - VGA mode(1=3DVGA) >=20 > + Xor(PARM, 1, PARM) // Invert the VGA mode polarity >=20 > + Or(PARM, ShiftLeft(GMFN, 1), PARM) // PARM[1] - # IGD PCI function= s-1 >=20 > + // PARM[3:2] - Reserved >=20 > + // PARM[4] - IGD D3 support(= 0=3Dcold) >=20 > + // PARM[10:5] - Reserved >=20 > + Or(PARM, ShiftLeft(3, 11), PARM) // PARM[12:11] - DVMT mode(11b =3D > 5.0) >=20 > + >=20 > + // >=20 > + // Report DVMT 5.0 Total Graphics memory size. >=20 > + // >=20 > + Or(PARM, ShiftLeft(IDMS, 17), PARM) // Bits 20:17 are for Gfx total > memory size >=20 > + // >=20 > + // If the "Set Internal Graphics" call is supported, the modified >=20 > + // settings flag must be programmed per the specification. This mea= ns >=20 > + // that the flag must be set to indicate that system BIOS requests >=20 > + // these settings. Once "Set Internal Graphics" is called, the >=20 > + // modified settings flag must be cleared on all subsequent calls t= o >=20 > + // this function. >=20 > + // Report the graphics frequency based on B0:D2:F0:RF0h[12]. Must >=20 > + // take into account the current VCO. >=20 > + // >=20 > + Or(ShiftLeft(Derefof(Index(Derefof(Index(CDCT, HVCO)), CDVL)), > 21),PARM, PARM) >=20 > + Store(1, GESF) // Set the modified settings flag >=20 > + Return(SUCC) >=20 > + } >=20 > + // >=20 > + // Spread spectrum clocks: Sub-function 10 >=20 > + // >=20 > + If (LEqual(GESF, 10)) >=20 > + { >=20 > + Store(0, PARM) // Assume SSC is disabled >=20 > + If(ISSC) >=20 > + { >=20 > + Or(PARM, 3, PARM) // If SSC enabled, return SSC1+Enabled >=20 > + } >=20 > + Store(0, GESF) // Set the modified settings flag >=20 > + Return(SUCC) // Success >=20 > + } >=20 > + >=20 > + If (LEqual(GESF, 11)) >=20 > + { >=20 > + Store(KSV0, PARM) // First four bytes of AKSV >=20 > + Store(KSV1, GESF) // Fifth byte of AKSV >=20 > + >=20 > + Return(SUCC) // Success >=20 > + } >=20 > + // >=20 > + // A call to a reserved "Get BIOS data" function was received. >=20 > + // >=20 > + Store(Zero, GESF) // Clear the exit parameter >=20 > + Return(CRIT) // Reserved, "Critical failure" >=20 > +} >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/AcpiTables/IgfxOpRn.= asl > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/AcpiTables/IgfxOpRn.= asl > new file mode 100644 > index 0000000000..410524b324 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/AcpiTables/IgfxOpRn.= asl > @@ -0,0 +1,314 @@ > +/** @file >=20 > + IGD OpRegion/Software SCI Reference Code. >=20 > + This file contains the interrupt handler code for the Integrated >=20 > + Graphics Device (IGD) OpRegion/Software SCI mechanism. >=20 > + It defines OperationRegions to cover the IGD PCI configuration space >=20 > + as described in the IGD OpRegion specification. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +// >=20 > +//NOTES: >=20 > +// >=20 > +// (1) The code contained in this file inherits the scope in which it >=20 > +// was included. So BIOS developers must be sure to include this >=20 > +// file in the scope associated with the graphics device >=20 > +// (ex. \_SB.PC00.GFX0). >=20 > +// (2) Create a _L06 method under the GPE scope to handle the event >=20 > +// generated by the graphics driver. The _L06 method must call >=20 > +// the GSCI method in this file. >=20 > +// (3) The MCHP operation region assumes that _ADR and _BBN names >=20 > +// corresponding to bus 0, device0, function 0 have been declared >=20 > +// under the PC00 scope. >=20 > +// (4) Before the first execution of the GSCI method, the base address >=20 > +// of the GMCH SCI OpRegion must be programmed where the driver can >=20 > +// access it. A 32bit scratch register at 0xFC in the IGD PCI >=20 > +// configuration space (B0/D2/F0/R0FCh) is used for this purpose. >=20 > + >=20 > +// Define an OperationRegion to cover the GMCH PCI configuration space > as >=20 > +// described in the IGD OpRegion specificiation. >=20 > +// >=20 > +Scope(\_SB.PC00) >=20 > +{ >=20 > + OperationRegion(MCHP, PCI_Config, 0x40, 0xC0) >=20 > + Field(MCHP, AnyAcc, NoLock, Preserve) >=20 > + { >=20 > + Offset(0x14), >=20 > + AUDE, 8, >=20 > + >=20 > + Offset(0x60), // Top of Memory register >=20 > + TASM, 10, // Total system memory (64MB gran) >=20 > + , 6, >=20 > + } >=20 > +} >=20 > + >=20 > +// >=20 > +// Define an OperationRegion to cover the IGD PCI configuration space a= s >=20 > +// described in the IGD OpRegion specificiation. >=20 > +// >=20 > +OperationRegion(IGDP, PCI_Config, 0x40, 0xC0) >=20 > +Field(IGDP, AnyAcc, NoLock, Preserve) >=20 > +{ >=20 > + Offset(0x10), // Mirror of gfx control reg >=20 > + , 1, >=20 > + GIVD, 1, // IGD VGA disable bit >=20 > + , 2, >=20 > + GUMA, 3, // Stolen memory size >=20 > + , 9, >=20 > + Offset(0x14), >=20 > + , 4, >=20 > + GMFN, 1, // Gfx function 1 enable >=20 > + , 27, >=20 > + Offset(0xA4), >=20 > + ASLE, 8, // Reg 0xE4, ASLE interrupt register >=20 > + , 24, // Only use first byte of ASLE reg >=20 > + Offset(0xA8), // Reg 0xE8, SWSCI control register >=20 > + GSSE, 1, // Graphics SCI event (1=3Devent pending) >=20 > + GSSB, 14, // Graphics SCI scratchpad bits >=20 > + GSES, 1, // Graphics event select (1=3DSCI) >=20 > + Offset(0xB0), // Gfx Clk Frequency and Gating Control >=20 > + , 12, >=20 > + CDVL, 1, // Core display clock value >=20 > + , 3, // Graphics Core Display Clock Select >=20 > + Offset(0xB5), >=20 > + LBPC, 8, // Legacy brightness control >=20 > + Offset(0xBC), >=20 > + ASLS, 32, // Reg 0xFC, Address of the IGD OpRegion >=20 > +} >=20 > + >=20 > +// >=20 > +// Define an OperationRegion to cover the IGD OpRegion layout. >=20 > +// >=20 > +OperationRegion(IGDM, SystemMemory, ASLB, 0x2000) >=20 > +Field(IGDM, AnyAcc, NoLock, Preserve) >=20 > +{ >=20 > + // >=20 > + // OpRegion Header >=20 > + // >=20 > + SIGN, 128, // Signature-"IntelGraphicsMem" >=20 > + SIZE, 32, // OpRegion Size >=20 > + OVER, 32, // OpRegion Version >=20 > + SVER, 256, // System BIOS Version >=20 > + VVER, 128, // VBIOS Version >=20 > + GVER, 128, // Driver version >=20 > + MBOX, 32, // Mailboxes supported >=20 > + DMOD, 32, // Driver Model >=20 > + PCON, 32, // Platform Configuration >=20 > + DVER, 64, // GOP Version >=20 > + // >=20 > + // OpRegion Mailbox 1 (Public ACPI Methods) >=20 > + // Note: Mailbox 1 is normally reserved for desktop platforms. >=20 > + // >=20 > + Offset(0x100), >=20 > + DRDY, 32, // Driver readiness (ACPI notification) >=20 > + CSTS, 32, // Notification status >=20 > + CEVT, 32, // Current event >=20 > + Offset(0x120), >=20 > + DIDL, 32, // Supported display device ID list >=20 > + DDL2, 32, // Allows for 8 devices >=20 > + DDL3, 32, >=20 > + DDL4, 32, >=20 > + DDL5, 32, >=20 > + DDL6, 32, >=20 > + DDL7, 32, >=20 > + DDL8, 32, >=20 > + CPDL, 32, // Currently present display list >=20 > + CPL2, 32, // Allows for 8 devices >=20 > + CPL3, 32, >=20 > + CPL4, 32, >=20 > + CPL5, 32, >=20 > + CPL6, 32, >=20 > + CPL7, 32, >=20 > + CPL8, 32, >=20 > + CADL, 32, // Currently active display list >=20 > + CAL2, 32, // Allows for 8 devices >=20 > + CAL3, 32, >=20 > + CAL4, 32, >=20 > + CAL5, 32, >=20 > + CAL6, 32, >=20 > + CAL7, 32, >=20 > + CAL8, 32, >=20 > + NADL, 32, // Next active display list >=20 > + NDL2, 32, // Allows for 8 devices >=20 > + NDL3, 32, >=20 > + NDL4, 32, >=20 > + NDL5, 32, >=20 > + NDL6, 32, >=20 > + NDL7, 32, >=20 > + NDL8, 32, >=20 > + ASLP, 32, // ASL sleep timeout >=20 > + TIDX, 32, // Toggle table index >=20 > + CHPD, 32, // Current hot plug enable indicator >=20 > + CLID, 32, // Current lid state indicator >=20 > + CDCK, 32, // Current docking state indicator >=20 > + SXSW, 32, // Display switch notify on resume >=20 > + EVTS, 32, // Events supported by ASL (diag only) >=20 > + CNOT, 32, // Current OS notifications (diag only) >=20 > + NRDY, 32, >=20 > + // >=20 > + //Extended DIDL list >=20 > + // >=20 > + DDL9, 32, >=20 > + DD10, 32, >=20 > + DD11, 32, >=20 > + DD12, 32, >=20 > + DD13, 32, >=20 > + DD14, 32, >=20 > + DD15, 32, >=20 > + // >=20 > + //Extended Currently attached Display Device List CPD2 >=20 > + // >=20 > + CPL9, 32, >=20 > + CP10, 32, >=20 > + CP11, 32, >=20 > + CP12, 32, >=20 > + CP13, 32, >=20 > + CP14, 32, >=20 > + CP15, 32, >=20 > + // >=20 > + // OpRegion Mailbox 2 (Software SCI Interface) >=20 > + // >=20 > + Offset(0x200), // SCIC >=20 > + SCIE, 1, // SCI entry bit (1=3Dcall unserviced) >=20 > + GEFC, 4, // Entry function code >=20 > + GXFC, 3, // Exit result >=20 > + GESF, 8, // Entry/exit sub-function/parameter >=20 > + , 16, // SCIC[31:16] reserved >=20 > + Offset(0x204), // PARM >=20 > + PARM, 32, // PARM register (extra parameters) >=20 > + DSLP, 32, // Driver sleep time out >=20 > + // >=20 > + // OpRegion Mailbox 3 (BIOS to Driver Notification) >=20 > + // Note: Mailbox 3 is normally reserved for desktop platforms. >=20 > + // >=20 > + Offset(0x300), >=20 > + ARDY, 32, // Driver readiness (power conservation) >=20 > + ASLC, 32, // ASLE interrupt command/status >=20 > + TCHE, 32, // Technology enabled indicator >=20 > + ALSI, 32, // Current ALS illuminance reading >=20 > + BCLP, 32, // Backlight brightness >=20 > + PFIT, 32, // Panel fitting state or request >=20 > + CBLV, 32, // Current brightness level >=20 > + BCLM, 320, // Backlight brightness level duty cycle mapping table >=20 > + CPFM, 32, // Current panel fitting mode >=20 > + EPFM, 32, // Enabled panel fitting modes >=20 > + PLUT, 592, // Optional. 74-byte Panel LUT Table >=20 > + PFMB, 32, // Optional. PWM Frequency and Minimum Brightness >=20 > + CCDV, 32, // Optional. Gamma, Brightness, Contrast values. >=20 > + PCFT, 32, // Optional. Power Conservation Features >=20 > + SROT, 32, // Supported rotation angle. >=20 > + IUER, 32, // Optional. Intel Ultrabook Event Register. >=20 > + FDSS, 64, // Optional. FFS Display Physical address >=20 > + FDSP, 32, // Optional. FFS Display Size >=20 > + STAT, 32, // State Indicator >=20 > + RVDA, 64, // Physical address of Raw VBT data >=20 > + RVDS, 32, // Size of Raw VBT data >=20 > + // >=20 > + // OpRegion Mailbox 4 (VBT) >=20 > + // >=20 > + Offset(0x400), >=20 > + RVBT, 0xC000, // 6K bytes maximum VBT image >=20 > + // >=20 > + // OpRegion Mailbox 5 (BIOS to Driver Notification Extension) >=20 > + // >=20 > + Offset(0x1C00), >=20 > + PHED, 32, // Panel Header >=20 > + BDDC, 2048, // Panel EDID (Max 256 bytes) >=20 > + >=20 > +} >=20 > + >=20 > +// >=20 > +// Convert boot display type into a port mask. >=20 > +// >=20 > +Name (DBTB, Package() >=20 > +{ >=20 > + 0x0000, // Automatic >=20 > + 0x0007, // Port-0 : Integrated CRT >=20 > + 0x0038, // Port-1 : DVO-A, or Integrated LVDS >=20 > + 0x01C0, // Port-2 : SDVO-B, or SDVO-B/C >=20 > + 0x0E00, // Port-3 : SDVO-C >=20 > + 0x003F, // [CRT + DVO-A / Integrated LVDS] >=20 > + 0x01C7, // [CRT + SDVO-B] or [CRT + SDVO-B/C] >=20 > + 0x0E07, // [CRT + SDVO-C] >=20 > + 0x01F8, // [DVO-A / Integrated LVDS + SDVO-B] >=20 > + 0x0E38, // [DVO-A / Integrated LVDS + SDVO-C] >=20 > + 0x0FC0, // [SDVO-B + SDVO-C] >=20 > + 0x0000, // Reserved >=20 > + 0x0000, // Reserved >=20 > + 0x0000, // Reserved >=20 > + 0x0000, // Reserved >=20 > + 0x0000, // Reserved >=20 > + 0x7000, // Port-4: Integrated TV >=20 > + 0x7007, // [Integrated TV + CRT] >=20 > + 0x7038, // [Integrated TV + LVDS] >=20 > + 0x71C0, // [Integrated TV + DVOB] >=20 > + 0x7E00 // [Integrated TV + DVOC] >=20 > +}) >=20 > + >=20 > +// >=20 > +// Core display clock value table. >=20 > +// >=20 > +Name (CDCT, Package() >=20 > +{ >=20 > + Package() {228, 320}, >=20 > + Package() {222, 333}, >=20 > + Package() {222, 333}, >=20 > + Package() { 0, 0}, >=20 > + Package() {222, 333}, >=20 > +}) >=20 > + >=20 > +// >=20 > +// Defined exit result values: >=20 > +// >=20 > +Name (SUCC, 1) // Exit result: Success >=20 > +Name (NVLD, 2) // Exit result: Invalid parameter >=20 > +Name (CRIT, 4) // Exit result: Critical failure >=20 > +Name (NCRT, 6) // Exit result: Non-critical failure >=20 > + >=20 > +/********************************************************* > ***************; >=20 > +;* >=20 > +;* Name: GSCI >=20 > +;* >=20 > +;* Description: Handles an SCI generated by the graphics driver. The >=20 > +;* PARM and SCIC input fields are parsed to determine the >=20 > +;* functionality requested by the driver. GBDA or SBCB >=20 > +;* is called based on the input data in SCIC. >=20 > +;* >=20 > +;* Usage: The method must be called in response to a GPE 06 event >=20 > +;* which will be generated by the graphics driver. >=20 > +;* Ex: Method(\_GPE._L06) {Return(\_SB.PC00.GFX0.GSCI())} >=20 > +;* >=20 > +;* Input: PARM and SCIC are indirect inputs >=20 > +;* >=20 > +;* Output: PARM and SIC are indirect outputs >=20 > +;* >=20 > +;* References: GBDA (Get BIOS Data method), SBCB (System BIOS Callback >=20 > +;* method) >=20 > +;* >=20 > +;********************************************************* > ***************/ >=20 > + >=20 > +Method (GSCI, 0, Serialized) >=20 > +{ >=20 > + Include("IgfxOpGbda.asl") // "Get BIOS Data" Functions >=20 > + Include("IgfxOpSbcb.asl") // "System BIOS CallBacks" >=20 > + >=20 > + If (LEqual(GEFC, 4)) >=20 > + { >=20 > + Store(GBDA(), GXFC) // Process Get BIOS Data functions >=20 > + } >=20 > + >=20 > + If (LEqual(GEFC, 6)) >=20 > + { >=20 > + Store(SBCB(), GXFC) // Process BIOS Callback functions >=20 > + } >=20 > + >=20 > + Store(0, GEFC) // Wipe out the entry function code >=20 > + Store(1, CPSC) // Clear CPUSCI_STS to clear the PCH TCO SCI = status >=20 > + Store(0, GSSE) // Clear the SCI generation bit in PCI space. >=20 > + Store(0, SCIE) // Clr SCI serviced bit to signal completion >=20 > + >=20 > + Return(Zero) >=20 > +} >=20 > + >=20 > +Include("IgfxCommon.asl") // IGD SCI mobile features >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/AcpiTables/IgfxOpSbc= b. > asl > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/AcpiTables/IgfxOpSbc= b. > asl > new file mode 100644 > index 0000000000..3c5d4d9862 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/AcpiTables/IgfxOpSbc= b. > asl > @@ -0,0 +1,261 @@ > +/** @file >=20 > + This file contains the system BIOS call back functionality for the >=20 > + OpRegion/Software SCI mechanism. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +Method (SBCB, 0, Serialized) >=20 > +{ >=20 > + // >=20 > + // Supported Callbacks: Sub-function 0 >=20 > + // >=20 > + If (LEqual(GESF, 0x0)) >=20 > + { >=20 > + // >=20 > + // An OEM may support the driver->SBIOS status callbacks, but >=20 > + // the supported callbacks value must be modified. The code that is >=20 > + // executed upon reception of the callbacks must be also be updated >=20 > + // to perform the desired functionality. >=20 > + // >=20 > + Store(0x00000000, PARM) // No callbacks supported >=20 > + //Store(0x000787FD, PARM) // Used for Intel test implementaion >=20 > + Store(0x000F87DD, PARM) >=20 > + Store(Zero, GESF) // Clear the exit parameter >=20 > + Return(SUCC) // "Success" >=20 > + } >=20 > + // >=20 > + // BIOS POST Completion: Sub-function 1 >=20 > + // >=20 > + If (LEqual(GESF, 1)) >=20 > + { >=20 > + Store(Zero, GESF) // Clear the exit parameter >=20 > + Store(Zero, PARM) >=20 > + Return(SUCC) // Not supported, but no failure >=20 > + } >=20 > + // >=20 > + // Pre-Hires Set Mode: Sub-function 3 >=20 > + // >=20 > + If (LEqual(GESF, 3)) >=20 > + { >=20 > + Store(Zero, GESF) // Clear the exit parameter >=20 > + Store(Zero, PARM) >=20 > + Return(SUCC) // Not supported, but no failure >=20 > + } >=20 > + // >=20 > + // Post-Hires Set Mode: Sub-function 4 >=20 > + // >=20 > + If (LEqual(GESF, 4)) >=20 > + { >=20 > + Store(Zero, GESF) // Clear the exit parameter >=20 > + Store(Zero, PARM) >=20 > + Return(SUCC) // Not supported, but no failure >=20 > + } >=20 > + // >=20 > + // Display Switch: Sub-function 5 >=20 > + // >=20 > + If (LEqual(GESF, 5)) >=20 > + { >=20 > + Store(Zero, GESF) // Clear the exit parameter >=20 > + Store(Zero, PARM) >=20 > + Return(SUCC) // Not supported, but no failure >=20 > + } >=20 > + // >=20 > + // Adapter Power State: Sub-function 7 >=20 > + // >=20 > + If (LEqual(GESF, 7)) >=20 > + { >=20 > + // >=20 > + // Handle Low Power S0 Idle Capability if enabled >=20 > + // >=20 > + If(LAnd(LEqual(S0ID, 1),LLess(OSYS, 2015))) { >=20 > + // >=20 > + // Call GUAM to trigger CS Entry >=20 > + // If Adapter Power State Notification =3D D1 (PARM[7:0]=3D0x01) >=20 > + // >=20 > + If (LEqual (And(PARM,0xFF), 0x01)) { >=20 > + // GUAM - Global User Absent Mode Notification Method >=20 > + \GUAM(One) // 0x01 - Power State Standby (CS Entry) >=20 > + } >=20 > + If (LEqual (And(PARM,0xFF), 0x00)) { >=20 > + // GUAM - Global User Absent Mode Notification Method >=20 > + \GUAM(0) >=20 > + } >=20 > + } >=20 > + // >=20 > + // Upon notification from driver that the Adapter Power State =3D D0= , >=20 > + // check if previous lid event failed. If it did, retry the lid >=20 > + // event here. >=20 > + // >=20 > + If(LEqual(PARM, 0)) >=20 > + { >=20 > + Store(CLID, Local0) >=20 > + If(And(0x80000000,Local0)) >=20 > + { >=20 > + And(CLID, 0x0000000F, CLID) >=20 > + GLID(CLID) >=20 > + } >=20 > + } >=20 > + Store(Zero, GESF) // Clear the exit parameter >=20 > + Store(Zero, PARM) >=20 > + Return(SUCC) // Not supported, but no failure >=20 > + } >=20 > + // >=20 > + // Display Power State: Sub-function 8 >=20 > + // >=20 > + If (LEqual(GESF, 8)) >=20 > + { >=20 > + Store(Zero, GESF) // Clear the exit parameter >=20 > + Store(Zero, PARM) >=20 > + Return(SUCC) // Not supported, but no failure >=20 > + } >=20 > + // >=20 > + // Set Boot Display: Sub-function 9 >=20 > + // >=20 > + If (LEqual(GESF, 9)) >=20 > + { >=20 > + // >=20 > + // An OEM may elect to implement this method. In that case, >=20 > + // the input values must be saved into non-volatile storage for >=20 > + // parsing during the next boot. The following Sample code is Intel >=20 > + // validated implementation. >=20 > + // >=20 > + And(PARM, 0xFF, IBTT) // Save the boot display to NVS >=20 > + Store(Zero, GESF) // Clear the exit parameter >=20 > + Store(Zero, PARM) >=20 > + Return(SUCC) // Reserved, "Critical failure" >=20 > + } >=20 > + // >=20 > + // Set Panel Details: Sub-function 10 (0Ah) >=20 > + // >=20 > + If (LEqual(GESF, 10)) >=20 > + { >=20 > + // >=20 > + // An OEM may elect to implement this method. In that case, >=20 > + // the input values must be saved into non-volatile storage for >=20 > + // parsing during the next boot. The following Sample code is Intel >=20 > + // validated implementation. >=20 > + // Set the panel-related NVRAM variables based the input from the > driver. >=20 > + // >=20 > + And(PARM, 0xFF, IPSC) >=20 > + // >=20 > + // Change panel type if a change is requested by the driver (Change = if >=20 > + // panel type input is non-zero). Zero=3DNo change requested. >=20 > + // >=20 > + If(And(ShiftRight(PARM, 8), 0xFF)) >=20 > + { >=20 > + And(ShiftRight(PARM, 8), 0xFF, IPAT) >=20 > + Decrement(IPAT) // 0 =3D no change, so fit to CMOS map >=20 > + } >=20 > + And(ShiftRight(PARM, 20), 0x7, IBIA) >=20 > + Store(Zero, GESF) // Clear the exit parameter >=20 > + Store(Zero, PARM) >=20 > + Return(SUCC) // Success >=20 > + } >=20 > + // >=20 > + // Set Internal Graphics: Sub-function 11 (0Bh) >=20 > + // >=20 > + If (LEqual(GESF, 11)) >=20 > + { >=20 > + // >=20 > + // An OEM may elect to implement this method. In that case, >=20 > + // the input values must be saved into non-volatile storage for >=20 > + // parsing during the next boot. The following Sample code is Intel >=20 > + // validated implementation. >=20 > + // >=20 > + And(ShiftRight(PARM, 1), 1, IF1E) // Program the function 1 opt= ion >=20 > + If(And(PARM, ShiftLeft(0xF, 13))) // Use fixed memory if fixed = size !=3D 0 >=20 > + { >=20 > + // >=20 > + // Fixed memory >=20 > + // >=20 > + And(ShiftRight(PARM, 13), 0xF, IDMS) // Program fixed memory size >=20 > + } >=20 > + Else >=20 > + { >=20 > + // >=20 > + // DVMT memory >=20 > + // >=20 > + And(ShiftRight(PARM, 17), 0xF, IDMS) // Program fixed memory size >=20 > + } >=20 > + Store(Zero, GESF) // Clear the exit parameter >=20 > + Store(Zero, PARM) >=20 > + Return(SUCC) // Success >=20 > + } >=20 > + // >=20 > + // Post-Hires to DOS FS: Sub-function 16 (10h) >=20 > + // >=20 > + If (LEqual(GESF, 16)) >=20 > + { >=20 > + Store(Zero, GESF) // Clear the exit parameter >=20 > + Store(Zero, PARM) >=20 > + Return(SUCC) // Not supported, but no failure >=20 > + } >=20 > + // >=20 > + // APM Complete: Sub-function 17 (11h) >=20 > + // >=20 > + If (LEqual(GESF, 17)) >=20 > + { >=20 > + Store(ShiftLeft(LIDS, 8), PARM) // Report the lid state >=20 > + Add(PARM, 0x100, PARM) // Adjust the lid state, 0 =3D Unkno= wn >=20 > + Store(Zero, GESF) // Clear the exit parameter >=20 > + Return(SUCC) // Not supported, but no failure >=20 > + } >=20 > + // >=20 > + // Set Spread Spectrum Clocks: Sub-function 18 (12h) >=20 > + // >=20 > + If (LEqual(GESF, 18)) >=20 > + { >=20 > + // >=20 > + // An OEM may elect to implement this method. In that case, >=20 > + // the input values must be saved into non-volatile storage for >=20 > + // parsing during the next boot. The following Sample code is Intel >=20 > + // validated implementation. >=20 > + // >=20 > + If(And(PARM, 1)) >=20 > + { >=20 > + If(LEqual(ShiftRight(PARM, 1), 1)) >=20 > + { >=20 > + Store(1, ISSC) // Enable HW SSC, only for clock 1 >=20 > + } >=20 > + Else >=20 > + { >=20 > + Store(Zero, GESF) >=20 > + Return(CRIT) // Failure, as the SSC clock must be 1 >=20 > + } >=20 > + } >=20 > + Else >=20 > + { >=20 > + Store(0, ISSC) // Disable SSC >=20 > + } >=20 > + Store(Zero, GESF) // Clear the exit parameter >=20 > + Store(Zero, PARM) >=20 > + Return(SUCC) // Success >=20 > + } >=20 > + // >=20 > + // Post VBE/PM Callback: Sub-function 19 (13h) >=20 > + // >=20 > + If (LEqual(GESF, 19)) >=20 > + { >=20 > + Store(Zero, GESF) // Clear the exit parameter >=20 > + Store(Zero, PARM) >=20 > + Return(SUCC) // Not supported, but no failure >=20 > + } >=20 > + // >=20 > + // Set PAVP Data: Sub-function 20 (14h) >=20 > + // >=20 > + If (LEqual(GESF, 20)) >=20 > + { >=20 > + And(PARM, 0xF, PAVP) // Store PAVP info >=20 > + Store(Zero, GESF) // Clear the exit parameter >=20 > + Store(Zero, PARM) >=20 > + Return(SUCC) // Success >=20 > + } >=20 > + >=20 > + // >=20 > + // A call to a reserved "System BIOS callbacks" function was received >=20 > + // >=20 > + Store(Zero, GESF) // Clear the exit parameter >=20 > + Return(SUCC) // Reserved, "Critical failure" >=20 > +} >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/AcpiTables/IgfxSsdt.= asl > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/AcpiTables/IgfxSsdt.= asl > new file mode 100644 > index 0000000000..99130a853d > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/AcpiTables/IgfxSsdt.= asl > @@ -0,0 +1,73 @@ > +/** @file >=20 > + This file contains the Intel Graphics SSDT Table ASL code. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +DefinitionBlock ( >=20 > + "IgfxSsdt.aml", >=20 > + "SSDT", >=20 > + 2, >=20 > + "INTEL ", >=20 > + "IgfxSsdt", >=20 > + 0x3000 >=20 > + ) >=20 > +{ >=20 > + External(\_SB.PC00, DeviceObj) >=20 > + External(\_SB.PC00.GFX0, DeviceObj) >=20 > + External(\NDID) >=20 > + External(\DID1) >=20 > + External(\DID2) >=20 > + External(\DID3) >=20 > + External(\DID4) >=20 > + External(\DID5) >=20 > + External(\DID6) >=20 > + External(\DID7) >=20 > + External(\DID8) >=20 > + External(\DID9) >=20 > + External(\DIDA) >=20 > + External(\DIDB) >=20 > + External(\DIDC) >=20 > + External(\DIDD) >=20 > + External(\DIDE) >=20 > + External(\DIDF) >=20 > + External(\DIDX) >=20 > + External(\DIDY) >=20 > + >=20 > + External(\NXD1) >=20 > + External(\NXD2) >=20 > + External(\NXD3) >=20 > + External(\NXD4) >=20 > + External(\NXD5) >=20 > + External(\NXD6) >=20 > + External(\NXD7) >=20 > + External(\NXD8) >=20 > + External(\NXDY) >=20 > + >=20 > + External(\IPTP) >=20 > + External(\EDPV) >=20 > + External(\NXDX) >=20 > + External(\HGMD) >=20 > + External(\LIDS) >=20 > + External(\BRTL) >=20 > + External(\NSTE) >=20 > + External(\CSTE) >=20 > + External(\ASLB) >=20 > + External(\IBTT) >=20 > + External(\IPSC) >=20 > + External(\IPAT) >=20 > + External(\IBIA) >=20 > + External(\IDMS) >=20 > + External(\HVCO) >=20 > + External(\ISSC) >=20 > + External(\KSV0) >=20 > + External(\KSV1) >=20 > + External(\IF1E) >=20 > + External(\PAVP) >=20 > + >=20 > + Scope (\_SB.PC00.GFX0) >=20 > + { >=20 > + include("Igfx.asl") >=20 > + } >=20 > +} >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/AcpiTables/IgfxSsdt.= inf > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/AcpiTables/IgfxSsdt.= inf > new file mode 100644 > index 0000000000..be28157cef > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/AcpiTables/IgfxSsdt.= inf > @@ -0,0 +1,23 @@ > +## @file >=20 > +# Component description file for the Igfx ACPI tables >=20 > +# >=20 > +# Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > +# SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +# >=20 > +## >=20 > + >=20 > +[Defines] >=20 > +INF_VERSION =3D 0x00010005 >=20 > +BASE_NAME =3D IgfxSsdt >=20 > +FILE_GUID =3D CE9CAA0E-8248-442C-9E57-50F212E2BAED >=20 > +MODULE_TYPE =3D USER_DEFINED >=20 > +VERSION_STRING =3D 1.0 >=20 > + >=20 > +[Sources] >=20 > + IgfxSsdt.asl >=20 > + >=20 > +[Packages] >=20 > + MdePkg/MdePkg.dec >=20 > + TigerlakeSiliconPkg/SiPkg.dec >=20 > + >=20 > +[FixedPcd] >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/IncludePrivate/Libra= ry/ > DxeGraphicsInitLib.h > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/IncludePrivate/Libra= ry/ > DxeGraphicsInitLib.h > new file mode 100644 > index 0000000000..0e9f119763 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/IncludePrivate/Libra= ry/ > DxeGraphicsInitLib.h > @@ -0,0 +1,53 @@ > +/** @file >=20 > + Header file for DXE Graphics Init Lib. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _DXE_GRAPHICS_INIT_LIB_H_ >=20 > +#define _DXE_GRAPHICS_INIT_LIB_H_ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +/** >=20 > + Initialize GT ACPI tables >=20 > + >=20 > + @param[in] ImageHandle - Handle for the image of this driver >=20 > + @param[in] SaPolicy - SA DXE Policy protocol >=20 > + >=20 > + @retval EFI_SUCCESS - GT ACPI initialization complete >=20 > + @retval EFI_NOT_FOUND - Dxe System Table not found. >=20 > + @retval EFI_OUT_OF_RESOURCES - Mmio not allocated successfully. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +GraphicsInit ( >=20 > + IN EFI_HANDLE ImageHandle, >=20 > + IN SA_POLICY_PROTOCOL *SaPolicy >=20 > + ); >=20 > + >=20 > +/** >=20 > + Do Post GT PM Init Steps after VBIOS Initialization. >=20 > + >=20 > + @retval EFI_SUCCESS Succeed. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +PostPmInitEndOfDxe ( >=20 > + VOID >=20 > + ); >=20 > +#endif >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/IncludePrivate/Libra= ry/ > DxeGraphicsPolicyLib.h > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/IncludePrivate/Libra= ry/ > DxeGraphicsPolicyLib.h > new file mode 100644 > index 0000000000..abb5dffc45 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/IncludePrivate/Libra= ry/ > DxeGraphicsPolicyLib.h > @@ -0,0 +1,71 @@ > +/** @file >=20 > + Header file for the DXE Graphics Policy Init library. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _DXE_GRAPHICS_POLICY_LIB_H_ >=20 > +#define _DXE_GRAPHICS_POLICY_LIB_H_ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +#define WORD_FIELD_VALID_BIT BIT15 >=20 > + >=20 > +extern EFI_GUID gGraphicsDxeConfigGuid; >=20 > + >=20 > +/** >=20 > + This function prints the Graphics DXE phase policy. >=20 > + >=20 > + @param[in] SaPolicy - SA DXE Policy protocol >=20 > +**/ >=20 > +VOID >=20 > +GraphicsDxePolicyPrint ( >=20 > + IN SA_POLICY_PROTOCOL *SaPolicy >=20 > + ); >=20 > + >=20 > +/** >=20 > + This function Load default Graphics DXE policy. >=20 > + >=20 > + @param[in] ConfigBlockPointer The pointer to add Graphics config bl= ock >=20 > +**/ >=20 > +VOID >=20 > +LoadIgdDxeDefault ( >=20 > + IN VOID *ConfigBlockPointer >=20 > + ); >=20 > + >=20 > + >=20 > +/** >=20 > + Get DXE Graphics config block table total size. >=20 > + >=20 > + @retval Size of DXE Graphics config block table >=20 > +**/ >=20 > +UINT16 >=20 > +EFIAPI >=20 > +GraphicsGetConfigBlockTotalSizeDxe ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + GraphicsAddConfigBlocksDxe add all DXE Graphics config block. >=20 > + >=20 > + @param[in] ConfigBlockTableAddress The pointer to add SA config blo= cks >=20 > + >=20 > + @retval EFI_SUCCESS The policy default is initialize= d. >=20 > + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create > buffer >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +GraphicsAddConfigBlocksDxe ( >=20 > + IN VOID *ConfigBlockTableAddress >=20 > + ); >=20 > + >=20 > +#endif // _DXE_GRAPHICs_POLICY_LIBRARY_H_ >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/IncludePrivate/Libra= ry/ > DxeIgdOpRegionInitLib.h > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/IncludePrivate/Libra= ry/ > DxeIgdOpRegionInitLib.h > new file mode 100644 > index 0000000000..683893f940 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/IncludePrivate/Libra= ry/ > DxeIgdOpRegionInitLib.h > @@ -0,0 +1,177 @@ > +/** @file >=20 > + This is part of the implementation of an Intel Graphics drivers OpRegi= on / >=20 > + Software SCI interface between system BIOS, ASL code, and Graphics > drivers. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _DXE_IGD_OPREGION_INIT_LIB_H_ >=20 > +#define _DXE_IGD_OPREGION_INIT_LIB_H_ >=20 > + >=20 > +/// >=20 > +/// Statements that include other header files. >=20 > +/// >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +/// >=20 > +/// Driver Consumed Protocol Prototypes >=20 > +/// >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +/// >=20 > +/// Driver Produced Protocol Prototypes >=20 > +/// >=20 > +#include >=20 > + >=20 > +#pragma pack(push, 1) >=20 > +/// >=20 > +/// >=20 > +/// OpRegion (Miscellaneous) defines. >=20 > +/// >=20 > +/// OpRegion Header defines. >=20 > +/// >=20 > +typedef UINT16 STRING_REF; >=20 > +#define HEADER_SIGNATURE "IntelGraphicsMem" >=20 > +#define HEADER_SIZE 0x2000 >=20 > +#define HEADER_OPREGION_REV 0x00 >=20 > +#define HEADER_MBOX_SUPPORT (HD_MBOX5 + HD_MBOX4 + > HD_MBOX3 + HD_MBOX2 + HD_MBOX1) >=20 > +#define HD_MBOX1 BIT0 >=20 > +#define HD_MBOX2 BIT1 >=20 > +#define HD_MBOX3 BIT2 >=20 > +#define HD_MBOX4 BIT3 >=20 > +#define HD_MBOX5 BIT4 >=20 > +#define SVER_SIZE 32 >=20 > + >=20 > +/// >=20 > +/// OpRegion Mailbox 1 EQUates. >=20 > +/// >=20 > +/// OpRegion Mailbox 3 EQUates. >=20 > +/// >=20 > +#define ALS_ENABLE BIT0 >=20 > +#define BACKLIGHT_BRIGHTNESS 0xFF >=20 > +#define FIELD_VALID_BIT BIT31 >=20 > +#define PFIT_ENABLE BIT2 >=20 > +#define PFIT_OPRN_AUTO 0x00000000 >=20 > +#define PFIT_OPRN_SCALING 0x00000007 >=20 > +#define PFIT_OPRN_OFF 0x00000000 >=20 > +#define PFIT_SETUP_AUTO 0 >=20 > +#define PFIT_SETUP_SCALING 1 >=20 > +#define PFIT_SETUP_OFF 2 >=20 > +#define INIT_BRIGHT_LEVEL 0x64 >=20 > +#define PFIT_STRETCH 6 >=20 > + >=20 > +/// >=20 > +/// Video BIOS / VBT defines >=20 > +/// >=20 > +#define OPTION_ROM_SIGNATURE 0xAA55 >=20 > +#define VBIOS_LOCATION_PRIMARY 0xC0000 >=20 > + >=20 > +#define VBT_SIGNATURE SIGNATURE_32 ('$', 'V', 'B', 'T') >=20 > +/// >=20 > +/// Typedef stuctures >=20 > +/// >=20 > +typedef struct { >=20 > + UINT16 Signature; /// 0xAA55 >=20 > + UINT8 Size512; >=20 > + UINT8 Reserved[21]; >=20 > + UINT16 PcirOffset; >=20 > + UINT16 VbtOffset; >=20 > +} INTEL_VBIOS_OPTION_ROM_HEADER; >=20 > + >=20 > +typedef struct { >=20 > + UINT32 Signature; /// "PCIR" >=20 > + UINT16 VendorId; /// 0x8086 >=20 > + UINT16 DeviceId; >=20 > + UINT16 Reserved0; >=20 > + UINT16 Length; >=20 > + UINT8 Revision; >=20 > + UINT8 ClassCode[3]; >=20 > + UINT16 ImageLength; >=20 > + UINT16 CodeRevision; >=20 > + UINT8 CodeType; >=20 > + UINT8 Indicator; >=20 > + UINT16 Reserved1; >=20 > +} INTEL_VBIOS_PCIR_STRUCTURE; >=20 > + >=20 > +typedef struct { >=20 > + UINT8 HeaderSignature[20]; >=20 > + UINT16 HeaderVersion; >=20 > + UINT16 HeaderSize; >=20 > + UINT16 HeaderVbtSize; >=20 > + UINT8 HeaderVbtCheckSum; >=20 > + UINT8 HeaderReserved; >=20 > + UINT32 HeaderOffsetVbtDataBlock; >=20 > + UINT32 HeaderOffsetAim1; >=20 > + UINT32 HeaderOffsetAim2; >=20 > + UINT32 HeaderOffsetAim3; >=20 > + UINT32 HeaderOffsetAim4; >=20 > + UINT8 DataHeaderSignature[16]; >=20 > + UINT16 DataHeaderVersion; >=20 > + UINT16 DataHeaderSize; >=20 > + UINT16 DataHeaderDataBlockSize; >=20 > + UINT8 CoreBlockId; >=20 > + UINT16 CoreBlockSize; >=20 > + UINT16 CoreBlockBiosSize; >=20 > + UINT8 CoreBlockBiosType; >=20 > + UINT8 CoreBlockReleaseStatus; >=20 > + UINT8 CoreBlockHWSupported; >=20 > + UINT8 CoreBlockIntegratedHW; >=20 > + UINT8 CoreBlockBiosBuild[4]; >=20 > + UINT8 CoreBlockBiosSignOn[155]; >=20 > +} VBIOS_VBT_STRUCTURE; >=20 > +#pragma pack(pop) >=20 > +/// >=20 > +/// Driver Private Function definitions >=20 > +/// >=20 > + >=20 > +/** >=20 > + Graphics OpRegion / Software SCI driver installation function. >=20 > + >=20 > + @retval EFI_SUCCESS - The driver installed without error. >=20 > + @retval EFI_ABORTED - The driver encountered an error and could no= t > complete >=20 > + installation of the ACPI tables. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +IgdOpRegionInit ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Get Intel video BIOS VBT information (i.e. Pointer to VBT and VBT size= ). >=20 > + The VBT (Video BIOS Table) is a block of customizable data that is bui= lt >=20 > + within the video BIOS and edited by customers. >=20 > + >=20 > + @retval EFI_SUCCESS - Video BIOS VBT information returned. >=20 > + @exception EFI_UNSUPPORTED - Could not find VBT information > (*VBiosVbtPtr =3D NULL). >=20 > +**/ >=20 > +EFI_STATUS >=20 > +GetVBiosVbtEndOfDxe ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Update Graphics OpRegion after PCI enumeration. >=20 > + >=20 > + @retval EFI_SUCCESS - The function completed successfully. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +UpdateIgdOpRegionEndOfDxe ( >=20 > + VOID >=20 > + ); >=20 > +#endif >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeGr= ap > hicsInitLib/DxeGraphicsInitLib.c > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeGr= ap > hicsInitLib/DxeGraphicsInitLib.c > new file mode 100644 > index 0000000000..8769f34021 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeGr= ap > hicsInitLib/DxeGraphicsInitLib.c > @@ -0,0 +1,135 @@ > +/** @file >=20 > + DXE Library for Initializing SystemAgent Graphics ACPI table initializ= ation. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#include >=20 > + >=20 > + >=20 > +typedef union { >=20 > + struct { >=20 > + UINT32 Low; >=20 > + UINT32 High; >=20 > + } Data32; >=20 > + UINT64 Data; >=20 > +} UINT64_STRUCT; >=20 > + >=20 > +GLOBAL_REMOVE_IF_UNREFERENCED UINT64_STRUCT > mMchBarBase; >=20 > +GLOBAL_REMOVE_IF_UNREFERENCED > GOP_COMPONENT_NAME2_PROTOCOL *GopComponentName2Protocol =3D > NULL; >=20 > + >=20 > +/** >=20 > + Do Post GT PM Init Steps after VBIOS Initialization. >=20 > + >=20 > + @retval EFI_SUCCESS Succeed. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +PostPmInitEndOfDxe ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + CHAR16 *DriverVersion; >=20 > + UINTN Index; >=20 > + EFI_STATUS Status; >=20 > + GRAPHICS_DXE_CONFIG *GraphicsDxeConfig; >=20 > + SA_POLICY_PROTOCOL *SaPolicy; >=20 > + >=20 > + /// >=20 > + /// Get the platform setup policy. >=20 > + /// >=20 > + DriverVersion =3D NULL; >=20 > + Status =3D gBS->LocateProtocol (&gSaPolicyProtocolGuid, NULL, (VOID **= ) > &SaPolicy); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + >=20 > + Status =3D GetConfigBlock ((VOID *) SaPolicy, &gGraphicsDxeConfigGuid, > (VOID *)&GraphicsDxeConfig); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + >=20 > + >=20 > + Status =3D gBS->LocateProtocol (&gGopComponentName2ProtocolGuid, > NULL, (VOID **)&GopComponentName2Protocol); >=20 > + if (!EFI_ERROR (Status)) { >=20 > + Status =3D GopComponentName2Protocol->GetDriverVersion ( >=20 > + GopComponentName2Protocol, >=20 > + "en-US", >=20 > + &DriverVersion >=20 > + ); >=20 > + if (!EFI_ERROR (Status)) { >=20 > + for (Index =3D 0; (DriverVersion[Index] !=3D '\0'); Index++) { >=20 > + } >=20 > + Index =3D (Index+1)*2; >=20 > + CopyMem (GraphicsDxeConfig->GopVersion, DriverVersion, Index); >=20 > + } >=20 > + } >=20 > + >=20 > + /// >=20 > + /// Return final status >=20 > + /// >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > + >=20 > +/** >=20 > +Initialize GT ACPI tables >=20 > + >=20 > + @param[in] ImageHandle - Handle for the image of this driver >=20 > + @param[in] SaPolicy - SA DXE Policy protocol >=20 > + >=20 > + @retval EFI_SUCCESS - GT ACPI initialization complete >=20 > + @retval EFI_NOT_FOUND - Dxe System Table not found. >=20 > + @retval EFI_OUT_OF_RESOURCES - Mmio not allocated successfully. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +GraphicsInit ( >=20 > + IN EFI_HANDLE ImageHandle, >=20 > + IN SA_POLICY_PROTOCOL *SaPolicy >=20 > + ) >=20 > +{ >=20 > + EFI_STATUS Status; >=20 > + GRAPHICS_DXE_CONFIG *GraphicsDxeConfig; >=20 > + SYSTEM_AGENT_NVS_AREA_PROTOCOL *SaNvsAreaProtocol; >=20 > + >=20 > + Status =3D EFI_SUCCESS; >=20 > + mMchBarBase.Data32.High =3D PciSegmentRead32 > (PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, SA_MC_BUS, 0, 0, > R_SA_MCHBAR + 4)); >=20 > + mMchBarBase.Data32.Low =3D PciSegmentRead32 > (PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, SA_MC_BUS, 0, 0, > R_SA_MCHBAR)); >=20 > + mMchBarBase.Data &=3D (UINT64) ~BIT0; >=20 > + >=20 > + Status =3D GetConfigBlock ((VOID *) SaPolicy, &gGraphicsDxeConfigGuid, > (VOID *)&GraphicsDxeConfig); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + >=20 > + /// >=20 > + /// Locate the SA Global NVS Protocol. >=20 > + /// >=20 > + Status =3D gBS->LocateProtocol (&gSaNvsAreaProtocolGuid, NULL, (VOID *= *) > &SaNvsAreaProtocol); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + >=20 > + /// >=20 > + /// Update IGD SA Global NVS >=20 > + /// >=20 > + DEBUG ((DEBUG_INFO, " Update Igd SA Global NVS Area.\n")); >=20 > + >=20 > + SaNvsAreaProtocol->Area->AlsEnable =3D GraphicsDxeC= onfig- > >AlsEnable; >=20 > + /// >=20 > + /// Initialize IGD state by checking if IGD Device 2 Function 0 is ena= bled in > the chipset >=20 > + /// >=20 > + if (PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, > SA_MC_BUS, 0, 0, R_SA_DEVEN)) & B_SA_DEVEN_D2EN_MASK) { >=20 > + SaNvsAreaProtocol->Area->IgdState =3D 1; >=20 > + } else { >=20 > + SaNvsAreaProtocol->Area->IgdState =3D 0; >=20 > + } >=20 > + >=20 > + SaNvsAreaProtocol->Area->BrightnessPercentage =3D 100; >=20 > + SaNvsAreaProtocol->Area->IgdBootType =3D GraphicsDxeC= onfig- > >IgdBootType; >=20 > + SaNvsAreaProtocol->Area->IgdPanelType =3D GraphicsDxeC= onfig- > >IgdPanelType; >=20 > + SaNvsAreaProtocol->Area->IgdPanelScaling =3D GraphicsDxeC= onfig- > >IgdPanelScaling; >=20 > + /// >=20 > + /// Get SFF power mode platform data for the IGD driver. Flip the bit > (bitwise xor) >=20 > + /// since Setup value is opposite of NVS and IGD OpRegion value. >=20 > + /// >=20 > + SaNvsAreaProtocol->Area->IgdDvmtMemSize =3D > GraphicsDxeConfig->IgdDvmtMemSize; >=20 > + SaNvsAreaProtocol->Area->IgdFunc1Enable =3D 0; >=20 > + SaNvsAreaProtocol->Area->IgdHpllVco =3D MmioRead8 > (mMchBarBase.Data + 0xC0F) & 0x07; >=20 > + SaNvsAreaProtocol->Area->IgdSciSmiMode =3D 0; >=20 > + SaNvsAreaProtocol->Area->GfxTurboIMON =3D GraphicsDxeC= onfig- > >GfxTurboIMON; >=20 > + SaNvsAreaProtocol->Area->EdpValid =3D 0; >=20 > + >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeGr= ap > hicsInitLib/DxeGraphicsInitLib.inf > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeGr= ap > hicsInitLib/DxeGraphicsInitLib.inf > new file mode 100644 > index 0000000000..78c115eb3c > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeGr= ap > hicsInitLib/DxeGraphicsInitLib.inf > @@ -0,0 +1,45 @@ > +## @file >=20 > +# Component description file for the Dxe Graphics Init library. >=20 > +# >=20 > +# Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > +# SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +# >=20 > +## >=20 > + >=20 > +[Defines] >=20 > +INF_VERSION =3D 0x00010017 >=20 > +BASE_NAME =3D DxeGraphicsInitLib >=20 > +FILE_GUID =3D 2E889319-7361-4F6C-B181-EBD7AEF1DE6A >=20 > +VERSION_STRING =3D 1.0 >=20 > +MODULE_TYPE =3D DXE_DRIVER >=20 > +LIBRARY_CLASS =3D DxeGraphicsInitLib >=20 > + >=20 > +[LibraryClasses] >=20 > +UefiLib >=20 > +UefiRuntimeServicesTableLib >=20 > +UefiBootServicesTableLib >=20 > +DebugLib >=20 > +PostCodeLib >=20 > +ConfigBlockLib >=20 > +IoLib >=20 > +PciSegmentLib >=20 > +BaseMemoryLib >=20 > +MemoryAllocationLib >=20 > +MmPciLib >=20 > + >=20 > +[Packages] >=20 > +MdePkg/MdePkg.dec >=20 > +TigerlakeSiliconPkg/SiPkg.dec >=20 > + >=20 > +[Sources] >=20 > +DxeGraphicsInitLib.c >=20 > + >=20 > +[Guids] >=20 > +gGraphicsDxeConfigGuid ## CONSUMES >=20 > + >=20 > +[Pcd] >=20 > + >=20 > +[Protocols] >=20 > +gSaPolicyProtocolGuid ## CONSUMES >=20 > +gSaNvsAreaProtocolGuid ## CONSUMES >=20 > +gGopComponentName2ProtocolGuid ## CONSUMES >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeGr= ap > hicsPolicyLib/DxeGraphicsPolicyLib.c > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeGr= ap > hicsPolicyLib/DxeGraphicsPolicyLib.c > new file mode 100644 > index 0000000000..fd284d5f42 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeGr= ap > hicsPolicyLib/DxeGraphicsPolicyLib.c > @@ -0,0 +1,118 @@ > +/** @file >=20 > + This file provide services for DXE phase Graphics policy default initi= alization. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +#include >=20 > + >=20 > +/** >=20 > + This function prints the Graphics DXE phase policy. >=20 > + >=20 > + @param[in] SaPolicy - SA DXE Policy protocol >=20 > +**/ >=20 > +VOID >=20 > +GraphicsDxePolicyPrint ( >=20 > + IN SA_POLICY_PROTOCOL *SaPolicy >=20 > + ) >=20 > +{ >=20 > + EFI_STATUS Status; >=20 > + GRAPHICS_DXE_CONFIG *GraphicsDxeConfig; >=20 > + >=20 > + // >=20 > + // Get requisite IP Config Blocks which needs to be used here >=20 > + // >=20 > + Status =3D GetConfigBlock ((VOID *) SaPolicy, &gGraphicsDxeConfigGuid, > (VOID *)&GraphicsDxeConfig); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + >=20 > + >=20 > + DEBUG_CODE_BEGIN (); >=20 > + DEBUG ((DEBUG_INFO, "\n------------------------ Graphics Policy (DXE) = print > BEGIN -----------------\n")); >=20 > + DEBUG ((DEBUG_INFO, " Revision : %d\n", GraphicsDxeConfig- > >Header.Revision)); >=20 > + ASSERT (GraphicsDxeConfig->Header.Revision =3D=3D > GRAPHICS_DXE_CONFIG_REVISION); >=20 > + DEBUG ((DEBUG_INFO, "\n------------------------ Graphics Policy (DXE) = print > END -----------------\n")); >=20 > + DEBUG_CODE_END (); >=20 > + >=20 > + return; >=20 > +} >=20 > + >=20 > + >=20 > +/** >=20 > + This function Load default Graphics DXE policy. >=20 > + >=20 > + @param[in] ConfigBlockPointer The pointer to add Graphics config bl= ock >=20 > +**/ >=20 > +VOID >=20 > +LoadIgdDxeDefault ( >=20 > + IN VOID *ConfigBlockPointer >=20 > + ) >=20 > +{ >=20 > + GRAPHICS_DXE_CONFIG *GraphicsDxeConfig; >=20 > + >=20 > + GraphicsDxeConfig =3D ConfigBlockPointer; >=20 > + DEBUG ((DEBUG_INFO, "GraphicsDxeConfig->Header.GuidHob.Name =3D > %g\n", &GraphicsDxeConfig->Header.GuidHob.Name)); >=20 > + DEBUG ((DEBUG_INFO, "GraphicsDxeConfig- > >Header.GuidHob.Header.HobLength =3D 0x%x\n", GraphicsDxeConfig- > >Header.GuidHob.Header.HobLength)); >=20 > + /// >=20 > + /// Initialize the Graphics configuration >=20 > + /// >=20 > + GraphicsDxeConfig->PlatformConfig =3D 1; >=20 > + GraphicsDxeConfig->AlsEnable =3D 2; >=20 > + GraphicsDxeConfig->BacklightControlSupport =3D 2; >=20 > + GraphicsDxeConfig->IgdBlcConfig =3D 2; >=20 > + GraphicsDxeConfig->IgdDvmtMemSize =3D 1; >=20 > + GraphicsDxeConfig->GfxTurboIMON =3D 31; >=20 > + /// >=20 > + /// Create a static Backlight Brightness Level Duty cycle > Mapping Table >=20 > + /// Possible 20 entries (example used 11), each 16 bits as follows: >=20 > + /// [15] =3D Field Valid bit, [14:08] =3D Level in Percentage (0-64h),= [07:00] =3D > Desired duty cycle (0 - FFh). >=20 > + /// >=20 > + GraphicsDxeConfig->BCLM[0] =3D (0x0000 + WORD_FIELD_VALID_BIT); ///< > 0% >=20 > + GraphicsDxeConfig->BCLM[1] =3D (0x0A19 + WORD_FIELD_VALID_BIT); ///< > 10% >=20 > + GraphicsDxeConfig->BCLM[2] =3D (0x1433 + WORD_FIELD_VALID_BIT); ///< > 20% >=20 > + GraphicsDxeConfig->BCLM[3] =3D (0x1E4C + WORD_FIELD_VALID_BIT); ///< > 30% >=20 > + GraphicsDxeConfig->BCLM[4] =3D (0x2866 + WORD_FIELD_VALID_BIT); ///< > 40% >=20 > + GraphicsDxeConfig->BCLM[5] =3D (0x327F + WORD_FIELD_VALID_BIT); ///< > 50% >=20 > + GraphicsDxeConfig->BCLM[6] =3D (0x3C99 + WORD_FIELD_VALID_BIT); ///< > 60% >=20 > + GraphicsDxeConfig->BCLM[7] =3D (0x46B2 + WORD_FIELD_VALID_BIT); ///< > 70% >=20 > + GraphicsDxeConfig->BCLM[8] =3D (0x50CC + WORD_FIELD_VALID_BIT); ///< > 80% >=20 > + GraphicsDxeConfig->BCLM[9] =3D (0x5AE5 + WORD_FIELD_VALID_BIT); ///< > 90% >=20 > + GraphicsDxeConfig->BCLM[10] =3D (0x64FF + WORD_FIELD_VALID_BIT); > ///< 100% >=20 > +} >=20 > + >=20 > +static COMPONENT_BLOCK_ENTRY mGraphicsDxeIpBlocks =3D { >=20 > + &gGraphicsDxeConfigGuid, sizeof (GRAPHICS_DXE_CONFIG), > GRAPHICS_DXE_CONFIG_REVISION, LoadIgdDxeDefault}; >=20 > + >=20 > + >=20 > +/** >=20 > + Get DXE Graphics config block table total size. >=20 > + >=20 > + @retval Size of DXE Graphics config block table >=20 > +**/ >=20 > +UINT16 >=20 > +EFIAPI >=20 > +GraphicsGetConfigBlockTotalSizeDxe ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return mGraphicsDxeIpBlocks.Size; >=20 > +} >=20 > + >=20 > +/** >=20 > + GraphicsAddConfigBlocksDxe add all DXE Graphics config block. >=20 > + >=20 > + @param[in] ConfigBlockTableAddress The pointer to add SA config blo= cks >=20 > + >=20 > + @retval EFI_SUCCESS The policy default is initialize= d. >=20 > + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create > buffer >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +GraphicsAddConfigBlocksDxe ( >=20 > + IN VOID *ConfigBlockTableAddress >=20 > + ) >=20 > +{ >=20 > + EFI_STATUS Status; >=20 > + Status =3D AddComponentConfigBlocks (ConfigBlockTableAddress, > &mGraphicsDxeIpBlocks, 1); >=20 > + return Status; >=20 > +} >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeGr= ap > hicsPolicyLib/DxeGraphicsPolicyLib.inf > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeGr= ap > hicsPolicyLib/DxeGraphicsPolicyLib.inf > new file mode 100644 > index 0000000000..d3ac3c24a1 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeGr= ap > hicsPolicyLib/DxeGraphicsPolicyLib.inf > @@ -0,0 +1,37 @@ > +## @file >=20 > +# Component description file for the DXE Graphics Policy Init library. >=20 > +# >=20 > +# Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > +# SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +# >=20 > +## >=20 > + >=20 > +[Defines] >=20 > +INF_VERSION =3D 0x00010017 >=20 > +BASE_NAME =3D DxeGraphicsPolicyLib >=20 > +FILE_GUID =3D C6190599-287E-40F9-9B46-EE112A322EBF >=20 > +VERSION_STRING =3D 1.0 >=20 > +MODULE_TYPE =3D BASE >=20 > +LIBRARY_CLASS =3D DxeGraphicsPolicyLib >=20 > + >=20 > +[LibraryClasses] >=20 > +BaseMemoryLib >=20 > +UefiRuntimeServicesTableLib >=20 > +UefiBootServicesTableLib >=20 > +DebugLib >=20 > +PostCodeLib >=20 > +ConfigBlockLib >=20 > +HobLib >=20 > +SiConfigBlockLib >=20 > + >=20 > +[Packages] >=20 > +MdePkg/MdePkg.dec >=20 > +TigerlakeSiliconPkg/SiPkg.dec >=20 > + >=20 > +[Sources] >=20 > +DxeGraphicsPolicyLib.c >=20 > + >=20 > +[Guids] >=20 > +gGraphicsDxeConfigGuid >=20 > + >=20 > +[Pcd] >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeIg= dO > pRegionInitLib/DxeIgdOpRegionInit.c > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeIg= dO > pRegionInitLib/DxeIgdOpRegionInit.c > new file mode 100644 > index 0000000000..0e12f62f4e > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeIg= dO > pRegionInitLib/DxeIgdOpRegionInit.c > @@ -0,0 +1,541 @@ > +/** @file >=20 > + This is part of the implementation of an Intel Graphics drivers OpRegi= on / >=20 > + Software SCI interface between system BIOS, ASL code, and Graphics > drivers. >=20 > + The code in this file will load the driver and initialize the interfac= e >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +#include >=20 > + >=20 > +#define HEADER_OPREGION_VER_GEN9 0x0200 >=20 > +#define HEADER_OPREGION_VER_GEN12 0x0201 >=20 > + >=20 > + >=20 > +GLOBAL_REMOVE_IF_UNREFERENCED IGD_OPREGION_PROTOCOL > mIgdOpRegion; >=20 > + >=20 > +/** >=20 > + Get VBT data using SaPlaformPolicy >=20 > + >=20 > + @param[out] VbtFileBuffer Pointer to VBT data buffer. >=20 > + >=20 > + @retval EFI_SUCCESS VBT data was returned. >=20 > + @retval EFI_NOT_FOUND VBT data not found. >=20 > + @exception EFI_UNSUPPORTED Invalid signature in VBT data. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +GetIntegratedIntelVbtPtr ( >=20 > + OUT VBIOS_VBT_STRUCTURE **VbtFileBuffer >=20 > + ) >=20 > +{ >=20 > + EFI_STATUS Status; >=20 > + EFI_PHYSICAL_ADDRESS VbtAddress; >=20 > + UINT32 Size; >=20 > + GRAPHICS_DXE_CONFIG *GraphicsDxeConfig; >=20 > + SA_POLICY_PROTOCOL *SaPolicy; >=20 > + >=20 > + /// >=20 > + /// Get the SA policy. >=20 > + /// >=20 > + Status =3D gBS->LocateProtocol ( >=20 > + &gSaPolicyProtocolGuid, >=20 > + NULL, >=20 > + (VOID **) &SaPolicy >=20 > + ); >=20 > + if (EFI_ERROR (Status)) { >=20 > + return Status; >=20 > + } >=20 > + >=20 > + Status =3D GetConfigBlock ((VOID *) SaPolicy, &gGraphicsDxeConfigGuid, > (VOID *)&GraphicsDxeConfig); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + >=20 > + VbtAddress =3D GraphicsDxeConfig->VbtAddress; >=20 > + Size =3D GraphicsDxeConfig->Size; >=20 > + >=20 > + if (VbtAddress =3D=3D 0x00000000) { >=20 > + return EFI_NOT_FOUND; >=20 > + } else { >=20 > + /// >=20 > + /// Check VBT signature >=20 > + /// >=20 > + *VbtFileBuffer =3D NULL; >=20 > + *VbtFileBuffer =3D (VBIOS_VBT_STRUCTURE *) (UINTN) VbtAddress; >=20 > + if ((*((UINT32 *) ((*VbtFileBuffer)->HeaderSignature))) !=3D > VBT_SIGNATURE) { >=20 > + FreePool (*VbtFileBuffer); >=20 > + *VbtFileBuffer =3D NULL; >=20 > + return EFI_UNSUPPORTED; >=20 > + } >=20 > + } >=20 > + if (Size =3D=3D 0) { >=20 > + return EFI_NOT_FOUND; >=20 > + } else { >=20 > + /// >=20 > + /// Check VBT size >=20 > + /// >=20 > + if ((*VbtFileBuffer)->HeaderVbtSize > Size) { >=20 > + (*VbtFileBuffer)->HeaderVbtSize =3D (UINT16) Size; >=20 > + } >=20 > + } >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > +/** >=20 > + Get a pointer to an uncompressed image of the Intel video BIOS. >=20 > + >=20 > + @Note: This function would only be called if the video BIOS at 0xC000 = is >=20 > + missing or not an Intel video BIOS. It may not be an Intel vid= eo BIOS >=20 > + if the Intel graphic contoller is considered a secondary adapte= r. >=20 > + >=20 > + @param[out] VBiosImage - Pointer to an uncompressed Intel video > BIOS. This pointer must >=20 > + be set to NULL if an uncompressed image o= f the Intel Video > BIOS >=20 > + is not obtainable. >=20 > + >=20 > + @retval EFI_SUCCESS - VBiosPtr is updated. >=20 > + @exception EFI_UNSUPPORTED - No Intel video BIOS found. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +GetIntegratedIntelVBiosPtr ( >=20 > + OUT INTEL_VBIOS_OPTION_ROM_HEADER **VBiosImage >=20 > + ) >=20 > +{ >=20 > + EFI_HANDLE *HandleBuffer; >=20 > + UINTN HandleCount; >=20 > + UINTN Index; >=20 > + INTEL_VBIOS_PCIR_STRUCTURE *PcirBlockPtr; >=20 > + EFI_STATUS Status; >=20 > + EFI_PCI_IO_PROTOCOL *PciIo; >=20 > + INTEL_VBIOS_OPTION_ROM_HEADER *VBiosRomImage; >=20 > + >=20 > + /// >=20 > + /// Set as if an umcompressed Intel video BIOS image was not obtainabl= e. >=20 > + /// >=20 > + VBiosRomImage =3D NULL; >=20 > + >=20 > + /// >=20 > + /// Get all PCI IO protocols >=20 > + /// >=20 > + Status =3D gBS->LocateHandleBuffer ( >=20 > + ByProtocol, >=20 > + &gEfiPciIoProtocolGuid, >=20 > + NULL, >=20 > + &HandleCount, >=20 > + &HandleBuffer >=20 > + ); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + >=20 > + /// >=20 > + /// Find the video BIOS by checking each PCI IO handle for an Intel vi= deo >=20 > + /// BIOS OPROM. >=20 > + /// >=20 > + for (Index =3D 0; Index < HandleCount; Index++) { >=20 > + Status =3D gBS->HandleProtocol ( >=20 > + HandleBuffer[Index], >=20 > + &gEfiPciIoProtocolGuid, >=20 > + (VOID **) &PciIo >=20 > + ); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + >=20 > + VBiosRomImage =3D PciIo->RomImage; >=20 > + >=20 > + /// >=20 > + /// If this PCI device doesn't have a ROM image, skip to the next de= vice. >=20 > + /// >=20 > + if (!VBiosRomImage) { >=20 > + continue; >=20 > + } >=20 > + /// >=20 > + /// Get pointer to PCIR structure >=20 > + /// >=20 > + PcirBlockPtr =3D (INTEL_VBIOS_PCIR_STRUCTURE *) ((UINT8 *) > VBiosRomImage + VBiosRomImage->PcirOffset); >=20 > + >=20 > + /// >=20 > + /// Check if we have an Intel video BIOS OPROM. >=20 > + /// >=20 > + if ((VBiosRomImage->Signature =3D=3D OPTION_ROM_SIGNATURE) && >=20 > + (PcirBlockPtr->VendorId =3D=3D V_SA_MC_VID) && >=20 > + (PcirBlockPtr->ClassCode[0] =3D=3D 0x00) && >=20 > + (PcirBlockPtr->ClassCode[1] =3D=3D 0x00) && >=20 > + (PcirBlockPtr->ClassCode[2] =3D=3D 0x03) >=20 > + ) { >=20 > + /// >=20 > + /// Found Intel video BIOS. >=20 > + /// >=20 > + *VBiosImage =3D VBiosRomImage; >=20 > + return EFI_SUCCESS; >=20 > + } >=20 > + } >=20 > + /// >=20 > + /// No Intel video BIOS found. >=20 > + /// >=20 > + /// >=20 > + /// Free any allocated buffers >=20 > + /// >=20 > + FreePool (HandleBuffer); >=20 > + return EFI_UNSUPPORTED; >=20 > +} >=20 > + >=20 > +/** >=20 > + Get Intel video BIOS VBT information (i.e. Pointer to VBT and VBT size= ). >=20 > + The VBT (Video BIOS Table) is a block of customizable data that is bui= lt >=20 > + within the video BIOS and edited by customers. >=20 > + >=20 > + @retval EFI_SUCCESS - Video BIOS VBT information returned. >=20 > + @exception EFI_UNSUPPORTED - Could not find VBT information > (*VBiosVbtPtr =3D NULL). >=20 > +**/ >=20 > +EFI_STATUS >=20 > +GetVBiosVbtEndOfDxe ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + INTEL_VBIOS_OPTION_ROM_HEADER *VBiosPtr; >=20 > + VBIOS_VBT_STRUCTURE *VBiosVbtPtr; >=20 > + EFI_STATUS Status; >=20 > + VBIOS_VBT_STRUCTURE *VbtFileBuffer; >=20 > + GRAPHICS_DXE_CONFIG *GraphicsDxeConfig; >=20 > + SA_POLICY_PROTOCOL *SaPolicy; >=20 > + >=20 > + VbtFileBuffer =3D NULL; >=20 > + >=20 > + /// >=20 > + /// Get the SA policy. >=20 > + /// >=20 > + Status =3D gBS->LocateProtocol ( >=20 > + &gSaPolicyProtocolGuid, >=20 > + NULL, >=20 > + (VOID **) &SaPolicy >=20 > + ); >=20 > + if (EFI_ERROR (Status)) { >=20 > + return Status; >=20 > + } >=20 > + >=20 > + Status =3D GetConfigBlock ((VOID *) SaPolicy, &gGraphicsDxeConfigGuid, > (VOID *)&GraphicsDxeConfig); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + >=20 > + VBiosPtr =3D NULL; >=20 > + /// >=20 > + /// Try to get VBT from FV. >=20 > + /// >=20 > + GetIntegratedIntelVbtPtr (&VbtFileBuffer); >=20 > + if (VbtFileBuffer !=3D NULL) { >=20 > + /// >=20 > + /// Video BIOS not found, use VBT from SaPolicy >=20 > + /// >=20 > + DEBUG ((DEBUG_INFO, "VBT data found\n")); >=20 > + CopyMem (mIgdOpRegion.OpRegion->Header.DVER, GraphicsDxeConfig- > >GopVersion, sizeof(GraphicsDxeConfig->GopVersion)); >=20 > + mIgdOpRegion.OpRegion->MBox3.RVDA =3D 0; >=20 > + mIgdOpRegion.OpRegion->MBox3.RVDS =3D 0; >=20 > + if ((VbtFileBuffer->HeaderVbtSize > 0x1800)) { // VBT > 6KB >=20 > + DEBUG ((DEBUG_INFO, "Extended VBT supported\n")); >=20 > + mIgdOpRegion.OpRegion->MBox3.RVDA =3D sizeof > (IGD_OPREGION_STRUCTURE); // Relative offset at the end of Op-region. >=20 > + mIgdOpRegion.OpRegion->MBox3.RVDS =3D ((VbtFileBuffer- > >HeaderVbtSize) & (UINT32)~(0x1FF)) + 0x200; // Aligned VBT Data Size to > 512 bytes. >=20 > + CopyMem ((CHAR8 *)(UINTN)(mIgdOpRegion.OpRegion) + sizeof > (IGD_OPREGION_STRUCTURE), VbtFileBuffer, mIgdOpRegion.OpRegion- > >MBox3.RVDS); >=20 > + } else { >=20 > + CopyMem (mIgdOpRegion.OpRegion->MBox4.RVBT, VbtFileBuffer, > VbtFileBuffer->HeaderVbtSize); >=20 > + } >=20 > + return EFI_SUCCESS; >=20 > + } >=20 > + >=20 > + if (VBiosPtr =3D=3D NULL) { >=20 > + return EFI_UNSUPPORTED; >=20 > + } >=20 > + >=20 > + DEBUG ((DEBUG_INFO, "VBIOS found at 0x%X\n", VBiosPtr)); >=20 > + VBiosVbtPtr =3D (VBIOS_VBT_STRUCTURE *) ((UINT8 *) VBiosPtr + VBiosPtr= - > >VbtOffset); >=20 > + >=20 > + if ((*((UINT32 *) (VBiosVbtPtr->HeaderSignature))) !=3D VBT_SIGNATURE)= { >=20 > + return EFI_UNSUPPORTED; >=20 > + } >=20 > + >=20 > + /// >=20 > + /// Initialize Video BIOS version with its build number. >=20 > + /// >=20 > + mIgdOpRegion.OpRegion->Header.VVER[0] =3D VBiosVbtPtr- > >CoreBlockBiosBuild[0]; >=20 > + mIgdOpRegion.OpRegion->Header.VVER[1] =3D VBiosVbtPtr- > >CoreBlockBiosBuild[1]; >=20 > + mIgdOpRegion.OpRegion->Header.VVER[2] =3D VBiosVbtPtr- > >CoreBlockBiosBuild[2]; >=20 > + mIgdOpRegion.OpRegion->Header.VVER[3] =3D VBiosVbtPtr- > >CoreBlockBiosBuild[3]; >=20 > + CopyMem (mIgdOpRegion.OpRegion->MBox4.RVBT, VBiosVbtPtr, > VBiosVbtPtr->HeaderVbtSize); >=20 > + >=20 > + /// >=20 > + /// Return final status >=20 > + /// >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > +/** >=20 > + Graphics OpRegion / Software SCI driver installation function. >=20 > + >=20 > + @param[in] void - None >=20 > + @retval EFI_SUCCESS - The driver installed without error. >=20 > + @retval EFI_ABORTED - The driver encountered an error and could no= t > complete >=20 > + installation of the ACPI tables. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +IgdOpRegionInit ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + EFI_HANDLE Handle; >=20 > + EFI_STATUS Status; >=20 > + UINT32 DwordData; >=20 > + UINT64 IgdBaseAddress; >=20 > + SA_POLICY_PROTOCOL *SaPolicy; >=20 > + GRAPHICS_DXE_CONFIG *GraphicsDxeConfig; >=20 > + UINT8 Index; >=20 > + SYSTEM_AGENT_NVS_AREA_PROTOCOL *SaNvsAreaProtocol; >=20 > + VBIOS_VBT_STRUCTURE *VbtFileBuffer; >=20 > + UINT16 ExtendedVbtSize; >=20 > + >=20 > + /// >=20 > + /// Get the SA policy. >=20 > + /// >=20 > + Status =3D gBS->LocateProtocol (&gSaPolicyProtocolGuid, NULL, (VOID > **)&SaPolicy); >=20 > + >=20 > + if (EFI_ERROR (Status)) { >=20 > + return Status; >=20 > + } >=20 > + >=20 > + Status =3D GetConfigBlock ((VOID *) SaPolicy, &gGraphicsDxeConfigGuid, > (VOID *)&GraphicsDxeConfig); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + >=20 > + VbtFileBuffer =3D NULL; >=20 > + ExtendedVbtSize =3D 0; >=20 > + >=20 > + GetIntegratedIntelVbtPtr (&VbtFileBuffer); >=20 > + /// >=20 > + /// Locate the SA Global NVS Protocol. >=20 > + /// >=20 > + Status =3D gBS->LocateProtocol ( >=20 > + &gSaNvsAreaProtocolGuid, >=20 > + NULL, >=20 > + (VOID **) &SaNvsAreaProtocol >=20 > + ); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + >=20 > + /// >=20 > + /// Check if VBT size is >6KB then allocate an ACPI NVS memory buffer = as > the IGD OpRegion + extended VBT size, >=20 > + /// zero initialize it, and set the IGD OpRegion pointer in the Global= NVS > area structure. >=20 > + /// >=20 > + if ((VbtFileBuffer !=3D NULL) && (VbtFileBuffer->HeaderVbtSize > 0x180= 0)) { >=20 > + ExtendedVbtSize =3D ((VbtFileBuffer->HeaderVbtSize) & (UINT32)~(0x1F= F)) > + 0x200; >=20 > + } >=20 > + >=20 > + Status =3D (gBS->AllocatePool) (EfiACPIMemoryNVS, sizeof > (IGD_OPREGION_STRUCTURE) + ExtendedVbtSize, (VOID **) > &mIgdOpRegion.OpRegion); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + SetMem (mIgdOpRegion.OpRegion, sizeof (IGD_OPREGION_STRUCTURE) > + ExtendedVbtSize, 0); >=20 > + SaNvsAreaProtocol->Area->IgdOpRegionAddress =3D (UINT32) (UINTN) > (mIgdOpRegion.OpRegion); >=20 > + >=20 > + /// >=20 > + /// If IGD is disabled return >=20 > + /// >=20 > + IgdBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, > IGD_BUS_NUM, IGD_DEV_NUM, IGD_FUN_NUM, 0); >=20 > + if (PciSegmentRead32 (IgdBaseAddress + 0) =3D=3D 0xFFFFFFFF) { >=20 > + return EFI_SUCCESS; >=20 > + } >=20 > + /// >=20 > + /// Initialize OpRegion Header >=20 > + /// >=20 > + CopyMem (mIgdOpRegion.OpRegion->Header.SIGN, > HEADER_SIGNATURE, sizeof (HEADER_SIGNATURE)); >=20 > + /// >=20 > + /// Set OpRegion Size in KBs >=20 > + /// >=20 > + mIgdOpRegion.OpRegion->Header.SIZE =3D HEADER_SIZE / 1024; >=20 > + mIgdOpRegion.OpRegion->Header.OVER =3D (UINT32) (LShiftU64 > (HEADER_OPREGION_VER_GEN12, 16) + LShiftU64 > (HEADER_OPREGION_REV, 8)); >=20 > + >=20 > + /// >=20 > + /// All Mailboxes are supported. >=20 > + /// >=20 > + mIgdOpRegion.OpRegion->Header.MBOX =3D HEADER_MBOX_SUPPORT; >=20 > + >=20 > + /// >=20 > + /// Initialize OpRegion Mailbox 1 (Public ACPI Methods). >=20 > + /// >=20 > + /// Note - The initial setting of mailbox 1 fields is implementation s= pecific. >=20 > + /// Adjust them as needed many even coming from user setting in setup. >=20 > + /// >=20 > + /// >=20 > + /// Initialize OpRegion Mailbox 3 (ASLE Interrupt and Power Conservati= on). >=20 > + /// >=20 > + /// Note - The initial setting of mailbox 3 fields is implementation s= pecific. >=20 > + /// Adjust them as needed many even coming from user setting in setup. >=20 > + /// >=20 > + /// >=20 > + /// Do not initialize TCHE. This field is written by the graphics driv= er only. >=20 > + /// >=20 > + /// >=20 > + /// The ALSI field is generally initialized by ASL code by reading the > embedded controller. >=20 > + /// >=20 > + mIgdOpRegion.OpRegion->Header.PCON =3D GraphicsDxeConfig- > >PlatformConfig; >=20 > + mIgdOpRegion.OpRegion->Header.PCON =3D mIgdOpRegion.OpRegion- > >Header.PCON | 0x2; >=20 > + >=20 > + mIgdOpRegion.OpRegion->MBox3.BCLP =3D BACKLIGHT_BRIGHTNESS; >=20 > + >=20 > + mIgdOpRegion.OpRegion->MBox3.PFIT =3D (FIELD_VALID_BIT | > PFIT_STRETCH); >=20 > + >=20 > + /// >=20 > + /// Reporting to driver for VR IMON Calibration. Bits [5-1] values sup= ported > 14A to 31A. >=20 > + /// >=20 > + mIgdOpRegion.OpRegion->MBox3.PCFT =3D (SaNvsAreaProtocol->Area- > >GfxTurboIMON << 1) & 0x003E; >=20 > + >=20 > + /// >=20 > + /// Set Initial current Brightness >=20 > + /// >=20 > + mIgdOpRegion.OpRegion->MBox3.CBLV =3D (INIT_BRIGHT_LEVEL | > FIELD_VALID_BIT); >=20 > + >=20 > + /// >=20 > + /// Static Backlight Brightness Level Duty cycle Mapping Table >=20 > + /// >=20 > + for (Index =3D 0; Index < MAX_BCLM_ENTRIES; Index++) { >=20 > + mIgdOpRegion.OpRegion->MBox3.BCLM[Index] =3D GraphicsDxeConfig- > >BCLM[Index]; >=20 > + } >=20 > + >=20 > + mIgdOpRegion.OpRegion->MBox3.IUER =3D 0x00; >=20 > + >=20 > + if (!EFI_ERROR (Status)) { >=20 > + mIgdOpRegion.OpRegion->MBox3.IUER =3D GraphicsDxeConfig- > >IuerStatusVal; >=20 > + } >=20 > + >=20 > + /// >=20 > + /// Initialize hardware state: >=20 > + /// Set ASLS Register to the OpRegion physical memory address. >=20 > + /// Set SWSCI register bit 15 to a "1" to activate SCI interrupts. >=20 > + /// >=20 > + PciSegmentWrite32 (IgdBaseAddress + R_SA_IGD_ASLS_OFFSET, (UINT32) > (UINTN) (mIgdOpRegion.OpRegion)); >=20 > + PciSegmentAndThenOr16 (IgdBaseAddress + R_SA_IGD_SWSCI_OFFSET, > (UINT16) ~(BIT0), BIT15); >=20 > + >=20 > + DwordData =3D PciSegmentRead32 (IgdBaseAddress + > R_SA_IGD_ASLS_OFFSET); >=20 > + S3BootScriptSaveMemWrite ( >=20 > + S3BootScriptWidthUint32, >=20 > + (UINTN) PcdGet64 (PcdPciExpressBaseAddress) + (IgdBaseAddress + > R_SA_IGD_ASLS_OFFSET), >=20 > + 1, >=20 > + &DwordData >=20 > + ); >=20 > + DwordData =3D PciSegmentRead32 (IgdBaseAddress + > R_SA_IGD_SWSCI_OFFSET); >=20 > + S3BootScriptSaveMemWrite ( >=20 > + S3BootScriptWidthUint32, >=20 > + (UINTN) PcdGet64 (PcdPciExpressBaseAddress) + (IgdBaseAddress + > R_SA_IGD_SWSCI_OFFSET), >=20 > + 1, >=20 > + &DwordData >=20 > + ); >=20 > + >=20 > + /// >=20 > + /// Install OpRegion / Software SCI protocol >=20 > + /// >=20 > + Handle =3D NULL; >=20 > + Status =3D gBS->InstallMultipleProtocolInterfaces ( >=20 > + &Handle, >=20 > + &gIgdOpRegionProtocolGuid, >=20 > + &mIgdOpRegion, >=20 > + NULL >=20 > + ); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + >=20 > + /// >=20 > + /// Return final status >=20 > + /// >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > +/** >=20 > + Update Graphics OpRegion after PCI enumeration. >=20 > + >=20 > + @param[in] void - None >=20 > + @retval EFI_SUCCESS - The function completed successfully. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +UpdateIgdOpRegionEndOfDxe ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + EFI_STATUS Status; >=20 > + UINTN HandleCount; >=20 > + EFI_HANDLE *HandleBuffer; >=20 > + UINTN Index; >=20 > + EFI_PCI_IO_PROTOCOL *PciIo; >=20 > + PCI_TYPE00 Pci; >=20 > + UINTN Segment; >=20 > + UINTN Bus; >=20 > + UINTN Device; >=20 > + UINTN Function; >=20 > + >=20 > + Bus =3D 0; >=20 > + Device =3D 0; >=20 > + Function =3D 0; >=20 > + >=20 > + DEBUG ((DEBUG_INFO, "UpdateIgdOpRegionEndOfDxe\n")); >=20 > + >=20 > + mIgdOpRegion.OpRegion->Header.PCON |=3D BIT8; //Set External Gfx > Adapter field is valid >=20 > + mIgdOpRegion.OpRegion->Header.PCON &=3D (UINT32) (~BIT7); //Assume > No External Gfx Adapter >=20 > + >=20 > + /// >=20 > + /// Get all PCI IO protocols handles >=20 > + /// >=20 > + Status =3D gBS->LocateHandleBuffer ( >=20 > + ByProtocol, >=20 > + &gEfiPciIoProtocolGuid, >=20 > + NULL, >=20 > + &HandleCount, >=20 > + &HandleBuffer >=20 > + ); >=20 > + >=20 > + if (!EFI_ERROR (Status)) { >=20 > + for (Index =3D 0; Index < HandleCount; Index++) { >=20 > + /// >=20 > + /// Get the PCI IO Protocol Interface corresponding to each handle >=20 > + /// >=20 > + Status =3D gBS->HandleProtocol ( >=20 > + HandleBuffer[Index], >=20 > + &gEfiPciIoProtocolGuid, >=20 > + (VOID **) &PciIo >=20 > + ); >=20 > + >=20 > + if (!EFI_ERROR (Status)) { >=20 > + /// >=20 > + /// Read the PCI configuration space >=20 > + /// >=20 > + Status =3D PciIo->Pci.Read ( >=20 > + PciIo, >=20 > + EfiPciIoWidthUint32, >=20 > + 0, >=20 > + sizeof (Pci) / sizeof (UINT32), >=20 > + &Pci >=20 > + ); >=20 > + >=20 > + /// >=20 > + /// Find the display controllers devices >=20 > + /// >=20 > + if (!EFI_ERROR (Status) && IS_PCI_DISPLAY (&Pci)) { >=20 > + Status =3D PciIo->GetLocation ( >=20 > + PciIo, >=20 > + &Segment, >=20 > + &Bus, >=20 > + &Device, >=20 > + &Function >=20 > + ); >=20 > + >=20 > + // >=20 > + // Assumption: Onboard devices will be sits on Bus no 0, while= external > devices will be sits on Bus no > 0 >=20 > + // >=20 > + if (!EFI_ERROR (Status) && (Bus > 0)) { >=20 > + //External Gfx Adapter Detected and Available >=20 > + DEBUG ((DEBUG_INFO, "PCON - External Gfx Adapter Detected an= d > Available\n")); >=20 > + mIgdOpRegion.OpRegion->Header.PCON |=3D BIT7; >=20 > + break; >=20 > + } >=20 > + } >=20 > + } >=20 > + } >=20 > + } >=20 > + >=20 > + /// >=20 > + /// Free any allocated buffers >=20 > + /// >=20 > + if (HandleBuffer !=3D NULL) { >=20 > + FreePool (HandleBuffer); >=20 > + } >=20 > + >=20 > + /// >=20 > + /// Return final status >=20 > + /// >=20 > + return Status; >=20 > +} >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeIg= dO > pRegionInitLib/DxeIgdOpRegionInitLib.inf > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeIg= dO > pRegionInitLib/DxeIgdOpRegionInitLib.inf > new file mode 100644 > index 0000000000..20c6265d8f > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeIg= dO > pRegionInitLib/DxeIgdOpRegionInitLib.inf > @@ -0,0 +1,49 @@ > +## @file >=20 > +# Component description file for the Dxe IGD OpRegion library. >=20 > +# >=20 > +# Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > +# SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +# >=20 > +## >=20 > + >=20 > +[Defines] >=20 > +INF_VERSION =3D 0x00010017 >=20 > +BASE_NAME =3D DxeIgdOpRegionInitLib >=20 > +FILE_GUID =3D 18D47D72-555E-475B-A4E4-AD20C3BD8B15 >=20 > +VERSION_STRING =3D 1.0 >=20 > +MODULE_TYPE =3D DXE_DRIVER >=20 > +UEFI_SPECIFICATION_VERSION =3D 2.00 >=20 > +LIBRARY_CLASS =3D DxeIgdOpRegionInitLib >=20 > + >=20 > +[LibraryClasses] >=20 > +UefiLib >=20 > +UefiRuntimeServicesTableLib >=20 > +UefiBootServicesTableLib >=20 > +DebugLib >=20 > +PostCodeLib >=20 > +ConfigBlockLib >=20 > +PciSegmentLib >=20 > +BaseMemoryLib >=20 > +MemoryAllocationLib >=20 > +IoLib >=20 > +S3BootScriptLib >=20 > + >=20 > +[Packages] >=20 > +MdePkg/MdePkg.dec >=20 > +TigerlakeSiliconPkg/SiPkg.dec >=20 > +IntelSiliconPkg/IntelSiliconPkg.dec >=20 > + >=20 > +[Pcd] >=20 > +gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress >=20 > + >=20 > +[Sources] >=20 > +DxeIgdOpRegionInit.c >=20 > + >=20 > +[Guids] >=20 > +gGraphicsDxeConfigGuid ## CONSUMES >=20 > + >=20 > +[Protocols] >=20 > +gIgdOpRegionProtocolGuid ## PRODUCES >=20 > +gSaPolicyProtocolGuid ## CONSUMES >=20 > +gEfiPciIoProtocolGuid ## CONSUMES >=20 > +gSaNvsAreaProtocolGuid ## CONSUMES >=20 > -- > 2.24.0.windows.2