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Thu, 4 Feb 2021 03:51:29 +0000 Received: from BN6PR1101MB2147.namprd11.prod.outlook.com ([fe80::203e:ed6b:a572:6453]) by BN6PR1101MB2147.namprd11.prod.outlook.com ([fe80::203e:ed6b:a572:6453%3]) with mapi id 15.20.3805.024; Thu, 4 Feb 2021 03:51:29 +0000 From: "Nate DeSimone" To: "Luo, Heng" , "devel@edk2.groups.io" CC: "Chaganty, Rangasai V" Subject: Re: [PATCH 02/40] TigerlakeSiliconPkg/Include: Add Library, PPI and Protocol include headers Thread-Topic: [PATCH 02/40] TigerlakeSiliconPkg/Include: Add Library, PPI and Protocol include headers Thread-Index: AQHW+DrGMKI3rG2Fs0KoBcQO8Jwp/6pHWFDQ Date: Thu, 4 Feb 2021 03:51:27 +0000 Message-ID: References: <20210201013657.1833-1-heng.luo@intel.com> <20210201013657.1833-2-heng.luo@intel.com> In-Reply-To: <20210201013657.1833-2-heng.luo@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-reaction: no-action dlp-version: 11.5.1.3 dlp-product: dlpe-windows authentication-results: intel.com; dkim=none (message not signed) header.d=none;intel.com; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hi Heng, FspmArchConfigPpi.h is a duplicate of a header file in IntelFsp2Pkg, please= remove this duplicate. Please also remove the #include for CpuPcieConfigGe= n3.h from SiPolicy.h, please see inline. Thanks, Nate > -----Original Message----- > From: Luo, Heng > Sent: Sunday, January 31, 2021 5:36 PM > To: devel@edk2.groups.io > Cc: Chaganty, Rangasai V ; Desimone, > Nathaniel L > Subject: [PATCH 02/40] TigerlakeSiliconPkg/Include: Add Library, PPI and > Protocol include headers >=20 > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3171 >=20 > Adds the following header files: > * Include/Library > * Include/Ppi > * Include/Protocol >=20 > Cc: Sai Chaganty > Cc: Nate DeSimone > Signed-off-by: Heng Luo > --- > Silicon/Intel/TigerlakeSiliconPkg/Include/Library/ConfigBlockLib.h = | 64 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++ > Silicon/Intel/TigerlakeSiliconPkg/Include/Library/CpuRegbarAccessLib.h = | > 332 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Include/Library/DxeHdaNhltLib.h = | 153 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Include/Library/EspiLib.h = | 140 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Include/Library/GbeLib.h = | 63 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++ > Silicon/Intel/TigerlakeSiliconPkg/Include/Library/GpioConfig.h = | 342 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Include/Library/GpioLib.h = | 720 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Include/Library/GpioNativeLib.h = | 149 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Include/Library/MmPciLib.h = | 27 > +++++++++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Include/Library/PchPcieRpLib.h = | 123 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++ > Silicon/Intel/TigerlakeSiliconPkg/Include/Library/PchPcrLib.h = | 256 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Include/Library/PcieHelperLib.h = | 173 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Include/Library/PmcLib.h = | 355 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++ > Silicon/Intel/TigerlakeSiliconPkg/Include/Library/ResetSystemLib.h = | 79 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Include/Library/SataLib.h = | 112 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Include/Library/SerialIoAccessLib.h = | 113 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++++++++++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Include/Library/SiConfigBlockLib.h = | 56 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Include/Library/SpiAccessLib.h = | 290 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Include/Library/VtdInfoLib.h = | 53 > +++++++++++++++++++++++++++++++++++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Include/Ppi/FspmArchConfigPpi.h = | 32 > ++++++++++++++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Include/Ppi/PeiPreMemSiDefaultPolicy.h= | > 34 ++++++++++++++++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Include/Ppi/PeiSiDefaultPolicy.h = | 33 > +++++++++++++++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Include/Ppi/SiPolicy.h = | 79 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Include/Protocol/GopComponentName2.h > | 61 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++ > Silicon/Intel/TigerlakeSiliconPkg/Include/Protocol/GopPolicy.h = | 73 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Include/Protocol/IgdOpRegion.h = | 22 > ++++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Include/Protocol/Spi.h = | 301 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++ > 27 files changed, 4235 insertions(+) >=20 > diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/ConfigBloc= kLib.h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/ConfigBlockLib.h > new file mode 100644 > index 0000000000..dbf786ec9a > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/ConfigBlockLib.h > @@ -0,0 +1,64 @@ > +/** @file >=20 > + Header file for Config Block Lib implementation >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +#ifndef _CONFIG_BLOCK_LIB_H_ >=20 > +#define _CONFIG_BLOCK_LIB_H_ >=20 > + >=20 > +/** >=20 > + Create config block table >=20 > + >=20 > + @param[in] TotalSize - Max size to be allocated= for the Config > Block Table >=20 > + @param[out] ConfigBlockTableAddress - On return, points to a p= ointer > to the beginning of Config Block Table Address >=20 > + >=20 > + @retval EFI_INVALID_PARAMETER - Invalid Parameter >=20 > + @retval EFI_OUT_OF_RESOURCES - Out of resources >=20 > + @retval EFI_SUCCESS - Successfully created Config Block Tabl= e at > ConfigBlockTableAddress >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +CreateConfigBlockTable ( >=20 > + IN UINT16 TotalSize, >=20 > + OUT VOID **ConfigBlockTableAddress >=20 > + ); >=20 > + >=20 > +/** >=20 > + Add config block into config block table structure >=20 > + >=20 > + @param[in] ConfigBlockTableAddress - A pointer to the beginni= ng of > Config Block Table Address >=20 > + @param[out] ConfigBlockAddress - On return, points to a p= ointer to > the beginning of Config Block Address >=20 > + >=20 > + @retval EFI_OUT_OF_RESOURCES - Config Block Table is full and cannot > add new Config Block or >=20 > + Config Block Offset Table is full and c= annot add new Config > Block. >=20 > + @retval EFI_SUCCESS - Successfully added Config Block >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +AddConfigBlock ( >=20 > + IN VOID *ConfigBlockTableAddress, >=20 > + OUT VOID **ConfigBlockAddress >=20 > + ); >=20 > + >=20 > +/** >=20 > + Retrieve a specific Config Block data by GUID >=20 > + >=20 > + @param[in] ConfigBlockTableAddress - A pointer to the beginn= ing of > Config Block Table Address >=20 > + @param[in] ConfigBlockGuid - A pointer to the GUID u= ses to > search specific Config Block >=20 > + @param[out] ConfigBlockAddress - On return, points to a = pointer to > the beginning of Config Block Address >=20 > + >=20 > + @retval EFI_NOT_FOUND - Could not find the Config Block >=20 > + @retval EFI_SUCCESS - Config Block found and return >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +GetConfigBlock ( >=20 > + IN VOID *ConfigBlockTableAddress, >=20 > + IN EFI_GUID *ConfigBlockGuid, >=20 > + OUT VOID **ConfigBlockAddress >=20 > + ); >=20 > + >=20 > +#endif // _CONFIG_BLOCK_LIB_H_ >=20 > + >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/CpuRegbarAccessLib.h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/CpuRegbarAccessLib.h > new file mode 100644 > index 0000000000..564fcccb43 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/CpuRegbarAccessLib.h > @@ -0,0 +1,332 @@ > +/** @file >=20 > + Header file for CPU REGBAR ACCESS library. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _CPU_REGBAR_ACCESS_LIB_H_ >=20 > +#define _CPU_REGBAR_ACCESS_LIB_H_ >=20 > + >=20 > +#define INVALID_DATA_64 0xFFFFFFFFFFFFFFFF >=20 > +#define INVALID_DATA_32 0xFFFFFFFF >=20 > +#define INVALID_DATA_16 0xFFFF >=20 > +#define INVALID_DATA_8 0xFF >=20 > +#define INVALID_PID 0xFF >=20 > + >=20 > +typedef UINT8 CPU_SB_DEVICE_PID; >=20 > + >=20 > +/** >=20 > + Read REGBAR register. >=20 > + It returns REGBAR register and size in 8bytes. >=20 > + The Offset should not exceed 0xFFFF and must be aligned with size. >=20 > + >=20 > + @param[in] CpuSbDevicePid CPU SB Device Port ID >=20 > + @param[in] Offset Register offset of this Port ID >=20 > + >=20 > + @retval UINT64 REGBAR register value. >=20 > +**/ >=20 > +UINT64 >=20 > +CpuRegbarRead64 ( >=20 > + IN CPU_SB_DEVICE_PID CpuSbDevicePid, >=20 > + IN UINT16 Offset >=20 > + ); >=20 > + >=20 > + >=20 > +/** >=20 > + Read REGBAR register. >=20 > + It returns REGBAR register and size in 4bytes. >=20 > + The Offset should not exceed 0xFFFF and must be aligned with size. >=20 > + >=20 > + @param[in] CpuSbDevicePid CPU SB Device Port ID >=20 > + @param[in] Offset Register offset of this Port ID >=20 > + >=20 > + @retval UINT32 REGBAR register value. >=20 > +**/ >=20 > +UINT32 >=20 > +CpuRegbarRead32 ( >=20 > + IN CPU_SB_DEVICE_PID CpuSbDevicePid, >=20 > + IN UINT16 Offset >=20 > + ); >=20 > + >=20 > +/** >=20 > + Read REGBAR register. >=20 > + It returns REGBAR register and size in 2bytes. >=20 > + The Offset should not exceed 0xFFFF and must be aligned with size. >=20 > + >=20 > + @param[in] CpuSbDevicePid CPU SB Device Port ID >=20 > + @param[in] Offset Register offset of this Port ID >=20 > + >=20 > + @retval UINT16 REGBAR register value. >=20 > +**/ >=20 > +UINT16 >=20 > +CpuRegbarRead16 ( >=20 > + IN CPU_SB_DEVICE_PID CpuSbDevicePid, >=20 > + IN UINT16 Offset >=20 > + ); >=20 > + >=20 > +/** >=20 > + Read REGBAR register. >=20 > + It returns REGBAR register and size in 1bytes. >=20 > + The Offset should not exceed 0xFFFF and must be aligned with size. >=20 > + >=20 > + @param[in] CpuSbDevicePid CPU SB Device Port ID >=20 > + @param[in] Offset Register offset of this Port ID >=20 > + >=20 > + @retval UINT8 REGBAR regsiter value >=20 > +**/ >=20 > +UINT8 >=20 > +CpuRegbarRead8 ( >=20 > + IN CPU_SB_DEVICE_PID CpuSbDevicePid, >=20 > + IN UINT16 Offset >=20 > + ); >=20 > + >=20 > +/** >=20 > + Write REGBAR register. >=20 > + It programs REGBAR register and size in 8bytes. >=20 > + The Offset should not exceed 0xFFFF and must be aligned with size. >=20 > + >=20 > + @param[in] CpuSbDevicePid CPU SB Device Port ID >=20 > + @param[in] Offset Register offset of Port ID. >=20 > + @param[in] Data Input Data. Must be the same size as Size > parameter. >=20 > + >=20 > + @retval UINT64 Value written to register >=20 > +**/ >=20 > +UINT64 >=20 > +CpuRegbarWrite64 ( >=20 > + IN CPU_SB_DEVICE_PID CpuSbDevicePid, >=20 > + IN UINT16 Offset, >=20 > + IN UINT64 Data >=20 > + ); >=20 > + >=20 > + >=20 > +/** >=20 > + Write REGBAR register. >=20 > + It programs REGBAR register and size in 4bytes. >=20 > + The Offset should not exceed 0xFFFF and must be aligned with size. >=20 > + >=20 > + @param[in] CpuSbDevicePid CPU SB Device Port ID >=20 > + @param[in] Offset Register offset of Port ID. >=20 > + @param[in] Data Input Data. Must be the same size as Size > parameter. >=20 > + >=20 > + @retval UINT32 Value written to register >=20 > +**/ >=20 > +UINT32 >=20 > +CpuRegbarWrite32 ( >=20 > + IN CPU_SB_DEVICE_PID CpuSbDevicePid, >=20 > + IN UINT16 Offset, >=20 > + IN UINT32 Data >=20 > + ); >=20 > + >=20 > +/** >=20 > + Write REGBAR register. >=20 > + It programs REGBAR register and size in 2bytes. >=20 > + The Offset should not exceed 0xFFFF and must be aligned with size. >=20 > + >=20 > + @param[in] CpuSbDevicePid CPU SB Device Port ID >=20 > + @param[in] Offset Register offset of Port ID. >=20 > + @param[in] Data Input Data. Must be the same size as Size > parameter. >=20 > + >=20 > + @retval UINT16 Value written to register >=20 > +**/ >=20 > +UINT16 >=20 > +CpuRegbarWrite16 ( >=20 > + IN CPU_SB_DEVICE_PID CpuSbDevicePid, >=20 > + IN UINT16 Offset, >=20 > + IN UINT16 Data >=20 > + ); >=20 > + >=20 > +/** >=20 > + Write REGBAR register. >=20 > + It programs REGBAR register and size in 1bytes. >=20 > + The Offset should not exceed 0xFFFF and must be aligned with size. >=20 > + >=20 > + @param[in] CpuSbDevicePid CPU SB Device Port ID >=20 > + @param[in] Offset Register offset of Port ID. >=20 > + @param[in] Data Input Data. Must be the same size as Size > parameter. >=20 > + >=20 > + @retval UINT8 Value written to register >=20 > +**/ >=20 > +UINT8 >=20 > +CpuRegbarWrite8 ( >=20 > + IN CPU_SB_DEVICE_PID CpuSbDevicePid, >=20 > + IN UINT16 Offset, >=20 > + IN UINT8 Data >=20 > + ); >=20 > + >=20 > +/** >=20 > + Write REGBAR register. >=20 > + It programs REGBAR register and size in 4bytes. >=20 > + The Offset should not exceed 0xFFFF and must be aligned with size. >=20 > + >=20 > + @param[in] CpuSbDevicePid CPU SB Device Port ID >=20 > + @param[in] Offset Register offset of Port ID. >=20 > + @param[in] OrData OR Data. Must be the same size as Size > parameter. >=20 > + >=20 > + @retval UINT32 Value written to register >=20 > + >=20 > +**/ >=20 > +UINT32 >=20 > +CpuRegbarOr32 ( >=20 > + IN CPU_SB_DEVICE_PID CpuSbDevicePid, >=20 > + IN UINT16 Offset, >=20 > + IN UINT32 OrData >=20 > + ); >=20 > + >=20 > +/** >=20 > + Write REGBAR register. >=20 > + It programs REGBAR register and size in 2bytes. >=20 > + The Offset should not exceed 0xFFFF and must be aligned with size. >=20 > + >=20 > + @param[in] CpuSbDevicePid CPU SB Device Port ID >=20 > + @param[in] Offset Register offset of Port ID. >=20 > + @param[in] OrData OR Data. Must be the same size as Size > parameter. >=20 > + >=20 > + @retval UINT16 Value written to register >=20 > + >=20 > +**/ >=20 > +UINT16 >=20 > +CpuRegbarOr16 ( >=20 > + IN CPU_SB_DEVICE_PID CpuSbDevicePid, >=20 > + IN UINT16 Offset, >=20 > + IN UINT16 OrData >=20 > + ); >=20 > + >=20 > +/** >=20 > + Write REGBAR register. >=20 > + It programs REGBAR register and size in 1bytes. >=20 > + The Offset should not exceed 0xFFFF and must be aligned with size. >=20 > + >=20 > + @param[in] CpuSbDevicePid CPU SB Device Port ID >=20 > + @param[in] Offset Register offset of Port ID. >=20 > + @param[in] OrData OR Data. Must be the same size as Size > parameter. >=20 > + >=20 > + @retval UINT8 Value written to register >=20 > + >=20 > +**/ >=20 > +UINT8 >=20 > +CpuRegbarOr8 ( >=20 > + IN CPU_SB_DEVICE_PID CpuSbDevicePid, >=20 > + IN UINT16 Offset, >=20 > + IN UINT8 OrData >=20 > + ); >=20 > + >=20 > +/** >=20 > + Performs a bitwise AND of a 32-bit data. >=20 > + It programs REGBAR register and size in 4bytes. >=20 > + The Offset should not exceed 0xFFFF and must be aligned with size. >=20 > + >=20 > + @param[in] CpuSbDevice CPU SB Device >=20 > + @param[in] Offset Register offset of Port ID. >=20 > + @param[in] AndData And Data. Must be the same size as Size > parameter. >=20 > + >=20 > + @retval UINT32 Value written to register >=20 > + >=20 > +**/ >=20 > +UINT32 >=20 > +CpuRegbarAnd32 ( >=20 > + IN CPU_SB_DEVICE_PID CpuSbDevicePid, >=20 > + IN UINT16 Offset, >=20 > + IN UINT32 AndData >=20 > + ); >=20 > + >=20 > +/** >=20 > + Performs a bitwise AND of a 16-bit data. >=20 > + It programs REGBAR register and size in 2bytes. >=20 > + The Offset should not exceed 0xFFFF and must be aligned with size. >=20 > + >=20 > + @param[in] CpuSbDevice CPU SB Device >=20 > + @param[in] Offset Register offset of Port ID. >=20 > + @param[in] AndData And Data. Must be the same size as Size > parameter. >=20 > + >=20 > + @retval UINT16 Value written to register >=20 > + >=20 > +**/ >=20 > +UINT16 >=20 > +CpuRegbarAnd16 ( >=20 > + IN CPU_SB_DEVICE_PID CpuSbDevicePid, >=20 > + IN UINT16 Offset, >=20 > + IN UINT16 AndData >=20 > + ); >=20 > + >=20 > +/** >=20 > + Performs a bitwise AND of a 8-bit data. >=20 > + It programs REGBAR register and size in 1byte. >=20 > + The Offset should not exceed 0xFFFF and must be aligned with size. >=20 > + >=20 > + @param[in] CpuSbDevice CPU SB Device >=20 > + @param[in] Offset Register offset of Port ID. >=20 > + @param[in] AndData And Data. Must be the same size as Size > parameter. >=20 > + >=20 > + @retval UINT8 Value written to register >=20 > + >=20 > +**/ >=20 > +UINT8 >=20 > +CpuRegbarAnd8 ( >=20 > + IN CPU_SB_DEVICE_PID CpuSbDevicePid, >=20 > + IN UINT16 Offset, >=20 > + IN UINT8 AndData >=20 > + ); >=20 > +/** >=20 > + Write REGBAR register. >=20 > + It programs REGBAR register and size in 4bytes. >=20 > + The Offset should not exceed 0xFFFF and must be aligned with size. >=20 > + >=20 > + @param[in] CpuSbDevicePid CPU SB Device Port ID >=20 > + @param[in] Offset Register offset of Port ID. >=20 > + @param[in] AndData AND Data. Must be the same size as Size > parameter. >=20 > + @param[in] OrData OR Data. Must be the same size as Size > parameter. >=20 > + >=20 > + @retval UINT32 Value written to register >=20 > + >=20 > +**/ >=20 > +UINT32 >=20 > +CpuRegbarAndThenOr32 ( >=20 > + IN CPU_SB_DEVICE_PID CpuSbDevicePid, >=20 > + IN UINT16 Offset, >=20 > + IN UINT32 AndData, >=20 > + IN UINT32 OrData >=20 > + ); >=20 > + >=20 > +/** >=20 > + Write REGBAR register. >=20 > + It programs REGBAR register and size in 2bytes. >=20 > + The Offset should not exceed 0xFFFF and must be aligned with size. >=20 > + >=20 > + @param[in] CpuSbDevicePid CPU SB Device Port ID >=20 > + @param[in] Offset Register offset of Port ID. >=20 > + @param[in] AndData AND Data. Must be the same size as Size > parameter. >=20 > + @param[in] OrData OR Data. Must be the same size as Size > parameter. >=20 > + >=20 > + @retval UINT16 Value written to register >=20 > + >=20 > +**/ >=20 > +UINT16 >=20 > +CpuRegbarAndThenOr16 ( >=20 > + IN CPU_SB_DEVICE_PID CpuSbDevicePid, >=20 > + IN UINT16 Offset, >=20 > + IN UINT16 AndData, >=20 > + IN UINT16 OrData >=20 > + ); >=20 > + >=20 > +/** >=20 > + Write REGBAR register. >=20 > + It programs REGBAR register and size in 1bytes. >=20 > + The Offset should not exceed 0xFFFF and must be aligned with size. >=20 > + >=20 > + @param[in] CpuSbDevicePid CPU SB Device Port ID >=20 > + @param[in] Offset Register offset of Port ID. >=20 > + @param[in] AndData AND Data. Must be the same size as Size > parameter. >=20 > + @param[in] OrData OR Data. Must be the same size as Size > parameter. >=20 > + >=20 > + @retval UINT8 Value written to register >=20 > + >=20 > +**/ >=20 > +UINT8 >=20 > +CpuRegbarAndThenOr8 ( >=20 > + IN CPU_SB_DEVICE_PID CpuSbDevicePid, >=20 > + IN UINT16 Offset, >=20 > + IN UINT8 AndData, >=20 > + IN UINT8 OrData >=20 > + ); >=20 > + >=20 > +#endif >=20 > diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/DxeHdaNhlt= Lib.h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/DxeHdaNhltLib.h > new file mode 100644 > index 0000000000..c48ea3667f > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/DxeHdaNhltLib.h > @@ -0,0 +1,153 @@ > +/** @file >=20 > + Prototype of the DxePchHdaNhltLib library. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +#ifndef _DXE_HDA_NHLT_LIB_H_ >=20 > +#define _DXE_HDA_NHLT_LIB_H_ >=20 > + >=20 > +#include >=20 > + >=20 > +/** >=20 > + Returns pointer to Endpoint ENDPOINT_DESCRIPTOR structure. >=20 > + >=20 > + @param[in] *NhltTable Endpoint for which Format address is retrieve= d >=20 > + @param[in] FormatIndex Index of Format to be retrieved >=20 > + >=20 > + @retval Pointer to ENDPOINT_DESCRIPTOR structure with= given > index >=20 > +**/ >=20 > +ENDPOINT_DESCRIPTOR * >=20 > +GetNhltEndpoint ( >=20 > + IN CONST NHLT_ACPI_TABLE *NhltTable, >=20 > + IN CONST UINT8 EndpointIndex >=20 > + ); >=20 > + >=20 > +/** >=20 > + Returns pointer to Endpoint Specific Configuration SPECIFIC_CONFIG > structure. >=20 > + >=20 > + @param[in] *Endpoint Endpoint for which config address is retrieve= d >=20 > + >=20 > + @retval Pointer to SPECIFIC_CONFIG structure with end= point's > capabilities >=20 > +**/ >=20 > +SPECIFIC_CONFIG * >=20 > +GetNhltEndpointDeviceCapabilities ( >=20 > + IN CONST ENDPOINT_DESCRIPTOR *Endpoint >=20 > + ); >=20 > + >=20 > +/** >=20 > + Returns pointer to all Formats Configuration FORMATS_CONFIG structure. >=20 > + >=20 > + @param[in] *Endpoint Endpoint for which Formats address is retriev= ed >=20 > + >=20 > + @retval Pointer to FORMATS_CONFIG structure >=20 > +**/ >=20 > +FORMATS_CONFIG * >=20 > +GetNhltEndpointFormatsConfig ( >=20 > + IN CONST ENDPOINT_DESCRIPTOR *Endpoint >=20 > + ); >=20 > + >=20 > +/** >=20 > + Returns pointer to Format Configuration FORMAT_CONFIG structure. >=20 > + >=20 > + @param[in] *Endpoint Endpoint for which Format address is retrieve= d >=20 > + @param[in] FormatIndex Index of Format to be retrieved >=20 > + >=20 > + @retval Pointer to FORMAT_CONFIG structure with given= index >=20 > +**/ >=20 > +FORMAT_CONFIG * >=20 > +GetNhltEndpointFormat ( >=20 > + IN CONST ENDPOINT_DESCRIPTOR *Endpoint, >=20 > + IN CONST UINT8 FormatIndex >=20 > + ); >=20 > + >=20 > +/** >=20 > + Returns pointer to all Device Information DEVICES_INFO structure. >=20 > + >=20 > + @param[in] *Endpoint Endpoint for which DevicesInfo address is > retrieved >=20 > + >=20 > + @retval Pointer to DEVICES_INFO structure >=20 > +**/ >=20 > +DEVICES_INFO * >=20 > +GetNhltEndpointDevicesInfo ( >=20 > + IN CONST ENDPOINT_DESCRIPTOR *Endpoint >=20 > + ); >=20 > + >=20 > +/** >=20 > + Returns pointer to Device Information DEVICES_INFO structure. >=20 > + >=20 > + @param[in] *Endpoint Endpoint for which Device Info address is > retrieved >=20 > + @param[in] DeviceInfoIndex Index of Device Info to be retrieved >=20 > + >=20 > + @retval Pointer to DEVICE_INFO structure with given= index >=20 > +**/ >=20 > +DEVICE_INFO * >=20 > +GetNhltEndpointDeviceInfo ( >=20 > + IN CONST ENDPOINT_DESCRIPTOR *Endpoint, >=20 > + IN CONST UINT8 DeviceInfoIndex >=20 > + ); >=20 > + >=20 > + >=20 > +/** >=20 > + Returns pointer to OED Configuration SPECIFIC_CONFIG structure. >=20 > + >=20 > + @param[in] *NhltTable NHLT table for which OED address is retrieved >=20 > + >=20 > + @retval Pointer to SPECIFIC_CONFIG structure with NHL= T > capabilities >=20 > +**/ >=20 > +SPECIFIC_CONFIG * >=20 > +GetNhltOedConfig ( >=20 > + IN CONST NHLT_ACPI_TABLE *NhltTable >=20 > + ); >=20 > + >=20 > +/** >=20 > + Prints Format configuration. >=20 > + >=20 > + @param[in] *Format Format to be printed >=20 > + >=20 > + @retval None >=20 > +**/ >=20 > +VOID >=20 > +NhltFormatDump ( >=20 > + IN CONST FORMAT_CONFIG *Format >=20 > + ); >=20 > + >=20 > + >=20 > +/** >=20 > + Prints Endpoint configuration. >=20 > + >=20 > + @param[in] *Endpoint Endpoint to be printed >=20 > + >=20 > + @retval None >=20 > +**/ >=20 > +VOID >=20 > +NhltEndpointDump ( >=20 > + IN CONST ENDPOINT_DESCRIPTOR *Endpoint >=20 > + ); >=20 > + >=20 > +/** >=20 > + Prints OED (Offload Engine Driver) configuration. >=20 > + >=20 > + @param[in] *OedConfig OED to be printed >=20 > + >=20 > + @retval None >=20 > +**/ >=20 > +VOID >=20 > +NhltOedConfigDump ( >=20 > + IN CONST SPECIFIC_CONFIG *OedConfig >=20 > + ); >=20 > + >=20 > +/** >=20 > + Prints NHLT (Non HDA-Link Table) to be exposed via ACPI (aka. OED > (Offload Engine Driver) Configuration Table). >=20 > + >=20 > + @param[in] *NhltTable The NHLT table to print >=20 > + >=20 > + @retval None >=20 > +**/ >=20 > +VOID >=20 > +NhltAcpiTableDump ( >=20 > + IN NHLT_ACPI_TABLE *NhltTable >=20 > + ); >=20 > + >=20 > +#endif // _DXE_HDA_NHLT_LIB_H_ >=20 > diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/EspiLib.h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/EspiLib.h > new file mode 100644 > index 0000000000..6d8466ab7a > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/EspiLib.h > @@ -0,0 +1,140 @@ > +/** @file >=20 > + Header file for PchEspiLib. >=20 > + All function in this library is available for PEI, DXE, and SMM, >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +#ifndef _ESPI_LIB_H_ >=20 > +#define _ESPI_LIB_H_ >=20 > + >=20 > +/** >=20 > + Checks if there's second slave connected under CS#1 >=20 > + >=20 > + @retval TRUE There's second slave >=20 > + @retval FALSE There's no second slave >=20 > +**/ >=20 > +BOOLEAN >=20 > +IsEspiSecondSlaveSupported ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Checks in slave General Capabilities register if it supports channel w= ith > requested number >=20 > + >=20 > + @param[in] SlaveId Id of slave to check >=20 > + @param[in] ChannelNumber Number of channel of which to check >=20 > + >=20 > + @retval TRUE Channel with requested number is supported by slave > device >=20 > + @retval FALSE Channel with requested number is not supported by sl= ave > device >=20 > +**/ >=20 > +BOOLEAN >=20 > +IsEspiSlaveChannelSupported ( >=20 > + UINT8 SlaveId, >=20 > + UINT8 ChannelNumber >=20 > + ); >=20 > + >=20 > +/** >=20 > + Is eSPI enabled in strap. >=20 > + >=20 > + @retval TRUE Espi is enabled in strap >=20 > + @retval FALSE Espi is disabled in strap >=20 > +**/ >=20 > +BOOLEAN >=20 > +IsEspiEnabled ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Get configuration from eSPI slave >=20 > + >=20 > + @param[in] SlaveId eSPI slave ID >=20 > + @param[in] SlaveAddress Slave Configuration Register Address >=20 > + @param[out] OutData Configuration data read >=20 > + >=20 > + @retval EFI_SUCCESS Operation succeed >=20 > + @retval EFI_INVALID_PARAMETER Slave ID is not supported >=20 > + @retval EFI_INVALID_PARAMETER Slave ID is not supported or SlaveId 1 i= s > used in PchLp >=20 > + @retval EFI_INVALID_PARAMETER Slave configuration register address > exceed maximum allowed >=20 > + @retval EFI_INVALID_PARAMETER Slave configuration register address is > not DWord aligned >=20 > + @retval EFI_DEVICE_ERROR Error in SCRS during polling stage of > operation >=20 > +**/ >=20 > +EFI_STATUS >=20 > +PchEspiSlaveGetConfig ( >=20 > + IN UINT32 SlaveId, >=20 > + IN UINT32 SlaveAddress, >=20 > + OUT UINT32 *OutData >=20 > + ); >=20 > + >=20 > +/** >=20 > + Set eSPI slave configuration >=20 > + >=20 > + Note: A Set_Configuration must always be followed by a > Get_Configuration in order to ensure >=20 > + that the internal state of the eSPI-MC is consistent with the Slave's = register > settings. >=20 > + >=20 > + @param[in] SlaveId eSPI slave ID >=20 > + @param[in] SlaveAddress Slave Configuration Register Address >=20 > + @param[in] InData Configuration data to write >=20 > + >=20 > + @retval EFI_SUCCESS Operation succeed >=20 > + @retval EFI_INVALID_PARAMETER Slave ID is not supported or SlaveId 1 i= s > used in PchLp >=20 > + @retval EFI_INVALID_PARAMETER Slave configuration register address > exceed maximum allowed >=20 > + @retval EFI_INVALID_PARAMETER Slave configuration register address is > not DWord aligned >=20 > + @retval EFI_ACCESS_DENIED eSPI Slave write to address range 0 to > 0x7FF has been locked >=20 > + @retval EFI_DEVICE_ERROR Error in SCRS during polling stage of > operation >=20 > +**/ >=20 > +EFI_STATUS >=20 > +PchEspiSlaveSetConfig ( >=20 > + IN UINT32 SlaveId, >=20 > + IN UINT32 SlaveAddress, >=20 > + IN UINT32 InData >=20 > + ); >=20 > + >=20 > +/** >=20 > + Get status from eSPI slave >=20 > + >=20 > + @param[in] SlaveId eSPI slave ID >=20 > + @param[out] OutData Configuration data read >=20 > + >=20 > + @retval EFI_SUCCESS Operation succeed >=20 > + @retval EFI_INVALID_PARAMETER Slave ID is not supported or SlaveId 1 i= s > used in PchLp >=20 > + @retval EFI_DEVICE_ERROR Error in SCRS during polling stage of > operation >=20 > +**/ >=20 > +EFI_STATUS >=20 > +PchEspiSlaveGetStatus ( >=20 > + IN UINT32 SlaveId, >=20 > + OUT UINT16 *OutData >=20 > + ); >=20 > + >=20 > +/** >=20 > + eSPI slave in-band reset >=20 > + >=20 > + @param[in] SlaveId eSPI slave ID >=20 > + >=20 > + @retval EFI_SUCCESS Operation succeed >=20 > + @retval EFI_INVALID_PARAMETER Slave ID is not supported or SlaveId 1 i= s > used in PchLp >=20 > + @retval EFI_DEVICE_ERROR Error in SCRS during polling stage of > operation >=20 > +**/ >=20 > +EFI_STATUS >=20 > +PchEspiSlaveInBandReset ( >=20 > + IN UINT32 SlaveId >=20 > + ); >=20 > + >=20 > +/** >=20 > + eSPI Slave channel reset helper function >=20 > + >=20 > + @param[in] SlaveId eSPI slave ID >=20 > + @param[in] ChannelNumber Number of channel to reset >=20 > + >=20 > + @retval EFI_SUCCESS Operation succeeded >=20 > + @retval EFI_UNSUPPORTED Slave doesn't support that channel or > invalid number specified >=20 > + @retval EFI_TIMEOUT Operation has timeouted >=20 > +**/ >=20 > +EFI_STATUS >=20 > +PchEspiSlaveChannelReset ( >=20 > + IN UINT8 SlaveId, >=20 > + IN UINT8 ChannelNumber >=20 > + ); >=20 > + >=20 > +#endif // _ESPI_LIB_H_ >=20 > diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/GbeLib.h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/GbeLib.h > new file mode 100644 > index 0000000000..9d72b9ac7c > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/GbeLib.h > @@ -0,0 +1,63 @@ > +/** @file >=20 > + Header file for GbeLib. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _GBE_LIB_H_ >=20 > +#define _GBE_LIB_H_ >=20 > + >=20 > +/** >=20 > + Check whether GbE region is valid >=20 > + Check SPI region directly since GbE might be disabled in SW. >=20 > + >=20 > + @retval TRUE Gbe Region is valid >=20 > + @retval FALSE Gbe Region is invalid >=20 > +**/ >=20 > +BOOLEAN >=20 > +IsGbeRegionValid ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Check whether GBE controller is enabled in the platform. >=20 > + >=20 > + @retval TRUE GbE is enabled >=20 > + @retval FALSE GbE is disabled >=20 > +**/ >=20 > +BOOLEAN >=20 > +IsGbePresent ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Checks if Gbe is Enabled or Disabled >=20 > + >=20 > + @retval BOOLEAN TRUE if device is enabled, FALSE otherwise. >=20 > +**/ >=20 > +BOOLEAN >=20 > +IsGbeEnabled ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Returns Gigabit Ethernet PCI Device Number >=20 > + >=20 > + @retval GbE device number >=20 > +**/ >=20 > +UINT8 >=20 > +GbeDevNumber ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Returns Gigabit Ethernet PCI Function Number >=20 > + >=20 > + @retval GbE function number >=20 > +**/ >=20 > +UINT8 >=20 > +GbeFuncNumber ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +#endif // _GBE_LIB_H_ >=20 > diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/GpioConfig= .h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/GpioConfig.h > new file mode 100644 > index 0000000000..88a21efb32 > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/GpioConfig.h > @@ -0,0 +1,342 @@ > +/** @file >=20 > + Header file for GpioConfig structure used by GPIO library. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _GPIO_CONFIG_H_ >=20 > +#define _GPIO_CONFIG_H_ >=20 > + >=20 > +#pragma pack(push, 1) >=20 > + >=20 > +/// >=20 > +/// For any GpioPad usage in code use GPIO_PAD type >=20 > +/// >=20 > +typedef UINT32 GPIO_PAD; >=20 > + >=20 > +/// >=20 > +/// GpioPad with additional native function information. >=20 > +/// This type is used to represent signal muxing alternatives. Platform = will > provide such value to >=20 > +/// identify muxing selection for given signal on a specific SOC. >=20 > +/// Please refer to the board layout >=20 > +/// >=20 > +typedef UINT32 GPIO_NATIVE_PAD; >=20 > + >=20 > + >=20 > +/// >=20 > +/// For any GpioGroup usage in code use GPIO_GROUP type >=20 > +/// >=20 > +typedef UINT32 GPIO_GROUP; >=20 > + >=20 > +/** >=20 > + GPIO configuration structure used for pin programming. >=20 > + Structure contains fields that can be used to configure pad. >=20 > +**/ >=20 > +typedef struct { >=20 > + /** >=20 > + Pad Mode >=20 > + Pad can be set as GPIO or one of its native functions. >=20 > + When in native mode setting Direction (except Inversion), OutputState, >=20 > + InterruptConfig, Host Software Pad Ownership and OutputStateLock are > unnecessary. >=20 > + Refer to definition of GPIO_PAD_MODE. >=20 > + Refer to EDS for each native mode according to the pad. >=20 > + **/ >=20 > + UINT32 PadMode : 5; >=20 > + /** >=20 > + Host Software Pad Ownership >=20 > + Set pad to ACPI mode or GPIO Driver Mode. >=20 > + Refer to definition of GPIO_HOSTSW_OWN. >=20 > + **/ >=20 > + UINT32 HostSoftPadOwn : 2; >=20 > + /** >=20 > + GPIO Direction >=20 > + Can choose between In, In with inversion, Out, both In and Out, both I= n > with inversion and out or disabling both. >=20 > + Refer to definition of GPIO_DIRECTION for supported settings. >=20 > + **/ >=20 > + UINT32 Direction : 6; >=20 > + /** >=20 > + Output State >=20 > + Set Pad output value. >=20 > + Refer to definition of GPIO_OUTPUT_STATE for supported settings. >=20 > + This setting takes place when output is enabled. >=20 > + **/ >=20 > + UINT32 OutputState : 2; >=20 > + /** >=20 > + GPIO Interrupt Configuration >=20 > + Set Pad to cause one of interrupts (IOxAPIC/SCI/SMI/NMI). >=20 > + This setting is applicable only if GPIO is in GpioMode with input enab= led. >=20 > + Refer to definition of GPIO_INT_CONFIG for supported settings. >=20 > + **/ >=20 > + UINT32 InterruptConfig : 9; >=20 > + /** >=20 > + GPIO Power Configuration. >=20 > + This setting controls Pad Reset Configuration. >=20 > + Refer to definition of GPIO_RESET_CONFIG for supported settings. >=20 > + **/ >=20 > + UINT32 PowerConfig : 8; >=20 > + /** >=20 > + GPIO Electrical Configuration >=20 > + This setting controls pads termination. >=20 > + Refer to definition of GPIO_ELECTRICAL_CONFIG for supported settings. >=20 > + **/ >=20 > + UINT32 ElectricalConfig : 9; >=20 > + /** >=20 > + GPIO Lock Configuration >=20 > + This setting controls pads lock. >=20 > + Refer to definition of GPIO_LOCK_CONFIG for supported settings. >=20 > + **/ >=20 > + UINT32 LockConfig : 4; >=20 > + /** >=20 > + Additional GPIO configuration >=20 > + Refer to definition of GPIO_OTHER_CONFIG for supported settings. >=20 > + **/ >=20 > + UINT32 OtherSettings : 9; >=20 > + >=20 > + UINT32 RsvdBits : 10; ///< Reserved bits for future exten= sion >=20 > +} GPIO_CONFIG; >=20 > + >=20 > + >=20 > +typedef enum { >=20 > + GpioHardwareDefault =3D 0x0 ///< Leave setting unmodified >=20 > +} GPIO_HARDWARE_DEFAULT; >=20 > + >=20 > +/** >=20 > + GPIO Pad Mode >=20 > + Refer to GPIO documentation on native functions available for certain = pad. >=20 > + If GPIO is set to one of NativeX modes then following settings are not > applicable >=20 > + and can be skipped: >=20 > + - Interrupt related settings >=20 > + - Host Software Ownership >=20 > + - Output/Input enabling/disabling >=20 > + - Output lock >=20 > +**/ >=20 > +typedef enum { >=20 > + GpioPadModeHwDefault =3D 0x0, >=20 > + GpioPadModeGpio =3D 0x1, >=20 > + GpioPadModeNative1 =3D 0x3, >=20 > + GpioPadModeNative2 =3D 0x5, >=20 > + GpioPadModeNative3 =3D 0x7, >=20 > + GpioPadModeNative4 =3D 0x9, >=20 > + GpioPadModeNative5 =3D 0xB, >=20 > + GpioPadModeNative6 =3D 0xD, >=20 > + GpioPadModeNative7 =3D 0xF >=20 > +} GPIO_PAD_MODE; >=20 > + >=20 > +/** >=20 > + Host Software Pad Ownership modes >=20 > + This setting affects GPIO interrupt status registers. Depending on cho= sen > ownership >=20 > + some GPIO Interrupt status register get updated and other masked. >=20 > + Please refer to EDS for HOSTSW_OWN register description. >=20 > +**/ >=20 > +typedef enum { >=20 > + GpioHostOwnDefault =3D 0x0, ///< Leave ownership value unmodified >=20 > + /** >=20 > + Set HOST ownership to ACPI. >=20 > + Use this setting if pad is not going to be used by GPIO OS driver. >=20 > + If GPIO is configured to generate SCI/SMI/NMI then this setting must b= e >=20 > + used for interrupts to work >=20 > + **/ >=20 > + GpioHostOwnAcpi =3D 0x1, >=20 > + /** >=20 > + Set HOST ownership to GPIO Driver mode. >=20 > + Use this setting only if GPIO pad should be controlled by GPIO OS Driv= er. >=20 > + GPIO OS Driver will be able to control the pad if appropriate entry in >=20 > + ACPI exists (refer to ACPI specification for GpioIo and GpioInt descri= ptors) >=20 > + **/ >=20 > + GpioHostOwnGpio =3D 0x3 >=20 > +} GPIO_HOSTSW_OWN; >=20 > + >=20 > +/// >=20 > +/// GPIO Direction >=20 > +/// >=20 > +typedef enum { >=20 > + GpioDirDefault =3D 0x0, ///< Leave pad directio= n setting > unmodified >=20 > + GpioDirInOut =3D (0x1 | (0x1 << 3)), ///< Set pad for both o= utput and > input >=20 > + GpioDirInInvOut =3D (0x1 | (0x3 << 3)), ///< Set pad for both o= utput and > input with inversion >=20 > + GpioDirIn =3D (0x3 | (0x1 << 3)), ///< Set pad for input = only >=20 > + GpioDirInInv =3D (0x3 | (0x3 << 3)), ///< Set pad for input = with inversion >=20 > + GpioDirOut =3D 0x5, ///< Set pad for output= only >=20 > + GpioDirNone =3D 0x7 ///< Disable both outpu= t and input >=20 > +} GPIO_DIRECTION; >=20 > + >=20 > +/** >=20 > + GPIO Output State >=20 > + This field is relevant only if output is enabled >=20 > +**/ >=20 > +typedef enum { >=20 > + GpioOutDefault =3D 0x0, ///< Leave output value unmodified >=20 > + GpioOutLow =3D 0x1, ///< Set output to low >=20 > + GpioOutHigh =3D 0x3 ///< Set output to high >=20 > +} GPIO_OUTPUT_STATE; >=20 > + >=20 > +/** >=20 > + GPIO interrupt configuration >=20 > + This setting is applicable only if pad is in GPIO mode and has input e= nabled. >=20 > + GPIO_INT_CONFIG allows to choose which interrupt is generated > (IOxAPIC/SCI/SMI/NMI) >=20 > + and how it is triggered (edge or level). Refer to PADCFG_DW0 register > description in >=20 > + EDS for details on this settings. >=20 > + Field from GpioIntNmi to GpioIntApic can be OR'ed with GpioIntLevel to > GpioIntBothEdge >=20 > + to describe an interrupt e.g. GpioIntApic | GpioIntLevel >=20 > + If GPIO is set to cause an SCI then also GPI_GPE_EN is enabled for thi= s pad. >=20 > + If GPIO is set to cause an NMI then also GPI_NMI_EN is enabled for thi= s > pad. >=20 > + Not all GPIO are capable of generating an SMI or NMI interrupt. >=20 > + When routing GPIO to cause an IOxAPIC interrupt care must be taken, as > this >=20 > + interrupt cannot be shared and its IRQn number is not configurable. >=20 > + Refer to EDS for GPIO pads IRQ numbers (PADCFG_DW1.IntSel) >=20 > + If GPIO is under GPIO OS driver control and appropriate ACPI GpioInt > descriptor >=20 > + exist then use only trigger type setting (from GpioIntLevel to > GpioIntBothEdge). >=20 > + This type of GPIO Driver interrupt doesn't have any additional routing > setting >=20 > + required to be set by BIOS. Interrupt is handled by GPIO OS Driver. >=20 > +**/ >=20 > + >=20 > +typedef enum { >=20 > + GpioIntDefault =3D 0x0, ///< Leave value of interrupt routi= ng > unmodified >=20 > + GpioIntDis =3D 0x1, ///< Disable IOxAPIC/SCI/SMI/NMI in= terrupt > generation >=20 > + GpioIntNmi =3D 0x3, ///< Enable NMI interrupt only >=20 > + GpioIntSmi =3D 0x5, ///< Enable SMI interrupt only >=20 > + GpioIntSci =3D 0x9, ///< Enable SCI interrupt only >=20 > + GpioIntApic =3D 0x11, ///< Enable IOxAPIC interrupt only >=20 > + GpioIntLevel =3D (0x1 << 5), ///< Set interrupt as level trigger= ed >=20 > + GpioIntEdge =3D (0x3 << 5), ///< Set interrupt as edge triggere= d (type of > edge depends on input inversion) >=20 > + GpioIntLvlEdgDis =3D (0x5 << 5), ///< Disable interrupt trigger >=20 > + GpioIntBothEdge =3D (0x7 << 5) ///< Set interrupt as both edge tri= ggered >=20 > +} GPIO_INT_CONFIG; >=20 > + >=20 > +#define B_GPIO_INT_CONFIG_INT_SOURCE_MASK 0x1F ///< Mask for > GPIO_INT_CONFIG for interrupt source >=20 > +#define B_GPIO_INT_CONFIG_INT_TYPE_MASK 0xE0 ///< Mask for > GPIO_INT_CONFIG for interrupt type >=20 > + >=20 > +/** >=20 > + GPIO Power Configuration >=20 > + GPIO_RESET_CONFIG allows to set GPIO Reset type > (PADCFG_DW0.PadRstCfg) which will >=20 > + be used to reset certain GPIO settings. >=20 > + Refer to EDS for settings that are controllable by PadRstCfg. >=20 > +**/ >=20 > +typedef enum { >=20 > + GpioResetDefault =3D 0x00, ///< Leave value of pad reset unmo= dified >=20 > + /** >=20 > + Resume Reset (RSMRST) >=20 > + GPP: PadRstCfg =3D 00b =3D "Powergood" >=20 > + GPD: PadRstCfg =3D 11b =3D "Resume Reset" >=20 > + Pad setting will reset on: >=20 > + - DeepSx transition >=20 > + - G3 >=20 > + Pad settings will not reset on: >=20 > + - S3/S4/S5 transition >=20 > + - Warm/Cold/Global reset >=20 > + **/ >=20 > + GpioResumeReset =3D 0x01, >=20 > + /** >=20 > + Host Deep Reset >=20 > + PadRstCfg =3D 01b =3D "Deep GPIO Reset" >=20 > + Pad settings will reset on: >=20 > + - Warm/Cold/Global reset >=20 > + - DeepSx transition >=20 > + - G3 >=20 > + Pad settings will not reset on: >=20 > + - S3/S4/S5 transition >=20 > + **/ >=20 > + GpioHostDeepReset =3D 0x03, >=20 > + /** >=20 > + Platform Reset (PLTRST) >=20 > + PadRstCfg =3D 10b =3D "GPIO Reset" >=20 > + Pad settings will reset on: >=20 > + - S3/S4/S5 transition >=20 > + - Warm/Cold/Global reset >=20 > + - DeepSx transition >=20 > + - G3 >=20 > + **/ >=20 > + GpioPlatformReset =3D 0x05, >=20 > + /** >=20 > + Deep Sleep Well Reset (DSW_PWROK) >=20 > + GPP: not applicable >=20 > + GPD: PadRstCfg =3D 00b =3D "Powergood" >=20 > + Pad settings will reset on: >=20 > + - G3 >=20 > + Pad settings will not reset on: >=20 > + - S3/S4/S5 transition >=20 > + - Warm/Cold/Global reset >=20 > + - DeepSx transition >=20 > + **/ >=20 > + GpioDswReset =3D 0x07 >=20 > +} GPIO_RESET_CONFIG; >=20 > + >=20 > +/** >=20 > + GPIO Electrical Configuration >=20 > + Configuration options for GPIO termination setting >=20 > +**/ >=20 > +typedef enum { >=20 > + GpioTermDefault =3D 0x0, ///< Leave termination setting unmo= dified >=20 > + GpioTermNone =3D 0x1, ///< none >=20 > + GpioTermWpd5K =3D 0x5, ///< 5kOhm weak pull-down >=20 > + GpioTermWpd20K =3D 0x9, ///< 20kOhm weak pull-down >=20 > + GpioTermWpu1K =3D 0x13, ///< 1kOhm weak pull-up >=20 > + GpioTermWpu2K =3D 0x17, ///< 2kOhm weak pull-up >=20 > + GpioTermWpu5K =3D 0x15, ///< 5kOhm weak pull-up >=20 > + GpioTermWpu20K =3D 0x19, ///< 20kOhm weak pull-up >=20 > + GpioTermWpu1K2K =3D 0x1B, ///< 1kOhm & 2kOhm weak pull-up >=20 > + /** >=20 > + Native function controls pads termination >=20 > + This setting is applicable only to some native modes. >=20 > + Please check EDS to determine which native functionality >=20 > + can control pads termination >=20 > + **/ >=20 > + GpioTermNative =3D 0x1F >=20 > +} GPIO_ELECTRICAL_CONFIG; >=20 > + >=20 > +#define B_GPIO_ELECTRICAL_CONFIG_TERMINATION_MASK 0x1F ///< > Mask for GPIO_ELECTRICAL_CONFIG for termination value >=20 > + >=20 > +/** >=20 > + GPIO LockConfiguration >=20 > + Set GPIO configuration lock and output state lock. >=20 > + GpioPadConfigUnlock/Lock and GpioOutputStateUnlock can be OR'ed. >=20 > + By default GPIO pads will be locked unless GPIO lib is explicitly >=20 > + informed that certain pad is to be left unlocked. >=20 > + Lock settings reset is in Powergood domain. Care must be taken when > using this setting >=20 > + as fields it locks may be reset by a different signal and can be contr= olled >=20 > + by what is in GPIO_RESET_CONFIG (PADCFG_DW0.PadRstCfg). GPIO > library provides >=20 > + functions which allow to unlock a GPIO pad. If possible each GPIO lib > function will try to unlock >=20 > + an already locked pad upon request for reconfiguration >=20 > +**/ >=20 > +typedef enum { >=20 > + /** >=20 > + Perform default action >=20 > + - if pad is an GPO, lock configuration but leave output unlocked >=20 > + - if pad is an GPI, lock everything >=20 > + - if pad is in native, lock everything >=20 > +**/ >=20 > + GpioLockDefault =3D 0x0, >=20 > + GpioPadConfigUnlock =3D 0x3, ///< Leave Pad configuration unlocke= d >=20 > + GpioPadConfigLock =3D 0x1, ///< Lock Pad configuration >=20 > + GpioOutputStateUnlock =3D 0xC, ///< Leave Pad output control unlock= ed >=20 > + GpioPadUnlock =3D 0xF, ///< Leave both Pad configuration an= d output > control unlocked >=20 > + GpioPadLock =3D 0x5, ///< Lock both Pad configuration and= output > control >=20 > + /** >=20 > + Below statuses are used for >=20 > + return from GpioGetPadConfig function >=20 > + **/ >=20 > + GpioLockTxLockCfgUnLock =3D 0x7, ///< Tx State locked, Pad Configurat= ion > unlocked >=20 > + GpioLockTxUnLockCfgLock =3D 0xD ///< Tx State unlocked, Pad > Configuration locked >=20 > +} GPIO_LOCK_CONFIG; >=20 > + >=20 > +#define B_GPIO_LOCK_CONFIG_PAD_CONF_LOCK_MASK 0x3 ///< Mask > for GPIO_LOCK_CONFIG for Pad Configuration Lock >=20 > +#define B_GPIO_LOCK_CONFIG_OUTPUT_LOCK_MASK 0xC ///< Mask > for GPIO_LOCK_CONFIG for Pad Output Lock >=20 > + >=20 > +/** >=20 > + Other GPIO Configuration >=20 > + GPIO_OTHER_CONFIG is used for less often settings and for future > extensions >=20 > + Supported settings: >=20 > + - RX raw override to '1' - allows to override input value to '1' >=20 > + This setting is applicable only if in input mode (both in GPIO and= native > usage). >=20 > + The override takes place at the internal pad state directly from b= uffer > and before the RXINV. >=20 > +**/ >=20 > +typedef enum { >=20 > + GpioRxRaw1Default =3D 0x0, ///< Use default input override = value >=20 > + GpioRxRaw1Dis =3D 0x1, ///< Don't override input >=20 > + GpioRxRaw1En =3D 0x3 ///< Override input to '1' >=20 > +} GPIO_OTHER_CONFIG; >=20 > + >=20 > +#define B_GPIO_OTHER_CONFIG_RXRAW_MASK 0x3 ///< Mask for > GPIO_OTHER_CONFIG for RxRaw1 setting >=20 > + >=20 > +#pragma pack(pop) >=20 > + >=20 > +#endif //_GPIO_CONFIG_H_ >=20 > diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/GpioLib.h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/GpioLib.h > new file mode 100644 > index 0000000000..5b3cf502a0 > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/GpioLib.h > @@ -0,0 +1,720 @@ > +/** @file >=20 > + Header file for GpioLib. >=20 > + All function in this library is available for PEI, DXE, and SMM >=20 > + >=20 > + @note: When GPIO pads are owned by ME Firmware, BIOS/host should > not >=20 > + attempt to access these GPIO Pads registers, registers value >=20 > + returned in this case will be 0xFF. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _GPIO_LIB_H_ >=20 > +#define _GPIO_LIB_H_ >=20 > + >=20 > +#include >=20 > + >=20 > +#define GPIO_NAME_LENGTH_MAX 32 >=20 > + >=20 > +typedef struct { >=20 > + GPIO_PAD GpioPad; >=20 > + GPIO_CONFIG GpioConfig; >=20 > +} GPIO_INIT_CONFIG; >=20 > + >=20 > +/** >=20 > + This procedure will initialize multiple GPIO pins. Use GPIO_INIT_CONFI= G > structure. >=20 > + Structure contains fields that can be used to configure each pad. >=20 > + Pad not configured using GPIO_INIT_CONFIG will be left with hardware > default values. >=20 > + Separate fields could be set to hardware default if it does not matter= , > except >=20 > + GpioPad and PadMode. >=20 > + Function will work in most efficient way if pads which belong to the s= ame > group are >=20 > + placed in adjacent records of the table. >=20 > + Although function can enable pads for Native mode, such programming is > done >=20 > + by reference code when enabling related silicon feature. >=20 > + >=20 > + @param[in] NumberofItem Number of GPIO pads to be update= d >=20 > + @param[in] GpioInitTableAddress GPIO initialization table >=20 > + >=20 > + @retval EFI_SUCCESS The function completed successfu= lly >=20 > + @retval EFI_INVALID_PARAMETER Invalid group or pad number >=20 > +**/ >=20 > +EFI_STATUS >=20 > +GpioConfigurePads ( >=20 > + IN UINT32 NumberOfItems, >=20 > + IN GPIO_INIT_CONFIG *GpioInitTableAddress >=20 > + ); >=20 > + >=20 > +// >=20 > +// Functions for setting/getting multiple GpioPad settings >=20 > +// >=20 > + >=20 > +/** >=20 > + This procedure will read multiple GPIO settings >=20 > + >=20 > + @param[in] GpioPad GPIO Pad >=20 > + @param[out] GpioData GPIO data structure >=20 > + >=20 > + @retval EFI_SUCCESS The function completed successfu= lly >=20 > + @retval EFI_INVALID_PARAMETER Invalid GpioPad >=20 > +**/ >=20 > +EFI_STATUS >=20 > +GpioGetPadConfig ( >=20 > + IN GPIO_PAD GpioPad, >=20 > + OUT GPIO_CONFIG *GpioData >=20 > + ); >=20 > + >=20 > +/** >=20 > + This procedure will configure multiple GPIO settings >=20 > + >=20 > + @param[in] GpioPad GPIO Pad >=20 > + @param[in] GpioData GPIO data structure >=20 > + >=20 > + @retval EFI_SUCCESS The function completed successfu= lly >=20 > + @retval EFI_INVALID_PARAMETER Invalid GpioPad >=20 > +**/ >=20 > +EFI_STATUS >=20 > +GpioSetPadConfig ( >=20 > + IN GPIO_PAD GpioPad, >=20 > + IN GPIO_CONFIG *GpioData >=20 > + ); >=20 > + >=20 > +// >=20 > +// Functions for setting/getting single GpioPad properties >=20 > +// >=20 > + >=20 > +/** >=20 > + This procedure will set GPIO output level >=20 > + >=20 > + @param[in] GpioPad GPIO pad >=20 > + @param[in] Value Output value >=20 > + 0: OutputLow, 1: OutputHigh >=20 > + >=20 > + @retval EFI_SUCCESS The function completed successfully >=20 > + @retval EFI_INVALID_PARAMETER Invalid GpioPad >=20 > +**/ >=20 > +EFI_STATUS >=20 > +GpioSetOutputValue ( >=20 > + IN GPIO_PAD GpioPad, >=20 > + IN UINT32 Value >=20 > + ); >=20 > + >=20 > +/** >=20 > + This procedure will get GPIO output level >=20 > + >=20 > + @param[in] GpioPad GPIO pad >=20 > + @param[out] OutputVal GPIO Output value >=20 > + 0: OutputLow, 1: OutputHigh >=20 > + >=20 > + @retval EFI_SUCCESS The function completed successfully >=20 > + @retval EFI_INVALID_PARAMETER Invalid GpioPad >=20 > +**/ >=20 > +EFI_STATUS >=20 > +GpioGetOutputValue ( >=20 > + IN GPIO_PAD GpioPad, >=20 > + OUT UINT32 *OutputVal >=20 > + ); >=20 > + >=20 > +/** >=20 > + This procedure will get GPIO input level >=20 > + >=20 > + @param[in] GpioPad GPIO pad >=20 > + @param[out] InputVal GPIO Input value >=20 > + 0: InputLow, 1: InputHigh >=20 > + >=20 > + @retval EFI_SUCCESS The function completed successfully >=20 > + @retval EFI_INVALID_PARAMETER Invalid GpioPad >=20 > +**/ >=20 > +EFI_STATUS >=20 > +GpioGetInputValue ( >=20 > + IN GPIO_PAD GpioPad, >=20 > + OUT UINT32 *InputVal >=20 > + ); >=20 > + >=20 > +/** >=20 > + This procedure will get GPIO IOxAPIC interrupt number >=20 > + >=20 > + @param[in] GpioPad GPIO pad >=20 > + @param[out] IrqNum IRQ number >=20 > + >=20 > + @retval EFI_SUCCESS The function completed successfully >=20 > + @retval EFI_INVALID_PARAMETER Invalid GpioPad >=20 > +**/ >=20 > +EFI_STATUS >=20 > +GpioGetPadIoApicIrqNumber ( >=20 > + IN GPIO_PAD GpioPad, >=20 > + OUT UINT32 *IrqNum >=20 > + ); >=20 > + >=20 > +/** >=20 > + This procedure will configure GPIO input inversion >=20 > + >=20 > + @param[in] GpioPad GPIO pad >=20 > + @param[in] Value Value for GPIO input inversion >=20 > + 0: No input inversion, 1: Invert input >=20 > + >=20 > + @retval EFI_SUCCESS The function completed successfully >=20 > + @retval EFI_INVALID_PARAMETER Invalid GpioPad >=20 > +**/ >=20 > +EFI_STATUS >=20 > +GpioSetInputInversion ( >=20 > + IN GPIO_PAD GpioPad, >=20 > + IN UINT32 Value >=20 > + ); >=20 > + >=20 > +/** >=20 > + This procedure will get GPIO pad input inversion value >=20 > + >=20 > + @param[in] GpioPad GPIO pad >=20 > + @param[out] InvertState GPIO inversion state >=20 > + 0: No input inversion, 1: Inverted inp= ut >=20 > + >=20 > + @retval EFI_SUCCESS The function completed successfully >=20 > + @retval EFI_INVALID_PARAMETER Invalid GpioPad >=20 > +**/ >=20 > +EFI_STATUS >=20 > +GpioGetInputInversion ( >=20 > + IN GPIO_PAD GpioPad, >=20 > + OUT UINT32 *InvertState >=20 > + ); >=20 > + >=20 > +/** >=20 > + This procedure will set GPIO interrupt settings >=20 > + >=20 > + @param[in] GpioPad GPIO pad >=20 > + @param[in] Value Value of Level/Edge >=20 > + use GPIO_INT_CONFIG as argument >=20 > + >=20 > + @retval EFI_SUCCESS The function completed successfully >=20 > + @retval EFI_INVALID_PARAMETER Invalid GpioPad >=20 > +**/ >=20 > +EFI_STATUS >=20 > +GpioSetPadInterruptConfig ( >=20 > + IN GPIO_PAD GpioPad, >=20 > + IN GPIO_INT_CONFIG Value >=20 > + ); >=20 > + >=20 > +/** >=20 > + This procedure will set GPIO electrical settings >=20 > + >=20 > + @param[in] GpioPad GPIO pad >=20 > + @param[in] Value Value of termination >=20 > + use GPIO_ELECTRICAL_CONFIG as argument >=20 > + >=20 > + @retval EFI_SUCCESS The function completed successfully >=20 > + @retval EFI_INVALID_PARAMETER Invalid GpioPad >=20 > +**/ >=20 > +EFI_STATUS >=20 > +GpioSetPadElectricalConfig ( >=20 > + IN GPIO_PAD GpioPad, >=20 > + IN GPIO_ELECTRICAL_CONFIG Value >=20 > + ); >=20 > + >=20 > +/** >=20 > + This procedure will set GPIO Reset settings >=20 > + >=20 > + @param[in] GpioPad GPIO pad >=20 > + @param[in] Value Value for Pad Reset Configuration >=20 > + use GPIO_RESET_CONFIG as argument >=20 > + >=20 > + @retval EFI_SUCCESS The function completed successfully >=20 > + @retval EFI_INVALID_PARAMETER Invalid GpioPad >=20 > +**/ >=20 > +EFI_STATUS >=20 > +GpioSetPadResetConfig ( >=20 > + IN GPIO_PAD GpioPad, >=20 > + IN GPIO_RESET_CONFIG Value >=20 > + ); >=20 > + >=20 > +/** >=20 > + This procedure will get GPIO Reset settings >=20 > + >=20 > + @param[in] GpioPad GPIO pad >=20 > + @param[in] Value Value of Pad Reset Configuration >=20 > + based on GPIO_RESET_CONFIG >=20 > + >=20 > + @retval EFI_SUCCESS The function completed successfully >=20 > + @retval EFI_INVALID_PARAMETER Invalid GpioPad >=20 > +**/ >=20 > +EFI_STATUS >=20 > +GpioGetPadResetConfig ( >=20 > + IN GPIO_PAD GpioPad, >=20 > + IN GPIO_RESET_CONFIG *Value >=20 > + ); >=20 > + >=20 > +/** >=20 > + This procedure will get Gpio Pad Host Software Ownership >=20 > + >=20 > + @param[in] GpioPad GPIO pad >=20 > + @param[out] PadHostSwOwn Value of Host Software Pad Owner >=20 > + 0: ACPI Mode, 1: GPIO Driver mode >=20 > + >=20 > + @retval EFI_SUCCESS The function completed successfully >=20 > + @retval EFI_INVALID_PARAMETER Invalid GpioPad >=20 > +**/ >=20 > +EFI_STATUS >=20 > +GpioGetHostSwOwnershipForPad ( >=20 > + IN GPIO_PAD GpioPad, >=20 > + OUT UINT32 *PadHostSwOwn >=20 > + ); >=20 > + >=20 > +/** >=20 > + This procedure will set Gpio Pad Host Software Ownership >=20 > + >=20 > + @param[in] GpioPad GPIO pad >=20 > + @param[in] PadHostSwOwn Pad Host Software Owner >=20 > + 0: ACPI Mode, 1: GPIO Driver mode >=20 > + >=20 > + @retval EFI_SUCCESS The function completed successfully >=20 > + @retval EFI_INVALID_PARAMETER Invalid GpioPad >=20 > +**/ >=20 > +EFI_STATUS >=20 > +GpioSetHostSwOwnershipForPad ( >=20 > + IN GPIO_PAD GpioPad, >=20 > + IN UINT32 PadHostSwOwn >=20 > + ); >=20 > + >=20 > +/// >=20 > +/// Possible values of Pad Ownership >=20 > +/// If Pad is not under Host ownership then GPIO registers >=20 > +/// are not accessible by host (e.g. BIOS) and reading them >=20 > +/// will return 0xFFs. >=20 > +/// >=20 > +typedef enum { >=20 > + GpioPadOwnHost =3D 0x0, >=20 > + GpioPadOwnCsme =3D 0x1, >=20 > + GpioPadOwnIsh =3D 0x2, >=20 > +} GPIO_PAD_OWN; >=20 > + >=20 > +/** >=20 > + This procedure will get Gpio Pad Ownership >=20 > + >=20 > + @param[in] GpioPad GPIO pad >=20 > + @param[out] PadOwnVal Value of Pad Ownership >=20 > + >=20 > + @retval EFI_SUCCESS The function completed successfully >=20 > + @retval EFI_INVALID_PARAMETER Invalid GpioPad >=20 > +**/ >=20 > +EFI_STATUS >=20 > +GpioGetPadOwnership ( >=20 > + IN GPIO_PAD GpioPad, >=20 > + OUT GPIO_PAD_OWN *PadOwnVal >=20 > + ); >=20 > + >=20 > +/** >=20 > + This procedure will check state of Pad Config Lock for pads within one > group >=20 > + >=20 > + @param[in] Group GPIO group >=20 > + @param[in] DwNum PadCfgLock register number for current > group. >=20 > + For group which has less then 32 pads = per group DwNum > must be 0. >=20 > + @param[out] PadCfgLockRegVal Value of PadCfgLock register >=20 > + Bit position - PadNumber >=20 > + Bit value - 0: NotLocked, 1: Locked >=20 > + >=20 > + @retval EFI_SUCCESS The function completed successfully >=20 > + @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter > number >=20 > +**/ >=20 > +EFI_STATUS >=20 > +GpioGetPadCfgLockForGroupDw ( >=20 > + IN GPIO_GROUP Group, >=20 > + IN UINT32 DwNum, >=20 > + OUT UINT32 *PadCfgLockRegVal >=20 > + ); >=20 > + >=20 > +/** >=20 > + This procedure will check state of Pad Config Lock for selected pad >=20 > + >=20 > + @param[in] GpioPad GPIO pad >=20 > + @param[out] PadCfgLock PadCfgLock for selected pad >=20 > + 0: NotLocked, 1: Locked >=20 > + >=20 > + @retval EFI_SUCCESS The function completed successfully >=20 > + @retval EFI_INVALID_PARAMETER Invalid GpioPad >=20 > +**/ >=20 > +EFI_STATUS >=20 > +GpioGetPadCfgLock ( >=20 > + IN GPIO_PAD GpioPad, >=20 > + OUT UINT32 *PadCfgLock >=20 > + ); >=20 > + >=20 > +/** >=20 > + This procedure will check state of Pad Config Tx Lock for pads within = one > group >=20 > + >=20 > + @param[in] Group GPIO group >=20 > + @param[in] DwNum PadCfgLockTx register number for curre= nt > group. >=20 > + For group which has less then 32 pads = per group DwNum > must be 0. >=20 > + @param[out] PadCfgLockTxRegVal Value of PadCfgLockTx register >=20 > + Bit position - PadNumber >=20 > + Bit value - 0: NotLockedTx, 1: LockedT= x >=20 > + >=20 > + @retval EFI_SUCCESS The function completed successfully >=20 > + @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter > number >=20 > +**/ >=20 > +EFI_STATUS >=20 > +GpioGetPadCfgLockTxForGroupDw ( >=20 > + IN GPIO_GROUP Group, >=20 > + IN UINT32 DwNum, >=20 > + OUT UINT32 *PadCfgLockTxRegVal >=20 > + ); >=20 > + >=20 > +/** >=20 > + This procedure will check state of Pad Config Tx Lock for selected pad >=20 > + >=20 > + @param[in] GpioPad GPIO pad >=20 > + @param[out] PadCfgLock PadCfgLockTx for selected pad >=20 > + 0: NotLockedTx, 1: LockedTx >=20 > + >=20 > + @retval EFI_SUCCESS The function completed successfully >=20 > + @retval EFI_INVALID_PARAMETER Invalid GpioPad >=20 > +**/ >=20 > +EFI_STATUS >=20 > +GpioGetPadCfgLockTx ( >=20 > + IN GPIO_PAD GpioPad, >=20 > + OUT UINT32 *PadCfgLockTx >=20 > + ); >=20 > + >=20 > +/** >=20 > + This procedure will clear PadCfgLock for selected pads within one grou= p. >=20 > + Unlocking a pad will cause an SMI (if enabled) >=20 > + >=20 > + @param[in] Group GPIO group >=20 > + @param[in] DwNum PadCfgLock register number for current > group. >=20 > + For group which has less then 32 pads = per group DwNum > must be 0. >=20 > + @param[in] PadsToUnlock Bitmask for pads which are going to be > unlocked, >=20 > + Bit position - PadNumber >=20 > + Bit value - 0: DoNotUnlock, 1: Unlock >=20 > + >=20 > + @retval EFI_SUCCESS The function completed successfully >=20 > + @retval EFI_INVALID_PARAMETER Invalid group or pad number >=20 > +**/ >=20 > +EFI_STATUS >=20 > +GpioUnlockPadCfgForGroupDw ( >=20 > + IN GPIO_GROUP Group, >=20 > + IN UINT32 DwNum, >=20 > + IN UINT32 PadsToUnlock >=20 > + ); >=20 > + >=20 > +/** >=20 > + This procedure will clear PadCfgLock for selected pad. >=20 > + Unlocking a pad will cause an SMI (if enabled) >=20 > + >=20 > + @param[in] GpioPad GPIO pad >=20 > + >=20 > + @retval EFI_SUCCESS The function completed successfully >=20 > + @retval EFI_INVALID_PARAMETER Invalid GpioPad >=20 > +**/ >=20 > +EFI_STATUS >=20 > +GpioUnlockPadCfg ( >=20 > + IN GPIO_PAD GpioPad >=20 > + ); >=20 > + >=20 > +/** >=20 > + This procedure will set PadCfgLock for selected pads within one group >=20 > + >=20 > + @param[in] Group GPIO group >=20 > + @param[in] DwNum PadCfgLock register number for current > group. >=20 > + For group which has less then 32 pads = per group DwNum > must be 0. >=20 > + @param[in] PadsToLock Bitmask for pads which are going to be > locked, >=20 > + Bit position - PadNumber >=20 > + Bit value - 0: DoNotLock, 1: Lock >=20 > + >=20 > + @retval EFI_SUCCESS The function completed successfully >=20 > + @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter > number >=20 > +**/ >=20 > +EFI_STATUS >=20 > +GpioLockPadCfgForGroupDw ( >=20 > + IN GPIO_GROUP Group, >=20 > + IN UINT32 DwNum, >=20 > + IN UINT32 PadsToLock >=20 > + ); >=20 > + >=20 > +/** >=20 > + This procedure will set PadCfgLock for selected pad >=20 > + >=20 > + @param[in] GpioPad GPIO pad >=20 > + >=20 > + @retval EFI_SUCCESS The function completed successfully >=20 > + @retval EFI_INVALID_PARAMETER Invalid GpioPad >=20 > +**/ >=20 > +EFI_STATUS >=20 > +GpioLockPadCfg ( >=20 > + IN GPIO_PAD GpioPad >=20 > + ); >=20 > + >=20 > +/** >=20 > + This procedure will clear PadCfgLockTx for selected pads within one gr= oup. >=20 > + Unlocking a pad will cause an SMI (if enabled) >=20 > + >=20 > + @param[in] Group GPIO group >=20 > + @param[in] DwNum PadCfgLockTx register number for curre= nt > group. >=20 > + For group which has less then 32 pads = per group DwNum > must be 0. >=20 > + @param[in] PadsToUnlockTx Bitmask for pads which are going to be > unlocked, >=20 > + Bit position - PadNumber >=20 > + Bit value - 0: DoNotUnLockTx, 1: LockT= x >=20 > + >=20 > + @retval EFI_SUCCESS The function completed successfully >=20 > + @retval EFI_INVALID_PARAMETER Invalid group or pad number >=20 > +**/ >=20 > +EFI_STATUS >=20 > +GpioUnlockPadCfgTxForGroupDw ( >=20 > + IN GPIO_GROUP Group, >=20 > + IN UINT32 DwNum, >=20 > + IN UINT32 PadsToUnlockTx >=20 > + ); >=20 > + >=20 > +/** >=20 > + This procedure will clear PadCfgLockTx for selected pad. >=20 > + Unlocking a pad will cause an SMI (if enabled) >=20 > + >=20 > + @param[in] GpioPad GPIO pad >=20 > + >=20 > + @retval EFI_SUCCESS The function completed successfully >=20 > + @retval EFI_INVALID_PARAMETER Invalid GpioPad >=20 > +**/ >=20 > +EFI_STATUS >=20 > +GpioUnlockPadCfgTx ( >=20 > + IN GPIO_PAD GpioPad >=20 > + ); >=20 > + >=20 > +/** >=20 > + This procedure will set PadCfgLockTx for selected pads within one grou= p >=20 > + >=20 > + @param[in] Group GPIO group >=20 > + @param[in] DwNum PadCfgLock register number for current > group. >=20 > + For group which has less then 32 pads = per group DwNum > must be 0. >=20 > + @param[in] PadsToLockTx Bitmask for pads which are going to be > locked, >=20 > + Bit position - PadNumber >=20 > + Bit value - 0: DoNotLockTx, 1: LockTx >=20 > + >=20 > + @retval EFI_SUCCESS The function completed successfully >=20 > + @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter > number >=20 > +**/ >=20 > +EFI_STATUS >=20 > +GpioLockPadCfgTxForGroupDw ( >=20 > + IN GPIO_GROUP Group, >=20 > + IN UINT32 DwNum, >=20 > + IN UINT32 PadsToLockTx >=20 > + ); >=20 > + >=20 > +/** >=20 > + This procedure will set PadCfgLockTx for selected pad >=20 > + >=20 > + @param[in] GpioPad GPIO pad >=20 > + >=20 > + @retval EFI_SUCCESS The function completed successfully >=20 > + @retval EFI_INVALID_PARAMETER Invalid GpioPad >=20 > +**/ >=20 > +EFI_STATUS >=20 > +GpioLockPadCfgTx ( >=20 > + IN GPIO_PAD GpioPad >=20 > + ); >=20 > + >=20 > +/** >=20 > + This procedure will get Group to GPE mapping. >=20 > + It will assume that only first 32 pads can be mapped to GPE. >=20 > + To handle cases where groups have more than 32 pads and higher part of > group >=20 > + can be mapped please refer to GpioGetGroupDwToGpeDwX() >=20 > + >=20 > + @param[out] GroupToGpeDw0 GPIO group to be mapped to GPE_DW0 >=20 > + @param[out] GroupToGpeDw1 GPIO group to be mapped to GPE_DW1 >=20 > + @param[out] GroupToGpeDw2 GPIO group to be mapped to GPE_DW2 >=20 > + >=20 > + @retval EFI_SUCCESS The function completed successfully >=20 > + @retval EFI_INVALID_PARAMETER Invalid group or pad number >=20 > +**/ >=20 > +EFI_STATUS >=20 > +GpioGetGroupToGpeDwX ( >=20 > + IN GPIO_GROUP *GroupToGpeDw0, >=20 > + IN GPIO_GROUP *GroupToGpeDw1, >=20 > + IN GPIO_GROUP *GroupToGpeDw2 >=20 > + ); >=20 > + >=20 > +/** >=20 > + This procedure will get Group to GPE mapping. If group has more than 3= 2 > bits >=20 > + it is possible to map only single DW of pins (e.g. 0-31, 32-63) becaus= e >=20 > + ACPI GPE_DWx register is 32 bits large. >=20 > + >=20 > + @param[out] GroupToGpeDw0 GPIO group mapped to GPE_DW0 >=20 > + @param[out] GroupDwForGpeDw0 DW of pins mapped to GPE_DW0 >=20 > + @param[out] GroupToGpeDw1 GPIO group mapped to GPE_DW1 >=20 > + @param[out] GroupDwForGpeDw1 DW of pins mapped to GPE_DW1 >=20 > + @param[out] GroupToGpeDw2 GPIO group mapped to GPE_DW2 >=20 > + @param[out] GroupDwForGpeDw2 DW of pins mapped to GPE_DW2 >=20 > + >=20 > + @retval EFI_SUCCESS The function completed successfully >=20 > + @retval EFI_INVALID_PARAMETER Invalid group or pad number >=20 > +**/ >=20 > +EFI_STATUS >=20 > +GpioGetGroupDwToGpeDwX ( >=20 > + OUT GPIO_GROUP *GroupToGpeDw0, >=20 > + OUT UINT32 *GroupDwForGpeDw0, >=20 > + OUT GPIO_GROUP *GroupToGpeDw1, >=20 > + OUT UINT32 *GroupDwForGpeDw1, >=20 > + OUT GPIO_GROUP *GroupToGpeDw2, >=20 > + OUT UINT32 *GroupDwForGpeDw2 >=20 > + ); >=20 > + >=20 > +/** >=20 > + This procedure will get GPE number for provided GpioPad. >=20 > + PCH allows to configure mapping between GPIO groups and related GPE > (GpioSetGroupToGpeDwX()) >=20 > + what results in the fact that certain Pad can cause different General > Purpose Event. Only three >=20 > + GPIO groups can be mapped to cause unique GPE (1-tier), all others gro= ups > will be under one common >=20 > + event (GPE_111 for 2-tier). >=20 > + >=20 > + 1-tier: >=20 > + Returned GpeNumber is in range <0,95>. GpioGetGpeNumber() can be > used >=20 > + to determine what _LXX ACPI method would be called on event on > selected GPIO pad >=20 > + >=20 > + 2-tier: >=20 > + Returned GpeNumber is 0x6F (111). All GPIO pads which are not mapped > to 1-tier GPE >=20 > + will be under one master GPE_111 which is linked to _L6F ACPI method. = If > it is needed to determine >=20 > + what Pad from 2-tier has caused the event, _L6F method should check > GPI_GPE_STS and GPI_GPE_EN >=20 > + registers for all GPIO groups not mapped to 1-tier GPE. >=20 > + >=20 > + @param[in] GpioPad GPIO pad >=20 > + @param[out] GpeNumber GPE number >=20 > + >=20 > + @retval EFI_SUCCESS The function completed successfully >=20 > + @retval EFI_INVALID_PARAMETER Invalid GpioPad >=20 > +**/ >=20 > +EFI_STATUS >=20 > +GpioGetGpeNumber ( >=20 > + IN GPIO_PAD GpioPad, >=20 > + OUT UINT32 *GpeNumber >=20 > + ); >=20 > + >=20 > +/** >=20 > + This procedure is used to clear SMI STS for a specified Pad >=20 > + >=20 > + @param[in] GpioPad GPIO pad >=20 > + >=20 > + @retval EFI_SUCCESS The function completed successfully >=20 > + @retval EFI_INVALID_PARAMETER Invalid GpioPad >=20 > +**/ >=20 > +EFI_STATUS >=20 > +GpioClearGpiSmiSts ( >=20 > + IN GPIO_PAD GpioPad >=20 > + ); >=20 > + >=20 > +/** >=20 > + This procedure is used by Smi Dispatcher and will clear >=20 > + all GPI SMI Status bits >=20 > + >=20 > + @retval EFI_SUCCESS The function completed successfully >=20 > +**/ >=20 > +EFI_STATUS >=20 > +GpioClearAllGpiSmiSts ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + This procedure is used to disable all GPI SMI >=20 > + >=20 > + @retval EFI_SUCCESS The function completed successfully >=20 > +**/ >=20 > +EFI_STATUS >=20 > +GpioDisableAllGpiSmi ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + This procedure is used to register GPI SMI dispatch function. >=20 > + >=20 > + @param[in] GpioPad GPIO pad >=20 > + @param[out] GpiNum GPI number >=20 > + >=20 > + @retval EFI_SUCCESS The function completed successfully >=20 > + @retval EFI_INVALID_PARAMETER Invalid GpioPad >=20 > +**/ >=20 > +EFI_STATUS >=20 > +GpioGetGpiSmiNum ( >=20 > + IN GPIO_PAD GpioPad, >=20 > + OUT UINTN *GpiNum >=20 > + ); >=20 > + >=20 > +/** >=20 > + This procedure is used to check GPIO inputs belongs to 2 tier or 1 tie= r > architecture >=20 > + >=20 > + @param[in] GpioPad GPIO pad >=20 > + >=20 > + @retval Data 0 means 1-tier, 1 means 2-tier >=20 > +**/ >=20 > +BOOLEAN >=20 > +GpioCheckFor2Tier ( >=20 > + IN GPIO_PAD GpioPad >=20 > + ); >=20 > + >=20 > +/** >=20 > + This procedure is used to clear GPE STS for a specified GpioPad >=20 > + >=20 > + @param[in] GpioPad GPIO pad >=20 > + >=20 > + @retval EFI_SUCCESS The function completed successfully >=20 > + @retval EFI_INVALID_PARAMETER Invalid GpioPad >=20 > +**/ >=20 > +EFI_STATUS >=20 > +GpioClearGpiGpeSts ( >=20 > + IN GPIO_PAD GpioPad >=20 > + ); >=20 > + >=20 > +/** >=20 > + This procedure is used to read GPE STS for a specified Pad >=20 > + >=20 > + @param[in] GpioPad GPIO pad >=20 > + @param[out] GpeSts Gpe status for given pad >=20 > + The GpeSts is true if the status regis= ter is set for given Pad > number >=20 > + >=20 > + @retval EFI_SUCCESS The function completed successfully >=20 > + @retval EFI_INVALID_PARAMETER Invalid GpioPad >=20 > +**/ >=20 > +EFI_STATUS >=20 > +GpioGetGpiGpeSts ( >=20 > + IN GPIO_PAD GpioPad, >=20 > + OUT BOOLEAN *GpeSts >=20 > + ); >=20 > + >=20 > +/** >=20 > + This procedure is used to get SMI STS for a specified Pad >=20 > + >=20 > + @param[in] GpioPad GPIO pad >=20 > + @param[out] SmiSts Smi status for given pad >=20 > + The SmiSts is true if the status regis= ter is set for given Pad > number >=20 > + >=20 > + @retval EFI_SUCCESS The function completed successfully >=20 > + @retval EFI_INVALID_PARAMETER Invalid GpioPad >=20 > +**/ >=20 > +EFI_STATUS >=20 > +GpioGetGpiSmiSts ( >=20 > + IN GPIO_PAD GpioPad, >=20 > + OUT BOOLEAN *SmiSts >=20 > + ); >=20 > + >=20 > +/** >=20 > + Generates GPIO name from GpioPad >=20 > + >=20 > + @param[in] GpioPad GpioPad >=20 > + @param[out] GpioNameBuffer Caller allocated buffer for GPIO name = of > GPIO_NAME_LENGTH_MAX size >=20 > + @param[in] GpioNameBufferSize Size of the buffer >=20 > + >=20 > + @retval CHAR8* Pointer to the GPIO name >=20 > +**/ >=20 > +CHAR8* >=20 > +GpioGetPadName ( >=20 > + IN GPIO_PAD GpioPad, >=20 > + OUT CHAR8* GpioNameBuffer, >=20 > + IN UINT32 GpioNameBufferSize >=20 > + ); >=20 > + >=20 > +/** >=20 > + Generates GPIO group name from GroupIndex >=20 > + >=20 > + @param[in] GroupIndex Gpio GroupIndex >=20 > + >=20 > + @retval CHAR8* Pointer to the GPIO group name >=20 > +**/ >=20 > +CONST >=20 > +CHAR8* >=20 > +GpioGetGroupName ( >=20 > + IN UINT32 GroupIndex >=20 > + ); >=20 > + >=20 > +#endif // _GPIO_LIB_H_ >=20 > diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/GpioNative= Lib.h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/GpioNativeLib.h > new file mode 100644 > index 0000000000..b09600dd30 > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/GpioNativeLib.h > @@ -0,0 +1,149 @@ > +/** @file >=20 > + Header file for GpioLib for native and Si specific usage. >=20 > + All function in this library is available for PEI, DXE, and SMM, >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _GPIO_NATIVE_LIB_H_ >=20 > +#define _GPIO_NATIVE_LIB_H_ >=20 > + >=20 > +#include >=20 > + >=20 > +/** >=20 > + This procedure will get number of pads for certain GPIO group >=20 > + >=20 > + @param[in] Group GPIO group number >=20 > + >=20 > + @retval Value Pad number for group >=20 > + If illegal group number then return 0 >=20 > +**/ >=20 > +UINT32 >=20 > +GpioGetPadPerGroup ( >=20 > + IN GPIO_GROUP Group >=20 > + ); >=20 > + >=20 > +/** >=20 > + This procedure will get number of groups >=20 > + >=20 > + @param[in] none >=20 > + >=20 > + @retval Value Group number >=20 > +**/ >=20 > +UINT32 >=20 > +GpioGetNumberOfGroups ( >=20 > + VOID >=20 > + ); >=20 > +/** >=20 > + This procedure will get lowest group >=20 > + >=20 > + @param[in] none >=20 > + >=20 > + @retval Value Lowest Group >=20 > +**/ >=20 > +GPIO_GROUP >=20 > +GpioGetLowestGroup ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + This procedure will get highest group >=20 > + >=20 > + @param[in] none >=20 > + >=20 > + @retval Value Highest Group >=20 > +**/ >=20 > +GPIO_GROUP >=20 > +GpioGetHighestGroup ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + This procedure will get group >=20 > + >=20 > + @param[in] GpioPad Gpio Pad >=20 > + >=20 > + @retval Value Group >=20 > +**/ >=20 > +GPIO_GROUP >=20 > +GpioGetGroupFromGpioPad ( >=20 > + IN GPIO_PAD GpioPad >=20 > + ); >=20 > + >=20 > +/** >=20 > + This procedure will get group index (0 based) from GpioPad >=20 > + >=20 > + @param[in] GpioPad Gpio Pad >=20 > + >=20 > + @retval Value Group Index >=20 > +**/ >=20 > +UINT32 >=20 > +GpioGetGroupIndexFromGpioPad ( >=20 > + IN GPIO_PAD GpioPad >=20 > + ); >=20 > + >=20 > +/** >=20 > + This procedure will get group index (0 based) from group >=20 > + >=20 > + @param[in] GpioGroup Gpio Group >=20 > + >=20 > + @retval Value Group Index >=20 > +**/ >=20 > +UINT32 >=20 > +GpioGetGroupIndexFromGroup ( >=20 > + IN GPIO_GROUP GpioGroup >=20 > + ); >=20 > + >=20 > +/** >=20 > + This procedure will get group from group index (0 based) >=20 > + >=20 > + @param[in] GroupIndex Group Index >=20 > + >=20 > + @retval GpioGroup Gpio Group >=20 > +**/ >=20 > +GPIO_GROUP >=20 > +GpioGetGroupFromGroupIndex ( >=20 > + IN UINT32 GroupIndex >=20 > + ); >=20 > + >=20 > +/** >=20 > + This procedure will get pad number (0 based) from Gpio Pad >=20 > + >=20 > + @param[in] GpioPad Gpio Pad >=20 > + >=20 > + @retval Value Pad Number >=20 > +**/ >=20 > +UINT32 >=20 > +GpioGetPadNumberFromGpioPad ( >=20 > + IN GPIO_PAD GpioPad >=20 > + ); >=20 > + >=20 > +/** >=20 > + This procedure will return GpioPad from Group and PadNumber >=20 > + >=20 > + @param[in] Group GPIO group >=20 > + @param[in] PadNumber GPIO PadNumber >=20 > + >=20 > + @retval GpioPad GpioPad >=20 > +**/ >=20 > +GPIO_PAD >=20 > +GpioGetGpioPadFromGroupAndPadNumber ( >=20 > + IN GPIO_GROUP Group, >=20 > + IN UINT32 PadNumber >=20 > + ); >=20 > + >=20 > +/** >=20 > + This procedure will return GpioPad from GroupIndex and PadNumber >=20 > + >=20 > + @param[in] GroupIndex GPIO GroupIndex >=20 > + @param[in] PadNumber GPIO PadNumber >=20 > + >=20 > + @retval GpioPad GpioPad >=20 > +**/ >=20 > +GPIO_PAD >=20 > +GpioGetGpioPadFromGroupIndexAndPadNumber ( >=20 > + IN UINT32 GroupIndex, >=20 > + IN UINT32 PadNumber >=20 > + ); >=20 > + >=20 > +#endif // _GPIO_NATIVE_LIB_H_ >=20 > diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/MmPciLib.h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/MmPciLib.h > new file mode 100644 > index 0000000000..a53887ffcb > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/MmPciLib.h > @@ -0,0 +1,27 @@ > +/** @file >=20 > + Get Pci Express address library implementation. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _MM_PCI_LIB_H_ >=20 > +#define _MM_PCI_LIB_H_ >=20 > + >=20 > +/** >=20 > + This procedure will get PCIE address >=20 > + >=20 > + @param[in] Bus Pci Bus Number >=20 > + @param[in] Device Pci Device Number >=20 > + @param[in] Function Pci Function Number >=20 > + >=20 > + @retval PCIE address >=20 > +**/ >=20 > +UINTN >=20 > +EFIAPI >=20 > +MmPciBase ( >=20 > + IN UINT32 Bus, >=20 > + IN UINT32 Device, >=20 > + IN UINT32 Function >=20 > +); >=20 > + >=20 > +#endif // _PEI_DXE_SMM_MM_PCI_LIB_H_ >=20 > diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/PchPcieRpL= ib.h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/PchPcieRpLib.h > new file mode 100644 > index 0000000000..3c46029b7f > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/PchPcieRpLib.h > @@ -0,0 +1,123 @@ > +/** @file >=20 > + Header file for PchPcieRpLib. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _PCH_PCIERP_LIB_H_ >=20 > +#define _PCH_PCIERP_LIB_H_ >=20 > + >=20 > +#include >=20 > + >=20 > +/** >=20 > + PCIe controller bifurcation configuration. >=20 > +**/ >=20 > +typedef enum { >=20 > + PcieBifurcationDefault =3D 0, >=20 > + PcieBifurcation4x1, >=20 > + PcieBifurcation1x2_2x1, >=20 > + PcieBifurcation2x2, >=20 > + PcieBifurcation1x4, >=20 > + PcieBifurcation4x2, >=20 > + PcieBifurcation1x4_2x2, >=20 > + PcieBifurcation2x2_1x4, >=20 > + PcieBifurcation2x4, >=20 > + PcieBifurcation1x8, >=20 > + PcieBifurcationUnknown, >=20 > + PcieBifurcationMax >=20 > +} PCIE_BIFURCATION_CONFIG; >=20 > + >=20 > +/** >=20 > + This function returns PID according to PCIe controller index >=20 > + >=20 > + @param[in] ControllerIndex PCIe controller index >=20 > + >=20 > + @retval PCH_SBI_PID Returns PID for SBI Access >=20 > +**/ >=20 > +PCH_SBI_PID >=20 > +PchGetPcieControllerSbiPid ( >=20 > + IN UINT32 ControllerIndex >=20 > + ); >=20 > + >=20 > +/** >=20 > + This function returns PID according to Root Port Number >=20 > + >=20 > + @param[in] RpIndex Root Port Index (0-based) >=20 > + >=20 > + @retval PCH_SBI_PID Returns PID for SBI Access >=20 > +**/ >=20 > +PCH_SBI_PID >=20 > +GetRpSbiPid ( >=20 > + IN UINTN RpIndex >=20 > + ); >=20 > + >=20 > +/** >=20 > + Get Pch Pcie Root Port Device and Function Number by Root Port physica= l > Number >=20 > + >=20 > + @param[in] RpNumber Root port physical number. (0-based) >=20 > + @param[out] RpDev Return corresponding root port device > number. >=20 > + @param[out] RpFun Return corresponding root port functio= n > number. >=20 > + >=20 > + @retval EFI_SUCCESS >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +GetPchPcieRpDevFun ( >=20 > + IN UINTN RpNumber, >=20 > + OUT UINTN *RpDev, >=20 > + OUT UINTN *RpFun >=20 > + ); >=20 > + >=20 > +/** >=20 > + Get Root Port physical Number by Pch Pcie Root Port Device and Functio= n > Number >=20 > + >=20 > + @param[in] RpDev Root port device number. >=20 > + @param[in] RpFun Root port function number. >=20 > + @param[out] RpNumber Return corresponding physical Root P= ort > index (0-based) >=20 > + >=20 > + @retval EFI_SUCCESS Physical root port is retrieved >=20 > + @retval EFI_INVALID_PARAMETER RpDev and/or RpFun are invalid >=20 > + @retval EFI_UNSUPPORTED Root port device and function is not > assigned to any physical root port >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +GetPchPcieRpNumber ( >=20 > + IN UINTN RpDev, >=20 > + IN UINTN RpFun, >=20 > + OUT UINTN *RpNumber >=20 > + ); >=20 > + >=20 > +/** >=20 > + Gets pci segment base address of PCIe root port. >=20 > + >=20 > + @param RpIndex Root Port Index (0 based) >=20 > + @return PCIe port base address. >=20 > +**/ >=20 > +UINT64 >=20 > +PchPcieBase ( >=20 > + IN UINT32 RpIndex >=20 > + ); >=20 > + >=20 > +/** >=20 > + Determines whether L0s is supported on current stepping. >=20 > + >=20 > + @return TRUE if L0s is supported, FALSE otherwise >=20 > +**/ >=20 > +BOOLEAN >=20 > +PchIsPcieL0sSupported ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Some early PCH steppings require Native ASPM to be disabled due to > hardware issues: >=20 > + - RxL0s exit causes recovery >=20 > + - Disabling PCIe L0s capability disables L1 >=20 > + Use this function to determine affected steppings. >=20 > + >=20 > + @return TRUE if Native ASPM is supported, FALSE otherwise >=20 > +**/ >=20 > +BOOLEAN >=20 > +PchIsPcieNativeAspmSupported ( >=20 > + VOID >=20 > + ); >=20 > +#endif // _PCH_PCIERP_LIB_H_ >=20 > diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/PchPcrLib.= h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/PchPcrLib.h > new file mode 100644 > index 0000000000..f46c3da0e1 > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/PchPcrLib.h > @@ -0,0 +1,256 @@ > +/** @file >=20 > + Header file for PchPcrLib. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _PCH_PCR_LIB_H_ >=20 > +#define _PCH_PCR_LIB_H_ >=20 > + >=20 > +#include >=20 > + >=20 > +/** >=20 > + Definition for PCR address >=20 > + The PCR address is used to the PCR MMIO programming >=20 > + >=20 > + SBREG_BAR_20BITADDRESS is configured by SoC >=20 > + >=20 > + SBREG_BAR_20BITADDRESS=3D1, the format has included 16b addressing. >=20 > + +---------------------------------------------------------------------= -------------------- > ----+ >=20 > + | Addr[63:28] | Addr[27:24] | Addr[23:16] | Addr[15:2= ] | > Addr[1:0] | >=20 > + +----------------+-----------------------+-----------------+----------= ------------------ > ------+ >=20 > + | REG_BAR[63:28] | TargetRegister[19:16] | TargetPort[7:0] | > TargetRegister[15:2] | >=20 > + +---------------------------------------------------------------------= -------------------- > ----+ >=20 > + >=20 > + SBREG_BAR_20BITADDRESS=3D0 >=20 > + +---------------------------------------------------------------------= -------------------- > ----+ >=20 > + | Addr[63:24] | Addr[27:24] | Addr[23:16] | Addr[15:2= ] | > Addr[1:0] | >=20 > + +----------------+-----------------------+-----------------+----------= ------------------ > ------+ >=20 > + | REG_BAR[63:24] | REG_BAR[27:24] | TargetPort[7:0] | > TargetRegister[15:2] | >=20 > + +---------------------------------------------------------------------= -------------------- > ----+ >=20 > +**/ >=20 > +#define PCH_PCR_ADDRESS(Pid, Offset) (PCH_PCR_BASE_ADDRESS | > (UINT32) (((Offset) & 0x0F0000) << 8) | ((UINT8)(Pid) << 16) | (UINT16) > ((Offset) & 0xFFFF)) >=20 > + >=20 > +/** >=20 > + PCH PCR boot script accessing macro >=20 > + Those macros are only available for DXE phase. >=20 > +**/ >=20 > +#define PCH_PCR_BOOT_SCRIPT_WRITE(Width, Pid, Offset, Count, Buffer) > \ >=20 > + S3BootScriptSaveMemWrite (Width, PCH_PCR_ADDRESS (Pid, Offset)= , > Count, Buffer); \ >=20 > + >=20 > +#define PCH_PCR_BOOT_SCRIPT_READ_WRITE(Width, Pid, Offset, DataOr, > DataAnd) \ >=20 > + S3BootScriptSaveMemReadWrite (Width, PCH_PCR_ADDRESS (Pid, > Offset), DataOr, DataAnd); \ >=20 > + >=20 > +#define PCH_PCR_BOOT_SCRIPT_READ(Width, Pid, Offset, BitMask, > BitValue) \ >=20 > + S3BootScriptSaveMemPoll (Width, PCH_PCR_ADDRESS (Pid, Offset), > BitMask, BitValue, 1, 1); >=20 > + >=20 > +typedef UINT8 PCH_SBI_PID; >=20 > + >=20 > +/** >=20 > + Read PCR register. >=20 > + It returns PCR register and size in 4bytes. >=20 > + The Offset should not exceed 0xFFFF and must be aligned with size. >=20 > + >=20 > + @param[in] Pid Port ID >=20 > + @param[in] Offset Register offset of this Port ID >=20 > + >=20 > + @retval UINT32 PCR register value. >=20 > +**/ >=20 > +UINT32 >=20 > +PchPcrRead32 ( >=20 > + IN PCH_SBI_PID Pid, >=20 > + IN UINT32 Offset >=20 > + ); >=20 > + >=20 > +/** >=20 > + Read PCR register. >=20 > + It returns PCR register and size in 2bytes. >=20 > + The Offset should not exceed 0xFFFF and must be aligned with size. >=20 > + >=20 > + @param[in] Pid Port ID >=20 > + @param[in] Offset Register offset of this Port ID >=20 > + >=20 > + @retval UINT16 PCR register value. >=20 > +**/ >=20 > +UINT16 >=20 > +PchPcrRead16 ( >=20 > + IN PCH_SBI_PID Pid, >=20 > + IN UINT32 Offset >=20 > + ); >=20 > + >=20 > +/** >=20 > + Read PCR register. >=20 > + It returns PCR register and size in 1bytes. >=20 > + The Offset should not exceed 0xFFFF and must be aligned with size. >=20 > + >=20 > + @param[in] Pid Port ID >=20 > + @param[in] Offset Register offset of this Port ID >=20 > + >=20 > + @retval UINT8 PCR register value >=20 > +**/ >=20 > +UINT8 >=20 > +PchPcrRead8 ( >=20 > + IN PCH_SBI_PID Pid, >=20 > + IN UINT32 Offset >=20 > + ); >=20 > + >=20 > +/** >=20 > + Write PCR register. >=20 > + It programs PCR register and size in 4bytes. >=20 > + The Offset should not exceed 0xFFFF and must be aligned with size. >=20 > + >=20 > + @param[in] Pid Port ID >=20 > + @param[in] Offset Register offset of Port ID. >=20 > + @param[in] Data Input Data. Must be the same size as Size paramet= er. >=20 > + >=20 > + @retval UINT32 Value written to register >=20 > +**/ >=20 > +UINT32 >=20 > +PchPcrWrite32 ( >=20 > + IN PCH_SBI_PID Pid, >=20 > + IN UINT32 Offset, >=20 > + IN UINT32 InData >=20 > + ); >=20 > + >=20 > +/** >=20 > + Write PCR register. >=20 > + It programs PCR register and size in 2bytes. >=20 > + The Offset should not exceed 0xFFFF and must be aligned with size. >=20 > + >=20 > + @param[in] Pid Port ID >=20 > + @param[in] Offset Register offset of Port ID. >=20 > + @param[in] Data Input Data. Must be the same size as Size paramet= er. >=20 > + >=20 > + @retval UINT16 Value written to register >=20 > +**/ >=20 > +UINT16 >=20 > +PchPcrWrite16 ( >=20 > + IN PCH_SBI_PID Pid, >=20 > + IN UINT32 Offset, >=20 > + IN UINT16 InData >=20 > + ); >=20 > + >=20 > +/** >=20 > + Write PCR register. >=20 > + It programs PCR register and size in 1bytes. >=20 > + The Offset should not exceed 0xFFFF and must be aligned with size. >=20 > + >=20 > + @param[in] Pid Port ID >=20 > + @param[in] Offset Register offset of Port ID. >=20 > + @param[in] Data Input Data. Must be the same size as Size paramet= er. >=20 > + >=20 > + @retval UINT8 Value written to register >=20 > +**/ >=20 > +UINT8 >=20 > +PchPcrWrite8 ( >=20 > + IN PCH_SBI_PID Pid, >=20 > + IN UINT32 Offset, >=20 > + IN UINT8 InData >=20 > + ); >=20 > + >=20 > +/** >=20 > + Write PCR register. >=20 > + It programs PCR register and size in 4bytes. >=20 > + The Offset should not exceed 0xFFFF and must be aligned with size. >=20 > + >=20 > + @param[in] Pid Port ID >=20 > + @param[in] Offset Register offset of Port ID. >=20 > + @param[in] AndData AND Data. Must be the same size as Size parameter= . >=20 > + @param[in] OrData OR Data. Must be the same size as Size parameter. >=20 > + >=20 > + @retval UINT32 Value written to register >=20 > + >=20 > +**/ >=20 > +UINT32 >=20 > +PchPcrAndThenOr32 ( >=20 > + IN PCH_SBI_PID Pid, >=20 > + IN UINT32 Offset, >=20 > + IN UINT32 AndData, >=20 > + IN UINT32 OrData >=20 > + ); >=20 > + >=20 > +/** >=20 > + Write PCR register and read back. >=20 > + The read back ensures the PCR cycle is completed before next operation= . >=20 > + It programs PCR register and size in 4bytes. >=20 > + The Offset should not exceed 0xFFFF and must be aligned with size. >=20 > + >=20 > + @param[in] Pid Port ID >=20 > + @param[in] Offset Register offset of Port ID. >=20 > + @param[in] AndData AND Data. Must be the same size as Size parameter= . >=20 > + @param[in] OrData OR Data. Must be the same size as Size parameter. >=20 > + >=20 > + @retval UINT32 Value read back from the register >=20 > +**/ >=20 > +UINT32 >=20 > +PchPcrAndThenOr32WithReadback ( >=20 > + IN PCH_SBI_PID Pid, >=20 > + IN UINT32 Offset, >=20 > + IN UINT32 AndData, >=20 > + IN UINT32 OrData >=20 > + ); >=20 > + >=20 > +/** >=20 > + Write PCR register. >=20 > + It programs PCR register and size in 2bytes. >=20 > + The Offset should not exceed 0xFFFF and must be aligned with size. >=20 > + >=20 > + @param[in] Pid Port ID >=20 > + @param[in] Offset Register offset of Port ID. >=20 > + @param[in] AndData AND Data. Must be the same size as Size parameter= . >=20 > + @param[in] OrData OR Data. Must be the same size as Size parameter. >=20 > + >=20 > + @retval UINT16 Value written to register >=20 > + >=20 > +**/ >=20 > +UINT16 >=20 > +PchPcrAndThenOr16 ( >=20 > + IN PCH_SBI_PID Pid, >=20 > + IN UINT32 Offset, >=20 > + IN UINT16 AndData, >=20 > + IN UINT16 OrData >=20 > + ); >=20 > + >=20 > +/** >=20 > + Write PCR register. >=20 > + It programs PCR register and size in 1bytes. >=20 > + The Offset should not exceed 0xFFFF and must be aligned with size. >=20 > + >=20 > + @param[in] Pid Port ID >=20 > + @param[in] Offset Register offset of Port ID. >=20 > + @param[in] AndData AND Data. Must be the same size as Size parameter= . >=20 > + @param[in] OrData OR Data. Must be the same size as Size parameter. >=20 > + >=20 > + @retval UINT8 Value written to register >=20 > + >=20 > +**/ >=20 > +UINT8 >=20 > +PchPcrAndThenOr8 ( >=20 > + IN PCH_SBI_PID Pid, >=20 > + IN UINT32 Offset, >=20 > + IN UINT8 AndData, >=20 > + IN UINT8 OrData >=20 > + ); >=20 > + >=20 > + >=20 > +typedef enum { >=20 > + PchIpDmi =3D 1, >=20 > + PchIpIclk, >=20 > +} PCH_IP_PID_ENUM; >=20 > + >=20 > +#define PCH_INVALID_PID 0 >=20 > + >=20 > +/** >=20 > + Get PCH IP PID number >=20 > + >=20 > + @param[in] IpEnum PCH IP in PCH_IP_PID_ENUM >=20 > + >=20 > + @retval 0 PID of this IP is not supported >=20 > + !0 PID of the IP. >=20 > +**/ >=20 > +PCH_SBI_PID >=20 > +PchPcrGetPid ( >=20 > + PCH_IP_PID_ENUM IpEnum >=20 > + ); >=20 > + >=20 > +#endif // _PCH_PCR_LIB_H_ >=20 > diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/PcieHelper= Lib.h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/PcieHelperLib.h > new file mode 100644 > index 0000000000..8ab20f0db7 > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/PcieHelperLib.h > @@ -0,0 +1,173 @@ > +/** @file >=20 > + Header file for PCI Express helpers base library >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _PCIE_HELPER_LIB_H_ >=20 > +#define _PCIE_HELPER_LIB_H_ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +/** >=20 > + Find the Offset to a given Capabilities ID >=20 > + CAPID list: >=20 > + 0x01 =3D PCI Power Management Interface >=20 > + 0x04 =3D Slot Identification >=20 > + 0x05 =3D MSI Capability >=20 > + 0x10 =3D PCI Express Capability >=20 > + >=20 > + @param[in] DeviceBase device's base address >=20 > + @param[in] CapId CAPID to search for >=20 > + >=20 > + @retval 0 CAPID not found >=20 > + @retval Other CAPID found, Offset of desired CAPID >=20 > +**/ >=20 > +UINT8 >=20 > +PcieBaseFindCapId ( >=20 > + IN UINT64 DeviceBase, >=20 > + IN UINT8 CapId >=20 > + ); >=20 > + >=20 > +/** >=20 > + Find the Offset to a given Capabilities ID >=20 > + CAPID list: >=20 > + 0x01 =3D PCI Power Management Interface >=20 > + 0x04 =3D Slot Identification >=20 > + 0x05 =3D MSI Capability >=20 > + 0x10 =3D PCI Express Capability >=20 > + >=20 > + @param[in] Segment Pci Segment Number >=20 > + @param[in] Bus Pci Bus Number >=20 > + @param[in] Device Pci Device Number >=20 > + @param[in] Function Pci Function Number >=20 > + @param[in] CapId CAPID to search for >=20 > + >=20 > + @retval 0 CAPID not found >=20 > + @retval Other CAPID found, Offset of desired CAPID >=20 > +**/ >=20 > +UINT8 >=20 > +PcieFindCapId ( >=20 > + IN UINT8 Segment, >=20 > + IN UINT8 Bus, >=20 > + IN UINT8 Device, >=20 > + IN UINT8 Function, >=20 > + IN UINT8 CapId >=20 > + ); >=20 > + >=20 > +/** >=20 > + Search and return the offset of desired Pci Express Capability ID >=20 > + CAPID list: >=20 > + 0x0001 =3D Advanced Error Reporting Capability >=20 > + 0x0002 =3D Virtual Channel Capability >=20 > + 0x0003 =3D Device Serial Number Capability >=20 > + 0x0004 =3D Power Budgeting Capability >=20 > + >=20 > + @param[in] DeviceBase device base address >=20 > + @param[in] CapId Extended CAPID to search for >=20 > + >=20 > + @retval 0 CAPID not found, this includes situati= on where device > doesn't exist >=20 > + @retval Other CAPID found, Offset of desired CAPID >=20 > +**/ >=20 > +UINT16 >=20 > +PcieBaseFindExtendedCapId ( >=20 > + IN UINT64 DeviceBase, >=20 > + IN UINT16 CapId >=20 > + ); >=20 > + >=20 > +/** >=20 > + Search and return the offset of desired Pci Express Capability ID >=20 > + CAPID list: >=20 > + 0x0001 =3D Advanced Error Rreporting Capability >=20 > + 0x0002 =3D Virtual Channel Capability >=20 > + 0x0003 =3D Device Serial Number Capability >=20 > + 0x0004 =3D Power Budgeting Capability >=20 > + >=20 > + @param[in] Segment Pci Segment Number >=20 > + @param[in] Bus Pci Bus Number >=20 > + @param[in] Device Pci Device Number >=20 > + @param[in] Function Pci Function Number >=20 > + @param[in] CapId Extended CAPID to search for >=20 > + >=20 > + @retval 0 CAPID not found >=20 > + @retval Other CAPID found, Offset of desired CAPID >=20 > +**/ >=20 > +UINT16 >=20 > +PcieFindExtendedCapId ( >=20 > + IN UINT8 Segment, >=20 > + IN UINT8 Bus, >=20 > + IN UINT8 Device, >=20 > + IN UINT8 Function, >=20 > + IN UINT16 CapId >=20 > + ); >=20 > + >=20 > +/* >=20 > + Checks device's Slot Clock Configuration >=20 > + >=20 > + @param[in] Base device's base address >=20 > + @param[in] PcieCapOffset devices Pci express capability list registe= r > offset >=20 > + >=20 > + @retval TRUE when device device uses slot clock, FALSE otherwise >=20 > +*/ >=20 > +BOOLEAN >=20 > +GetScc ( >=20 > + UINT64 Base, >=20 > + UINT8 PcieCapOffset >=20 > + ); >=20 > + >=20 > +/* >=20 > + Sets Common Clock Configuration bit for given device. >=20 > + @param[in] PcieCapOffset devices Pci express capability list registe= r > offset >=20 > + @param[in] Base device's base address >=20 > +*/ >=20 > +VOID >=20 > +EnableCcc ( >=20 > + UINT64 Base, >=20 > + UINT8 PcieCapOffset >=20 > + ); >=20 > + >=20 > +/* >=20 > + Retrains link behind given device. >=20 > + It only makes sense to call it for downstream ports. >=20 > + If called for upstream port nothing will happen, it won't enter infini= te loop. >=20 > + >=20 > + @param[in] Base device's base address >=20 > + @param[in] PcieCapOffset devices Pci express capability list re= gister > offset >=20 > + @param[boolean] WaitUnitlDone when TRUE, function waits until link h= as > retrained >=20 > +*/ >=20 > +VOID >=20 > +RetrainLink ( >=20 > + UINT64 Base, >=20 > + UINT8 PcieCapOffset, >=20 > + BOOLEAN WaitUntilDone >=20 > + ); >=20 > + >=20 > +/* >=20 > + Checks if device at given address exists >=20 > + >=20 > + @param[in] Base device's base address >=20 > + >=20 > + @retval TRUE when device exists; FALSE otherwise >=20 > +*/ >=20 > +BOOLEAN >=20 > +IsDevicePresent ( >=20 > + UINT64 Base >=20 > + ); >=20 > + >=20 > +/* >=20 > + Checks if device is a multifunction device >=20 > + >=20 > + @param[in] Base device's base address >=20 > + >=20 > + @retval TRUE if multifunction; FALSE otherwise >=20 > +*/ >=20 > +BOOLEAN >=20 > +IsMultifunctionDevice ( >=20 > + UINT64 Base >=20 > + ); >=20 > +#endif // _PCIE_HELPER_LIB_H_ >=20 > diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/PmcLib.h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/PmcLib.h > new file mode 100644 > index 0000000000..0b8ad7a182 > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/PmcLib.h > @@ -0,0 +1,355 @@ > +/** @file >=20 > + Header file for PmcLib. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _PMC_LIB_H_ >=20 > +#define _PMC_LIB_H_ >=20 > + >=20 > +#pragma pack(1) >=20 > + >=20 > +typedef enum { >=20 > + PmcTPch25_10us =3D 0, >=20 > + PmcTPch25_100us, >=20 > + PmcTPch25_1ms, >=20 > + PmcTPch25_10ms, >=20 > +} PMC_TPCH25_TIMING; >=20 > + >=20 > +typedef enum { >=20 > + PmcNotASleepState, >=20 > + PmcInS0State, >=20 > + PmcS1SleepState, >=20 > + PmcS2SleepState, >=20 > + PmcS3SleepState, >=20 > + PmcS4SleepState, >=20 > + PmcS5SleepState, >=20 > + PmcUndefinedState, >=20 > +} PMC_SLEEP_STATE; >=20 > + >=20 > +typedef struct { >=20 > + UINT32 Buf0; >=20 > + UINT32 Buf1; >=20 > + UINT32 Buf2; >=20 > + UINT32 Buf3; >=20 > +} PMC_IPC_COMMAND_BUFFER; >=20 > + >=20 > +// >=20 > +// Structure to Check different attributes for CrashLog supported by PMC= . >=20 > +// >=20 > +typedef union { >=20 > + struct { >=20 > + UINT32 Avail : 1; ///< CrashLog feature availability bi= t >=20 > + UINT32 Dis : 1; ///< CrasLog Disable bit >=20 > + UINT32 Rsvd : 2; ///< Reserved >=20 > + UINT32 Size : 12; ///< CrasLog data size. (If it is zer= o, use default size > 0xC00) >=20 > + UINT32 BaseOffset : 16; ///< Start offset of CrashLog in PMC = SSRAM >=20 > + } Bits; >=20 > + struct { >=20 > + UINT32 Avail : 1; ///< CrashLog feature availability bi= t >=20 > + UINT32 Dis : 1; ///< CrasLog Disable bit >=20 > + UINT32 Mech : 2; ///< CrashLog mechanism >=20 > + UINT32 ManuTri : 1; ///< Manul trigger command. >=20 > + UINT32 Clr : 1; ///< Clear Command >=20 > + UINT32 AllReset : 1; ///< Trigger on all reset command >=20 > + UINT32 ReArm : 1; ///< Re-arm command >=20 > + UINT32 Rsvd : 20; ///< Pch Specific reserved >=20 > + UINT32 CrashLogReq: 1; ///< Crash log requestor flow >=20 > + UINT32 TriArmedSts: 1; ///< Trigger armed status, re-arm ind= ication > bit. >=20 > + UINT32 TriAllReset: 1; ///< Trigger on all resets status >=20 > + UINT32 CrashDisSts: 1; ///< Crash log disabled status >=20 > + UINT32 PchRsvd : 16; ///< Pch Specific reserved >=20 > + UINT32 DesTableOffset: 16; ///< Descriptor Table offset >=20 > + } Bits64; >=20 > + UINT32 Uint32; >=20 > + UINT64 Uint64; >=20 > +} PMC_IPC_DISCOVERY_BUF; >=20 > + >=20 > +typedef union { >=20 > + struct { >=20 > + UINT32 Offset : 16; >=20 > + UINT32 Size : 16; >=20 > + } Info; >=20 > + UINT32 Uint32; >=20 > +} PMC_CRASHLOG_RECORDS; >=20 > + >=20 > +typedef struct PmcCrashLogLink { >=20 > + PMC_CRASHLOG_RECORDS Record; >=20 > + UINT64 AllocateAddress; >=20 > + struct PmcCrashLogLink *Next; >=20 > +} PMC_CRASHLOG_LINK; >=20 > + >=20 > +#pragma pack() >=20 > + >=20 > +/** >=20 > + Get PCH ACPI base address. >=20 > + >=20 > + @retval Address Address of PWRM base address. >=20 > +**/ >=20 > +UINT16 >=20 > +PmcGetAcpiBase ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Get PCH PWRM base address. >=20 > + >=20 > + @retval Address Address of PWRM base address. >=20 > +**/ >=20 > +UINT32 >=20 > +PmcGetPwrmBase ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + This function sets tPCH25 timing >=20 > + >=20 > + @param[in] TimingValue tPCH25 timing value (10us, 100us, 1ms, 10= ms) >=20 > +**/ >=20 > +VOID >=20 > +PmcSetTPch25Timing ( >=20 > + IN PMC_TPCH25_TIMING TimingValue >=20 > + ); >=20 > + >=20 > +/** >=20 > + This function checks if RTC Power Failure occurred by >=20 > + reading RTC_PWR_FLR bit >=20 > + >=20 > + @retval RTC Power Failure state: TRUE - Battery is always present. >=20 > + FALSE - CMOS is cleared. >=20 > +**/ >=20 > +BOOLEAN >=20 > +PmcIsRtcBatteryGood ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + This function checks if Power Failure occurred by >=20 > + reading PWR_FLR bit >=20 > + >=20 > + @retval Power Failure state >=20 > +**/ >=20 > +BOOLEAN >=20 > +PmcIsPowerFailureDetected ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + This function checks if Power Failure occurred by >=20 > + reading SUS_PWR_FLR bit >=20 > + >=20 > + @retval SUS Power Failure state >=20 > +**/ >=20 > +BOOLEAN >=20 > +PmcIsSusPowerFailureDetected ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + This function clears Power Failure status (PWR_FLR) >=20 > +**/ >=20 > +VOID >=20 > +PmcClearPowerFailureStatus ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + This function clears Global Reset status (GBL_RST_STS) >=20 > +**/ >=20 > +VOID >=20 > +PmcClearGlobalResetStatus ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + This function clears Host Reset status (HOST_RST_STS) >=20 > +**/ >=20 > +VOID >=20 > +PmcClearHostResetStatus ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + This function clears SUS Power Failure status (SUS_PWR_FLR) >=20 > +**/ >=20 > +VOID >=20 > +PmcClearSusPowerFailureStatus ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + This function sets state to which platform will get after power is rea= pplied >=20 > + >=20 > + @param[in] PowerStateAfterG3 0: S0 state (boot) >=20 > + 1: S5/S4 State >=20 > +**/ >=20 > +VOID >=20 > +PmcSetPlatformStateAfterPowerFailure ( >=20 > + IN UINT8 PowerStateAfterG3 >=20 > + ); >=20 > + >=20 > +/** >=20 > + This function enables Power Button SMI >=20 > +**/ >=20 > +VOID >=20 > +PmcEnablePowerButtonSmi ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + This function disables Power Button SMI >=20 > +**/ >=20 > +VOID >=20 > +PmcDisablePowerButtonSmi ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + This function reads PM Timer Count driven by 3.579545 MHz clock >=20 > + >=20 > + @retval PM Timer Count >=20 > +**/ >=20 > +UINT32 >=20 > +PmcGetTimerCount ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Get Sleep Type that platform has waken from >=20 > + >=20 > + @retval SleepType Sleep Type >=20 > +**/ >=20 > +PMC_SLEEP_STATE >=20 > +PmcGetSleepTypeAfterWake ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Clear PMC Wake Status >=20 > +**/ >=20 > +VOID >=20 > +PmcClearWakeStatus ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Configure sleep state >=20 > + >=20 > + @param[in] SleepState S0/S1/S3/S4/S5, refer to PMC_SLEEP_STATE >=20 > +**/ >=20 > +VOID >=20 > +PmcSetSleepState ( >=20 > + PMC_SLEEP_STATE SleepState >=20 > + ); >=20 > + >=20 > +/** >=20 > + Check if platform boots after shutdown caused by power button override > event >=20 > + >=20 > + @retval TRUE Power Button Override occurred in last system boot >=20 > + @retval FALSE Power Button Override didn't occur >=20 > +**/ >=20 > +BOOLEAN >=20 > +PmcIsPowerButtonOverrideDetected ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + This function will set the DISB - DRAM Initialization Scratchpad Bit. >=20 > +**/ >=20 > +VOID >=20 > +PmcSetDramInitScratchpad ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Check global SMI enable is set >=20 > + >=20 > + @retval TRUE Global SMI enable is set >=20 > + FALSE Global SMI enable is not set >=20 > +**/ >=20 > +BOOLEAN >=20 > +PmcIsGblSmiEn ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + This function checks if SMI Lock is set >=20 > + >=20 > + @retval SMI Lock state >=20 > +**/ >=20 > +BOOLEAN >=20 > +PmcIsSmiLockSet ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + This function checks if Debug Mode is locked >=20 > + >=20 > + @retval Debug Mode Lock state >=20 > +**/ >=20 > +BOOLEAN >=20 > +PmcIsDebugModeLocked ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Check TCO second timeout status. >=20 > + >=20 > + @retval TRUE TCO reboot happened. >=20 > + @retval FALSE TCO reboot didn't happen. >=20 > +**/ >=20 > +BOOLEAN >=20 > +TcoSecondToHappened ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + This function clears the Second TO status bit >=20 > +**/ >=20 > +VOID >=20 > +TcoClearSecondToStatus ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Check TCO SMI ENABLE is locked >=20 > + >=20 > + @retval TRUE TCO SMI ENABLE is locked >=20 > + FALSE TCO SMI ENABLE is not locked >=20 > +**/ >=20 > +BOOLEAN >=20 > +TcoIsSmiLock ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Check if user wants to turn off in PEI phase >=20 > + >=20 > +**/ >=20 > +VOID >=20 > +CheckPowerOffNow( >=20 > + VOID >=20 > + ); >=20 > + >=20 > + >=20 > +/** >=20 > + Clear any SMI status or wake status left from boot. >=20 > +**/ >=20 > +VOID >=20 > +ClearSmiAndWake ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Function to check if Dirty Warm Reset occurs >=20 > + (Global Reset has been converted to Host Reset) >=20 > + >=20 > + @reval TRUE DWR occurs >=20 > + @reval FALSE Normal boot flow >=20 > +**/ >=20 > +BOOLEAN >=20 > +PmcIsDwrBootMode ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +#endif // _PMC_LIB_H_ >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/ResetSystemLib.h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/ResetSystemLib.h > new file mode 100644 > index 0000000000..9ab55ad9d0 > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/ResetSystemLib.h > @@ -0,0 +1,79 @@ > +/** @file >=20 > + System reset Library Services. This library class defines a set of >=20 > + methods that reset the whole system. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +#ifndef __RESET_SYSTEM_LIB_H__ >=20 > +#define __RESET_SYSTEM_LIB_H__ >=20 > + >=20 > +/** >=20 > + This function causes a system-wide reset (cold reset), in which >=20 > + all circuitry within the system returns to its initial state. This typ= e of reset >=20 > + is asynchronous to system operation and operates without regard to >=20 > + cycle boundaries. >=20 > + >=20 > + If this function returns, it means that the system does not support co= ld > reset. >=20 > +**/ >=20 > +VOID >=20 > +EFIAPI >=20 > +ResetCold ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + This function causes a system-wide initialization (warm reset), in whi= ch all > processors >=20 > + are set to their initial state. Pending cycles are not corrupted. >=20 > + >=20 > + If this function returns, it means that the system does not support wa= rm > reset. >=20 > +**/ >=20 > +VOID >=20 > +EFIAPI >=20 > +ResetWarm ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + This function causes the system to enter a power state equivalent >=20 > + to the ACPI G2/S5 or G3 states. >=20 > + >=20 > + If this function returns, it means that the system does not support > shutdown reset. >=20 > +**/ >=20 > +VOID >=20 > +EFIAPI >=20 > +ResetShutdown ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + This function causes the system to enter S3 and then wake up > immediately. >=20 > + >=20 > + If this function returns, it means that the system does not support S3 > feature. >=20 > +**/ >=20 > +VOID >=20 > +EFIAPI >=20 > +EnterS3WithImmediateWake ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + This function causes a systemwide reset. The exact type of the reset i= s >=20 > + defined by the EFI_GUID that follows the Null-terminated Unicode strin= g > passed >=20 > + into ResetData. If the platform does not recognize the EFI_GUID in > ResetData >=20 > + the platform must pick a supported reset type to perform.The platform > may >=20 > + optionally log the parameters from any non-normal reset that occurs. >=20 > + >=20 > + @param[in] DataSize The size, in bytes, of ResetData. >=20 > + @param[in] ResetData The data buffer starts with a Null-terminated > string, >=20 > + followed by the EFI_GUID. >=20 > +**/ >=20 > +VOID >=20 > +EFIAPI >=20 > +ResetPlatformSpecific ( >=20 > + IN UINTN DataSize, >=20 > + IN VOID *ResetData >=20 > + ); >=20 > + >=20 > +#endif >=20 > diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/SataLib.h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/SataLib.h > new file mode 100644 > index 0000000000..bc1555ed19 > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/SataLib.h > @@ -0,0 +1,112 @@ > +/** @file >=20 > + Header file for SataLib. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _SATA_LIB_H_ >=20 > +#define _SATA_LIB_H_ >=20 > + >=20 > +#define SATA_1_CONTROLLER_INDEX 0 >=20 > +#define SATA_2_CONTROLLER_INDEX 1 >=20 > +#define SATA_3_CONTROLLER_INDEX 2 >=20 > + >=20 > +/** >=20 > + Get Maximum Sata Port Number >=20 > + >=20 > + @param[in] SataCtrlIndex SATA controller index >=20 > + >=20 > + @retval Maximum Sata Port Number >=20 > +**/ >=20 > +UINT8 >=20 > +MaxSataPortNum ( >=20 > + IN UINT32 SataCtrlIndex >=20 > + ); >=20 > + >=20 > +/** >=20 > + Gets Maximum Sata Controller Number >=20 > + >=20 > + @retval Maximum Sata Controller Number >=20 > +**/ >=20 > +UINT8 >=20 > +MaxSataControllerNum ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Get SATA controller's Port Present Status >=20 > + >=20 > + @param[in] SataCtrlIndex SATA controller index >=20 > + >=20 > + @retval Port Present Status >=20 > +**/ >=20 > +UINT8 >=20 > +GetSataPortPresentStatus ( >=20 > + IN UINT32 SataCtrlIndex >=20 > + ); >=20 > + >=20 > +/** >=20 > + Get SATA controller Function Disable Status >=20 > + >=20 > + @param[in] SataCtrlIndex SATA controller index >=20 > + >=20 > + @retval 0 SATA Controller is not Function Disabled >=20 > + @retval 1 SATA Controller is Function Disabled >=20 > +**/ >=20 > +BOOLEAN >=20 > +SataControllerFunctionDisableStatus ( >=20 > + IN UINT32 SataCtrlIndex >=20 > + ); >=20 > + >=20 > +/** >=20 > + Get SATA controller ABAR size >=20 > + >=20 > + @param[in] SataCtrlIndex SATA controller index >=20 > + >=20 > + @retval SATA controller ABAR size >=20 > +**/ >=20 > +UINT32 >=20 > +GetSataAbarSize ( >=20 > + IN UINT32 SataCtrlIndex >=20 > + ); >=20 > + >=20 > +/** >=20 > + Get SATA controller AHCI base address >=20 > + >=20 > + @param[in] SataCtrlIndex SATA controller index >=20 > + >=20 > + @retval SATA controller AHCI base address >=20 > +**/ >=20 > +UINT32 >=20 > +GetSataAhciBase ( >=20 > + IN UINT32 SataCtrlIndex >=20 > + ); >=20 > + >=20 > +/** >=20 > + Check if SATA controller supports RST remapping >=20 > + >=20 > + @param[in] SataCtrlIndex SATA controller index >=20 > + >=20 > + @retval TRUE Controller supports remapping >=20 > + @retval FALSE Controller does not support remapping >=20 > +**/ >=20 > +BOOLEAN >=20 > +IsRemappingSupportedOnSata ( >=20 > + IN UINT32 SataCtrlIndex >=20 > + ); >=20 > + >=20 > +/** >=20 > + Checks if SoC supports the SATA PGD power down on given >=20 > + SATA controller. >=20 > + >=20 > + @param[in] SataCtrlIndex SATA controller index >=20 > + >=20 > + @retval TRUE SATA PGD power down supported >=20 > + @retval FALSE SATA PGD power down not supported >=20 > +**/ >=20 > +BOOLEAN >=20 > +IsSataPowerGatingSupported ( >=20 > + IN UINT32 SataCtrlIndex >=20 > + ); >=20 > + >=20 > +#endif // _SATA_LIB_H_ >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/SerialIoAccessLib.h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/SerialIoAccessLib.h > new file mode 100644 > index 0000000000..3c8aae6ac2 > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/SerialIoAccessLib= .h > @@ -0,0 +1,113 @@ > +/** @file >=20 > + Header file for Serial Io Common Lib >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _SERIAL_IO_ACCESS_LIB_H_ >=20 > +#define _SERIAL_IO_ACCESS_LIB_H_ >=20 > + >=20 > +/** >=20 > + Returns BAR0 >=20 > + >=20 > + @param[in] PciCfgBase Pci Config Base >=20 > + >=20 > + @retval 64bit MMIO BAR Address >=20 > +**/ >=20 > +UINT64 >=20 > +GetSerialIoBar ( >=20 > + IN UINT64 PciCfgBase >=20 > + ); >=20 > + >=20 > +/** >=20 > + Returns I2C Pci Config Space >=20 > + >=20 > + @param[in] I2cNumber I2C Number >=20 > + >=20 > + @retval I2C Pci Config Space Address >=20 > +**/ >=20 > +UINT64 >=20 > +GetSerialIoI2cPciCfg ( >=20 > + IN UINT8 I2cNumber >=20 > + ); >=20 > + >=20 > +/** >=20 > + Returns SPI Pci Config Space >=20 > + >=20 > + @param[in] SpiNumber SPI Number >=20 > + >=20 > + @retval SPI Pci Config Space Address >=20 > +**/ >=20 > +UINT64 >=20 > +GetSerialIoSpiPciCfg ( >=20 > + IN UINT8 SpiNumber >=20 > + ); >=20 > + >=20 > +/** >=20 > + Returns UART Pci Config Space >=20 > + >=20 > + @param[in] UartNumber UART Number >=20 > + >=20 > + @retval UART Pci Config Space Address >=20 > +**/ >=20 > +UINT64 >=20 > +GetSerialIoUartPciCfg ( >=20 > + IN UINT8 UartNumber >=20 > + ); >=20 > + >=20 > +/** >=20 > + Checks if Device with given PciDeviceId is one of SerialIo I2C control= lers >=20 > + If yes, its number is returned through I2cIndex parameter, otherwise > I2cIndex is not updated >=20 > + >=20 > + @param[in] PciDevId Device ID >=20 > + @param[out] I2cNumber Number of SerialIo I2C controlle= r >=20 > + >=20 > + @retval TRUE yes it is a SerialIo I2C control= ler >=20 > + @retval FALSE no it isn't a SerialIo I2C contr= oller >=20 > +**/ >=20 > +BOOLEAN >=20 > +IsSerialIoI2cDeviceId ( >=20 > + IN UINT16 PciDevId, >=20 > + OUT UINT8 *I2cNumber >=20 > + ); >=20 > + >=20 > +/** >=20 > + Checks if I2c is Function 0 Enabled >=20 > + >=20 > + @param[in] I2cIndex Number of the SerialIo I2C contr= oller >=20 > + >=20 > + @retval TRUE Enabled >=20 > + @retval FALSE Disabled >=20 > +**/ >=20 > +BOOLEAN >=20 > +IsSerialIoI2cFunction0Enabled ( >=20 > + IN UINT8 I2cIndex >=20 > + ); >=20 > + >=20 > +/** >=20 > + Checks if Uart is Function 0 Enabled >=20 > + >=20 > + @param[in] UartIndex Number of the SerialIo Uart con= troller >=20 > + >=20 > + @retval TRUE Enabled >=20 > + @retval FALSE Disabled >=20 > +**/ >=20 > +BOOLEAN >=20 > +IsSerialIoUartFunction0Enabled ( >=20 > + IN UINT8 UartIndex >=20 > + ); >=20 > + >=20 > +/** >=20 > + Checks if Spi is Function 0 Enabled >=20 > + >=20 > + @param[in] SpiIndex Number of the SerialIo Spi contr= oller >=20 > + >=20 > + @retval TRUE Enabled >=20 > + @retval FALSE Disabled >=20 > +**/ >=20 > +BOOLEAN >=20 > +IsSerialIoSpiFunction0Enabled ( >=20 > + IN UINT8 SpiIndex >=20 > + ); >=20 > + >=20 > +#endif // _SERIAL_IO_ACCESS_LIB_H_ >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/SiConfigBlockLib.h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/SiConfigBlockLib.h > new file mode 100644 > index 0000000000..7732ccf59e > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/SiConfigBlockLib.= h > @@ -0,0 +1,56 @@ > +/** @file >=20 > + Prototype of the SiConfigBlockLib library. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _SI_CONFIG_BLOCK_LIB_H_ >=20 > +#define _SI_CONFIG_BLOCK_LIB_H_ >=20 > + >=20 > + >=20 > +typedef >=20 > +VOID >=20 > +(*LOAD_DEFAULT_FUNCTION) ( >=20 > + IN VOID *ConfigBlockPointer >=20 > + ); >=20 > + >=20 > +typedef struct { >=20 > + EFI_GUID *Guid; >=20 > + UINT16 Size; >=20 > + UINT8 Revision; >=20 > + LOAD_DEFAULT_FUNCTION LoadDefault; >=20 > +} COMPONENT_BLOCK_ENTRY; >=20 > + >=20 > +/** >=20 > + GetComponentConfigBlockTotalSize get config block table total size. >=20 > + >=20 > + @param[in] ComponentBlocks Component blocks array >=20 > + @param[in] TotalBlockCount Number of blocks >=20 > + >=20 > + @retval Size of config block table >=20 > +**/ >=20 > +UINT16 >=20 > +EFIAPI >=20 > +GetComponentConfigBlockTotalSize ( >=20 > + IN COMPONENT_BLOCK_ENTRY *ComponentBlocks, >=20 > + IN UINT16 TotalBlockCount >=20 > + ); >=20 > + >=20 > +/** >=20 > + AddComponentConfigBlocks add all config blocks. >=20 > + >=20 > + @param[in] ConfigBlockTableAddress The pointer to add config blocks >=20 > + @param[in] ComponentBlocks Config blocks array >=20 > + @param[in] TotalBlockCount Number of blocks >=20 > + >=20 > + @retval EFI_SUCCESS The policy default is initialize= d. >=20 > + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create > buffer >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +AddComponentConfigBlocks ( >=20 > + IN VOID *ConfigBlockTableAddress, >=20 > + IN COMPONENT_BLOCK_ENTRY *ComponentBlocks, >=20 > + IN UINT16 TotalBlockCount >=20 > + ); >=20 > +#endif // _SI_CONFIG_BLOCK_LIB_H_ >=20 > diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/SpiAccessL= ib.h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/SpiAccessLib.h > new file mode 100644 > index 0000000000..50f9e048b3 > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/SpiAccessLib.h > @@ -0,0 +1,290 @@ > +/** @file >=20 > + SPI library header for abstraction of SPI HW registers accesses >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _SPI_ACCESS_LIB_H_ >=20 > +#define _SPI_ACCESS_LIB_H_ >=20 > + >=20 > +/** >=20 > + Returns SPI PCI Config Space base address >=20 > + >=20 > + @retval UINT64 SPI Config Space base address >=20 > +**/ >=20 > +UINT64 >=20 > +SpiGetPciCfgAddress ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Returns SPI BAR0 value >=20 > + >=20 > + @retval UINT32 PCH SPI BAR0 value >=20 > +**/ >=20 > +UINT32 >=20 > +SpiGetBar0 ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Returns SPI Device number >=20 > + >=20 > + @retval UINT8 PCH SPI Device number >=20 > +**/ >=20 > +UINT8 >=20 > +SpiDeviceNumber ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Returns SPI Function number >=20 > + >=20 > + @retval UINT8 PCH SPI Function number >=20 > +**/ >=20 > +UINT8 >=20 > +SpiFunctionNumber ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Returns descriptor signature >=20 > + >=20 > + @retval UINT32 Descriptor signature >=20 > +**/ >=20 > +UINT32 >=20 > +SpiGetDescriptorSignature ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Returns supported features and R/W frequencies of Flash Component >=20 > + >=20 > + @retval UINT32 Flash Component features descriptor >=20 > +**/ >=20 > +UINT32 >=20 > +SpiGetFlashComponentDescription ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Returns number of Flash Components >=20 > + >=20 > + @retval UINT32 Flash components number >=20 > +**/ >=20 > +UINT32 >=20 > +SpiGetFlashComponentsNumber ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Returns total Flash size with regards to number of flash components >=20 > + >=20 > + @retval UINT32 Total Flash Memory size >=20 > +**/ >=20 > +UINT32 >=20 > +SpiGetTotalFlashSize ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Checks if PCH SPI Controler is present and available >=20 > + >=20 > + @retval TRUE PCH SPI controller is avaialable >=20 > + @retval FALSE PCH SPI controller is not available >=20 > +**/ >=20 > +BOOLEAN >=20 > +SpiIsControllerAvailable ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Checks BIOS lock bits for proper value and checks if write protection = is > enabled >=20 > + Expected vales are: LE bit set, EISS bit set and WPD bit cleared >=20 > + >=20 > + @retval TRUE All protection bits are set correctly >=20 > + @retval FALSE Not all protection bits had exepcted values >=20 > +**/ >=20 > +BOOLEAN >=20 > +SpiIsWriteProtectionEnabled ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Returns Flash Descriptor Override Pin Strap status >=20 > + >=20 > + @retval TRUE Flash Descriptor override is enabled >=20 > + @retval FALSE Flash Descriptor override is disabled >=20 > +**/ >=20 > +BOOLEAN >=20 > +SpiIsFlashDescriptorOverrideEnabled ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Returns Flash Configuration Lock Down bit status >=20 > + >=20 > + @retval TRUE Flash Configuration Lock Down bit is set >=20 > + @retval FALSE Flash Configuration Lock Down bit is not set >=20 > +**/ >=20 > +BOOLEAN >=20 > +SpiIsFlashConfigurationLockDownEnabled ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Returns Top Swap functionality enable state >=20 > + >=20 > + @retval TRUE Top Swap is enabled >=20 > + @retval FALSE Top Swap is disabled >=20 > +**/ >=20 > +BOOLEAN >=20 > +SpiIsTopSwapEnabled ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Return Component Property Parameter Table for a given component > number >=20 > + >=20 > + @param[in] ComponentNumber SPI Component number >=20 > + @param[out] CppTable Component Poperty Parameter Table value >=20 > + >=20 > + @retval TRUE Vendor Specific Component Capabilities Register value wa= s > read >=20 > + @reval FALSE Vendor Specific Component Capabilities Register value wa= s > not present >=20 > +**/ >=20 > +BOOLEAN >=20 > +SpiGetComponentPropertyParameterTable ( >=20 > + IN UINT8 ComponentNumber, >=20 > + OUT UINT32 *CppTable >=20 > + ); >=20 > + >=20 > +/** >=20 > + Returns valid bit status in given Component Property Parameter Table >=20 > + >=20 > + @param[in] CppTable Component Poperty Parameter Table value >=20 > + >=20 > + @retval TRUE Valid bit is set >=20 > + @reval FALSE Valid bit is not set >=20 > +**/ >=20 > +BOOLEAN >=20 > +SpiIsCppValidBitSet ( >=20 > + IN UINT32 CppTable >=20 > + ); >=20 > + >=20 > +/** >=20 > + Checks if Flash Descriptor is valid >=20 > + >=20 > + @retval TRUE Flash Descriptor is valid >=20 > + @retval FALSE Flash Descriptor is invalid >=20 > +**/ >=20 > +BOOLEAN >=20 > +SpiIsFlashDescriptorValid ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Returns masked BIOS Master Read Access >=20 > + >=20 > + @retval UINT32 Already masked BIOS Master Read Access >=20 > +**/ >=20 > +UINT32 >=20 > +SpiGetMasterReadAccess ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Returns masked BIOS Master Write Access >=20 > + >=20 > + @retval UINT32 Already masked BIOS Master Write Access >=20 > +**/ >=20 > +UINT32 >=20 > +SpiGetMasterWriteAccess ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Returns GbE Region Access rights >=20 > + >=20 > + @retval UINT32 GbE Region access rights >=20 > +**/ >=20 > +UINT32 >=20 > +SpiGetGbeRegionAccess ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Returns CSME region access rights >=20 > + >=20 > + @retval UINT32 CSME Region Access rights >=20 > +**/ >=20 > +UINT32 >=20 > +SpiGetCsmeRegionAccess ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Returns EC region access right >=20 > + >=20 > + @retval UINT32 EC Region access rights >=20 > +**/ >=20 > +UINT32 >=20 > +SpiGetEcRegionAccess ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Checks if Slave Attached Flash (SAF) mode is active >=20 > + >=20 > + @retval TRUE SAF mode is active >=20 > + @retval FALSE SAF mode is not active >=20 > +**/ >=20 > +BOOLEAN >=20 > +SpiIsSafModeActive ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Checks validity of GbE region >=20 > + >=20 > + @retval TRUE GbE region is valid >=20 > + @retval FALSE GbE regios in invalid >=20 > +**/ >=20 > +BOOLEAN >=20 > +SpiIsGbeRegionValid ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Returns status of BIOS Interface Lockdown >=20 > + >=20 > + @retval TRUE BIOS Interface Lockdown is enabled >=20 > + @retval FALSE BIOS Interface Lockdown is disabled >=20 > +**/ >=20 > +BOOLEAN >=20 > +SpiIsBiosInterfaceLockdownEnabled ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Returns TRUE if BIOS Boot Strap is set to SPI >=20 > + >=20 > + @retval TRUE BIOS Boot strap is set to SPI >=20 > + @retval FALSE BIOS Boot strap is set to LPC/eSPI >=20 > +**/ >=20 > +BOOLEAN >=20 > +SpiIsBiosBootFromSpi ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/** >=20 > + Check SPI write status disable is set >=20 > + >=20 > + @retval TRUE Write status disable is set >=20 > + @retval FALSE Write status disable is not set >=20 > +**/ >=20 > +BOOLEAN >=20 > +SpiIsWriteStatusDisable ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +#endif // _SPI_ACCESS_LIB_H_ >=20 > diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/VtdInfoLib= .h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/VtdInfoLib.h > new file mode 100644 > index 0000000000..69eed8d32d > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/VtdInfoLib.h > @@ -0,0 +1,53 @@ > +/** @file >=20 > + Header file for VtdInfoLib. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _VTD_INFO_LIB_H_ >=20 > +#define _VTD_INFO_LIB_H_ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +#define VTD_ENGINE_NUMBER 7 >=20 > + >=20 > +#pragma pack(1) >=20 > + >=20 > +/** >=20 > + Get VTD Engine Base Address from PCD values. >=20 > + >=20 > + @param[in] VtdEngineNumber - Engine number for which VTD Base > Adderess is required. >=20 > + >=20 > + @retval VTD Engine Base Address >=20 > +**/ >=20 > +UINT32 >=20 > +GetVtdBaseAddress ( >=20 > + IN UINT8 VtdEngineNumber >=20 > + ); >=20 > + >=20 > +/** >=20 > + Read VTD Engine Base Address from VTD BAR Offsets. >=20 > + >=20 > + @param[in] VtdEngineNumber - Engine number for which VTD Base > Adderess is required. >=20 > + >=20 > + @retval VTD Engine Base Address >=20 > +**/ >=20 > +UINT32 >=20 > +ReadVtdBaseAddress ( >=20 > + IN UINT8 VtdEngineNumber >=20 > + ); >=20 > + >=20 > +/** >=20 > + GetMaxVtdEngineNumber: Get Maximum Vtd Engine Number >=20 > + >=20 > + @retval Vtd Engine Number >=20 > +**/ >=20 > +UINT8 >=20 > +GetMaxVtdEngineNumber( >=20 > + VOID >=20 > +); >=20 > + >=20 > +#pragma pack() >=20 > +#endif // _VTD_INFO_LIB_H_ >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Include/Ppi/FspmArchConfigPpi.h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/Ppi/FspmArchConfigPpi.h > new file mode 100644 > index 0000000000..f296c780f5 > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Ppi/FspmArchConfigPpi.h > @@ -0,0 +1,32 @@ > +/** @file >=20 > + Header file for FSP-M Arch Config PPI >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +#ifndef _FSPM_ARCH_CONFIG_PPI_H_ >=20 > +#define _FSPM_ARCH_CONFIG_PPI_H_ >=20 > + >=20 > +/// >=20 > +/// Global ID for the FSPM_ARCH_CONFIG_PPI. >=20 > +/// >=20 > +#define FSPM_ARCH_CONFIG_GUID \ >=20 > + { \ >=20 > + 0x824d5a3a, 0xaf92, 0x4c0c, { 0x9f, 0x19, 0x19, 0x52, 0x6d, 0xca, 0x= 4a, > 0xbb } \ >=20 > + } >=20 > + >=20 > +/// >=20 > +/// This PPI provides FSP-M Arch Config PPI. >=20 > +/// >=20 > +typedef struct { >=20 > + UINT8 Revision; >=20 > + UINT8 Reserved[3]; >=20 > + VOID *NvsBufferPtr; >=20 > + UINT32 BootLoaderTolumSize; >=20 > + UINT8 Reserved1[4]; >=20 > +} FSPM_ARCH_CONFIG_PPI; >=20 > + >=20 > +extern EFI_GUID gFspmArchConfigPpiGuid; >=20 > + >=20 > +#endif // _FSPM_ARCH_CONFIG_PPI_H_ >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Include/Ppi/PeiPreMemSiDefaultPolicy.= h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/Ppi/PeiPreMemSiDefaultPolicy.= h > new file mode 100644 > index 0000000000..3fd917c2b9 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/Include/Ppi/PeiPreMemSiDefaultPolicy.= h > @@ -0,0 +1,34 @@ > +/** @file >=20 > + This file defines the function to initialize default silicon policy PP= I. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +#ifndef _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI_H_ >=20 > +#define _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI_H_ >=20 > + >=20 > +// >=20 > +// Forward declaration for the > PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI. >=20 > +// >=20 > +typedef struct _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI > PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI; >=20 > + >=20 > +/** >=20 > + Initialize and install default silicon policy PPI >=20 > +**/ >=20 > +typedef >=20 > +EFI_STATUS >=20 > +(EFIAPI *PEI_PREMEM_POLICY_INIT) ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/// >=20 > +/// This PPI provides function to install default silicon policy >=20 > +/// >=20 > +struct _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI { >=20 > + PEI_PREMEM_POLICY_INIT PeiPreMemPolicyInit; ///< > PeiPreMemPolicyInit() >=20 > +}; >=20 > + >=20 > +extern EFI_GUID gSiPreMemDefaultPolicyInitPpiGuid; >=20 > + >=20 > +#endif // _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI_H_ >=20 > diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Ppi/PeiSiDefaultPo= licy.h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/Ppi/PeiSiDefaultPolicy.h > new file mode 100644 > index 0000000000..9cb34728cc > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Ppi/PeiSiDefaultPolicy.h > @@ -0,0 +1,33 @@ > +/** @file >=20 > + This file defines the function to initialize default silicon policy PP= I. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _PEI_SI_DEFAULT_POLICY_INIT_PPI_H_ >=20 > +#define _PEI_SI_DEFAULT_POLICY_INIT_PPI_H_ >=20 > + >=20 > +// >=20 > +// Forward declaration for the PEI_SI_DEFAULT_POLICY_INIT_PPI. >=20 > +// >=20 > +typedef struct _PEI_SI_DEFAULT_POLICY_INIT_PPI > PEI_SI_DEFAULT_POLICY_INIT_PPI; >=20 > + >=20 > +/** >=20 > + Initialize and install default silicon policy PPI >=20 > +**/ >=20 > +typedef >=20 > +EFI_STATUS >=20 > +(EFIAPI *PEI_POLICY_INIT) ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +/// >=20 > +/// This PPI provides function to install default silicon policy >=20 > +/// >=20 > +struct _PEI_SI_DEFAULT_POLICY_INIT_PPI { >=20 > + PEI_POLICY_INIT PeiPolicyInit; ///< PeiPolicyInit() >=20 > +}; >=20 > + >=20 > +extern EFI_GUID gSiDefaultPolicyInitPpiGuid; >=20 > + >=20 > +#endif // _PEI_SI_DEFAULT_POLICY_INIT_PPI_H_ >=20 > diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Ppi/SiPolicy.h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/Ppi/SiPolicy.h > new file mode 100644 > index 0000000000..eb75c4cc4d > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Ppi/SiPolicy.h > @@ -0,0 +1,79 @@ > +/** @file >=20 > + Silicon Policy PPI is used for specifying platform >=20 > + related Intel silicon information and policy setting. >=20 > + This PPI is consumed by the silicon PEI modules and carried >=20 > + over to silicon DXE modules. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +#ifndef _SI_POLICY_PPI_H_ >=20 > +#define _SI_POLICY_PPI_H_ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +#ifndef DISABLED >=20 > +#define DISABLED 0 >=20 > +#endif >=20 > +#ifndef ENABLED >=20 > +#define ENABLED 1 >=20 > +#endif >=20 > + >=20 > +extern EFI_GUID gSiPreMemPolicyPpiGuid; >=20 > +extern EFI_GUID gSiPolicyPpiGuid; >=20 > + >=20 > + >=20 > +#include >=20 > +extern EFI_GUID gGraphicsPeiPreMemConfigGuid; >=20 > +extern EFI_GUID gGraphicsPeiConfigGuid; >=20 > + >=20 > +#include >=20 > +extern EFI_GUID gVtdConfigGuid; >=20 > + >=20 > +#include >=20 > +extern EFI_GUID gGnaConfigGuid; >=20 > + >=20 > + >=20 > + >=20 > +#include Remove this line. >=20 > +#include >=20 > +extern EFI_GUID gCpuPciePeiPreMemConfigGuid; >=20 > +extern EFI_GUID gCpuPcieRpConfigGuid; >=20 > + >=20 > + >=20 > +#include >=20 > +extern EFI_GUID gHybridGraphicsConfigGuid; >=20 > + >=20 > +#include >=20 > +#include >=20 > +extern EFI_GUID gMemoryConfigGuid; >=20 > +extern EFI_GUID gMemoryConfigNoCrcGuid; >=20 > + >=20 > +#include >=20 > +extern EFI_GUID gSaMiscPeiPreMemConfigGuid; >=20 > + >=20 > +#include >=20 > +extern EFI_GUID gSaMiscPeiConfigGuid; >=20 > + >=20 > + >=20 > +#include >=20 > +extern EFI_GUID gCpuTraceHubConfigGuid; >=20 > + >=20 > +#include >=20 > +extern EFI_GUID gHostBridgePeiPreMemConfigGuid; >=20 > +extern EFI_GUID gHostBridgePeiConfigGuid; >=20 > + >=20 > +#include >=20 > +extern EFI_GUID gCpuDmiPreMemConfigGuid; >=20 > + >=20 > +typedef struct _SI_PREMEM_POLICY_STRUCT SI_PREMEM_POLICY_PPI; >=20 > +typedef struct _SI_POLICY_STRUCT SI_POLICY_PPI; >=20 > + >=20 > +#endif // _SI_POLICY_PPI_H_ >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Include/Protocol/GopComponentName2. > h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/Protocol/GopComponentName2. > h > new file mode 100644 > index 0000000000..1d69ee0e8d > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/Include/Protocol/GopComponentName2. > h > @@ -0,0 +1,61 @@ > +/** @file >=20 > + Protocol to retrieve the GOP driver version >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _GOP_COMPONENT_NAME2_H_ >=20 > +#define _GOP_COMPONENT_NAME2_H_ >=20 > + >=20 > + >=20 > +typedef struct _GOP_COMPONENT_NAME2_PROTOCOL > GOP_COMPONENT_NAME2_PROTOCOL; >=20 > + >=20 > +/// >=20 > +/// GOP Component protocol for retrieving driver name >=20 > +/// >=20 > +typedef >=20 > +EFI_STATUS >=20 > +(EFIAPI *GOP_COMPONENT_NAME2_GET_DRIVER_NAME) ( >=20 > + IN GOP_COMPONENT_NAME2_PROTOCOL * This, >=20 > + IN CHAR8 *Language, >=20 > + OUT CHAR16 **DriverName >=20 > + ); >=20 > + >=20 > +/// >=20 > +/// GOP Component protocol for retrieving controller name >=20 > +/// >=20 > +typedef >=20 > +EFI_STATUS >=20 > +(EFIAPI *GOP_COMPONENT_NAME2_GET_CONTROLLER_NAME) ( >=20 > + IN GOP_COMPONENT_NAME2_PROTOCOL * This, >=20 > + IN EFI_HANDLE ControllerHandle, >=20 > + IN EFI_HANDLE ChildHandle OPTIONAL, >=20 > + IN CHAR8 *Language, >=20 > + OUT CHAR16 **ControllerName >=20 > + ); >=20 > + >=20 > +/// >=20 > +/// GOP Component protocol for retrieving driver version >=20 > +/// >=20 > +typedef >=20 > +EFI_STATUS >=20 > +(EFIAPI *GOP_COMPONENT_NAME2_GET_DRIVER_VERSION) ( >=20 > + IN GOP_COMPONENT_NAME2_PROTOCOL * This, >=20 > + IN CHAR8 *Language, >=20 > + OUT CHAR16 **DriverVersion >=20 > + ); >=20 > + >=20 > +/** >=20 > + GOP Component protocol\n >=20 > + This protocol will be installed by GOP driver and can be used to retri= eve > GOP information. >=20 > +**/ >=20 > +struct _GOP_COMPONENT_NAME2_PROTOCOL { >=20 > + GOP_COMPONENT_NAME2_GET_DRIVER_NAME GetDriverName; > ///< Protocol function to get driver name >=20 > + GOP_COMPONENT_NAME2_GET_DRIVER_VERSION GetDriverVersion; > ///< Protocol function to get driver version >=20 > + GOP_COMPONENT_NAME2_GET_CONTROLLER_NAME > GetControllerName; ///< Protocol function to get controller name >=20 > + CHAR8 *SupportedLanguages; ///< = Number of > Supported languages. >=20 > +}; >=20 > + >=20 > +extern EFI_GUID gGopComponentName2ProtocolGuid; >=20 > + >=20 > +#endif >=20 > diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Protocol/GopPolicy= .h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/Protocol/GopPolicy.h > new file mode 100644 > index 0000000000..c8dc17008e > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Protocol/GopPolicy.h > @@ -0,0 +1,73 @@ > +/** @file >=20 > + Interface definition for GopPolicy Protocol. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _GOP_POLICY_PROTOCOL_H_ >=20 > +#define _GOP_POLICY_PROTOCOL_H_ >=20 > + >=20 > + >=20 > +#define GOP_POLICY_PROTOCOL_REVISION_01 0x01 >=20 > +#define GOP_POLICY_PROTOCOL_REVISION_03 0x03 >=20 > + >=20 > +typedef enum { >=20 > + LidClosed, >=20 > + LidOpen, >=20 > + LidStatusMax >=20 > +} LID_STATUS; >=20 > + >=20 > +typedef enum { >=20 > + Docked, >=20 > + UnDocked, >=20 > + DockStatusMax >=20 > +} DOCK_STATUS; >=20 > + >=20 > +/// >=20 > +/// Function to retrieve LID status >=20 > +/// >=20 > +typedef >=20 > +EFI_STATUS >=20 > +(EFIAPI *GET_PLATFORM_LID_STATUS) ( >=20 > + OUT LID_STATUS * CurrentLidStatus >=20 > + ); >=20 > + >=20 > +/// >=20 > +/// Function to retrieve Dock status >=20 > +/// >=20 > +typedef >=20 > +EFI_STATUS >=20 > +(EFIAPI *GET_PLATFORM_DOCK_STATUS) ( >=20 > + OUT DOCK_STATUS CurrentDockStatus >=20 > +); >=20 > + >=20 > +/// >=20 > +/// Function to retrieve VBT table address and size >=20 > +/// >=20 > +typedef >=20 > +EFI_STATUS >=20 > +(EFIAPI *GET_VBT_DATA) ( >=20 > + OUT EFI_PHYSICAL_ADDRESS * VbtAddress, >=20 > + OUT UINT32 *VbtSize >=20 > + ); >=20 > + >=20 > +/** >=20 > + System Agent Graphics Output Protocol (GOP) - Policy Protocol\n >=20 > + Graphics Output Protocol (GOP) is a UEFI API replacing legacy Video RO= Ms > for EFI boot\n >=20 > + When GOP Driver is used this protocol can be consumed by GOP driver or > platform code for GOP relevant initialization\n >=20 > + All functions in this protocol should be initialized by platform code = basing > on platform implementation\n >=20 > +**/ >=20 > +typedef struct { >=20 > + UINT32 Revision; ///< Protocol revisio= n >=20 > + GET_PLATFORM_LID_STATUS GetPlatformLidStatus; ///< Protocol > function to get Lid Status. Platform code should provide this function ba= sing > on design. >=20 > + GET_VBT_DATA GetVbtData; ///< Protocol functio= n to get Vbt > Data address and size. Platform code should provide this function basing = on > design. >=20 > + GET_PLATFORM_DOCK_STATUS GetPlatformDockStatus; ///< Function > pointer for get platform dock status. >=20 > + EFI_GUID GopOverrideGuid; ///< A GUID provided= by BIOS in > case GOP is to be overridden. >=20 > +} GOP_POLICY_PROTOCOL; >=20 > + >=20 > +extern EFI_GUID gGopPolicyProtocolGuid; >=20 > +extern EFI_GUID gGen12PolicyProtocolGuid; >=20 > +extern EFI_GUID gGen9PolicyProtocolGuid; >=20 > +extern EFI_GUID gIntelGraphicsVbtGuid; >=20 > + >=20 > +#endif >=20 > diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Protocol/IgdOpRegi= on.h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/Protocol/IgdOpRegion.h > new file mode 100644 > index 0000000000..c030f771e3 > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Protocol/IgdOpRegion.h > @@ -0,0 +1,22 @@ > +/** @file >=20 > + This file is part of the IGD OpRegion Implementation. The IGD OpRegio= n is >=20 > + an interface between system BIOS, ASL code, and Graphics drivers. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _IGD_OPREGION_PROTOCOL_H_ >=20 > +#define _IGD_OPREGION_PROTOCOL_H_ >=20 > + >=20 > +#include >=20 > + >=20 > +extern EFI_GUID gIgdOpRegionProtocolGuid; >=20 > + >=20 > +/// >=20 > +/// IGD OpRegion Protocol >=20 > +/// >=20 > +typedef struct { >=20 > + IGD_OPREGION_STRUCTURE *OpRegion; ///< IGD Operation Region > Structure >=20 > +} IGD_OPREGION_PROTOCOL; >=20 > + >=20 > +#endif >=20 > diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Protocol/Spi.h > b/Silicon/Intel/TigerlakeSiliconPkg/Include/Protocol/Spi.h > new file mode 100644 > index 0000000000..c13dc5a5f5 > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Protocol/Spi.h > @@ -0,0 +1,301 @@ > +/** @file >=20 > + This file defines the PCH SPI Protocol which implements the >=20 > + Intel(R) PCH SPI Host Controller Compatibility Interface. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _PCH_SPI_PROTOCOL_H_ >=20 > +#define _PCH_SPI_PROTOCOL_H_ >=20 > + >=20 > +// >=20 > +// Extern the GUID for protocol users. >=20 > +// >=20 > +extern EFI_GUID gPchSpiProtocolGuid; >=20 > +extern EFI_GUID gPchSmmSpiProtocolGuid; >=20 > + >=20 > +// >=20 > +// Forward reference for ANSI C compatibility >=20 > +// >=20 > +typedef struct _PCH_SPI_PROTOCOL PCH_SPI_PROTOCOL; >=20 > + >=20 > +// >=20 > +// SPI protocol data structures and definitions >=20 > +// >=20 > + >=20 > +/** >=20 > + Flash Region Type >=20 > +**/ >=20 > +typedef enum { >=20 > + FlashRegionDescriptor, >=20 > + FlashRegionBios, >=20 > + FlashRegionMe, >=20 > + FlashRegionGbE, >=20 > + FlashRegionPlatformData, >=20 > + FlashRegionDer, >=20 > + FlashRegionSecondaryBios, >=20 > + FlashRegionuCodePatch, >=20 > + FlashRegionEC, >=20 > + FlashRegionDeviceExpansion2, >=20 > + FlashRegionIE, >=20 > + FlashRegion10Gbe_A, >=20 > + FlashRegion10Gbe_B, >=20 > + FlashRegion13, >=20 > + FlashRegion14, >=20 > + FlashRegion15, >=20 > + FlashRegionAll, >=20 > + FlashRegionMax >=20 > +} FLASH_REGION_TYPE; >=20 > +// >=20 > +// Protocol member functions >=20 > +// >=20 > + >=20 > +/** >=20 > + Read data from the flash part. >=20 > + >=20 > + @param[in] This Pointer to the PCH_SPI_PROTOCOL instan= ce. >=20 > + @param[in] FlashRegionType The Flash Region type for flash cycle = which > is listed in the Descriptor. >=20 > + @param[in] Address The Flash Linear Address must fall wit= hin a > region for which BIOS has access permissions. >=20 > + @param[in] ByteCount Number of bytes in the data portion of= the > SPI cycle. >=20 > + @param[out] Buffer The Pointer to caller-allocated buffer > containing the dada received. >=20 > + It is the caller's responsibility to m= ake sure Buffer is large > enough for the total number of bytes read. >=20 > + >=20 > + @retval EFI_SUCCESS Command succeed. >=20 > + @retval EFI_INVALID_PARAMETER The parameters specified are not > valid. >=20 > + @retval EFI_DEVICE_ERROR Device error, command aborts abnormall= y. >=20 > +**/ >=20 > +typedef >=20 > +EFI_STATUS >=20 > +(EFIAPI *PCH_SPI_FLASH_READ) ( >=20 > + IN PCH_SPI_PROTOCOL *This, >=20 > + IN FLASH_REGION_TYPE FlashRegionType, >=20 > + IN UINT32 Address, >=20 > + IN UINT32 ByteCount, >=20 > + OUT UINT8 *Buffer >=20 > + ); >=20 > + >=20 > +/** >=20 > + Write data to the flash part. Remark: Erase may be needed before write= to > the flash part. >=20 > + >=20 > + @param[in] This Pointer to the PCH_SPI_PROTOCOL instan= ce. >=20 > + @param[in] FlashRegionType The Flash Region type for flash cycle = which > is listed in the Descriptor. >=20 > + @param[in] Address The Flash Linear Address must fall wit= hin a > region for which BIOS has access permissions. >=20 > + @param[in] ByteCount Number of bytes in the data portion of= the > SPI cycle. >=20 > + @param[in] Buffer Pointer to caller-allocated buffer con= taining the > data sent during the SPI cycle. >=20 > + >=20 > + @retval EFI_SUCCESS Command succeed. >=20 > + @retval EFI_INVALID_PARAMETER The parameters specified are not > valid. >=20 > + @retval EFI_DEVICE_ERROR Device error, command aborts abnormall= y. >=20 > +**/ >=20 > +typedef >=20 > +EFI_STATUS >=20 > +(EFIAPI *PCH_SPI_FLASH_WRITE) ( >=20 > + IN PCH_SPI_PROTOCOL *This, >=20 > + IN FLASH_REGION_TYPE FlashRegionType, >=20 > + IN UINT32 Address, >=20 > + IN UINT32 ByteCount, >=20 > + IN UINT8 *Buffer >=20 > + ); >=20 > + >=20 > +/** >=20 > + Erase some area on the flash part. >=20 > + >=20 > + @param[in] This Pointer to the PCH_SPI_PROTOCOL instan= ce. >=20 > + @param[in] FlashRegionType The Flash Region type for flash cycle = which > is listed in the Descriptor. >=20 > + @param[in] Address The Flash Linear Address must fall wit= hin a > region for which BIOS has access permissions. >=20 > + @param[in] ByteCount Number of bytes in the data portion of= the > SPI cycle. >=20 > + >=20 > + @retval EFI_SUCCESS Command succeed. >=20 > + @retval EFI_INVALID_PARAMETER The parameters specified are not > valid. >=20 > + @retval EFI_DEVICE_ERROR Device error, command aborts abnormall= y. >=20 > +**/ >=20 > +typedef >=20 > +EFI_STATUS >=20 > +(EFIAPI *PCH_SPI_FLASH_ERASE) ( >=20 > + IN PCH_SPI_PROTOCOL *This, >=20 > + IN FLASH_REGION_TYPE FlashRegionType, >=20 > + IN UINT32 Address, >=20 > + IN UINT32 ByteCount >=20 > + ); >=20 > + >=20 > +/** >=20 > + Read SFDP data from the flash part. >=20 > + >=20 > + @param[in] This Pointer to the PCH_SPI_PROTOCOL instan= ce. >=20 > + @param[in] ComponentNumber The Componen Number for chip select >=20 > + @param[in] Address The starting byte address for SFDP dat= a read. >=20 > + @param[in] ByteCount Number of bytes in SFDP data portion o= f the > SPI cycle >=20 > + @param[out] SfdpData The Pointer to caller-allocated buffer > containing the SFDP data received >=20 > + It is the caller's responsibility to m= ake sure Buffer is large > enough for the total number of bytes read >=20 > + >=20 > + @retval EFI_SUCCESS Command succeed. >=20 > + @retval EFI_INVALID_PARAMETER The parameters specified are not > valid. >=20 > + @retval EFI_DEVICE_ERROR Device error, command aborts abnormall= y. >=20 > +**/ >=20 > +typedef >=20 > +EFI_STATUS >=20 > +(EFIAPI *PCH_SPI_FLASH_READ_SFDP) ( >=20 > + IN PCH_SPI_PROTOCOL *This, >=20 > + IN UINT8 ComponentNumber, >=20 > + IN UINT32 Address, >=20 > + IN UINT32 ByteCount, >=20 > + OUT UINT8 *SfdpData >=20 > + ); >=20 > + >=20 > +/** >=20 > + Read Jedec Id from the flash part. >=20 > + >=20 > + @param[in] This Pointer to the PCH_SPI_PROTOCOL instan= ce. >=20 > + @param[in] ComponentNumber The Componen Number for chip select >=20 > + @param[in] ByteCount Number of bytes in JedecId data portio= n of > the SPI cycle, the data size is 3 typically >=20 > + @param[out] JedecId The Pointer to caller-allocated buffer > containing JEDEC ID received >=20 > + It is the caller's responsibility to m= ake sure Buffer is large > enough for the total number of bytes read. >=20 > + >=20 > + @retval EFI_SUCCESS Command succeed. >=20 > + @retval EFI_INVALID_PARAMETER The parameters specified are not > valid. >=20 > + @retval EFI_DEVICE_ERROR Device error, command aborts abnormall= y. >=20 > +**/ >=20 > +typedef >=20 > +EFI_STATUS >=20 > +(EFIAPI *PCH_SPI_FLASH_READ_JEDEC_ID) ( >=20 > + IN PCH_SPI_PROTOCOL *This, >=20 > + IN UINT8 ComponentNumber, >=20 > + IN UINT32 ByteCount, >=20 > + OUT UINT8 *JedecId >=20 > + ); >=20 > + >=20 > +/** >=20 > + Write the status register in the flash part. >=20 > + >=20 > + @param[in] This Pointer to the PCH_SPI_PROTOCOL instan= ce. >=20 > + @param[in] ByteCount Number of bytes in Status data portion= of the > SPI cycle, the data size is 1 typically >=20 > + @param[in] StatusValue The Pointer to caller-allocated buffer > containing the value of Status register writing >=20 > + >=20 > + @retval EFI_SUCCESS Command succeed. >=20 > + @retval EFI_INVALID_PARAMETER The parameters specified are not > valid. >=20 > + @retval EFI_DEVICE_ERROR Device error, command aborts abnormall= y. >=20 > +**/ >=20 > +typedef >=20 > +EFI_STATUS >=20 > +(EFIAPI *PCH_SPI_FLASH_WRITE_STATUS) ( >=20 > + IN PCH_SPI_PROTOCOL *This, >=20 > + IN UINT32 ByteCount, >=20 > + IN UINT8 *StatusValue >=20 > + ); >=20 > + >=20 > +/** >=20 > + Read status register in the flash part. >=20 > + >=20 > + @param[in] This Pointer to the PCH_SPI_PROTOCOL instan= ce. >=20 > + @param[in] ByteCount Number of bytes in Status data portion= of the > SPI cycle, the data size is 1 typically >=20 > + @param[out] StatusValue The Pointer to caller-allocated buffer > containing the value of Status register received. >=20 > + >=20 > + @retval EFI_SUCCESS Command succeed. >=20 > + @retval EFI_INVALID_PARAMETER The parameters specified are not > valid. >=20 > + @retval EFI_DEVICE_ERROR Device error, command aborts abnormall= y. >=20 > +**/ >=20 > +typedef >=20 > +EFI_STATUS >=20 > +(EFIAPI *PCH_SPI_FLASH_READ_STATUS) ( >=20 > + IN PCH_SPI_PROTOCOL *This, >=20 > + IN UINT32 ByteCount, >=20 > + OUT UINT8 *StatusValue >=20 > + ); >=20 > + >=20 > +/** >=20 > + Get the SPI region base and size, based on the enum type >=20 > + >=20 > + @param[in] This Pointer to the PCH_SPI_PROTOCOL instan= ce. >=20 > + @param[in] FlashRegionType The Flash Region type for for the base > address which is listed in the Descriptor. >=20 > + @param[out] BaseAddress The Flash Linear Address for the Regio= n 'n' > Base >=20 > + @param[out] RegionSize The size for the Region 'n' >=20 > + >=20 > + @retval EFI_SUCCESS Read success >=20 > + @retval EFI_INVALID_PARAMETER Invalid region type given >=20 > + @retval EFI_DEVICE_ERROR The region is not used >=20 > +**/ >=20 > +typedef >=20 > +EFI_STATUS >=20 > +(EFIAPI *PCH_SPI_GET_REGION_ADDRESS) ( >=20 > + IN PCH_SPI_PROTOCOL *This, >=20 > + IN FLASH_REGION_TYPE FlashRegionType, >=20 > + OUT UINT32 *BaseAddress, >=20 > + OUT UINT32 *RegionSize >=20 > + ); >=20 > + >=20 > +/** >=20 > + Read PCH Soft Strap Values >=20 > + >=20 > + @param[in] This Pointer to the PCH_SPI_PROTOCOL instan= ce. >=20 > + @param[in] SoftStrapAddr PCH Soft Strap address offset from FPS= BA. >=20 > + @param[in] ByteCount Number of bytes in SoftStrap data port= ion of > the SPI cycle >=20 > + @param[out] SoftStrapValue The Pointer to caller-allocated buffer > containing PCH Soft Strap Value. >=20 > + If the value of ByteCount is 0, the da= ta type of > SoftStrapValue should be UINT16 and SoftStrapValue will be PCH Soft Strap > Length >=20 > + It is the caller's responsibility to m= ake sure Buffer is large > enough for the total number of bytes read. >=20 > + >=20 > + @retval EFI_SUCCESS Command succeed. >=20 > + @retval EFI_INVALID_PARAMETER The parameters specified are not > valid. >=20 > + @retval EFI_DEVICE_ERROR Device error, command aborts abnormall= y. >=20 > +**/ >=20 > +typedef >=20 > +EFI_STATUS >=20 > +(EFIAPI *PCH_SPI_READ_PCH_SOFTSTRAP) ( >=20 > + IN PCH_SPI_PROTOCOL *This, >=20 > + IN UINT32 SoftStrapAddr, >=20 > + IN UINT32 ByteCount, >=20 > + OUT VOID *SoftStrapValue >=20 > + ); >=20 > + >=20 > +/** >=20 > + Read CPU Soft Strap Values >=20 > + >=20 > + @param[in] This Pointer to the PCH_SPI_PROTOCOL instan= ce. >=20 > + @param[in] SoftStrapAddr CPU Soft Strap address offset from > FCPUSBA. >=20 > + @param[in] ByteCount Number of bytes in SoftStrap data port= ion of > the SPI cycle. >=20 > + @param[out] SoftStrapValue The Pointer to caller-allocated buffer > containing CPU Soft Strap Value. >=20 > + If the value of ByteCount is 0, the da= ta type of > SoftStrapValue should be UINT16 and SoftStrapValue will be PCH Soft Strap > Length >=20 > + It is the caller's responsibility to m= ake sure Buffer is large > enough for the total number of bytes read. >=20 > + >=20 > + @retval EFI_SUCCESS Command succeed. >=20 > + @retval EFI_INVALID_PARAMETER The parameters specified are not > valid. >=20 > + @retval EFI_DEVICE_ERROR Device error, command aborts abnormall= y. >=20 > +**/ >=20 > +typedef >=20 > +EFI_STATUS >=20 > +(EFIAPI *PCH_SPI_READ_CPU_SOFTSTRAP) ( >=20 > + IN PCH_SPI_PROTOCOL *This, >=20 > + IN UINT32 SoftStrapAddr, >=20 > + IN UINT32 ByteCount, >=20 > + OUT VOID *SoftStrapValue >=20 > + ); >=20 > + >=20 > +/** >=20 > + These protocols/PPI allows a platform module to perform SPI operations > through the >=20 > + Intel PCH SPI Host Controller Interface. >=20 > +**/ >=20 > +struct _PCH_SPI_PROTOCOL { >=20 > + /** >=20 > + This member specifies the revision of this structure. This field is = used to >=20 > + indicate backwards compatible changes to the protocol. >=20 > + **/ >=20 > + UINT8 Revision; >=20 > + PCH_SPI_FLASH_READ FlashRead; ///< Read data f= rom the > flash part. >=20 > + PCH_SPI_FLASH_WRITE FlashWrite; ///< Write data = to the flash > part. Remark: Erase may be needed before write to the flash part. >=20 > + PCH_SPI_FLASH_ERASE FlashErase; ///< Erase some = area on the > flash part. >=20 > + PCH_SPI_FLASH_READ_SFDP FlashReadSfdp; ///< Read SFDP d= ata > from the flash part. >=20 > + PCH_SPI_FLASH_READ_JEDEC_ID FlashReadJedecId; ///< Read Jedec > Id from the flash part. >=20 > + PCH_SPI_FLASH_WRITE_STATUS FlashWriteStatus; ///< Write the > status register in the flash part. >=20 > + PCH_SPI_FLASH_READ_STATUS FlashReadStatus; ///< Read status > register in the flash part. >=20 > + PCH_SPI_GET_REGION_ADDRESS GetRegionAddress; ///< Get the SPI > region base and size >=20 > + PCH_SPI_READ_PCH_SOFTSTRAP ReadPchSoftStrap; ///< Read PCH > Soft Strap Values >=20 > + PCH_SPI_READ_CPU_SOFTSTRAP ReadCpuSoftStrap; ///< Read CPU > Soft Strap Values >=20 > +}; >=20 > + >=20 > +/** >=20 > + PCH SPI PPI/PROTOCOL revision number >=20 > + >=20 > + Revision 1: Initial version >=20 > +**/ >=20 > +#define PCH_SPI_SERVICES_REVISION 1 >=20 > + >=20 > +#endif >=20 > -- > 2.24.0.windows.2