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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Nate DeSimone > -----Original Message----- > From: Luo, Heng > Sent: Sunday, January 31, 2021 5:36 PM > To: devel@edk2.groups.io > Cc: Chaganty, Rangasai V ; Desimone, > Nathaniel L > Subject: [PATCH 11/40] TigerlakeSiliconPkg/Fru: Add TglPch/Include header= s >=20 > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3171 >=20 > Adds the following header files: > * Fru/TglPch/Include >=20 > Cc: Sai Chaganty > Cc: Nate DeSimone > Signed-off-by: Heng Luo > --- > Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/Include/PchBdfAssignment.h > | 326 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/Include/PchPcieRpInfo.h = | > 16 ++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/Include/PchReservedResources= . > h | 55 > +++++++++++++++++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 397 insertions(+) >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/Include/PchBdfAssignment.h > b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/Include/PchBdfAssignment.h > new file mode 100644 > index 0000000000..0d00f25d5e > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/Include/PchBdfAssignment.h > @@ -0,0 +1,326 @@ > +/** @file >=20 > + Header file for TigerLake PCH devices PCI Bus Device Function map. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _PCH_BDF_ASSIGNMENT_H_ >=20 > +#define _PCH_BDF_ASSIGNMENT_H_ >=20 > + >=20 > +#define NOT_PRESENT 0xFF >=20 > + >=20 > +#define MAX_SATA_CONTROLLER 1 >=20 > + >=20 > +// >=20 > +// PCH PCIe Controllers >=20 > +// >=20 > +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_1 28 >=20 > +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_2 28 >=20 > +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_3 28 >=20 > +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_4 28 >=20 > +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_5 28 >=20 > +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_6 28 >=20 > +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_7 28 >=20 > +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_8 28 >=20 > +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_9 29 >=20 > +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_10 29 >=20 > +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_11 29 >=20 > +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_12 29 >=20 > +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_13 29 >=20 > +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_14 29 >=20 > +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_15 29 >=20 > +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_16 29 >=20 > +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_17 27 >=20 > +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_18 27 >=20 > +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_19 27 >=20 > +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_20 27 >=20 > +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_21 27 >=20 > +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_22 27 >=20 > +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_23 27 >=20 > +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_24 27 >=20 > +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_25 > NOT_PRESENT >=20 > +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_26 > NOT_PRESENT >=20 > +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_27 > NOT_PRESENT >=20 > +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_28 > NOT_PRESENT >=20 > + >=20 > +// >=20 > +// USB3 (XHCI) Controller PCI config >=20 > +// >=20 > +#define PCI_DEVICE_NUMBER_PCH_XHCI 20 >=20 > +#define PCI_FUNCTION_NUMBER_PCH_XHCI 0 >=20 > + >=20 > +// >=20 > +// xDCI (OTG) USB Device Controller >=20 > +// >=20 > +#define PCI_DEVICE_NUMBER_PCH_XDCI 20 >=20 > +#define PCI_FUNCTION_NUMBER_PCH_XDCI 1 >=20 > + >=20 > +// >=20 > +// Thermal Device >=20 > +// >=20 > +#define PCI_DEVICE_NUMBER_PCH_THERMAL NOT_PRESENT >=20 > +#define PCI_FUNCTION_NUMBER_PCH_THERMAL NOT_PRESENT >=20 > + >=20 > +// >=20 > +// CSME HECI #1 >=20 > +// >=20 > +#define PCI_DEVICE_NUMBER_PCH_HECI1 22 >=20 > +#define PCI_FUNCTION_NUMBER_PCH_HECI1 0 >=20 > + >=20 > +// >=20 > +// CSME HECI #2 >=20 > +// >=20 > +#define PCI_DEVICE_NUMBER_PCH_HECI2 22 >=20 > +#define PCI_FUNCTION_NUMBER_PCH_HECI2 1 >=20 > + >=20 > +// >=20 > +// CSME IDE-Redirection (IDE-R) >=20 > +// >=20 > +#define PCI_DEVICE_NUMBER_PCH_IDER 22 >=20 > +#define PCI_FUNCTION_NUMBER_PCH_IDER 2 >=20 > + >=20 > +// >=20 > +// CSME Keyboard and Text (KT) Redirection >=20 > +// >=20 > +#define PCI_DEVICE_NUMBER_PCH_KTR 22 >=20 > +#define PCI_FUNCTION_NUMBER_PCH_KTR 3 >=20 > + >=20 > +// >=20 > +// CSME HECI #3 >=20 > +// >=20 > +#define PCI_DEVICE_NUMBER_PCH_HECI3 22 >=20 > +#define PCI_FUNCTION_NUMBER_PCH_HECI3 4 >=20 > + >=20 > +// >=20 > +// CSME HECI #4 >=20 > +// >=20 > +#define PCI_DEVICE_NUMBER_PCH_HECI4 22 >=20 > +#define PCI_FUNCTION_NUMBER_PCH_HECI4 5 >=20 > + >=20 > +// >=20 > +// CSME MROM >=20 > +// >=20 > +#define PCI_DEVICE_NUMBER_PCH_MROM NOT_PRESENT >=20 > +#define PCI_FUNCTION_NUMBER_PCH_MROM NOT_PRESENT >=20 > + >=20 > +// >=20 > +// CSME WLAN >=20 > +// >=20 > +#define PCI_DEVICE_NUMBER_PCH_WLAN 22 >=20 > +#define PCI_FUNCTION_NUMBER_PCH_WLAN 7 >=20 > + >=20 > +// >=20 > +// SATA Controllers >=20 > +// >=20 > +#define PCI_DEVICE_NUMBER_PCH_SATA_1 23 >=20 > +#define PCI_FUNCTION_NUMBER_PCH_SATA_1 0 >=20 > +#define PCI_DEVICE_NUMBER_PCH_SATA_2 NOT_PRESENT >=20 > +#define PCI_FUNCTION_NUMBER_PCH_SATA_2 NOT_PRESENT >=20 > +#define PCI_DEVICE_NUMBER_PCH_SATA_3 NOT_PRESENT >=20 > +#define PCI_FUNCTION_NUMBER_PCH_SATA_3 NOT_PRESENT >=20 > + >=20 > +// >=20 > +// PCH LP Serial IO I2C #0 Controller >=20 > +// >=20 > +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C0 21 >=20 > +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C0 0 >=20 > + >=20 > +// >=20 > +// PCH LP Serial IO I2C #1 Controller >=20 > +// >=20 > +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C1 21 >=20 > +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C1 1 >=20 > + >=20 > +// >=20 > +// PCH LP Serial IO I2C #2 Controller >=20 > +// >=20 > +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C2 21 >=20 > +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C2 2 >=20 > + >=20 > +// >=20 > +// PCH LP Serial IO I2C #3 Controller >=20 > +// >=20 > +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C3 21 >=20 > +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C3 3 >=20 > + >=20 > +// >=20 > +// PCH LP Serial IO I2C #4 Controller >=20 > +// >=20 > +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C4 25 >=20 > +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C4 0 >=20 > + >=20 > +// >=20 > +// PCH LP Serial IO I2C #5 Controller >=20 > +// >=20 > +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C5 25 >=20 > +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C5 1 >=20 > + >=20 > +// >=20 > +// PCH LP Serial IO I2C #6 Controller >=20 > +// >=20 > +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C6 16 >=20 > +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C6 0 >=20 > + >=20 > +// >=20 > +// PCH LP Serial IO I2C #7 Controller >=20 > +// >=20 > +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C7 16 >=20 > +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C7 1 >=20 > + >=20 > +// >=20 > +// PCH LP Serial IO SPI #0 Controller >=20 > +// >=20 > +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_SPI0 30 >=20 > +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_SPI0 2 >=20 > + >=20 > +// >=20 > +// PCH LP Serial IO SPI #1 Controller >=20 > +// >=20 > +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_SPI1 30 >=20 > +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_SPI1 3 >=20 > + >=20 > +// >=20 > +// PCH LP Serial IO SPI #2 Controller >=20 > +// >=20 > +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_SPI2 18 >=20 > +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_SPI2 6 >=20 > + >=20 > +// >=20 > +// PCH LP Serial IO SPI #3 Controller >=20 > +// >=20 > +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_SPI3 19 >=20 > +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_SPI3 0 >=20 > + >=20 > +// >=20 > +// PCH LP Serial IO SPI #4 Controller >=20 > +// >=20 > +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_SPI4 19 >=20 > +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_SPI4 1 >=20 > + >=20 > +// >=20 > +// PCH LP Serial IO SPI #5 Controller >=20 > +// >=20 > +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_SPI5 19 >=20 > +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_SPI5 2 >=20 > + >=20 > +// >=20 > +// PCH LP Serial IO SPI #6 Controller >=20 > +// >=20 > +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_SPI6 19 >=20 > +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_SPI6 3 >=20 > + >=20 > +// >=20 > +// PCH LP Serial IO UART #0 Controller >=20 > +// >=20 > +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_UART0 30 >=20 > +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART0 0 >=20 > + >=20 > +// >=20 > +// PCH LP Serial IO UART #1 Controller >=20 > +// >=20 > +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_UART1 30 >=20 > +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART1 1 >=20 > + >=20 > +// >=20 > +// PCH LP Serial IO UART #2 Controller >=20 > +// >=20 > +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_UART2 25 >=20 > +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART2 2 >=20 > + >=20 > +// >=20 > +// PCH LP Serial IO UART #3 Controller >=20 > +// >=20 > +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_UART3 17 >=20 > +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART3 0 >=20 > + >=20 > +// >=20 > +// PCH LP Serial IO UART #4 Controller >=20 > +// >=20 > +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_UART4 17 >=20 > +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART4 1 >=20 > + >=20 > +// >=20 > +// PCH LP Serial IO UART #5 Controller >=20 > +// >=20 > +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_UART5 17 >=20 > +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART5 2 >=20 > + >=20 > +// >=20 > +// PCH LP Serial IO UART #6 Controller >=20 > +// >=20 > +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_UART6 17 >=20 > +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART6 3 >=20 > + >=20 > +// >=20 > +// DMA-SMBus Controller >=20 > +// >=20 > +#define PCI_DEVICE_NUMBER_PCH_DMA_SMBUS 30 >=20 > +#define PCI_FUNCTION_NUMBER_PCH_DMA_SMBUS 4 >=20 > + >=20 > +// >=20 > +// TSN GbE Controller #1 >=20 > +// >=20 > +#define PCI_DEVICE_NUMBER_PCH_TSN0 30 >=20 > +#define PCI_FUNCTION_NUMBER_PCH_TSN0 4 >=20 > + >=20 > +// >=20 > +// TSN GbE Controller #2 >=20 > +// >=20 > +#define PCI_DEVICE_NUMBER_PCH_TSN1 30 >=20 > +#define PCI_FUNCTION_NUMBER_PCH_TSN1 5 >=20 > + >=20 > +// >=20 > +// LPC Controller >=20 > +// >=20 > +#define PCI_DEVICE_NUMBER_PCH_LPC 31 >=20 > +#define PCI_FUNCTION_NUMBER_PCH_LPC 0 >=20 > + >=20 > +// >=20 > +// eSPI Controller >=20 > +// >=20 > +#define PCI_DEVICE_NUMBER_PCH_ESPI 31 >=20 > +#define PCI_FUNCTION_NUMBER_PCH_ESPI 0 >=20 > + >=20 > +// >=20 > +// Primary to Sideband (P2SB) Bridge >=20 > +// >=20 > +#define PCI_DEVICE_NUMBER_PCH_P2SB 31 >=20 > +#define PCI_FUNCTION_NUMBER_PCH_P2SB 1 >=20 > + >=20 > +// >=20 > +// PMC (D31:F2) >=20 > +// >=20 > +#define PCI_DEVICE_NUMBER_PCH_PMC 31 >=20 > +#define PCI_FUNCTION_NUMBER_PCH_PMC 2 >=20 > + >=20 > +// >=20 > +// PMC SSRAM Registers >=20 > +// >=20 > +#define PCI_DEVICE_NUMBER_PCH_PMC_SSRAM 20 >=20 > +#define PCI_FUNCTION_NUMBER_PCH_PMC_SSRAM 2 >=20 > + >=20 > +// >=20 > +// HD-A Controller >=20 > +// >=20 > +#define PCI_DEVICE_NUMBER_PCH_HDA 31 >=20 > +#define PCI_FUNCTION_NUMBER_PCH_HDA 3 >=20 > + >=20 > +// >=20 > +// SMBus Controller >=20 > +// >=20 > +#define PCI_DEVICE_NUMBER_PCH_SMBUS 31 >=20 > +#define PCI_FUNCTION_NUMBER_PCH_SMBUS 4 >=20 > + >=20 > +// >=20 > +// SPI Controller (D31:F5) >=20 > +// >=20 > +#define PCI_DEVICE_NUMBER_PCH_SPI 31 >=20 > +#define PCI_FUNCTION_NUMBER_PCH_SPI 5 >=20 > + >=20 > +// >=20 > +// Gigabit Ethernet LAN Controller (D31:F6) >=20 > +// >=20 > +#define PCI_DEVICE_NUMBER_GBE 31 >=20 > +#define PCI_FUNCTION_NUMBER_GBE 6 >=20 > + >=20 > +#endif // _PCH_BDF_ASSIGNMENT_H_ >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/Include/PchPcieRpInfo.h > b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/Include/PchPcieRpInfo.h > new file mode 100644 > index 0000000000..d3548796a3 > --- /dev/null > +++ b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/Include/PchPcieRpInfo.= h > @@ -0,0 +1,16 @@ > +/** @file >=20 > + Pcie Root Port info header >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +#ifndef _PCH_PCIERP_INFO_H_ >=20 > +#define _PCH_PCIERP_INFO_H_ >=20 > + >=20 > +// >=20 > +// Number of PCIe ports per PCIe controller >=20 > +// >=20 > +#define PCH_PCIE_CONTROLLER_PORTS 4u >=20 > + >=20 > +#endif >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/Include/PchReservedResourc > es.h > b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/Include/PchReservedResourc > es.h > new file mode 100644 > index 0000000000..283246692f > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/Include/PchReservedResourc > es.h > @@ -0,0 +1,55 @@ > +/** @file >=20 > + PCH preserved MMIO resource definitions. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _PCH_PRESERVED_RESOURCES_H_ >=20 > +#define _PCH_PRESERVED_RESOURCES_H_ >=20 > + >=20 > +/** >=20 > + Detailed recommended static allocation >=20 > + +---------------------------------------------------------------------= ----+ >=20 > + | PCH preserved MMIO range, 32 MB, from 0xFC800000 to 0xFE7FFFFF > | >=20 > + +---------------------------------------------------------------------= ----+ >=20 > + | Size | Start | End | Usage = | >=20 > + | 8 MB | 0xFC800000 | 0xFCFFFFFF | TraceHub SW BAR = | >=20 > + | 16 MB | 0xFD000000 | 0xFDFFFFFF | SBREG = | >=20 > + | 64 KB | 0xFE000000 | 0xFE00FFFF | PMC MBAR = | >=20 > + | 4 KB | 0xFE010000 | 0xFE010FFF | SPI BAR0 = | >=20 > + | 176 KB | 0xFE020000 | 0xFE04BFFF | SerialIo BAR in ACPI mode = | >=20 > + | 400 KB | 0xFE04C000 | 0xFE0AFFFF | Unused = | >=20 > + | 64 KB | 0xFE0B0000 | 0xFE0BFFFF | eSPI LGMR BAR = | >=20 > + | 64 KB | 0xFE0C0000 | 0xFE0CFFFF | eSPI2 SEGMR BAR = | >=20 > + | 192 KB | 0xFE0D0000 | 0xFE0FFFFF | Unused = | >=20 > + | 1 MB | 0xFE100000 | 0xFE1FFFFF | TraceHub MTB BAR = | >=20 > + | 2 MB | 0xFE200000 | 0xFE3FFFFF | TraceHub FW BAR = | >=20 > + | 2 MB | 0xFE400000 | 0xFE5FFFFF | Unused = | >=20 > + | 2 MB | 0xFE600000 | 0xFE7FFFFF | Temp address = | >=20 > + +---------------------------------------------------------------------= ----+ >=20 > +**/ >=20 > +#define PCH_PRESERVED_BASE_ADDRESS 0xFC800000 ///< Pch > preserved MMIO base address >=20 > +#define PCH_PRESERVED_MMIO_SIZE 0x02000000 ///< 32MB >=20 > +#define PCH_TRACE_HUB_SW_BASE_ADDRESS 0xFC800000 ///< > TraceHub SW MMIO base address >=20 > +#define PCH_TRACE_HUB_SW_MMIO_SIZE 0x00800000 ///< 8MB >=20 > +#define PCH_PCR_BASE_ADDRESS 0xFD000000 ///< SBREG MMIO > base address >=20 > +#define PCH_PCR_MMIO_SIZE 0x01000000 ///< 16MB >=20 > +#define PCH_PWRM_BASE_ADDRESS 0xFE000000 ///< PMC MBAR > MMIO base address >=20 > +#define PCH_PWRM_MMIO_SIZE 0x00010000 ///< 64KB >=20 > +#define PCH_SPI_BASE_ADDRESS 0xFE010000 ///< SPI BAR0 MMI= O > base address >=20 > +#define PCH_SPI_MMIO_SIZE 0x00001000 ///< 4KB >=20 > +#define PCH_SERIAL_IO_BASE_ADDRESS 0xFE020000 ///< SerialIo > MMIO base address >=20 > +#define PCH_SERIAL_IO_MMIO_SIZE 0x0002C000 ///< 176KB >=20 > +#define PCH_ESPI_LGMR_BASE_ADDRESS 0xFE0B0000 ///< eSPI LGMR > MMIO base address >=20 > +#define PCH_ESPI_LGMR_MMIO_SIZE 0x00010000 ///< 64KB >=20 > +#define PCH_ESPI_SEGMR_BASE_ADDRESS 0xFE0C0000 ///< Second > eSPI GMR MMIO base address >=20 > +#define PCH_ESPI_SEGMR_MMIO_SIZE 0x00010000 ///< 64KB >=20 > +#define PCH_TRACE_HUB_MTB_BASE_ADDRESS 0xFE100000 ///< > TraceHub MTB MMIO base address >=20 > +#define PCH_TRACE_HUB_MTB_MMIO_SIZE 0x00100000 ///< 1MB >=20 > +#define PCH_TRACE_HUB_FW_BASE_ADDRESS 0xFE200000 ///< > TraceHub FW MMIO base address >=20 > +#define PCH_TRACE_HUB_FW_MMIO_SIZE 0x00200000 ///< 2MB >=20 > +#define PCH_TEMP_BASE_ADDRESS 0xFE600000 ///< preserved > temp address for misc usage, >=20 > +#define PCH_TEMP_MMIO_SIZE 0x00200000 ///< 2MB >=20 > + >=20 > +#endif // _PCH_PRESERVED_RESOURCES_H_ >=20 > + >=20 > -- > 2.24.0.windows.2