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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Nate DeSimone > -----Original Message----- > From: Luo, Heng > Sent: Sunday, January 31, 2021 5:37 PM > To: devel@edk2.groups.io > Cc: Chaganty, Rangasai V ; Desimone, > Nathaniel L > Subject: [PATCH 30/40] TigerlakeSiliconPkg/IpBlock: Add Vtd component >=20 > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3171 >=20 > Adds the following files: > * IpBlock/Vtd/IncludePrivate > * IpBlock/Vtd/Library > * IpBlock/Vtd/LibraryPrivate >=20 > Cc: Sai Chaganty > Cc: Nate DeSimone > Signed-off-by: Heng Luo > --- >=20 > Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Vtd/IncludePrivate/Library/DxeV= tdI > nitLib.h | 62 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Vtd/IncludePrivate/Library/DxeV= td > PolicyLib.h | 67 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++ > Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Vtd/IncludePrivate/VtdDataHob.= h > | 32 ++++++++++++++++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Vtd/Library/PeiDxeSmmVtdInfoLib= / > PeiDxeSmmVtdInfoLib.inf | 45 > +++++++++++++++++++++++++++++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Vtd/Library/PeiDxeSmmVtdInfoLib= / > VtdInfoLib.c | 86 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Vtd/LibraryPrivate/DxeVtdInitLi= b/D > xeVtdInitLib.c | 684 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Vtd/LibraryPrivate/DxeVtdInitLi= b/D > xeVtdInitLib.inf | 71 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Vtd/LibraryPrivate/DxeVtdPolicy= Lib > /DxeVtdPolicyLib.c | 90 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Vtd/LibraryPrivate/DxeVtdPolicy= Lib > /DxeVtdPolicyLib.inf | 35 +++++++++++++++++++++++++++++++++++ > 9 files changed, 1172 insertions(+) >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Vtd/IncludePrivate/Library/Dx= eVt > dInitLib.h > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Vtd/IncludePrivate/Library/Dx= eVt > dInitLib.h > new file mode 100644 > index 0000000000..e439cfbac2 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Vtd/IncludePrivate/Library/Dx= eVt > dInitLib.h > @@ -0,0 +1,62 @@ > +/** @file >=20 > + Header file for DXE VTD Init Lib. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _DXE_VTD_INIT_LIB_H_ >=20 > +#define _DXE_VTD_INIT_LIB_H_ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +/** >=20 > + Locate the VT-d ACPI tables data file and read ACPI SSDT tables. >=20 > + Publish the appropriate SSDT based on current configuration and > capabilities. >=20 > + >=20 > + @param[in] SaPolicy SA DXE Policy protocol >=20 > + >=20 > + @retval EFI_SUCCESS - Vtd initialization complete >=20 > + @retval Other - No Vtd function initiated >=20 > +**/ >=20 > +EFI_STATUS >=20 > +VtdInit ( >=20 > + IN SA_POLICY_PROTOCOL *SaPolicy >=20 > + ); >=20 > + >=20 > +/** >=20 > + EndOfPcieEnum routine for update DMAR >=20 > +**/ >=20 > +VOID >=20 > +UpdateDmarEndOfPcieEnum ( >=20 > + VOID >=20 > + ); >=20 > +#endif >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Vtd/IncludePrivate/Library/Dx= eVt > dPolicyLib.h > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Vtd/IncludePrivate/Library/Dx= eVt > dPolicyLib.h > new file mode 100644 > index 0000000000..d55cf6bc34 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Vtd/IncludePrivate/Library/Dx= eVt > dPolicyLib.h > @@ -0,0 +1,67 @@ > +/** @file >=20 > + Prototype of the DXE VTD Policy Init library. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _DXE_VTD_POLICY_INIT_LIB_H_ >=20 > +#define _DXE_VTD_POLICY_INIT_LIB_H_ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +extern EFI_GUID gVtdDxeConfigGuid; >=20 > + >=20 > +/** >=20 > + This function Load default Vtd DXE policy. >=20 > + >=20 > + @param[in] ConfigBlockPointer The pointer to add VTD config block >=20 > +**/ >=20 > +VOID >=20 > +VtdLoadDefaultDxe ( >=20 > + IN VOID *ConfigBlockPointer >=20 > + ); >=20 > + >=20 > +/** >=20 > + This function prints the DXE phase VTD policy. >=20 > + >=20 > + @param[in] SaPolicy - Instance of SA_POLICY_PROTOCOL >=20 > +**/ >=20 > +VOID >=20 > +VtdPrintPolicyDxe ( >=20 > + IN SA_POLICY_PROTOCOL *SaPolicy >=20 > + ); >=20 > + >=20 > +/** >=20 > + This function is used to add VTD Config Block. >=20 > + >=20 > + @param[in] ConfigBlockTableAddress The pointer to add VTD config > blocks >=20 > + >=20 > + @retval EFI_SUCCESS The policy default is initialize= d. >=20 > + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create > buffer >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +VtdAddConfigBlocksDxe ( >=20 > + IN VOID *ConfigBlockTableAddress >=20 > + ); >=20 > + >=20 > +/** >=20 > + Get VTD DXE config block table total size. >=20 > + >=20 > + @retval Size of VTD DXE config block table >=20 > +**/ >=20 > +UINT16 >=20 > +EFIAPI >=20 > +VtdGetConfigBlockTotalSizeDxe ( >=20 > + VOID >=20 > + ); >=20 > +#endif // _DXE_VTD_POLICY_INIT_LIB_H_ >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Vtd/IncludePrivate/VtdDataHob= . > h > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Vtd/IncludePrivate/VtdDataHob= . > h > new file mode 100644 > index 0000000000..0f9d500af9 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Vtd/IncludePrivate/VtdDataHob= . > h > @@ -0,0 +1,32 @@ > +/** @file >=20 > + The GUID definition for Vtd Data Hob >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _VTD_DATA_HOB_H_ >=20 > +#define _VTD_DATA_HOB_H_ >=20 > + >=20 > +#include >=20 > +#include >=20 > + >=20 > +extern EFI_GUID gVtdDataHobGuid; >=20 > + >=20 > +#pragma pack (push,1) >=20 > + >=20 > +/// >=20 > +/// The data elements should be initialized by a Platform Module. >=20 > +/// The data structure is for VT-d driver initialization >=20 > +/// >=20 > +typedef struct { >=20 > + EFI_HOB_GUID_TYPE EfiHobGuidType; ///< GUID Hob= type > structure for gVtdDataHobGuid >=20 > + BOOLEAN VtdDisable; ///< 1 =3D Av= oids programming Vtd > bars, Vtd overrides and DMAR table >=20 > + UINT32 BaseAddress[VTD_ENGINE_NUMBER]; ///< This fie= ld is > used to describe the base addresses for VT-d function >=20 > + BOOLEAN X2ApicOptOut; ///< This fie= ld is used to enable > the X2APIC_OPT_OUT bit in the DMAR table. 1=3DEnable/Set and > 0=3DDisable/Clear >=20 > + BOOLEAN DmaControlGuarantee; ///< This fie= ld is used to > enable the DMA_CONTROL_GUARANTEE bit in the DMAR table. > 1=3DEnable/Set and 0=3DDisable/Clear >=20 > + BOOLEAN InterruptRemappingSupport; ///< This fie= ld is used to > indicate Interrupt Remapping supported or not >=20 > + UINT32 DmaBufferBase; ///< Iommu PE= I DMA buffer > base in low memory region, in Mbytes units >=20 > +} VTD_DATA_HOB; >=20 > + >=20 > +#pragma pack (pop) >=20 > +#endif >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Vtd/Library/PeiDxeSmmVtdInfoL= i > b/PeiDxeSmmVtdInfoLib.inf > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Vtd/Library/PeiDxeSmmVtdInfoL= i > b/PeiDxeSmmVtdInfoLib.inf > new file mode 100644 > index 0000000000..c7c5e56b84 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Vtd/Library/PeiDxeSmmVtdInfoL= i > b/PeiDxeSmmVtdInfoLib.inf > @@ -0,0 +1,45 @@ > +## @file >=20 > +# VTD Common Library. >=20 > +# >=20 > +# All function in this library is available for PEI, DXE, and SMM, >=20 > +# But do not support UEFI RUNTIME environment call. >=20 > +# >=20 > +# Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > +# SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +# >=20 > +## >=20 > + >=20 > + >=20 > +[Defines] >=20 > +INF_VERSION =3D 0x00010017 >=20 > +BASE_NAME =3D PeiDxeSmmVtdInfoLib >=20 > +FILE_GUID =3D A1480873-3FDA-4E90-B450-743D8031F9DE >=20 > +VERSION_STRING =3D 1.0 >=20 > +MODULE_TYPE =3D BASE >=20 > +LIBRARY_CLASS =3D VtdInfoLib >=20 > + >=20 > +[LibraryClasses] >=20 > +BaseLib >=20 > +IoLib >=20 > +DebugLib >=20 > +PciSegmentLib >=20 > +HobLib >=20 > +VtdInfoLib >=20 > + >=20 > +[Packages] >=20 > +MdePkg/MdePkg.dec >=20 > +TigerlakeSiliconPkg/SiPkg.dec >=20 > + >=20 > +[Sources] >=20 > +VtdInfoLib.c >=20 > + >=20 > +[Pcd] >=20 > +gSiPkgTokenSpaceGuid.VtdEngine1BaseAddeess >=20 > +gSiPkgTokenSpaceGuid.VtdEngine2BaseAddeess >=20 > +gSiPkgTokenSpaceGuid.VtdEngine3BaseAddeess >=20 > +gSiPkgTokenSpaceGuid.VtdEngine4BaseAddeess >=20 > +gSiPkgTokenSpaceGuid.VtdEngine5BaseAddeess >=20 > +gSiPkgTokenSpaceGuid.VtdEngine6BaseAddeess >=20 > +gSiPkgTokenSpaceGuid.VtdEngine7BaseAddeess >=20 > + >=20 > +[FixedPcd] >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Vtd/Library/PeiDxeSmmVtdInfoL= i > b/VtdInfoLib.c > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Vtd/Library/PeiDxeSmmVtdInfoL= i > b/VtdInfoLib.c > new file mode 100644 > index 0000000000..e4f08592cc > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Vtd/Library/PeiDxeSmmVtdInfoL= i > b/VtdInfoLib.c > @@ -0,0 +1,86 @@ > +/** @file >=20 > + VTD Info library. >=20 > + All function in this library is available for PEI, DXE, and SMM, >=20 > + But do not support UEFI RUNTIME environment call. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +/** >=20 > + Get VTD Engine Base Address from PCD value >=20 > + >=20 > + @param[in] VtdEngineNumber - Engine number for which VTD Base > Adderess is required. >=20 > + >=20 > + @retval VTD Engine Base Address >=20 > +**/ >=20 > +UINT32 >=20 > +GetVtdBaseAddress ( >=20 > + IN UINT8 VtdEngineNumber >=20 > + ) >=20 > +{ >=20 > + switch (VtdEngineNumber) { >=20 > + case 0: >=20 > + return PcdGet32(VtdEngine1BaseAddeess); >=20 > + break; >=20 > + case 2: >=20 > + return PcdGet32(VtdEngine3BaseAddeess); >=20 > + break; >=20 > + default: >=20 > + return 0x0; >=20 > + break; >=20 > + } >=20 > +} >=20 > + >=20 > + >=20 > +/** >=20 > + Read VTD Engine Base Address from VTD BAR Offsets. >=20 > + >=20 > + @param[in] VtdEngineNumber - Engine number for which VTD Base > Adderess is required. >=20 > + >=20 > + @retval VTD Engine Base Address >=20 > +**/ >=20 > +UINT32 >=20 > +ReadVtdBaseAddress ( >=20 > + IN UINT8 VtdEngineNumber >=20 > + ) >=20 > +{ >=20 > + UINT64 McD0BaseAddress; >=20 > + UINTN MchBar; >=20 > + >=20 > + McD0BaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, > SA_MC_BUS, 0, 0, 0); >=20 > + MchBar =3D PciSegmentRead32 (McD0BaseAddress + R_SA_MCHBAR) & > (~BIT0); >=20 > + >=20 > + switch (VtdEngineNumber) { >=20 > + case 0: >=20 > + return (MmioRead32 (MchBar + R_MCHBAR_VTD1_OFFSET) & (~BIT0)); >=20 > + break; >=20 > + case 2: >=20 > + return (MmioRead32 (MchBar + R_MCHBAR_VTD3_OFFSET) & (~BIT0)); >=20 > + break; >=20 > + default: >=20 > + return 0x0; >=20 > + break; >=20 > + } >=20 > +} >=20 > + >=20 > +/** >=20 > + GetMaxVtdEngineNumber: Get Maximum Vtd Engine Number >=20 > + >=20 > + @retval Vtd Engine Number >=20 > +**/ >=20 > +UINT8 >=20 > +GetMaxVtdEngineNumber( >=20 > + VOID >=20 > +) >=20 > +{ >=20 > + return (UINT8)VTD_ENGINE_NUMBER; >=20 > +} >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Vtd/LibraryPrivate/DxeVtdInit= Lib/ > DxeVtdInitLib.c > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Vtd/LibraryPrivate/DxeVtdInit= Lib/ > DxeVtdInitLib.c > new file mode 100644 > index 0000000000..faac07c45d > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Vtd/LibraryPrivate/DxeVtdInit= Lib/ > DxeVtdInitLib.c > @@ -0,0 +1,684 @@ > +/** @file >=20 > + DXE Library for VTD ACPI table initialization. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +/// >=20 > +/// Global Variables >=20 > +/// >=20 > +GLOBAL_REMOVE_IF_UNREFERENCED VTD_DATA_HOB *mVtdDataHob; >=20 > + >=20 > +BOOLEAN mInterruptRemappingSupport; >=20 > + >=20 > +/** >=20 > + Get the corresponding device Enable/Disable bit according DevNum and > FunNum >=20 > + >=20 > + @param[in] DevNum - Device Number >=20 > + @param[in] FunNum - Function Number >=20 > + >=20 > + @retval If the device is found, return disable/Enable bit in FD/Deven > reigster >=20 > + @retval If not found return 0xFF >=20 > +**/ >=20 > +UINT16 >=20 > +GetFunDisableBit ( >=20 > + UINT8 DevNum, >=20 > + UINT8 FunNum >=20 > + ) >=20 > +{ >=20 > + UINTN Index; >=20 > + >=20 > + for (Index =3D 0; Index < mDevEnMapSize; Index++) { >=20 > + if (mDevEnMap[Index][0] =3D=3D ((DevNum << 0x08) | FunNum)) { >=20 > + return mDevEnMap[Index][1]; >=20 > + } >=20 > + } >=20 > + >=20 > + return 0xFF; >=20 > +} >=20 > + >=20 > +/** >=20 > + Update the DRHD structure >=20 > + >=20 > + @param[in, out] DrhdEnginePtr - A pointer to DRHD structure >=20 > +**/ >=20 > +VOID >=20 > +UpdateDrhd ( >=20 > + IN OUT VOID *DrhdEnginePtr >=20 > + ) >=20 > +{ >=20 > + UINT16 Length; >=20 > + UINT16 DisableBit; >=20 > + BOOLEAN NeedRemove; >=20 > + EFI_ACPI_DRHD_ENGINE1_STRUCT *DrhdEngine; >=20 > + >=20 > + // >=20 > + // Convert DrhdEnginePtr to EFI_ACPI_DRHD_ENGINE1_STRUCT Pointer >=20 > + // >=20 > + DrhdEngine =3D (EFI_ACPI_DRHD_ENGINE1_STRUCT *) DrhdEnginePtr; >=20 > + Length =3D DrhdEngine->DrhdHeader.Header.Length; >=20 > + DisableBit =3D GetFunDisableBit ( >=20 > + DrhdEngine->DeviceScope[0].PciPath.Device, >=20 > + DrhdEngine->DeviceScope[0].PciPath.Function >=20 > + ); >=20 > + NeedRemove =3D FALSE; >=20 > + >=20 > + if ((DisableBit =3D=3D 0xFF) || >=20 > + (DrhdEngine->DrhdHeader.RegisterBaseAddress =3D=3D 0) || >=20 > + ((DisableBit =3D=3D 0x80) && >=20 > + (PciSegmentRead32 (PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, 0, > DrhdEngine->DeviceScope[0].PciPath.Device, DrhdEngine- > >DeviceScope[0].PciPath.Function, 0x00)) =3D=3D 0xFFFFFFFF)) >=20 > + ) { >=20 > + NeedRemove =3D TRUE; >=20 > + } >=20 > + if ((DrhdEngine->DeviceScope[0].PciPath.Device =3D=3D IGD_DEV_NUM) && > (DrhdEngine->DeviceScope[0].PciPath.Function =3D=3D IGD_FUN_NUM) && >=20 > + (PciSegmentRead32 (PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, 0, > DrhdEngine->DeviceScope[0].PciPath.Device, DrhdEngine- > >DeviceScope[0].PciPath.Function, 0x00)) !=3D 0xFFFFFFFF)) { >=20 > + NeedRemove =3D FALSE; >=20 > + } >=20 > + if (NeedRemove) { >=20 > + Length -=3D sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE); >=20 > + } >=20 > + /// >=20 > + /// If no devicescope is left, we set the structure length as 0x00 >=20 > + /// >=20 > + if ((Length > EFI_ACPI_DRHD_ENGINE_HEADER_LENGTH) || (DrhdEngine- > >DrhdHeader.Flags =3D=3D 0x01)) { >=20 > + DrhdEngine->DrhdHeader.Header.Length =3D Length; >=20 > + } else { >=20 > + DrhdEngine->DrhdHeader.Header.Length =3D 0; >=20 > + } >=20 > +} >=20 > + >=20 > +/** >=20 > + Get IOAPIC ID from LPC >=20 > + >=20 > + @retval APIC ID >=20 > +**/ >=20 > +UINT8 >=20 > +GetIoApicId ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + UINT32 IoApicAddress; >=20 > + UINT32 IoApicId; >=20 > + >=20 > + IoApicAddress =3D PcdGet32 (PcdSiIoApicBaseAddress); >=20 > + /// >=20 > + /// Get current IO APIC ID >=20 > + /// >=20 > + MmioWrite8 ((UINTN) (IoApicAddress + > R_IO_APIC_MEM_INDEX_OFFSET), 0); >=20 > + IoApicId =3D MmioRead32 ((UINTN) (IoApicAddress + > R_IO_APIC_MEM_DATA_OFFSET)) >> 24; >=20 > + >=20 > + return (UINT8) IoApicId; >=20 > +} >=20 > + >=20 > +/** >=20 > + Update the second DRHD structure >=20 > + >=20 > + @param[in, out] DrhdEnginePtr - A pointer to DRHD structure >=20 > +**/ >=20 > +VOID >=20 > +UpdateDrhd2 ( >=20 > + IN OUT VOID *DrhdEnginePtr >=20 > + ) >=20 > +{ >=20 > + UINT16 Length; >=20 > + UINTN DeviceScopeNum; >=20 > + UINTN ValidDeviceScopeNum; >=20 > + UINT16 Index; >=20 > + UINT8 Bus; >=20 > + UINT8 Path[2]; >=20 > + BOOLEAN NeedRemove; >=20 > + EFI_ACPI_DRHD_ENGINE3_STRUCT *DrhdEngine; >=20 > + VOID *HobPtr; >=20 > + PCH_INFO_HOB *PchInfoHob; >=20 > + >=20 > + /// >=20 > + /// Convert DrhdEnginePtr to EFI_ACPI_DRHD_ENGINE3_STRUCT Pointer >=20 > + /// >=20 > + DrhdEngine =3D (EFI_ACPI_DRHD_ENGINE3_STRUCT *) DrhdEnginePtr; >=20 > + >=20 > + Length =3D DrhdEngine->DrhdHeader.Header.Length; >=20 > + DeviceScopeNum =3D (DrhdEngine->DrhdHeader.Header.Length - > EFI_ACPI_DRHD_ENGINE_HEADER_LENGTH) / sizeof > (EFI_ACPI_DEV_SCOPE_STRUCTURE); >=20 > + Bus =3D 0; >=20 > + ValidDeviceScopeNum =3D 0; >=20 > + Path[0] =3D 0; >=20 > + Path[1] =3D 0; >=20 > + >=20 > + HobPtr =3D GetFirstGuidHob (&gPchInfoHobGuid); >=20 > + ASSERT (HobPtr !=3D NULL); >=20 > + if (HobPtr =3D=3D NULL) { >=20 > + return; >=20 > + } >=20 > + PchInfoHob =3D (PCH_INFO_HOB *) GET_GUID_HOB_DATA (HobPtr); >=20 > + ASSERT (PchInfoHob !=3D NULL); >=20 > + if (PchInfoHob =3D=3D NULL) { >=20 > + return; >=20 > + } >=20 > + >=20 > + for (Index =3D 0; Index < DeviceScopeNum; Index++) { >=20 > + NeedRemove =3D FALSE; >=20 > + /** >=20 > + For HPET and APIC, update device scope if Interrupt remapping is > supported. remove device scope >=20 > + if interrupt remapping is not supported. >=20 > + - Index =3D 0 - IOAPIC >=20 > + - Index =3D 1 - HPET >=20 > + **/ >=20 > + if (mInterruptRemappingSupport) { >=20 > + if (Index =3D=3D 0) { >=20 > + /// >=20 > + /// Update source id for IoApic's device scope entry >=20 > + /// >=20 > + Bus =3D (UINT8) PchInfoHob->IoApicBusNum; >=20 > + Path[0] =3D (UINT8) PchInfoHob->IoApicDevNum; >=20 > + Path[1] =3D (UINT8) PchInfoHob->IoApicFuncNum; >=20 > + DrhdEngine- > >DeviceScope[Index].DeviceScopeStructureHeader.StartBusNumber =3D Bus; >=20 > + DrhdEngine->DeviceScope[Index].PciPath.Device =3D Path[0]; >=20 > + DrhdEngine->DeviceScope[Index].PciPath.Function =3D Path[1]; >=20 > + // >=20 > + // Update APIC ID >=20 > + // >=20 > + DrhdEngine- > >DeviceScope[Index].DeviceScopeStructureHeader.EnumerationId =3D > GetIoApicId (); >=20 > + } >=20 > + if (Index =3D=3D 1) { >=20 > + /// >=20 > + /// Update source id for HPET's device scope entry >=20 > + /// >=20 > + Bus =3D (UINT8) PchInfoHob->HpetBusNum; >=20 > + Path[0] =3D (UINT8) PchInfoHob->HpetDevNum; >=20 > + Path[1] =3D (UINT8) PchInfoHob->HpetFuncNum; >=20 > + DrhdEngine- > >DeviceScope[Index].DeviceScopeStructureHeader.StartBusNumber =3D Bus; >=20 > + DrhdEngine->DeviceScope[Index].PciPath.Device =3D Path[0]; >=20 > + DrhdEngine->DeviceScope[Index].PciPath.Function =3D Path[1]; >=20 > + } >=20 > + } else { >=20 > + if ((Index =3D=3D 0) || (Index =3D=3D 1)) { >=20 > + NeedRemove =3D TRUE; >=20 > + } >=20 > + } >=20 > + >=20 > + CopyMem ( >=20 > + &DrhdEngine->DeviceScope[ValidDeviceScopeNum], >=20 > + &DrhdEngine->DeviceScope[Index], >=20 > + sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE) >=20 > + ); >=20 > + if (NeedRemove) { >=20 > + Length -=3D sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE); >=20 > + } else { >=20 > + ValidDeviceScopeNum++; >=20 > + } >=20 > + } >=20 > + /// >=20 > + /// If no devicescope is left, we set the structure length as 0x00 >=20 > + /// >=20 > + if ((Length > EFI_ACPI_DRHD_ENGINE_HEADER_LENGTH) || (DrhdEngine- > >DrhdHeader.Flags =3D=3D 0x01)) { >=20 > + DrhdEngine->DrhdHeader.Header.Length =3D Length; >=20 > + } else { >=20 > + DrhdEngine->DrhdHeader.Header.Length =3D 0; >=20 > + } >=20 > +} >=20 > + >=20 > +/** >=20 > + Update the RMRR structure >=20 > + >=20 > + @param[in, out] RmrrPtr - A pointer to RMRR structure >=20 > +**/ >=20 > +VOID >=20 > +UpdateRmrr ( >=20 > + IN OUT VOID *RmrrPtr >=20 > + ) >=20 > +{ >=20 > + UINT16 Length; >=20 > + UINT16 DisableBit; >=20 > + UINTN DeviceScopeNum; >=20 > + UINTN ValidDeviceScopeNum; >=20 > + UINTN Index; >=20 > + BOOLEAN NeedRemove; >=20 > + EFI_ACPI_RMRR_USB_STRUC *Rmrr; >=20 > + >=20 > + /// >=20 > + /// To make sure all devicescope can be checked, >=20 > + /// we convert the RmrrPtr to EFI_ACPI_RMRR_USB_STRUC pointer >=20 > + /// >=20 > + Rmrr =3D (EFI_ACPI_RMRR_USB_STRUC *) RmrrPtr; >=20 > + >=20 > + Length =3D Rmrr->RmrrHeader.Header.Length; >=20 > + ValidDeviceScopeNum =3D 0; >=20 > + DeviceScopeNum =3D (Rmrr->RmrrHeader.Header.Length - > EFI_ACPI_RMRR_HEADER_LENGTH) / sizeof > (EFI_ACPI_DEV_SCOPE_STRUCTURE); >=20 > + for (Index =3D 0; Index < DeviceScopeNum; Index++) { >=20 > + DisableBit =3D GetFunDisableBit ( >=20 > + Rmrr->DeviceScope[Index].PciPath.Device, >=20 > + Rmrr->DeviceScope[Index].PciPath.Function >=20 > + ); >=20 > + NeedRemove =3D FALSE; >=20 > + if ((DisableBit =3D=3D 0xFF) || >=20 > + ((DisableBit =3D=3D 0x80) && >=20 > + (PciSegmentRead32 (PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, 0, > Rmrr->DeviceScope[Index].PciPath.Device, Rmrr- > >DeviceScope[Index].PciPath.Function, 0x00)) =3D=3D 0xFFFFFFFF)) >=20 > + ) { >=20 > + NeedRemove =3D TRUE; >=20 > + } else if (DisableBit =3D=3D 0x8F) { >=20 > + DEBUG ((DEBUG_ERROR, "Rmrr- > >RmrrHeader.ReservedMemoryRegionBaseAddress %x\n", Rmrr- > >RmrrHeader.ReservedMemoryRegionBaseAddress)); >=20 > + >=20 > + if (Rmrr->RmrrHeader.ReservedMemoryRegionBaseAddress !=3D 0) { >=20 > + DEBUG ((DEBUG_ERROR, "NeedRemove =3D FALSE\n")); >=20 > + NeedRemove =3D FALSE; >=20 > + } else { >=20 > + DEBUG ((DEBUG_ERROR, "NeedRemove =3D TRUE\n")); >=20 > + NeedRemove =3D TRUE; >=20 > + } >=20 > + } >=20 > + CopyMem ( >=20 > + &Rmrr->DeviceScope[ValidDeviceScopeNum], >=20 > + &Rmrr->DeviceScope[Index], >=20 > + sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE) >=20 > + ); >=20 > + >=20 > + if (Rmrr->RmrrHeader.ReservedMemoryRegionLimitAddress =3D=3D 0x0) { >=20 > + NeedRemove =3D TRUE; >=20 > + } >=20 > + >=20 > + if (NeedRemove) { >=20 > + Length -=3D sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE); >=20 > + } else { >=20 > + ValidDeviceScopeNum++; >=20 > + } >=20 > + } >=20 > + /// >=20 > + /// If No deviceScope is left, set length as 0x00 >=20 > + /// >=20 > + if (Length > EFI_ACPI_RMRR_HEADER_LENGTH) { >=20 > + Rmrr->RmrrHeader.Header.Length =3D Length; >=20 > + } else { >=20 > + Rmrr->RmrrHeader.Header.Length =3D 0; >=20 > + } >=20 > +} >=20 > + >=20 > +/** >=20 > + Update the DMAR table >=20 > + >=20 > + @param[in, out] TableHeader - The table to be set >=20 > + @param[in, out] Version - Version to publish >=20 > +**/ >=20 > +VOID >=20 > +DmarTableUpdate ( >=20 > + IN OUT EFI_ACPI_DESCRIPTION_HEADER *TableHeader, >=20 > + IN OUT EFI_ACPI_TABLE_VERSION *Version >=20 > + ) >=20 > +{ >=20 > + EFI_ACPI_DMAR_TABLE *DmarTable; >=20 > + EFI_ACPI_DMAR_TABLE TempDmarTable; >=20 > + UINTN Offset; >=20 > + UINTN StructureLen; >=20 > + UINT64 McD0BaseAddress; >=20 > + UINT32 GttMmAdr; >=20 > + UINT64 McD2BaseAddress; >=20 > + UINT16 IgdMode; >=20 > + UINT16 GttMode; >=20 > + UINT32 IgdMemSize; >=20 > + UINT32 GttMemSize; >=20 > + EFI_STATUS Status; >=20 > + VTD_DXE_CONFIG *VtdDxeConfig; >=20 > + SA_POLICY_PROTOCOL *SaPolicy; >=20 > + >=20 > + >=20 > + IgdMemSize =3D 0; >=20 > + GttMemSize =3D 0; >=20 > + DmarTable =3D (EFI_ACPI_DMAR_TABLE *) TableHeader; >=20 > + >=20 > + Status =3D gBS->LocateProtocol (&gSaPolicyProtocolGuid, NULL, (VOID **= ) > &SaPolicy); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + >=20 > + Status =3D GetConfigBlock ((VOID *) SaPolicy, &gVtdDxeConfigGuid, (VOI= D > *)&VtdDxeConfig); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + >=20 > + /// >=20 > + /// Set INTR_REMAP bit (BIT 0) if interrupt remapping is supported >=20 > + /// >=20 > + if (mInterruptRemappingSupport) { >=20 > + DmarTable->DmarHeader.Flags |=3D BIT0; >=20 > + } >=20 > + >=20 > + if (mVtdDataHob->X2ApicOptOut =3D=3D 1) { >=20 > + DmarTable->DmarHeader.Flags |=3D BIT1; >=20 > + } else { >=20 > + DmarTable->DmarHeader.Flags &=3D 0xFD; >=20 > + } >=20 > + >=20 > + /// >=20 > + /// Set DMA_CONTROL_GUARANTEE bit (BIT 2) if Dma Control Guarantee > is supported >=20 > + /// >=20 > + if (mVtdDataHob->DmaControlGuarantee =3D=3D 1) { >=20 > + DmarTable->DmarHeader.Flags |=3D BIT2; >=20 > + } >=20 > + /// >=20 > + /// Get OemId >=20 > + /// >=20 > + CopyMem (DmarTable->DmarHeader.Header.OemId, PcdGetPtr > (PcdAcpiDefaultOemId), sizeof (DmarTable->DmarHeader.Header.OemId)); >=20 > + DmarTable->DmarHeader.Header.OemTableId =3D PcdGet64 > (PcdAcpiDefaultOemTableId); >=20 > + DmarTable->DmarHeader.Header.OemRevision =3D PcdGet32 > (PcdAcpiDefaultOemRevision); >=20 > + DmarTable->DmarHeader.Header.CreatorId =3D PcdGet32 > (PcdAcpiDefaultCreatorId); >=20 > + DmarTable->DmarHeader.Header.CreatorRevision =3D PcdGet32 > (PcdAcpiDefaultCreatorRevision); >=20 > + >=20 > + /// >=20 > + /// Calculate IGD memsize >=20 > + /// >=20 > + McD0BaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, > SA_MC_BUS, 0, 0, 0); >=20 > + IgdMode =3D ((PciSegmentRead16 (McD0BaseAddress + R_SA_GGC) & > B_SA_GGC_GMS_MASK) >> N_SA_GGC_GMS_OFFSET) & 0xFF; >=20 > + if (IgdMode < 0xF0) { >=20 > + IgdMemSize =3D IgdMode * 32 * (1024) * (1024); >=20 > + } else { >=20 > + IgdMemSize =3D 4 * (IgdMode - 0xF0 + 1) * (1024) * (1024); >=20 > + } >=20 > + /// >=20 > + /// Calculate GTT mem size >=20 > + /// >=20 > + GttMemSize =3D 0; >=20 > + GttMode =3D (PciSegmentRead16 (McD0BaseAddress + R_SA_GGC) & > B_SA_GGC_GGMS_MASK) >> N_SA_GGC_GGMS_OFFSET; >=20 > + if (GttMode <=3D V_SA_GGC_GGMS_8MB) { >=20 > + GttMemSize =3D (1 << GttMode) * (1024) * (1024); >=20 > + } >=20 > + >=20 > + McD2BaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, > IGD_BUS_NUM, IGD_DEV_NUM, IGD_FUN_NUM, 0); >=20 > + GttMmAdr =3D (PciSegmentRead32 (McD2BaseAddress + > R_SA_IGD_GTTMMADR)) & 0xFFFFFFF0; >=20 > + >=20 > + DmarTable->RmrrIgd.RmrrHeader.ReservedMemoryRegionBaseAddress > =3D (PciSegmentRead32 (McD0BaseAddress + R_SA_BGSM) & ~(0x01)); >=20 > + DmarTable->RmrrIgd.RmrrHeader.ReservedMemoryRegionLimitAddress > =3D DmarTable->RmrrIgd.RmrrHeader.ReservedMemoryRegionBaseAddress + > IgdMemSize + GttMemSize - 1; >=20 > + DEBUG ((DEBUG_INFO, "RMRR Base address IGD %016lX\n", DmarTable- > >RmrrIgd.RmrrHeader.ReservedMemoryRegionBaseAddress)); >=20 > + DEBUG ((DEBUG_INFO, "RMRR Limit address IGD %016lX\n", DmarTable- > >RmrrIgd.RmrrHeader.ReservedMemoryRegionLimitAddress)); >=20 > + >=20 > + /// >=20 > + /// Update DRHD structures of DmarTable >=20 > + /// >=20 > + DmarTable->DrhdEngine1.DrhdHeader.RegisterBaseAddress =3D > ReadVtdBaseAddress(0); >=20 > + DmarTable->DrhdEngine3.DrhdHeader.RegisterBaseAddress =3D > ReadVtdBaseAddress (2); >=20 > + >=20 > + DEBUG ((DEBUG_INFO, "VTD base address 1 =3D %x\n", DmarTable- > >DrhdEngine1.DrhdHeader.RegisterBaseAddress)); >=20 > + DEBUG ((DEBUG_INFO, "VTD base address 3 =3D %x\n", DmarTable- > >DrhdEngine3.DrhdHeader.RegisterBaseAddress)); >=20 > + /// >=20 > + /// copy DmarTable to TempDmarTable to be processed >=20 > + /// >=20 > + CopyMem (&TempDmarTable, DmarTable, sizeof > (EFI_ACPI_DMAR_TABLE)); >=20 > + >=20 > + /// >=20 > + /// Update DRHD structures of temp DMAR table >=20 > + /// >=20 > + UpdateDrhd (&TempDmarTable.DrhdEngine1); >=20 > + UpdateDrhd2 (&TempDmarTable.DrhdEngine3); >=20 > + >=20 > + /// >=20 > + /// Remove unused device scope or entire DRHD structures >=20 > + /// >=20 > + Offset =3D (UINTN) (&TempDmarTable.DrhdEngine1); >=20 > + if (TempDmarTable.DrhdEngine1.DrhdHeader.Header.Length !=3D 0) { >=20 > + Offset +=3D TempDmarTable.DrhdEngine1.DrhdHeader.Header.Length; >=20 > + } >=20 > + if (TempDmarTable.DrhdEngine3.DrhdHeader.Header.Length !=3D 0) { >=20 > + StructureLen =3D > TempDmarTable.DrhdEngine3.DrhdHeader.Header.Length; >=20 > + CopyMem ((VOID *) Offset, (VOID *) &TempDmarTable.DrhdEngine3, > TempDmarTable.DrhdEngine3.DrhdHeader.Header.Length); >=20 > + Offset +=3D StructureLen; >=20 > + } >=20 > + /// >=20 > + /// Remove unused device scope or entire RMRR structures >=20 > + /// >=20 > + if (TempDmarTable.RmrrIgd.RmrrHeader.Header.Length !=3D 0) { >=20 > + StructureLen =3D TempDmarTable.RmrrIgd.RmrrHeader.Header.Length; >=20 > + CopyMem ((VOID *) Offset, (VOID *) &TempDmarTable.RmrrIgd, > TempDmarTable.RmrrIgd.RmrrHeader.Header.Length); >=20 > + Offset +=3D StructureLen; >=20 > + } >=20 > + Offset =3D Offset - (UINTN) &TempDmarTable; >=20 > + /// >=20 > + /// Re-calculate DMAR table check sum >=20 > + /// >=20 > + TempDmarTable.DmarHeader.Header.Checksum =3D (UINT8) > (TempDmarTable.DmarHeader.Header.Checksum + > TempDmarTable.DmarHeader.Header.Length - Offset); >=20 > + /// >=20 > + /// Set DMAR table length >=20 > + /// >=20 > + TempDmarTable.DmarHeader.Header.Length =3D (UINT32) Offset; >=20 > + /// >=20 > + /// Replace DMAR table with rebuilt table TempDmarTable >=20 > + /// >=20 > + CopyMem ((VOID *) DmarTable, (VOID *) &TempDmarTable, > TempDmarTable.DmarHeader.Header.Length); >=20 > +} >=20 > + >=20 > +/** >=20 > + EndOfPcieEnumration routine for update DMAR >=20 > +**/ >=20 > +VOID >=20 > +UpdateDmarEndOfPcieEnum ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + EFI_STATUS Status; >=20 > + EFI_HANDLE *HandleBuffer; >=20 > + UINTN NumberOfHandles; >=20 > + EFI_FV_FILETYPE FileType; >=20 > + UINT32 FvStatus; >=20 > + EFI_FV_FILE_ATTRIBUTES Attributes; >=20 > + UINTN Size; >=20 > + UINTN i; >=20 > + INTN Instance; >=20 > + EFI_ACPI_TABLE_VERSION Version; >=20 > + EFI_ACPI_COMMON_HEADER *CurrentTable; >=20 > + UINTN AcpiTableHandle; >=20 > + EFI_FIRMWARE_VOLUME2_PROTOCOL *FwVol; >=20 > + EFI_ACPI_TABLE_PROTOCOL *AcpiTable; >=20 > + EFI_ACPI_DESCRIPTION_HEADER *VtdAcpiTable; >=20 > + STATIC BOOLEAN Triggered =3D FALSE; >=20 > + >=20 > + >=20 > + if (Triggered) { >=20 > + return; >=20 > + } >=20 > + >=20 > + Triggered =3D TRUE; >=20 > + >=20 > + FwVol =3D NULL; >=20 > + AcpiTable =3D NULL; >=20 > + VtdAcpiTable =3D NULL; >=20 > + >=20 > + DEBUG ((DEBUG_INFO, "UpdateDmarEndOfPcieEnum \n")); >=20 > + >=20 > + >=20 > + /// >=20 > + /// Fix DMAR Table always created, skip install when disabled >=20 > + /// >=20 > + if ((mVtdDataHob->VtdDisable =3D=3D TRUE) || (PciSegmentRead32 > (PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, SA_MC_BUS, 0, 0, > R_SA_MC_CAPID0_A_OFFSET)) & BIT23)) { >=20 > + DEBUG ((DEBUG_INFO, "Vtd Disabled, skip DMAR Table install\n")); >=20 > + return; >=20 > + } >=20 > + >=20 > + >=20 > + /// >=20 > + /// Locate ACPI support protocol >=20 > + /// >=20 > + Status =3D gBS->LocateProtocol (&gEfiAcpiTableProtocolGuid, NULL, (VOI= D > **) &AcpiTable); >=20 > + >=20 > + /// >=20 > + /// Locate protocol. >=20 > + /// There is little chance we can't find an FV protocol >=20 > + /// >=20 > + Status =3D gBS->LocateHandleBuffer ( >=20 > + ByProtocol, >=20 > + &gEfiFirmwareVolume2ProtocolGuid, >=20 > + NULL, >=20 > + &NumberOfHandles, >=20 > + &HandleBuffer >=20 > + ); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + >=20 > + /// >=20 > + /// Looking for FV with ACPI storage file >=20 > + /// >=20 > + for (i =3D 0; i < NumberOfHandles; i++) { >=20 > + /// >=20 > + /// Get the protocol on this handle >=20 > + /// This should not fail because of LocateHandleBuffer >=20 > + /// >=20 > + Status =3D gBS->HandleProtocol ( >=20 > + HandleBuffer[i], >=20 > + &gEfiFirmwareVolume2ProtocolGuid, >=20 > + (VOID **) &FwVol >=20 > + ); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + >=20 > + /// >=20 > + /// See if it has the ACPI storage file >=20 > + /// >=20 > + Size =3D 0; >=20 > + FvStatus =3D 0; >=20 > + Status =3D FwVol->ReadFile ( >=20 > + FwVol, >=20 > + &gSaAcpiTableStorageGuid, >=20 > + NULL, >=20 > + &Size, >=20 > + &FileType, >=20 > + &Attributes, >=20 > + &FvStatus >=20 > + ); >=20 > + >=20 > + /// >=20 > + /// If we found it, then we are done >=20 > + /// >=20 > + if (Status =3D=3D EFI_SUCCESS) { >=20 > + break; >=20 > + } >=20 > + } >=20 > + /// >=20 > + /// Our exit status is determined by the success of the previous opera= tions >=20 > + /// If the protocol was found, Instance already points to it. >=20 > + /// >=20 > + /// >=20 > + /// Free any allocated buffers >=20 > + /// >=20 > + FreePool (HandleBuffer); >=20 > + >=20 > + /// >=20 > + /// Sanity check that we found our data file >=20 > + /// >=20 > + ASSERT (FwVol); >=20 > + if (FwVol =3D=3D NULL) { >=20 > + return; >=20 > + } >=20 > + /// >=20 > + /// By default, a table belongs in all ACPI table versions published. >=20 > + /// >=20 > + Version =3D EFI_ACPI_TABLE_VERSION_1_0B | > EFI_ACPI_TABLE_VERSION_2_0 | EFI_ACPI_TABLE_VERSION_3_0; >=20 > + >=20 > + /// >=20 > + /// Read tables from the storage file. >=20 > + /// >=20 > + Instance =3D 0; >=20 > + CurrentTable =3D NULL; >=20 > + >=20 > + while (Status =3D=3D EFI_SUCCESS) { >=20 > + Status =3D FwVol->ReadSection ( >=20 > + FwVol, >=20 > + &gSaAcpiTableStorageGuid, >=20 > + EFI_SECTION_RAW, >=20 > + Instance, >=20 > + (VOID **) &CurrentTable, >=20 > + &Size, >=20 > + &FvStatus >=20 > + ); >=20 > + >=20 > + if (!EFI_ERROR (Status)) { >=20 > + /// >=20 > + /// Check the Signature ID to modify the table >=20 > + /// >=20 > + if ((CurrentTable !=3D NULL) && ((EFI_ACPI_DESCRIPTION_HEADER *) > CurrentTable)->Signature =3D=3D EFI_ACPI_VTD_DMAR_TABLE_SIGNATURE) { >=20 > + VtdAcpiTable =3D (EFI_ACPI_DESCRIPTION_HEADER *) CurrentTable; >=20 > + DmarTableUpdate (VtdAcpiTable, &Version); >=20 > + break; >=20 > + } >=20 > + /// >=20 > + /// Increment the instance >=20 > + /// >=20 > + Instance++; >=20 > + if (CurrentTable !=3D NULL) { >=20 > + gBS->FreePool (CurrentTable); >=20 > + CurrentTable =3D NULL; >=20 > + } >=20 > + } >=20 > + } >=20 > + /// >=20 > + /// Update the VTD table in the ACPI tables. >=20 > + /// >=20 > + AcpiTableHandle =3D 0; >=20 > + if (VtdAcpiTable !=3D NULL) { >=20 > + Status =3D AcpiTable->InstallAcpiTable ( >=20 > + AcpiTable, >=20 > + VtdAcpiTable, >=20 > + VtdAcpiTable->Length, >=20 > + &AcpiTableHandle >=20 > + ); >=20 > + FreePool (VtdAcpiTable); >=20 > + } >=20 > +} >=20 > + >=20 > +/** >=20 > + Locate the VT-d ACPI tables data file and read ACPI SSDT tables. >=20 > + Publish the appropriate SSDT based on current configuration and > capabilities. >=20 > + >=20 > + @param[in] SaPolicy - SA DXE Policy protocol >=20 > + >=20 > + @retval EFI_SUCCESS - Vtd initialization complete >=20 > + @exception EFI_UNSUPPORTED - Vtd is not enabled by policy >=20 > +**/ >=20 > +EFI_STATUS >=20 > +VtdInit ( >=20 > + IN SA_POLICY_PROTOCOL *SaPolicy >=20 > + ) >=20 > +{ >=20 > + EFI_STATUS Status; >=20 > + UINT64 McD0BaseAddress; >=20 > + UINT64 McD2BaseAddress; >=20 > + SYSTEM_AGENT_NVS_AREA_PROTOCOL *SaNvsAreaProtocol; >=20 > + UINT8 Index; >=20 > + >=20 > + mInterruptRemappingSupport =3D FALSE; >=20 > + mVtdDataHob =3D NULL; >=20 > + mVtdDataHob =3D GetFirstGuidHob(&gVtdDataHobGuid); >=20 > + if (mVtdDataHob !=3D NULL) { >=20 > + mInterruptRemappingSupport =3D mVtdDataHob- > >InterruptRemappingSupport; >=20 > + } >=20 > + >=20 > + /// >=20 > + /// Locate the SA Global NVS Protocol. >=20 > + /// >=20 > + Status =3D gBS->LocateProtocol ( >=20 > + &gSaNvsAreaProtocolGuid, >=20 > + NULL, >=20 > + (VOID **) &SaNvsAreaProtocol >=20 > + ); >=20 > + if (EFI_ERROR (Status)) { >=20 > + return Status; >=20 > + } >=20 > + >=20 > + McD0BaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, > SA_MC_BUS, 0, 0, 0); >=20 > + McD2BaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, > IGD_BUS_NUM, IGD_DEV_NUM, IGD_FUN_NUM, 0); >=20 > + >=20 > + if (mVtdDataHob !=3D NULL) { >=20 > + SaNvsAreaProtocol->Area->VtdDisable =3D mVtdDataHob->VtdDisable; >=20 > + } >=20 > + >=20 > + for (Index =3D 0; Index < VTD_ENGINE_NUMBER; Index++) { >=20 > + SaNvsAreaProtocol->Area->VtdBaseAddress[Index] =3D > ReadVtdBaseAddress (Index); >=20 > + } >=20 > + SaNvsAreaProtocol->Area->VtdEngine1Vid =3D > PciSegmentRead16(McD2BaseAddress + PCI_VENDOR_ID_OFFSET); >=20 > + >=20 > + if (mVtdDataHob !=3D NULL) { >=20 > + if ((mVtdDataHob->VtdDisable) || (PciSegmentRead32 > (McD0BaseAddress + R_SA_MC_CAPID0_A_OFFSET) & BIT23)) { >=20 > + DEBUG ((DEBUG_WARN, "VTd disabled or no capability!\n")); >=20 > + return EFI_UNSUPPORTED; >=20 > + } >=20 > + } >=20 > + /// >=20 > + /// Check SA supports VTD and VTD is enabled in setup menu >=20 > + /// >=20 > + DEBUG ((DEBUG_INFO, "VTd enabled\n")); >=20 > + >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Vtd/LibraryPrivate/DxeVtdInit= Lib/ > DxeVtdInitLib.inf > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Vtd/LibraryPrivate/DxeVtdInit= Lib/ > DxeVtdInitLib.inf > new file mode 100644 > index 0000000000..9797c31cc6 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Vtd/LibraryPrivate/DxeVtdInit= Lib/ > DxeVtdInitLib.inf > @@ -0,0 +1,71 @@ > +## @file >=20 > +# Component description file for the Dxe VTD Init library. >=20 > +# >=20 > +# Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > +# SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +# >=20 > +## >=20 > + >=20 > +[Defines] >=20 > +INF_VERSION =3D 0x00010017 >=20 > +BASE_NAME =3D DxeVtdInitLib >=20 > +FILE_GUID =3D 9BD11E68-923C-424C-A278-716084B4C931 >=20 > +VERSION_STRING =3D 1.0 >=20 > +MODULE_TYPE =3D DXE_DRIVER >=20 > +LIBRARY_CLASS =3D DxeVtdInitLib >=20 > + >=20 > +[LibraryClasses] >=20 > +UefiLib >=20 > +UefiRuntimeServicesTableLib >=20 > +UefiBootServicesTableLib >=20 > +DebugLib >=20 > +PostCodeLib >=20 > +ConfigBlockLib >=20 > +HobLib >=20 > +IoLib >=20 > +PciSegmentLib >=20 > +BaseMemoryLib >=20 > +MemoryAllocationLib >=20 > +MmPciLib >=20 > +VtdInfoLib >=20 > +PchInfoLib >=20 > +PchCycleDecodingLib >=20 > +SaPlatformLib >=20 > +DxeVtdInitFruLib >=20 > + >=20 > +[Packages] >=20 > +MdePkg/MdePkg.dec >=20 > +TigerlakeSiliconPkg/SiPkg.dec >=20 > + >=20 > +[Sources] >=20 > +DxeVtdInitLib.c >=20 > + >=20 > +[Pcd] >=20 > +gSiPkgTokenSpaceGuid.PcdSiIoApicBaseAddress >=20 > +gSiPkgTokenSpaceGuid.PcdAcpiDefaultOemId >=20 > +gSiPkgTokenSpaceGuid.PcdAcpiDefaultOemTableId >=20 > +gSiPkgTokenSpaceGuid.PcdAcpiDefaultOemRevision >=20 > +gSiPkgTokenSpaceGuid.PcdAcpiDefaultCreatorId >=20 > +gSiPkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision >=20 > + >=20 > +[FixedPcd] >=20 > + >=20 > +[Guids] >=20 > +gPchInfoHobGuid ## CONSUMES >=20 > +gSaAcpiTableStorageGuid >=20 > +gVtdDataHobGuid >=20 > +gVtdDxeConfigGuid >=20 > + >=20 > +[Protocols] >=20 > +gSaPolicyProtocolGuid ## CONSUMES >=20 > +gSaNvsAreaProtocolGuid ## CONSUMES >=20 > +gEfiFirmwareVolume2ProtocolGuid >=20 > +gEfiAcpiTableProtocolGuid >=20 > + >=20 > +[Depex] >=20 > +gEfiAcpiTableProtocolGuid AND >=20 > +gEfiFirmwareVolume2ProtocolGuid AND >=20 > +gSaPolicyProtocolGuid AND >=20 > +gEfiPciRootBridgeIoProtocolGuid AND >=20 > +gEfiPciHostBridgeResourceAllocationProtocolGuid AND # This is to ensure > that PCI MMIO resource has been prepared and available for this driver to > allocate. >=20 > +gEfiHiiDatabaseProtocolGuid >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Vtd/LibraryPrivate/DxeVtdPoli= cyLi > b/DxeVtdPolicyLib.c > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Vtd/LibraryPrivate/DxeVtdPoli= cyL > ib/DxeVtdPolicyLib.c > new file mode 100644 > index 0000000000..168de0c0a9 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Vtd/LibraryPrivate/DxeVtdPoli= cyL > ib/DxeVtdPolicyLib.c > @@ -0,0 +1,90 @@ > +/** @file >=20 > + This file provides services for DXE VTD policy default initialization >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +#include >=20 > + >=20 > +/** >=20 > + This function prints the DXE phase VTD policy. >=20 > + >=20 > + @param[in] SaPolicy - Instance of SA_POLICY_PROTOCOL >=20 > +**/ >=20 > +VOID >=20 > +VtdPrintPolicyDxe ( >=20 > + IN SA_POLICY_PROTOCOL *SaPolicy >=20 > + ) >=20 > +{ >=20 > + EFI_STATUS Status; >=20 > + VTD_DXE_CONFIG *VtdDxeConfig; >=20 > + >=20 > + // >=20 > + // Get requisite IP Config Blocks which needs to be used here >=20 > + // >=20 > + Status =3D GetConfigBlock ((VOID *) SaPolicy, &gVtdDxeConfigGuid, (VOI= D > *)&VtdDxeConfig); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + >=20 > + DEBUG_CODE_BEGIN (); >=20 > + DEBUG ((DEBUG_INFO, "\n------------------------ Vtd Policy (DXE) print > BEGIN -----------------\n")); >=20 > + DEBUG ((DEBUG_INFO, " Revision : %d\n", VtdDxeConfig- > >Header.Revision)); >=20 > + ASSERT (VtdDxeConfig->Header.Revision =3D=3D > VTD_DXE_CONFIG_REVISION); >=20 > + DEBUG ((DEBUG_INFO, "\n------------------------ Vtd Policy (DXE) print= END - > ----------------\n")); >=20 > + DEBUG_CODE_END (); >=20 > + return; >=20 > +} >=20 > + >=20 > +/** >=20 > + This function Load default Vtd DXE policy. >=20 > + >=20 > + @param[in] ConfigBlockPointer The pointer to add VTD config block >=20 > +**/ >=20 > +VOID >=20 > +VtdLoadDefaultDxe ( >=20 > + IN VOID *ConfigBlockPointer >=20 > + ) >=20 > +{ >=20 > + VTD_DXE_CONFIG *VtdDxeConfig; >=20 > + >=20 > + VtdDxeConfig =3D ConfigBlockPointer; >=20 > + DEBUG ((DEBUG_INFO, "VtdDxeConfig->Header.GuidHob.Name =3D %g\n", > &VtdDxeConfig->Header.GuidHob.Name)); >=20 > + DEBUG ((DEBUG_INFO, "VtdDxeConfig- > >Header.GuidHob.Header.HobLength =3D 0x%x\n", VtdDxeConfig- > >Header.GuidHob.Header.HobLength)); >=20 > +} >=20 > + >=20 > +static COMPONENT_BLOCK_ENTRY mVtdDxeIpBlock =3D { >=20 > + &gVtdDxeConfigGuid, sizeof (VTD_DXE_CONFIG), > VTD_DXE_CONFIG_REVISION, VtdLoadDefaultDxe >=20 > +}; >=20 > + >=20 > +/** >=20 > + Get VTD DXE config block table total size. >=20 > + >=20 > + @retval Size of VTD DXE config block table >=20 > +**/ >=20 > +UINT16 >=20 > +EFIAPI >=20 > +VtdGetConfigBlockTotalSizeDxe ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return mVtdDxeIpBlock.Size; >=20 > +} >=20 > + >=20 > +/** >=20 > + VtdAddConfigBlocks add VTD DXE config block. >=20 > + >=20 > + @param[in] ConfigBlockTableAddress The pointer to add VTD config > blocks >=20 > + >=20 > + @retval EFI_SUCCESS The policy default is initialize= d. >=20 > + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create > buffer >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +VtdAddConfigBlocksDxe ( >=20 > + IN VOID *ConfigBlockTableAddress >=20 > + ) >=20 > +{ >=20 > + EFI_STATUS Status; >=20 > + Status =3D AddComponentConfigBlocks (ConfigBlockTableAddress, > &mVtdDxeIpBlock, 1); >=20 > + return Status; >=20 > +} >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Vtd/LibraryPrivate/DxeVtdPoli= cyLi > b/DxeVtdPolicyLib.inf > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Vtd/LibraryPrivate/DxeVtdPoli= cyL > ib/DxeVtdPolicyLib.inf > new file mode 100644 > index 0000000000..1fe288416a > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Vtd/LibraryPrivate/DxeVtdPoli= cyL > ib/DxeVtdPolicyLib.inf > @@ -0,0 +1,35 @@ > +## @file >=20 > +# Component description file for the DxeVtdPolicy library. >=20 > +# >=20 > +# Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > +# SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +# >=20 > +## >=20 > + >=20 > +[Defines] >=20 > +INF_VERSION =3D 0x00010017 >=20 > +BASE_NAME =3D DxeVtdPolicyLib >=20 > +FILE_GUID =3D 54754C6D-4883-4B67-BBBA-49D241539BE7 >=20 > +VERSION_STRING =3D 1.0 >=20 > +MODULE_TYPE =3D BASE >=20 > +LIBRARY_CLASS =3D DxeVtdPolicyLib >=20 > + >=20 > +[LibraryClasses] >=20 > +BaseMemoryLib >=20 > +UefiRuntimeServicesTableLib >=20 > +UefiBootServicesTableLib >=20 > +DebugLib >=20 > +PostCodeLib >=20 > +ConfigBlockLib >=20 > +HobLib >=20 > +SiConfigBlockLib >=20 > + >=20 > +[Packages] >=20 > +MdePkg/MdePkg.dec >=20 > +TigerlakeSiliconPkg/SiPkg.dec >=20 > + >=20 > +[Sources] >=20 > +DxeVtdPolicyLib.c >=20 > + >=20 > +[Guids] >=20 > +gVtdDxeConfigGuid >=20 > -- > 2.24.0.windows.2