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Thread-Topic: [edk2-devel] [PATCH v1 4/9] MdePkg/BaseCacheMaintenanceLib: RISC-V cache maintenance implementation. Thread-Index: AQHWDw32FSOrqFSvLUy7Zy6q+yfpdaiDLytQ Date: Tue, 21 Apr 2020 06:32:37 +0000 Message-ID: References: <20200410072112.7310-1-abner.chang@hpe.com> <20200410072112.7310-5-abner.chang@hpe.com> In-Reply-To: <20200410072112.7310-5-abner.chang@hpe.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-reaction: no-action dlp-version: 11.2.0.6 dlp-product: dlpe-windows authentication-results: spf=none (sender IP is ) smtp.mailfrom=zhiguang.liu@intel.com; x-originating-ip: [192.102.204.36] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 87f76864-6272-46fd-3029-08d7e5bdc8de x-ms-traffictypediagnostic: BN7PR11MB2722: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:5516; x-forefront-prvs: 038002787A x-forefront-antispam-report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:BN7PR11MB2804.namprd11.prod.outlook.com;PTR:;CAT:NONE;SFTY:;SFS:(10019020)(396003)(366004)(376002)(39860400002)(136003)(346002)(4326008)(316002)(55016002)(110136005)(53546011)(9686003)(26005)(30864003)(2906002)(5660300002)(6506007)(86362001)(107886003)(54906003)(7696005)(81156014)(8936002)(186003)(76116006)(52536014)(71200400001)(33656002)(966005)(478600001)(66946007)(66446008)(66476007)(64756008)(66556008)(8676002);DIR:OUT;SFP:1102; x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: t5WqWhoa9Dw8PVyonafOH00NDAufl8p7/yzowf5kjUkri/aqagP6w7hkwPKV9CbVt6M1VvOHMcaGmB06qGp0Y4h7IgyB6YQnH4mMH3GBi3+N9ORdEHbgG8kDA7IyH7grPTN+dHvpnTCEmRoPCibVIKdsmMtQ6is9eF3SCvGiV1wEP4W1sqNSGwPj3ZZIYM6ZfOWUE4EdfsHebyd9o4i2ttwZ7znFlS4iREi1fFmM9n2h12q71JbW7peTbEhZ8r0WvRSroCYXYhjOuBKol8AuMuYFoTTZZAdIazYoGoTa39IGj6+O37k2JGnyoxoCetsfJZdr29qCNOQwRVktjXNn5P/I8r7wa+Vh/t20AQnfzBxWCBLsdcKvmYO58gw8chyayNP0Y+yWSSKhuaOlGL6tJENoznVcORDyw329JWncdU0tCltSPl/8uPpOOeTM0InCaSxP9IxjXE3FTNRhYawHkD52mf8Kj3AxI92RnHpooz6aBUEvGNLF7G3NkK0MMFQzy1oIZSvcNl5IUE3LUpisbw== x-ms-exchange-antispam-messagedata: hLR/9+ww2s0V//cbXHZGO9RxAZ8BZ5xibqXhYaL6MxrO/d4oOTg6lwOuq0GPM5pD54ecO2r6g2IIzxt6DdJxrldCwe+GzQpJO+a/fPi1pehobPuBc7Z1WeV03UrbiOjQLEzfJMN3lX5I0TncW4lrcA== MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 87f76864-6272-46fd-3029-08d7e5bdc8de X-MS-Exchange-CrossTenant-originalarrivaltime: 21 Apr 2020 06:32:37.6419 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: wRN+ztrrtuh/6FL534BHvi7iemFfdG0u7GtfuBmcC6zkVpuyB3ha2LgqYHBFzc+k2l+zrlKglPPMZ7HmK/Akdg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN7PR11MB2722 Return-Path: zhiguang.liu@intel.com X-OriginatorOrg: intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Zhiguang Liu -----Original Message----- From: devel@edk2.groups.io On Behalf Of Abner Chang Sent: Friday, April 10, 2020 3:21 PM To: devel@edk2.groups.io Cc: abner.chang@hpe.com; Gilbert Chen ; Leif Lindholm= ; Kinney, Michael D = ; Gao, Liming Subject: [edk2-devel] [PATCH v1 4/9] MdePkg/BaseCacheMaintenanceLib: RISC-V= cache maintenance implementation. Implement RISC-V cache maintenance functions in BaseCacheMaintenanceLib. Signed-off-by: Abner Chang Co-authored-by: Gilbert Chen Reviewed-by: Leif Lindholm Cc: Michael D Kinney Cc: Liming Gao Cc: Leif Lindholm Cc: Gilbert Chen --- .../BaseCacheMaintenanceLib.inf | 4 + .../BaseCacheMaintenanceLib/RiscVCache.c | 250 ++++++++++++++++++ 2 files changed, 254 insertions(+) create mode 100644 MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib= .inf b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf index ec7feecf9c..33114243d5 100644 --- a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf +++ b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf @@ -6,6 +6,7 @@ # # Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -41,6 +42,9 @@ [Sources.AARCH64] ArmCache.c =20 +[Sources.RISCV64] + RiscVCache.c + [Packages] MdePkg/MdePkg.dec =20 diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c b/MdePkg/L= ibrary/BaseCacheMaintenanceLib/RiscVCache.c new file mode 100644 index 0000000000..21a695c843 --- /dev/null +++ b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c @@ -0,0 +1,250 @@ +/** @file + RISC-V specific functionality for cache. + + Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include + +/** + RISC-V invalidate instruction cache. + +**/ +VOID +EFIAPI +RiscVInvalidateInstCacheAsm ( + VOID + ); + +/** + RISC-V invalidate data cache. + +**/ +VOID +EFIAPI +RiscVInvalidateDataCacheAsm ( + VOID + ); + +/** + Invalidates the entire instruction cache in cache coherency domain of th= e + calling CPU. + +**/ +VOID +EFIAPI +InvalidateInstructionCache ( + VOID + ) +{ + RiscVInvalidateInstCacheAsm (); +} + +/** + Invalidates a range of instruction cache lines in the cache coherency do= main + of the calling CPU. + + Invalidates the instruction cache lines specified by Address and Length.= If + Address is not aligned on a cache line boundary, then entire instruction + cache line containing Address is invalidated. If Address + Length is not + aligned on a cache line boundary, then the entire instruction cache line + containing Address + Length -1 is invalidated. This function may choose = to + invalidate the entire instruction cache if that is more efficient than + invalidating the specified range. If Length is 0, then no instruction ca= che + lines are invalidated. Address is returned. + + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). + + @param Address The base address of the instruction cache lines to + invalidate. If the CPU is in a physical addressing mode,= then + Address is a physical address. If the CPU is in a virtua= l + addressing mode, then Address is a virtual address. + + @param Length The number of bytes to invalidate from the instruction c= ache. + + @return Address. + +**/ +VOID * +EFIAPI +InvalidateInstructionCacheRange ( + IN VOID *Address, + IN UINTN Length + ) +{ + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __FUNCTION__)); + return Address; +} + +/** + Writes back and invalidates the entire data cache in cache coherency dom= ain + of the calling CPU. + + Writes back and invalidates the entire data cache in cache coherency dom= ain + of the calling CPU. This function guarantees that all dirty cache lines = are + written back to system memory, and also invalidates all the data cache l= ines + in the cache coherency domain of the calling CPU. + +**/ +VOID +EFIAPI +WriteBackInvalidateDataCache ( + VOID + ) +{ + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __FUNCTION__)); +} + +/** + Writes back and invalidates a range of data cache lines in the cache + coherency domain of the calling CPU. + + Writes back and invalidates the data cache lines specified by Address an= d + Length. If Address is not aligned on a cache line boundary, then entire = data + cache line containing Address is written back and invalidated. If Addres= s + + Length is not aligned on a cache line boundary, then the entire data cac= he + line containing Address + Length -1 is written back and invalidated. Thi= s + function may choose to write back and invalidate the entire data cache i= f + that is more efficient than writing back and invalidating the specified + range. If Length is 0, then no data cache lines are written back and + invalidated. Address is returned. + + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). + + @param Address The base address of the data cache lines to write back a= nd + invalidate. If the CPU is in a physical addressing mode,= then + Address is a physical address. If the CPU is in a virtua= l + addressing mode, then Address is a virtual address. + @param Length The number of bytes to write back and invalidate from th= e + data cache. + + @return Address of cache invalidation. + +**/ +VOID * +EFIAPI +WriteBackInvalidateDataCacheRange ( + IN VOID *Address, + IN UINTN Length + ) +{ + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __FUNCTION__)); + return Address; +} + +/** + Writes back the entire data cache in cache coherency domain of the calli= ng + CPU. + + Writes back the entire data cache in cache coherency domain of the calli= ng + CPU. This function guarantees that all dirty cache lines are written bac= k to + system memory. This function may also invalidate all the data cache line= s in + the cache coherency domain of the calling CPU. + +**/ +VOID +EFIAPI +WriteBackDataCache ( + VOID + ) +{ + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __FUNCTION__)); +} + +/** + Writes back a range of data cache lines in the cache coherency domain of= the + calling CPU. + + Writes back the data cache lines specified by Address and Length. If Add= ress + is not aligned on a cache line boundary, then entire data cache line + containing Address is written back. If Address + Length is not aligned o= n a + cache line boundary, then the entire data cache line containing Address = + + Length -1 is written back. This function may choose to write back the en= tire + data cache if that is more efficient than writing back the specified ran= ge. + If Length is 0, then no data cache lines are written back. This function= may + also invalidate all the data cache lines in the specified range of the c= ache + coherency domain of the calling CPU. Address is returned. + + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). + + @param Address The base address of the data cache lines to write back. = If + the CPU is in a physical addressing mode, then Address i= s a + physical address. If the CPU is in a virtual addressing + mode, then Address is a virtual address. + @param Length The number of bytes to write back from the data cache. + + @return Address of cache written in main memory. + +**/ +VOID * +EFIAPI +WriteBackDataCacheRange ( + IN VOID *Address, + IN UINTN Length + ) +{ + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __FUNCTION__)); + return Address; +} + +/** + Invalidates the entire data cache in cache coherency domain of the calli= ng + CPU. + + Invalidates the entire data cache in cache coherency domain of the calli= ng + CPU. This function must be used with care because dirty cache lines are = not + written back to system memory. It is typically used for cache diagnostic= s. If + the CPU does not support invalidation of the entire data cache, then a w= rite + back and invalidate operation should be performed on the entire data cac= he. + +**/ +VOID +EFIAPI +InvalidateDataCache ( + VOID + ) +{ + RiscVInvalidateDataCacheAsm (); +} + +/** + Invalidates a range of data cache lines in the cache coherency domain of= the + calling CPU. + + Invalidates the data cache lines specified by Address and Length. If Add= ress + is not aligned on a cache line boundary, then entire data cache line + containing Address is invalidated. If Address + Length is not aligned on= a + cache line boundary, then the entire data cache line containing Address = + + Length -1 is invalidated. This function must never invalidate any cache = lines + outside the specified range. If Length is 0, then no data cache lines ar= e + invalidated. Address is returned. This function must be used with care + because dirty cache lines are not written back to system memory. It is + typically used for cache diagnostics. If the CPU does not support + invalidation of a data cache range, then a write back and invalidate + operation should be performed on the data cache range. + + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). + + @param Address The base address of the data cache lines to invalidate. = If + the CPU is in a physical addressing mode, then Address i= s a + physical address. If the CPU is in a virtual addressing = mode, + then Address is a virtual address. + @param Length The number of bytes to invalidate from the data cache. + + @return Address. + +**/ +VOID * +EFIAPI +InvalidateDataCacheRange ( + IN VOID *Address, + IN UINTN Length + ) +{ + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __FUNCTION__)); + return Address; +} --=20 2.25.0 -=3D-=3D-=3D-=3D-=3D-=3D Groups.io Links: You receive all messages sent to this group. View/Reply Online (#57195): https://edk2.groups.io/g/devel/message/57195 Mute This Topic: https://groups.io/mt/72916362/1779286 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [zhiguang.liu@intel.com] -=3D-=3D-=3D-=3D-=3D-=3D