From: "Zhiguang Liu" <zhiguang.liu@intel.com>
To: "devel@edk2.groups.io" <devel@edk2.groups.io>,
"abner.chang@hpe.com" <abner.chang@hpe.com>
Cc: Gilbert Chen <gilbert.chen@hpe.com>,
Leif Lindholm <leif.lindholm@linaro.org>,
"Kinney, Michael D" <michael.d.kinney@intel.com>,
"Gao, Liming" <liming.gao@intel.com>
Subject: Re: [edk2-devel] [PATCH v1 8/9] MdePkg/BaseSynchronizationLib: RISC-V cache related code.
Date: Tue, 21 Apr 2020 06:36:35 +0000 [thread overview]
Message-ID: <BN7PR11MB280437D353A2D7489868856F90D50@BN7PR11MB2804.namprd11.prod.outlook.com> (raw)
In-Reply-To: <20200410072112.7310-9-abner.chang@hpe.com>
Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com>
-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Abner Chang
Sent: Friday, April 10, 2020 3:21 PM
To: devel@edk2.groups.io
Cc: abner.chang@hpe.com; Gilbert Chen <gilbert.chen@hpe.com>; Leif Lindholm <leif.lindholm@linaro.org>; Kinney, Michael D <michael.d.kinney@intel.com>; Gao, Liming <liming.gao@intel.com>
Subject: [edk2-devel] [PATCH v1 8/9] MdePkg/BaseSynchronizationLib: RISC-V cache related code.
Support RISC-V cache related functions.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
---
.../BaseSynchronizationLib.inf | 5 ++
.../RiscV64/SynchronizationAsm.S | 78 +++++++++++++++++++
2 files changed, 83 insertions(+)
create mode 100644 MdePkg/Library/BaseSynchronizationLib/RiscV64/SynchronizationAsm.S
diff --git a/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf b/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
index 446bc19b63..9309d2e1d5 100755
--- a/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
+++ b/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
@@ -3,6 +3,7 @@
# # Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR> # Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>+# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR> # # SPDX-License-Identifier: BSD-2-Clause-Patent #@@ -78,6 +79,10 @@
AArch64/Synchronization.S | GCC AArch64/Synchronization.asm | MSFT +[Sources.RISCV64]+ Synchronization.c+ RiscV64/SynchronizationAsm.S+ [Packages] MdePkg/MdePkg.dec diff --git a/MdePkg/Library/BaseSynchronizationLib/RiscV64/SynchronizationAsm.S b/MdePkg/Library/BaseSynchronizationLib/RiscV64/SynchronizationAsm.S
new file mode 100644
index 0000000000..bac80d6871
--- /dev/null
+++ b/MdePkg/Library/BaseSynchronizationLib/RiscV64/SynchronizationAsm.S
@@ -0,0 +1,78 @@
+//------------------------------------------------------------------------------+//+// RISC-V synchronization functions.+//+// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>+//+// SPDX-License-Identifier: BSD-2-Clause-Patent+//+//------------------------------------------------------------------------------+#include <Base.h>++.data++.text+.align 3++.global ASM_PFX(InternalSyncCompareExchange32)+.global ASM_PFX(InternalSyncCompareExchange64)+.global ASM_PFX(InternalSyncIncrement)+.global ASM_PFX(InternalSyncDecrement)++//+// ompare and xchange a 32-bit value.+//+// @param a0 : Pointer to 32-bit value.+// @param a1 : Compare value.+// @param a2 : Exchange value.+//+ASM_PFX (InternalSyncCompareExchange32):+ lr.w a3, (a0) // Load the value from a0 and make+ // the reservation of address.+ bne a3, a1, exit+ sc.w a3, a2, (a0) // Write the value back to the address.+ mv a3, a1+exit:+ mv a0, a3+ ret++.global ASM_PFX(InternalSyncCompareExchange64)++//+// Compare and xchange a 64-bit value.+//+// @param a0 : Pointer to 64-bit value.+// @param a1 : Compare value.+// @param a2 : Exchange value.+//+ASM_PFX (SyncCompareExchange64):+ lr.d a3, (a0) // Load the value from a0 and make+ // the reservation of address.+ bne a3, a1, exit+ sc.d a3, a2, (a0) // Write the value back to the address.+ mv a3, a1+exit2:+ mv a0, a3+ ret++//+// Performs an atomic increment of an 32-bit unsigned integer.+//+// @param a0 : Pointer to 32-bit value.+//+ASM_PFX (InternalSyncIncrement):+ li a1, 1+ amoadd.w a2, a1, (a0)+ mv a0, a2+ ret++//+// Performs an atomic decrement of an 32-bit unsigned integer.+//+// @param a0 : Pointer to 32-bit value.+//+ASM_PFX (InternalSyncDecrement):+ li a1, -1+ amoadd.w a2, a1, (a0)+ mv a0, a2+ ret--
2.25.0
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next prev parent reply other threads:[~2020-04-21 6:36 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-10 7:21 [PATCH v1 0/9] MdePkg changes for RISC-V edk2 port Abner Chang
2020-04-10 7:21 ` [PATCH v1 1/9] MdePkg: RISC-V RV64 binding in MdePkg Abner Chang
2020-04-21 6:30 ` [edk2-devel] " Zhiguang Liu
2020-04-10 7:21 ` [PATCH v1 2/9] MdePkg/Include: RISC-V definitions Abner Chang
2020-04-21 6:32 ` [edk2-devel] " Zhiguang Liu
2020-04-10 7:21 ` [PATCH v1 3/9] MdePkg/BaseLib: BaseLib for RISC-V RV64 Processor Abner Chang
2020-04-21 6:32 ` [edk2-devel] " Zhiguang Liu
2020-04-10 7:21 ` [PATCH v1 4/9] MdePkg/BaseCacheMaintenanceLib: RISC-V cache maintenance implementation Abner Chang
2020-04-21 6:32 ` [edk2-devel] " Zhiguang Liu
2020-04-10 7:21 ` [PATCH v1 5/9] MdePkg/BaseIoLibIntrinsic: Rename IoLibArm.c=>IoLibNoIo.c Abner Chang
2020-04-21 6:36 ` [edk2-devel] " Zhiguang Liu
2020-04-21 8:21 ` Abner Chang
2020-04-10 7:21 ` [PATCH v1 6/9] MdePkg/BasePeCoff: Add RISC-V PE/Coff related code Abner Chang
2020-04-21 6:36 ` [edk2-devel] " Zhiguang Liu
2020-04-10 7:21 ` [PATCH v1 7/9] MdePkg/BaseCpuLib: RISC-V Base CPU library implementation Abner Chang
2020-04-21 6:36 ` [edk2-devel] " Zhiguang Liu
2020-04-10 7:21 ` [PATCH v1 8/9] MdePkg/BaseSynchronizationLib: RISC-V cache related code Abner Chang
2020-04-21 6:36 ` Zhiguang Liu [this message]
2020-04-10 7:21 ` [PATCH v1 9/9] MdePkg/BaseSafeIntLib: Add RISCV64 arch for BaseSafeIntLib Abner Chang
2020-04-21 6:36 ` [edk2-devel] " Zhiguang Liu
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