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Thread-Topic: [edk2-devel] [PATCH v1 8/9] MdePkg/BaseSynchronizationLib: RISC-V cache related code. Thread-Index: AQHWDw4EdV/2MLYjRUmntzJSwmRRRKiDMETQ Date: Tue, 21 Apr 2020 06:36:35 +0000 Message-ID: References: <20200410072112.7310-1-abner.chang@hpe.com> <20200410072112.7310-9-abner.chang@hpe.com> In-Reply-To: <20200410072112.7310-9-abner.chang@hpe.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-reaction: no-action dlp-version: 11.2.0.6 dlp-product: dlpe-windows authentication-results: spf=none (sender IP is ) smtp.mailfrom=zhiguang.liu@intel.com; x-originating-ip: [192.102.204.36] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: f89b5002-7bc3-48a8-e526-08d7e5be56ee x-ms-traffictypediagnostic: BN7PR11MB2722: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:3383; x-forefront-prvs: 038002787A x-forefront-antispam-report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:BN7PR11MB2804.namprd11.prod.outlook.com;PTR:;CAT:NONE;SFTY:;SFS:(10019020)(396003)(366004)(376002)(39860400002)(136003)(346002)(4326008)(316002)(55016002)(110136005)(53546011)(9686003)(26005)(2906002)(5660300002)(19627235002)(6506007)(86362001)(107886003)(54906003)(7696005)(81156014)(8936002)(186003)(76116006)(52536014)(71200400001)(33656002)(966005)(478600001)(66946007)(66446008)(66476007)(64756008)(66556008)(8676002);DIR:OUT;SFP:1102; x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: FpEB72BVqyTapm6QnsDphDYt53DRQA+YKFH/0FxtjUW+//+HWXWEcl79b2dogkD89KeEvOQslZC7Rthn/w9W7+Ll2H/ErDMU31bk+6mdR1R+sYPd9L8yJvVh9MUS/VN8/7tDQ3UUiPX5dp0Dx4bGW9WiFM3ITjVvLuycPOPzPpD9UwkB/ZQO8RqvuKMPElNRC2YbMduX2eEwlQxMsFUntv90SDoPfKy+KPWo+Wl87w2Dt91CuLQ43TCQ0GGiCocMsgn8KMTRDabxRDfa5MJ0QFBAUoTUIRl+KwhvIRUyhiajc4f8eTkRCuPYtMZqe3BNu4NlAYPSvsgxgOOxuawmuHIX4Jkyy4meCIeSUKaYteNHAzHAodgDmelRhaayg1rFNv22KH4PUQTVY3jKxpn4soma/26Exl5M6gCtmFHfSqNYo5uTBjFAK4n7UxoRNLaL3mcuCdetu8lRYXseB6bQoGbFphISWJDriMH9Acv1Cw8R4B+KoB9NgYJKFQfni+uW+6JcCrScRiwkAMWwNmLxwQ== x-ms-exchange-antispam-messagedata: 1aVnmM+OKxzVSQORd7m9wZIc/zJZUo+7OrDjU+pm76BxKZL/3mhcD0lXke6YXVUx4U9W74p7zo6l5PcJqUXf4Lhuo67bWYpM2h8O3HkkMlzeNer0GSFb+GqLU0JjwR03qtQZK7OreDsGtv2JAMzvlg== MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: f89b5002-7bc3-48a8-e526-08d7e5be56ee X-MS-Exchange-CrossTenant-originalarrivaltime: 21 Apr 2020 06:36:35.9879 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: fxBxcdnfpwTe2ZpU+HnVFvBnsX3XL++RjhL4DmMWlvw+BPkmTOI4cGkACy1Nl6RnvZNdCSoXJ7lET53Pulz2qQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN7PR11MB2722 Return-Path: zhiguang.liu@intel.com X-OriginatorOrg: intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Zhiguang Liu -----Original Message----- From: devel@edk2.groups.io On Behalf Of Abner Chang Sent: Friday, April 10, 2020 3:21 PM To: devel@edk2.groups.io Cc: abner.chang@hpe.com; Gilbert Chen ; Leif Lindholm= ; Kinney, Michael D = ; Gao, Liming Subject: [edk2-devel] [PATCH v1 8/9] MdePkg/BaseSynchronizationLib: RISC-V = cache related code. Support RISC-V cache related functions. Signed-off-by: Abner Chang Co-authored-by: Gilbert Chen Reviewed-by: Leif Lindholm Cc: Michael D Kinney Cc: Liming Gao Cc: Leif Lindholm Cc: Gilbert Chen --- .../BaseSynchronizationLib.inf | 5 ++ .../RiscV64/SynchronizationAsm.S | 78 +++++++++++++++++++ 2 files changed, 83 insertions(+) create mode 100644 MdePkg/Library/BaseSynchronizationLib/RiscV64/Synchroni= zationAsm.S diff --git a/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.i= nf b/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf index 446bc19b63..9309d2e1d5 100755 --- a/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf +++ b/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf @@ -3,6 +3,7 @@ # # Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved. # Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.+# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rig= hts reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent #@@ -78= ,6 +79,10 @@ AArch64/Synchronization.S | GCC AArch64/Synchronization.asm | MS= FT +[Sources.RISCV64]+ Synchronization.c+ RiscV64/SynchronizationAsm.S+ [= Packages] MdePkg/MdePkg.dec diff --git a/MdePkg/Library/BaseSynchronizati= onLib/RiscV64/SynchronizationAsm.S b/MdePkg/Library/BaseSynchronizationLib/= RiscV64/SynchronizationAsm.S new file mode 100644 index 0000000000..bac80d6871 --- /dev/null +++ b/MdePkg/Library/BaseSynchronizationLib/RiscV64/SynchronizationAsm.S @@ -0,0 +1,78 @@ +//------------------------------------------------------------------------= ------+//+// RISC-V synchronization functions.+//+// Copyright (c) 2020, He= wlett Packard Enterprise Development LP. All rights reserved.
+//+// SPD= X-License-Identifier: BSD-2-Clause-Patent+//+//----------------------------= --------------------------------------------------+#include ++.data= ++.text+.align 3++.global ASM_PFX(InternalSyncCompareExchange32)+.global AS= M_PFX(InternalSyncCompareExchange64)+.global ASM_PFX(InternalSyncIncrement)= +.global ASM_PFX(InternalSyncDecrement)++//+// ompare and xchange a 32-bit = value.+//+// @param a0 : Pointer to 32-bit value.+// @param a1 : Compare va= lue.+// @param a2 : Exchange value.+//+ASM_PFX (InternalSyncCompareExchange= 32):+ lr.w a3, (a0) // Load the value from a0 and make+ = // the reservation of address.+ bne a3, a1, exit+ = sc.w a3, a2, (a0) // Write the value back to the address.+ mv a3,= a1+exit:+ mv a0, a3+ ret++.global ASM_PFX(InternalSyncCompareExch= ange64)++//+// Compare and xchange a 64-bit value.+//+// @param a0 : Pointe= r to 64-bit value.+// @param a1 : Compare value.+// @param a2 : Exchange va= lue.+//+ASM_PFX (SyncCompareExchange64):+ lr.d a3, (a0) // Load t= he value from a0 and make+ // the reservation of ad= dress.+ bne a3, a1, exit+ sc.d a3, a2, (a0) // Write the value b= ack to the address.+ mv a3, a1+exit2:+ mv a0, a3+ ret++//+//= Performs an atomic increment of an 32-bit unsigned integer.+//+// @param a= 0 : Pointer to 32-bit value.+//+ASM_PFX (InternalSyncIncrement):+ li a1= , 1+ amoadd.w a2, a1, (a0)+ mv a0, a2+ ret++//+// Performs an at= omic decrement of an 32-bit unsigned integer.+//+// @param a0 : Pointer to = 32-bit value.+//+ASM_PFX (InternalSyncDecrement):+ li a1, -1+ amoadd= .w a2, a1, (a0)+ mv a0, a2+ ret--=20 2.25.0 -=3D-=3D-=3D-=3D-=3D-=3D Groups.io Links: You receive all messages sent to this group. View/Reply Online (#57198): https://edk2.groups.io/g/devel/message/57198 Mute This Topic: https://groups.io/mt/72916365/1779286 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [zhiguang.liu@intel.com]= -=3D-=3D-=3D-=3D-=3D-=3D