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Thread-Topic: [edk2-devel] [PATCH v1 7/9] MdePkg/BaseCpuLib: RISC-V Base CPU library implementation. Thread-Index: AQHWDw4FKq1ly1cYtEOZ0GPv3eLrMaiDME0Q Date: Tue, 21 Apr 2020 06:36:45 +0000 Message-ID: References: <20200410072112.7310-1-abner.chang@hpe.com> <20200410072112.7310-8-abner.chang@hpe.com> In-Reply-To: <20200410072112.7310-8-abner.chang@hpe.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-reaction: no-action dlp-version: 11.2.0.6 dlp-product: dlpe-windows authentication-results: spf=none (sender IP is ) smtp.mailfrom=zhiguang.liu@intel.com; x-originating-ip: [192.102.204.36] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: a8b2c9d9-3d46-4938-8f27-08d7e5be5ca6 x-ms-traffictypediagnostic: BN7PR11MB2722: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:513; x-forefront-prvs: 038002787A x-forefront-antispam-report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:BN7PR11MB2804.namprd11.prod.outlook.com;PTR:;CAT:NONE;SFTY:;SFS:(10019020)(396003)(366004)(376002)(39860400002)(136003)(346002)(4326008)(316002)(55016002)(110136005)(53546011)(9686003)(26005)(2906002)(5660300002)(19627235002)(6506007)(86362001)(107886003)(54906003)(7696005)(81156014)(8936002)(186003)(76116006)(52536014)(71200400001)(33656002)(966005)(478600001)(66946007)(66446008)(66476007)(64756008)(66556008)(8676002);DIR:OUT;SFP:1102; x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: A1TD15JyiA0LgAkUTW5Oy9JtPhHx2qzaqkTDBeUo+ZwWzuwAYKHZy5njSN4HQk/ULbrBKkIWURo96+Llc3x2MY6LEkHccHQt4nOcq9PnH5SKS7vQUMJu8KRLfT/6g1pJKJKpV5YE6+i4v8yUQIgr10YMeR4Z4hhkOZCxfCMKg91JVDJmSuCOYr7gtUrIZBh8vftJ9bmoamJpz0FQLRWBW8M6q2NlTDg0bPOAWQSkovsc70BftLJ7xIGqMxpKos1rG2Jsdso/MhTHeELtRBl89uhEoZy0Beh9+rw68iS2YsvA9DICnoz+S2wilpBxpYRj9gTjD5Zf3jXjiYzaAdMr7ePcO940tXBWGCNu+5gV1aoZm8hfn70U0Wm21bK3ZC6G99a4sqvHKDpq8F+9ifypOmdQLectRUrxz4NDc39YX7WV4tzfNCCQVT1TW1l7EfKQqEhnpfa7tCn0J31ng3ky0ofdG2nKUk21EBgpTZdRxW3ilQ+Ns7qo0jka2rYVA40/fFIUyjKuEAfTXVRSs1rX/Q== x-ms-exchange-antispam-messagedata: iR2S7WdcbxgC1kwRbdo3ILdBKr0ar9oVQDaAITFSNYOjG6gEbMFT7bsKCRVmCwBa2A/nPoq5UQt1DfpclNvT3nGV/U+klg2phJwIStRgmTEiKU4b7pIbuAcjwankHVowJYaiXhioNtllz+GqIsE2dw== MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: a8b2c9d9-3d46-4938-8f27-08d7e5be5ca6 X-MS-Exchange-CrossTenant-originalarrivaltime: 21 Apr 2020 06:36:45.4972 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 1303PaMNF+F5lQxrkiKHCLHJ6B9TTFHOxARU803DGIU1XzlNHiXy95B5oB8Lh6o26VA7Mar9ZXhdOBFBj45rLA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN7PR11MB2722 Return-Path: zhiguang.liu@intel.com X-OriginatorOrg: intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Zhiguang Liu -----Original Message----- From: devel@edk2.groups.io On Behalf Of Abner Chang Sent: Friday, April 10, 2020 3:21 PM To: devel@edk2.groups.io Cc: abner.chang@hpe.com; Gilbert Chen ; Leif Lindholm= ; Kinney, Michael D = ; Gao, Liming Subject: [edk2-devel] [PATCH v1 7/9] MdePkg/BaseCpuLib: RISC-V Base CPU lib= rary implementation. Implement RISC-V CPU related functions in BaseCpuLib. Signed-off-by: Abner Chang Co-authored-by: Gilbert Chen Reviewed-by: Leif Lindholm Cc: Michael D Kinney Cc: Liming Gao Cc: Leif Lindholm Cc: Gilbert Chen --- MdePkg/Library/BaseCpuLib/BaseCpuLib.inf | 6 +++++- MdePkg/Library/BaseC= puLib/BaseCpuLib.uni | 5 +++-- MdePkg/Library/BaseCpuLib/RiscV/Cpu.S | 19 +++++++++++++++++++ 3 files changed, 27 insertions(+), 3 deletions(-) create mode 100644 MdeP= kg/Library/BaseCpuLib/RiscV/Cpu.S diff --git a/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf b/MdePkg/Library/Base= CpuLib/BaseCpuLib.inf index a7cb381a85..950f5229b2 100644 --- a/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf +++ b/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf @@ -7,6 +7,7 @@ # Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
= # Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
= # Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
+# = Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights = reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent #@@ -24,7 += 25,7 @@ #-# VALID_ARCHITECTURES =3D IA32 X64 EBC ARM AARCH64+# VALID= _ARCHITECTURES =3D IA32 X64 EBC ARM AARCH64 RISCV64 # [Sources.I= A32]@@ -59,6 +60,9 @@ AArch64/CpuFlushTlb.asm | MSFT AArch64/CpuSleep.asm | MSFT +[Source= s.RISCV64]+ RiscV/Cpu.S+ [Packages] MdePkg/MdePkg.dec diff --git a/MdePk= g/Library/BaseCpuLib/BaseCpuLib.uni b/MdePkg/Library/BaseCpuLib/BaseCpuLib.= uni index fc95cda9fc..80dc495786 100644 --- a/MdePkg/Library/BaseCpuLib/BaseCpuLib.uni +++ b/MdePkg/Library/BaseCpuLib/BaseCpuLib.uni @@ -1,12 +1,13 @@ // /** @file // Instance of CPU Library for various architecture. //-// CP= U Library implemented using ASM functions for IA-32 and X64,+// CPU Library= implemented using ASM functions for IA-32, X64 and RISCV64, // PAL CALLs f= or IPF, and empty functions for EBC. // // Copyright (c) 2007 - 2014, Intel= Corporation. All rights reserved.
// Portions copyright (c) 2008 - 200= 9, Apple Inc. All rights reserved.
// Portions copyright (c) 2011 - 201= 3, ARM Ltd. All rights reserved.
+// Copyright (c) 2020, Hewlett Packard= Enterprise Development LP. All rights reserved.
// // SPDX-License-Ide= ntifier: BSD-2-Clause-Patent //@@ -15,5 +16,5 @@ #string STR_MODULE_ABSTRACT #language en-US "Instance of CPU = Library for various architectures" -#string STR_MODULE_DESCRIPTION = #language en-US "CPU Library implemented using ASM functions for IA-32 and= X64, PAL CALLs for IPF, and empty functions for EBC."+#string STR_MODULE_D= ESCRIPTION #language en-US "CPU Library implemented using ASM func= tions for IA-32, X64 and RISCV64, PAL CALLs for IPF, and empty functions fo= r EBC." diff --git a/MdePkg/Library/BaseCpuLib/RiscV/Cpu.S b/MdePkg/Library= /BaseCpuLib/RiscV/Cpu.S new file mode 100644 index 0000000000..375b91d314 --- /dev/null +++ b/MdePkg/Library/BaseCpuLib/RiscV/Cpu.S @@ -0,0 +1,19 @@ +//------------------------------------------------------------------------= ------+//+// CpuSleep for RISC-V+//+// Copyright (c) 2020, Hewlett Packard = Enterprise Development LP. All rights reserved.
+// SPDX-License-Identif= ier: BSD-2-Clause-Patent+//+//---------------------------------------------= ---------------------------------+.data+.align 3+.section .text++.global AS= M_PFX(_CpuSleep)++ASM_PFX(_CpuSleep):+ wfi+ ret++--=20 2.25.0 -=3D-=3D-=3D-=3D-=3D-=3D Groups.io Links: You receive all messages sent to this group. View/Reply Online (#57200): https://edk2.groups.io/g/devel/message/57200 Mute This Topic: https://groups.io/mt/72916367/1779286 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [zhiguang.liu@intel.com]= -=3D-=3D-=3D-=3D-=3D-=3D