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Thread-Topic: [edk2-devel] [PATCH v1 6/9] MdePkg/BasePeCoff: Add RISC-V PE/Coff related code. Thread-Index: AQHWDw36BuVfW9pcmkqGmZ8B+6GAdqiDMDJA Date: Tue, 21 Apr 2020 06:36:22 +0000 Message-ID: References: <20200410072112.7310-1-abner.chang@hpe.com> <20200410072112.7310-7-abner.chang@hpe.com> In-Reply-To: <20200410072112.7310-7-abner.chang@hpe.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-reaction: no-action dlp-version: 11.2.0.6 dlp-product: dlpe-windows authentication-results: spf=none (sender IP is ) smtp.mailfrom=zhiguang.liu@intel.com; x-originating-ip: [192.102.204.36] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: df6ca7c4-7974-47af-ce18-08d7e5be4f0f x-ms-traffictypediagnostic: BN7PR11MB2722: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:5516; x-forefront-prvs: 038002787A x-forefront-antispam-report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:BN7PR11MB2804.namprd11.prod.outlook.com;PTR:;CAT:NONE;SFTY:;SFS:(10019020)(6029001)(396003)(366004)(376002)(39860400002)(136003)(346002)(4326008)(316002)(55016002)(110136005)(53546011)(9686003)(26005)(2906002)(5660300002)(6506007)(86362001)(107886003)(54906003)(7696005)(81156014)(8936002)(186003)(76116006)(52536014)(71200400001)(33656002)(966005)(478600001)(66946007)(66446008)(66476007)(64756008)(66556008)(8676002);DIR:OUT;SFP:1102; x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: ml7SNWlT8rDTW0VKOQMy7kgjLwH0oqMn771Ph7cwWGXIm43DQjb6UEF+MYIRO2QIHzLfrRlWXuGgm/fPTOE44HEGbUGIKKHX21OnJUZTuYQcG03KlcVdSQXG8bzALWb46+gEzijwx/rj9ckJ5Dv+XLuzkqbNnxw6OwYF1nQROJLuyxLhEiMeQ6hgcrDfP59HfstnRozobTbjO0pYE9Igh7zmkxd9a6euw/ybAEDqYR+77aIek2g+SBqGGfrczWBjJLFt0rUgxCzotF6lCRQNNfgzpGBjBuCkyyDb4ZRZm7amSKNBHKnWch8Nq3oNXKRAGDxXOMU+aL82f6LYXzrjsToLPk0SW3WmKa0rFXFjUVGTJxeN92oZlzyuAvECKZXGVu/Yt0+lNbfEiwUsJwHder4xaWOobh8LGy7SxwGm1mTd2n5ObV3NnFBM+ABfYhSqr+B5rPc1rbyREGX1DKJeMGLE2048BcyvsBxCN9oNY48h3dr48Lzz2jzXtT9ZwmHsckHwik9+08tehxst1WH5Ng== x-ms-exchange-antispam-messagedata: gXYoorJzNcaRAyqVFgp/ZVSIgtgb3m98k2eaZv5y95D909GNTx1R+eFyawvM0w0/6BToi9M9NVyJD0W2zOvBlyQXYoP8XWkNgzMi5dj/mYN3FCuL46oumDc9RhPlkAofsNyAZiPNIEdh2aoMuBc8Iw== MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: df6ca7c4-7974-47af-ce18-08d7e5be4f0f X-MS-Exchange-CrossTenant-originalarrivaltime: 21 Apr 2020 06:36:22.7048 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: fdGckpMuMITAbNrtSzdhVYshWk6Dcypq8yHxbFUez3OmyDzgWInv9qHXVeJypOfk2yYEPaveYWlUfHy/RLBOnA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN7PR11MB2722 Return-Path: zhiguang.liu@intel.com X-OriginatorOrg: intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Zhiguang Liu -----Original Message----- From: devel@edk2.groups.io On Behalf Of Abner Chang Sent: Friday, April 10, 2020 3:21 PM To: devel@edk2.groups.io Cc: abner.chang@hpe.com; Gilbert Chen ; Leif Lindholm= ; Kinney, Michael D = ; Gao, Liming Subject: [edk2-devel] [PATCH v1 6/9] MdePkg/BasePeCoff: Add RISC-V PE/Coff = related code. Support RISC-V image relocation. Signed-off-by: Abner Chang Co-authored-by: Gilbert Chen Reviewed-by: Leif Lindholm Cc: Michael D Kinney Cc: Liming Gao Cc: Leif Lindholm Cc: Gilbert Chen --- .../Library/BasePeCoffLib/BasePeCoffLib.inf | 5 + .../BasePeCoffLib/BasePeCoffLibInternals.h | 9 ++ MdePkg/Library/BasePeCoffLib/BasePeCoff.c | 3 +- .../BasePeCoffLib/RiscV/PeCoffLoaderEx.c | 133 ++++++++++++++++++ .../Library/BasePeCoffLib/BasePeCoffLib.uni | 2 + 5 files changed, 151 insertions(+), 1 deletion(-) create mode 100644 MdeP= kg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c diff --git a/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf b/MdePkg/Librar= y/BasePeCoffLib/BasePeCoffLib.inf index 395c1403c0..110b6d5a09 100644 --- a/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf +++ b/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf @@ -3,6 +3,7 @@ # The IPF version library supports loading IPF and EBC PE/COFF image. # = The IA32 version library support loading IA32, X64 and EBC PE/COFF images. = # The X64 version library support loading IA32, X64 and EBC PE/COFF images= .+# The RISC-V version library support loading RISC-V images. # # Caution= : This module requires additional review when modified. # This library wil= l have external input - PE/COFF image.@@ -11,6 +12,7 @@ # # Copyright (c)= 2006 - 2018, Intel Corporation. All rights reserved.
# Portions copyr= ight (c) 2008 - 2009, Apple Inc. All rights reserved.
+# Portions Copyr= ight (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserv= ed.
# # SPDX-License-Identifier: BSD-2-Clause-Patent #@@ -41,6 +43,9 @= @ [Sources.ARM] Arm/PeCoffLoaderEx.c +[Sources.RISCV64]+ RiscV/PeCoffLoad= erEx.c+ [Packages] MdePkg/MdePkg.dec diff --git a/MdePkg/Library/BasePeCo= ffLib/BasePeCoffLibInternals.h b/MdePkg/Library/BasePeCoffLib/BasePeCoffLib= Internals.h index b74277f3e8..3ee56e0e5f 100644 --- a/MdePkg/Library/BasePeCoffLib/BasePeCoffLibInternals.h +++ b/MdePkg/Library/BasePeCoffLib/BasePeCoffLibInternals.h @@ -2,6 +2,7 @@ Declaration of internal functions in PE/COFF Lib. Copyright (c) 2006 = - 2010, Intel Corporation. All rights reserved.
+ Portions Copyright (c= ) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.
= SPDX-License-Identifier: BSD-2-Clause-Patent **/@@ -16,6 +17,14 @@ #include #include +//+// Macro definitions for RISC-V architecture.+//+#define RV_X(x, = s, n) (((x) >> (s)) & ((1<<(n))-1))+#define RISCV_IMM_BITS 12+#define RISCV= _IMM_REACH (1LL< = Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+ = Portions Copyright (c) 2020, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent **/d= iff --git a/MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c b/MdePkg/Li= brary/BasePeCoffLib/RiscV/PeCoffLoaderEx.c new file mode 100644 index 0000000000..23170a6603 --- /dev/null +++ b/MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c @@ -0,0 +1,133 @@ +/** @file+ PE/Coff loader for RISC-V PE image++ Portions Copyright (c) 2= 020, Hewlett Packard Enterprise Development LP. All rights reserved.
+ = SPDX-License-Identifier: BSD-2-Clause-Patent+**/+#include "BasePeCoffLibInt= ernals.h"+#include ++/**+ Performs an RISC-V specific r= elocation fixup and is a no-op on+ other instruction sets.+ RISC-V splits= 32-bit fixup into 20bit and 12-bit with two relocation+ types. We have to= know the lower 12-bit fixup first then we can deal+ carry over on high 20= -bit fixup. So we log the high 20-bit in+ FixupData.++ @param Reloc = The pointer to the relocation record.+ @param Fixup The pointer t= o the address to fix up.+ @param FixupData The pointer to a buffer to l= og the fixups.+ @param Adjust The offset to adjust the fixup.++ @re= turn Status code.++**/+RETURN_STATUS+PeCoffLoaderRelocateImageEx (+ IN UIN= T16 *Reloc,+ IN OUT CHAR8 *Fixup,+ IN OUT CHAR8 **FixupData,+ I= N UINT64 Adjust+ )+{+ UINT32 Value;+ UINT32 Value2;+ UINT32 *RiscV= Hi20Fixup;++ switch ((*Reloc) >> 12) {+ case EFI_IMAGE_REL_BASED_RISCV_HI= 20:+ *(UINT64 *)(*FixupData) =3D (UINT64)(UINTN)Fixup;+ break;++ = case EFI_IMAGE_REL_BASED_RISCV_LOW12I:+ RiscVHi20Fixup =3D (UINT32 *= )(*(UINT64 *)(*FixupData));+ if (RiscVHi20Fixup !=3D NULL) {++ = Value =3D (UINT32)(RV_X(*RiscVHi20Fixup, 12, 20) << 12);+ Value2 =3D= (UINT32)(RV_X(*(UINT32 *)Fixup, 20, 12));+ if (Value2 & (RISCV_IMM_= REACH/2)) {+ Value2 |=3D ~(RISCV_IMM_REACH-1);+ }+ V= alue +=3D Value2;+ Value +=3D (UINT32)Adjust;+ Value2 =3D RIS= CV_CONST_HIGH_PART (Value);+ *(UINT32 *)RiscVHi20Fixup =3D (RV_X (Va= lue2, 12, 20) << 12) |\+ (RV_X (*= (UINT32 *)RiscVHi20Fixup, 0, 12));+ *(UINT32 *)Fixup =3D (RV_X (Valu= e, 0, 12) << 20) |\+ (RV_X (*(UINT32 *)Fixup, 0, = 20));+ }+ break;++ case EFI_IMAGE_REL_BASED_RISCV_LOW12S:+ = RiscVHi20Fixup =3D (UINT32 *)(*(UINT64 *)(*FixupData));+ if (RiscVHi2= 0Fixup !=3D NULL) {+ Value =3D (UINT32)(RV_X(*RiscVHi20Fixup, 12, 20= ) << 12);+ Value2 =3D (UINT32)(RV_X(*(UINT32 *)Fixup, 7, 5) | (RV_X(= *(UINT32 *)Fixup, 25, 7) << 5));+ if (Value2 & (RISCV_IMM_REACH/2)) = {+ Value2 |=3D ~(RISCV_IMM_REACH-1);+ }+ Value +=3D = Value2;+ Value +=3D (UINT32)Adjust;+ Value2 =3D RISCV_CONST_H= IGH_PART (Value);+ *(UINT32 *)RiscVHi20Fixup =3D (RV_X (Value2, 12, = 20) << 12) | \+ (RV_X (*(UINT32 *= )RiscVHi20Fixup, 0, 12));+ Value2 =3D *(UINT32 *)Fixup & 0x01fff07f;= + Value &=3D RISCV_IMM_REACH - 1;+ *(UINT32 *)Fixup =3D Value= 2 | (UINT32)(((RV_X(Value, 0, 5) << 7) | (RV_X(Value, 5, 7) << 25)));+ = }+ break;++ default:+ return RETURN_UNSUPPORTED;++ }+ return = RETURN_SUCCESS;+}++/**+ Returns TRUE if the machine type of PE/COFF image = is supported. Supported+ does not mean the image can be executed it means = the PE/COFF loader supports+ loading and relocating of the image type. It'= s up to the caller to support+ the entry point.++ @param Machine Machi= ne type from the PE Header.++ @return TRUE if this PE/COFF loader can load= the image++**/+BOOLEAN+PeCoffLoaderImageFormatSupported (+ IN UINT16 Ma= chine+ )+{+ if (Machine =3D=3D IMAGE_FILE_MACHINE_RISCV64) {+ return = TRUE;+ }++ return FALSE;+}++/**+ Performs an Itanium-based specific re-r= elocation fixup and is a no-op on other+ instruction sets. This is used to= re-relocated the image into the EFI virtual+ space for runtime calls.++ = @param Reloc The pointer to the relocation record.+ @param Fixup = The pointer to the address to fix up.+ @param FixupData The pointe= r to a buffer to log the fixups.+ @param Adjust The offset to adjust= the fixup.++ @return Status code.++**/+RETURN_STATUS+PeHotRelocateImageEx= (+ IN UINT16 *Reloc,+ IN OUT CHAR8 *Fixup,+ IN OUT CHAR8 **Fix= upData,+ IN UINT64 Adjust+ )+{+ return RETURN_UNSUPPORTED;+}diff --= git a/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni b/MdePkg/Library/BaseP= eCoffLib/BasePeCoffLib.uni index b0ea702f76..55417029f2 100644 --- a/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni +++ b/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni @@ -4,6 +4,7 @@ // The IPF version library supports loading IPF and EBC PE/COFF image. // = The IA32 version library support loading IA32, X64 and EBC PE/COFF images. = // The X64 version library support loading IA32, X64 and EBC PE/COFF images= .+// The RISC-V version library support loading RISC-V32 and RISC-V64 PE/CO= FF images. // // Caution: This module requires additional review when modif= ied. // This library will have external input - PE/COFF image.@@ -12,6 +13,= 7 @@ // // Copyright (c) 2006 - 2018, Intel Corporation. All rights reserv= ed.
// Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserv= ed.
+// Portions Copyright (c) 2020, Hewlett Packard Enterprise Developm= ent LP. All rights reserved.
// // SPDX-License-Identifier: BSD-2-Claus= e-Patent //-- 2.25.0 -=3D-=3D-=3D-=3D-=3D-=3D Groups.io Links: You receive all messages sent to this group. View/Reply Online (#57197): https://edk2.groups.io/g/devel/message/57197 Mute This Topic: https://groups.io/mt/72916364/1779286 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [zhiguang.liu@intel.com] -=3D-=3D-=3D-=3D-=3D-=3D