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Thread-Topic: [edk2-devel] [PATCH v2 8/9] MdePkg/BaseSynchronizationLib: RISC-V cache related code. Thread-Index: AQHWF7dbdQ2ZNe1mqUS+9nRpA/88eqiE2mmw Date: Wed, 22 Apr 2020 09:03:47 +0000 Message-ID: References: <20200421075317.26008-1-abner.chang@hpe.com> In-Reply-To: <20200421075317.26008-1-abner.chang@hpe.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-reaction: no-action dlp-version: 11.2.0.6 dlp-product: dlpe-windows authentication-results: spf=none (sender IP is ) smtp.mailfrom=zhiguang.liu@intel.com; x-originating-ip: [192.102.204.45] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: f9c384a9-11ee-4b9f-2a00-08d7e69c1158 x-ms-traffictypediagnostic: BN7PR11MB2722: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:3383; x-forefront-prvs: 03818C953D x-forefront-antispam-report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:BN7PR11MB2804.namprd11.prod.outlook.com;PTR:;CAT:NONE;SFTY:;SFS:(10019020)(136003)(346002)(376002)(366004)(396003)(39860400002)(316002)(186003)(8936002)(66556008)(478600001)(66946007)(71200400001)(8676002)(64756008)(966005)(33656002)(66446008)(66476007)(110136005)(76116006)(9686003)(2906002)(26005)(7696005)(55016002)(53546011)(81156014)(52536014)(54906003)(5660300002)(6506007)(19627235002)(107886003)(4326008)(86362001);DIR:OUT;SFP:1102; x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: STICa/OUdP5Cy+sosFSixbOylPP4/XCQ1Truf9tqdy48VSCnqD1K2vn4P2+jChFCJK48OVJhztlSfN5xq7cVXmPUjEkPGY4LCCACbVAU3bp0FXxrgN1gEIhiOqqAK4GFeJokVq4DLBA9BzL0i9Ed7+5qjCEDOnloH/PHdd7+ug507rntjn9ZdqeLnc/mZz4GIqu4K02HTYQIX9XYLSMGDCYsLP/BwaQ4WBQ5B4ADFPnrcVcGk7YrWaGS3DCbmRu+2ULxkTe0yUVATYCCZbHOHoxlze2NhyBb4Th7Nz/2o9ytPcDCIG9RNMa0AG9vZ+yNQwFHcUgXMXYmuaiY71of4IFkXPXTq/Bgfiy2uBHsLsTgCx+Rv/b5ppQ9T3E0RTM5aQk+akhpv6F7HBhlIVCU/UgWPpy0rspkf19z6Xzl+0A10WNm2ZO/c6HQm1yCzOEdJeugQLjNQQnB2r7+FfojRBOHykJpO9ILkSNlp7RlxoVoSP8zBhCc5VAm64n3cATJJZVF9tFScEkGZQjDrq43LQ== x-ms-exchange-antispam-messagedata: SbbRxcCPfWyRpsUmixFLOGV6/EG48CpQbxGrAIMrUuMTE1ngA3aU/iJhVMLpV/bJxw8X7q8U3OU6cb8rShYePphaHLZKg6MYzALWRujMg1gM35Lyr6GDNhlvZK2hHbORPbyemWGkV27h8Lxz4ph5rA== MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: f9c384a9-11ee-4b9f-2a00-08d7e69c1158 X-MS-Exchange-CrossTenant-originalarrivaltime: 22 Apr 2020 09:03:47.5432 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: dfF8XOOlsjdbjNW+BHLGVHpWCIuQVroo8+Be6+Kr6qrXUyXwJNU6qnyp1JvYWAhWiJt4UeWCCfHg1Qv7ZcPAew== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN7PR11MB2722 Return-Path: zhiguang.liu@intel.com X-OriginatorOrg: intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Zhiguang Liu -----Original Message----- From: devel@edk2.groups.io On Behalf Of Abner Chang Sent: Tuesday, April 21, 2020 3:53 PM To: devel@edk2.groups.io Cc: abner.chang@hpe.com; Gilbert Chen ; Leif Lindholm= ; Kinney, Michael D = ; Gao, Liming Subject: [edk2-devel] [PATCH v2 8/9] MdePkg/BaseSynchronizationLib: RISC-V = cache related code. Support RISC-V cache related functions. Signed-off-by: Abner Chang Co-authored-by: Gilbert Chen Reviewed-by: Leif Lindholm Cc: Michael D Kinney Cc: Liming Gao Cc: Leif Lindholm Cc: Gilbert Chen --- .../BaseSynchronizationLib.inf | 5 ++ .../RiscV64/Synchronization.S | 78 +++++++++++++++++++ 2 files changed, 83 insertions(+) create mode 100644 MdePkg/Library/BaseSynchronizationLib/RiscV64/Synchroni= zation.S diff --git a/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.i= nf b/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf index 446bc19b63..83d5b8ed7c 100755 --- a/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf +++ b/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf @@ -3,6 +3,7 @@ # # Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -78,6 +79,10 @@ AArch64/Synchronization.S | GCC AArch64/Synchronization.asm | MSFT =20 +[Sources.RISCV64] + Synchronization.c + RiscV64/Synchronization.S + [Packages] MdePkg/MdePkg.dec =20 diff --git a/MdePkg/Library/BaseSynchronizationLib/RiscV64/Synchronization.= S b/MdePkg/Library/BaseSynchronizationLib/RiscV64/Synchronization.S new file mode 100644 index 0000000000..bac80d6871 --- /dev/null +++ b/MdePkg/Library/BaseSynchronizationLib/RiscV64/Synchronization.S @@ -0,0 +1,78 @@ +//------------------------------------------------------------------------= ------ +// +// RISC-V synchronization functions. +// +// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +//------------------------------------------------------------------------= ------ +#include + +.data + +.text +.align 3 + +.global ASM_PFX(InternalSyncCompareExchange32) +.global ASM_PFX(InternalSyncCompareExchange64) +.global ASM_PFX(InternalSyncIncrement) +.global ASM_PFX(InternalSyncDecrement) + +// +// ompare and xchange a 32-bit value. +// +// @param a0 : Pointer to 32-bit value. +// @param a1 : Compare value. +// @param a2 : Exchange value. +// +ASM_PFX (InternalSyncCompareExchange32): + lr.w a3, (a0) // Load the value from a0 and make + // the reservation of address. + bne a3, a1, exit + sc.w a3, a2, (a0) // Write the value back to the address. + mv a3, a1 +exit: + mv a0, a3 + ret + +.global ASM_PFX(InternalSyncCompareExchange64) + +// +// Compare and xchange a 64-bit value. +// +// @param a0 : Pointer to 64-bit value. +// @param a1 : Compare value. +// @param a2 : Exchange value. +// +ASM_PFX (SyncCompareExchange64): + lr.d a3, (a0) // Load the value from a0 and make + // the reservation of address. + bne a3, a1, exit + sc.d a3, a2, (a0) // Write the value back to the address. + mv a3, a1 +exit2: + mv a0, a3 + ret + +// +// Performs an atomic increment of an 32-bit unsigned integer. +// +// @param a0 : Pointer to 32-bit value. +// +ASM_PFX (InternalSyncIncrement): + li a1, 1 + amoadd.w a2, a1, (a0) + mv a0, a2 + ret + +// +// Performs an atomic decrement of an 32-bit unsigned integer. +// +// @param a0 : Pointer to 32-bit value. +// +ASM_PFX (InternalSyncDecrement): + li a1, -1 + amoadd.w a2, a1, (a0) + mv a0, a2 + ret --=20 2.25.0 -=3D-=3D-=3D-=3D-=3D-=3D Groups.io Links: You receive all messages sent to this group. View/Reply Online (#57720): https://edk2.groups.io/g/devel/message/57720 Mute This Topic: https://groups.io/mt/73168213/1779286 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [zhiguang.liu@intel.com] -=3D-=3D-=3D-=3D-=3D-=3D