* [PATCH v2 8/9] MdePkg/BaseSynchronizationLib: RISC-V cache related code.
@ 2020-04-21 7:53 Abner Chang
2020-04-21 8:53 ` [edk2-devel] " Zhiguang Liu
2020-04-22 9:03 ` Zhiguang Liu
0 siblings, 2 replies; 4+ messages in thread
From: Abner Chang @ 2020-04-21 7:53 UTC (permalink / raw)
To: devel
Cc: abner.chang, Gilbert Chen, Leif Lindholm, Michael D Kinney,
Liming Gao
Support RISC-V cache related functions.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
---
.../BaseSynchronizationLib.inf | 5 ++
.../RiscV64/Synchronization.S | 78 +++++++++++++++++++
2 files changed, 83 insertions(+)
create mode 100644 MdePkg/Library/BaseSynchronizationLib/RiscV64/Synchronization.S
diff --git a/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf b/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
index 446bc19b63..83d5b8ed7c 100755
--- a/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
+++ b/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
@@ -3,6 +3,7 @@
#
# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -78,6 +79,10 @@
AArch64/Synchronization.S | GCC
AArch64/Synchronization.asm | MSFT
+[Sources.RISCV64]
+ Synchronization.c
+ RiscV64/Synchronization.S
+
[Packages]
MdePkg/MdePkg.dec
diff --git a/MdePkg/Library/BaseSynchronizationLib/RiscV64/Synchronization.S b/MdePkg/Library/BaseSynchronizationLib/RiscV64/Synchronization.S
new file mode 100644
index 0000000000..bac80d6871
--- /dev/null
+++ b/MdePkg/Library/BaseSynchronizationLib/RiscV64/Synchronization.S
@@ -0,0 +1,78 @@
+//------------------------------------------------------------------------------
+//
+// RISC-V synchronization functions.
+//
+// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+//------------------------------------------------------------------------------
+#include <Base.h>
+
+.data
+
+.text
+.align 3
+
+.global ASM_PFX(InternalSyncCompareExchange32)
+.global ASM_PFX(InternalSyncCompareExchange64)
+.global ASM_PFX(InternalSyncIncrement)
+.global ASM_PFX(InternalSyncDecrement)
+
+//
+// ompare and xchange a 32-bit value.
+//
+// @param a0 : Pointer to 32-bit value.
+// @param a1 : Compare value.
+// @param a2 : Exchange value.
+//
+ASM_PFX (InternalSyncCompareExchange32):
+ lr.w a3, (a0) // Load the value from a0 and make
+ // the reservation of address.
+ bne a3, a1, exit
+ sc.w a3, a2, (a0) // Write the value back to the address.
+ mv a3, a1
+exit:
+ mv a0, a3
+ ret
+
+.global ASM_PFX(InternalSyncCompareExchange64)
+
+//
+// Compare and xchange a 64-bit value.
+//
+// @param a0 : Pointer to 64-bit value.
+// @param a1 : Compare value.
+// @param a2 : Exchange value.
+//
+ASM_PFX (SyncCompareExchange64):
+ lr.d a3, (a0) // Load the value from a0 and make
+ // the reservation of address.
+ bne a3, a1, exit
+ sc.d a3, a2, (a0) // Write the value back to the address.
+ mv a3, a1
+exit2:
+ mv a0, a3
+ ret
+
+//
+// Performs an atomic increment of an 32-bit unsigned integer.
+//
+// @param a0 : Pointer to 32-bit value.
+//
+ASM_PFX (InternalSyncIncrement):
+ li a1, 1
+ amoadd.w a2, a1, (a0)
+ mv a0, a2
+ ret
+
+//
+// Performs an atomic decrement of an 32-bit unsigned integer.
+//
+// @param a0 : Pointer to 32-bit value.
+//
+ASM_PFX (InternalSyncDecrement):
+ li a1, -1
+ amoadd.w a2, a1, (a0)
+ mv a0, a2
+ ret
--
2.25.0
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [edk2-devel] [PATCH v2 8/9] MdePkg/BaseSynchronizationLib: RISC-V cache related code.
2020-04-21 7:53 [PATCH v2 8/9] MdePkg/BaseSynchronizationLib: RISC-V cache related code Abner Chang
@ 2020-04-21 8:53 ` Zhiguang Liu
2020-04-22 9:03 ` Zhiguang Liu
1 sibling, 0 replies; 4+ messages in thread
From: Zhiguang Liu @ 2020-04-21 8:53 UTC (permalink / raw)
To: devel@edk2.groups.io, abner.chang@hpe.com
Cc: Gilbert Chen, Leif Lindholm, Kinney, Michael D, Gao, Liming
Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com>
-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Abner Chang
Sent: Tuesday, April 21, 2020 3:53 PM
To: devel@edk2.groups.io
Cc: abner.chang@hpe.com; Gilbert Chen <gilbert.chen@hpe.com>; Leif Lindholm <leif.lindholm@linaro.org>; Kinney, Michael D <michael.d.kinney@intel.com>; Gao, Liming <liming.gao@intel.com>
Subject: [edk2-devel] [PATCH v2 8/9] MdePkg/BaseSynchronizationLib: RISC-V cache related code.
Support RISC-V cache related functions.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
---
.../BaseSynchronizationLib.inf | 5 ++
.../RiscV64/Synchronization.S | 78 +++++++++++++++++++
2 files changed, 83 insertions(+)
create mode 100644 MdePkg/Library/BaseSynchronizationLib/RiscV64/Synchronization.S
diff --git a/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf b/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
index 446bc19b63..83d5b8ed7c 100755
--- a/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
+++ b/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
@@ -3,6 +3,7 @@
#
# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -78,6 +79,10 @@
AArch64/Synchronization.S | GCC
AArch64/Synchronization.asm | MSFT
+[Sources.RISCV64]
+ Synchronization.c
+ RiscV64/Synchronization.S
+
[Packages]
MdePkg/MdePkg.dec
diff --git a/MdePkg/Library/BaseSynchronizationLib/RiscV64/Synchronization.S b/MdePkg/Library/BaseSynchronizationLib/RiscV64/Synchronization.S
new file mode 100644
index 0000000000..bac80d6871
--- /dev/null
+++ b/MdePkg/Library/BaseSynchronizationLib/RiscV64/Synchronization.S
@@ -0,0 +1,78 @@
+//------------------------------------------------------------------------------
+//
+// RISC-V synchronization functions.
+//
+// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+//------------------------------------------------------------------------------
+#include <Base.h>
+
+.data
+
+.text
+.align 3
+
+.global ASM_PFX(InternalSyncCompareExchange32)
+.global ASM_PFX(InternalSyncCompareExchange64)
+.global ASM_PFX(InternalSyncIncrement)
+.global ASM_PFX(InternalSyncDecrement)
+
+//
+// ompare and xchange a 32-bit value.
+//
+// @param a0 : Pointer to 32-bit value.
+// @param a1 : Compare value.
+// @param a2 : Exchange value.
+//
+ASM_PFX (InternalSyncCompareExchange32):
+ lr.w a3, (a0) // Load the value from a0 and make
+ // the reservation of address.
+ bne a3, a1, exit
+ sc.w a3, a2, (a0) // Write the value back to the address.
+ mv a3, a1
+exit:
+ mv a0, a3
+ ret
+
+.global ASM_PFX(InternalSyncCompareExchange64)
+
+//
+// Compare and xchange a 64-bit value.
+//
+// @param a0 : Pointer to 64-bit value.
+// @param a1 : Compare value.
+// @param a2 : Exchange value.
+//
+ASM_PFX (SyncCompareExchange64):
+ lr.d a3, (a0) // Load the value from a0 and make
+ // the reservation of address.
+ bne a3, a1, exit
+ sc.d a3, a2, (a0) // Write the value back to the address.
+ mv a3, a1
+exit2:
+ mv a0, a3
+ ret
+
+//
+// Performs an atomic increment of an 32-bit unsigned integer.
+//
+// @param a0 : Pointer to 32-bit value.
+//
+ASM_PFX (InternalSyncIncrement):
+ li a1, 1
+ amoadd.w a2, a1, (a0)
+ mv a0, a2
+ ret
+
+//
+// Performs an atomic decrement of an 32-bit unsigned integer.
+//
+// @param a0 : Pointer to 32-bit value.
+//
+ASM_PFX (InternalSyncDecrement):
+ li a1, -1
+ amoadd.w a2, a1, (a0)
+ mv a0, a2
+ ret
--
2.25.0
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^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [edk2-devel] [PATCH v2 8/9] MdePkg/BaseSynchronizationLib: RISC-V cache related code.
2020-04-21 7:53 [PATCH v2 8/9] MdePkg/BaseSynchronizationLib: RISC-V cache related code Abner Chang
2020-04-21 8:53 ` [edk2-devel] " Zhiguang Liu
@ 2020-04-22 9:03 ` Zhiguang Liu
1 sibling, 0 replies; 4+ messages in thread
From: Zhiguang Liu @ 2020-04-22 9:03 UTC (permalink / raw)
To: devel@edk2.groups.io, abner.chang@hpe.com
Cc: Gilbert Chen, Leif Lindholm, Kinney, Michael D, Gao, Liming
Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com>
-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Abner Chang
Sent: Tuesday, April 21, 2020 3:53 PM
To: devel@edk2.groups.io
Cc: abner.chang@hpe.com; Gilbert Chen <gilbert.chen@hpe.com>; Leif Lindholm <leif.lindholm@linaro.org>; Kinney, Michael D <michael.d.kinney@intel.com>; Gao, Liming <liming.gao@intel.com>
Subject: [edk2-devel] [PATCH v2 8/9] MdePkg/BaseSynchronizationLib: RISC-V cache related code.
Support RISC-V cache related functions.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
---
.../BaseSynchronizationLib.inf | 5 ++
.../RiscV64/Synchronization.S | 78 +++++++++++++++++++
2 files changed, 83 insertions(+)
create mode 100644 MdePkg/Library/BaseSynchronizationLib/RiscV64/Synchronization.S
diff --git a/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf b/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
index 446bc19b63..83d5b8ed7c 100755
--- a/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
+++ b/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
@@ -3,6 +3,7 @@
#
# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -78,6 +79,10 @@
AArch64/Synchronization.S | GCC
AArch64/Synchronization.asm | MSFT
+[Sources.RISCV64]
+ Synchronization.c
+ RiscV64/Synchronization.S
+
[Packages]
MdePkg/MdePkg.dec
diff --git a/MdePkg/Library/BaseSynchronizationLib/RiscV64/Synchronization.S b/MdePkg/Library/BaseSynchronizationLib/RiscV64/Synchronization.S
new file mode 100644
index 0000000000..bac80d6871
--- /dev/null
+++ b/MdePkg/Library/BaseSynchronizationLib/RiscV64/Synchronization.S
@@ -0,0 +1,78 @@
+//------------------------------------------------------------------------------
+//
+// RISC-V synchronization functions.
+//
+// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+//------------------------------------------------------------------------------
+#include <Base.h>
+
+.data
+
+.text
+.align 3
+
+.global ASM_PFX(InternalSyncCompareExchange32)
+.global ASM_PFX(InternalSyncCompareExchange64)
+.global ASM_PFX(InternalSyncIncrement)
+.global ASM_PFX(InternalSyncDecrement)
+
+//
+// ompare and xchange a 32-bit value.
+//
+// @param a0 : Pointer to 32-bit value.
+// @param a1 : Compare value.
+// @param a2 : Exchange value.
+//
+ASM_PFX (InternalSyncCompareExchange32):
+ lr.w a3, (a0) // Load the value from a0 and make
+ // the reservation of address.
+ bne a3, a1, exit
+ sc.w a3, a2, (a0) // Write the value back to the address.
+ mv a3, a1
+exit:
+ mv a0, a3
+ ret
+
+.global ASM_PFX(InternalSyncCompareExchange64)
+
+//
+// Compare and xchange a 64-bit value.
+//
+// @param a0 : Pointer to 64-bit value.
+// @param a1 : Compare value.
+// @param a2 : Exchange value.
+//
+ASM_PFX (SyncCompareExchange64):
+ lr.d a3, (a0) // Load the value from a0 and make
+ // the reservation of address.
+ bne a3, a1, exit
+ sc.d a3, a2, (a0) // Write the value back to the address.
+ mv a3, a1
+exit2:
+ mv a0, a3
+ ret
+
+//
+// Performs an atomic increment of an 32-bit unsigned integer.
+//
+// @param a0 : Pointer to 32-bit value.
+//
+ASM_PFX (InternalSyncIncrement):
+ li a1, 1
+ amoadd.w a2, a1, (a0)
+ mv a0, a2
+ ret
+
+//
+// Performs an atomic decrement of an 32-bit unsigned integer.
+//
+// @param a0 : Pointer to 32-bit value.
+//
+ASM_PFX (InternalSyncDecrement):
+ li a1, -1
+ amoadd.w a2, a1, (a0)
+ mv a0, a2
+ ret
--
2.25.0
-=-=-=-=-=-=
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#57720): https://edk2.groups.io/g/devel/message/57720
Mute This Topic: https://groups.io/mt/73168213/1779286
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^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [edk2-devel] [PATCH v2 8/9] MdePkg/BaseSynchronizationLib: RISC-V cache related code.
[not found] <1607C88B87B941AC.8676@groups.io>
@ 2020-04-22 9:15 ` Liming Gao
0 siblings, 0 replies; 4+ messages in thread
From: Liming Gao @ 2020-04-22 9:15 UTC (permalink / raw)
To: devel@edk2.groups.io, Chang, Abner (HPS SW/FW Technologist)
Cc: Chen, Gilbert, Leif Lindholm, Kinney, Michael D
Reviewed-by: Liming Gao <liming.gao@intel.com>
> -----Original Message-----
> From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Chang, Abner (HPS SW/FW Technologist)
> Sent: Tuesday, April 21, 2020 3:53 PM
> To: devel@edk2.groups.io
> Cc: Chang, Abner (HPS SW/FW Technologist) <abner.chang@hpe.com>; Chen, Gilbert <gilbert.chen@hpe.com>; Leif Lindholm
> <leif.lindholm@linaro.org>; Kinney, Michael D <michael.d.kinney@intel.com>; Gao, Liming <liming.gao@intel.com>
> Subject: [edk2-devel] [PATCH v2 8/9] MdePkg/BaseSynchronizationLib: RISC-V cache related code.
>
> Support RISC-V cache related functions.
>
> Signed-off-by: Abner Chang <abner.chang@hpe.com>
> Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com>
> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
>
> Cc: Michael D Kinney <michael.d.kinney@intel.com>
> Cc: Liming Gao <liming.gao@intel.com>
> Cc: Leif Lindholm <leif.lindholm@linaro.org>
> Cc: Gilbert Chen <gilbert.chen@hpe.com>
> ---
> .../BaseSynchronizationLib.inf | 5 ++
> .../RiscV64/Synchronization.S | 78 +++++++++++++++++++
> 2 files changed, 83 insertions(+)
> create mode 100644 MdePkg/Library/BaseSynchronizationLib/RiscV64/Synchronization.S
>
> diff --git a/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
> b/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
> index 446bc19b63..83d5b8ed7c 100755
> --- a/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
> +++ b/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
> @@ -3,6 +3,7 @@
> #
> # Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
> # Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
> +# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> #
> # SPDX-License-Identifier: BSD-2-Clause-Patent
> #
> @@ -78,6 +79,10 @@
> AArch64/Synchronization.S | GCC
> AArch64/Synchronization.asm | MSFT
>
> +[Sources.RISCV64]
> + Synchronization.c
> + RiscV64/Synchronization.S
> +
> [Packages]
> MdePkg/MdePkg.dec
>
> diff --git a/MdePkg/Library/BaseSynchronizationLib/RiscV64/Synchronization.S
> b/MdePkg/Library/BaseSynchronizationLib/RiscV64/Synchronization.S
> new file mode 100644
> index 0000000000..bac80d6871
> --- /dev/null
> +++ b/MdePkg/Library/BaseSynchronizationLib/RiscV64/Synchronization.S
> @@ -0,0 +1,78 @@
> +//------------------------------------------------------------------------------
> +//
> +// RISC-V synchronization functions.
> +//
> +// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +//
> +// SPDX-License-Identifier: BSD-2-Clause-Patent
> +//
> +//------------------------------------------------------------------------------
> +#include <Base.h>
> +
> +.data
> +
> +.text
> +.align 3
> +
> +.global ASM_PFX(InternalSyncCompareExchange32)
> +.global ASM_PFX(InternalSyncCompareExchange64)
> +.global ASM_PFX(InternalSyncIncrement)
> +.global ASM_PFX(InternalSyncDecrement)
> +
> +//
> +// ompare and xchange a 32-bit value.
> +//
> +// @param a0 : Pointer to 32-bit value.
> +// @param a1 : Compare value.
> +// @param a2 : Exchange value.
> +//
> +ASM_PFX (InternalSyncCompareExchange32):
> + lr.w a3, (a0) // Load the value from a0 and make
> + // the reservation of address.
> + bne a3, a1, exit
> + sc.w a3, a2, (a0) // Write the value back to the address.
> + mv a3, a1
> +exit:
> + mv a0, a3
> + ret
> +
> +.global ASM_PFX(InternalSyncCompareExchange64)
> +
> +//
> +// Compare and xchange a 64-bit value.
> +//
> +// @param a0 : Pointer to 64-bit value.
> +// @param a1 : Compare value.
> +// @param a2 : Exchange value.
> +//
> +ASM_PFX (SyncCompareExchange64):
> + lr.d a3, (a0) // Load the value from a0 and make
> + // the reservation of address.
> + bne a3, a1, exit
> + sc.d a3, a2, (a0) // Write the value back to the address.
> + mv a3, a1
> +exit2:
> + mv a0, a3
> + ret
> +
> +//
> +// Performs an atomic increment of an 32-bit unsigned integer.
> +//
> +// @param a0 : Pointer to 32-bit value.
> +//
> +ASM_PFX (InternalSyncIncrement):
> + li a1, 1
> + amoadd.w a2, a1, (a0)
> + mv a0, a2
> + ret
> +
> +//
> +// Performs an atomic decrement of an 32-bit unsigned integer.
> +//
> +// @param a0 : Pointer to 32-bit value.
> +//
> +ASM_PFX (InternalSyncDecrement):
> + li a1, -1
> + amoadd.w a2, a1, (a0)
> + mv a0, a2
> + ret
> --
> 2.25.0
>
>
>
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2020-04-22 9:16 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
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2020-04-21 7:53 [PATCH v2 8/9] MdePkg/BaseSynchronizationLib: RISC-V cache related code Abner Chang
2020-04-21 8:53 ` [edk2-devel] " Zhiguang Liu
2020-04-22 9:03 ` Zhiguang Liu
[not found] <1607C88B87B941AC.8676@groups.io>
2020-04-22 9:15 ` Liming Gao
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