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boundary="_000_BN8PR11MB3666214D66E8EF96887B2D81CACC9BN8PR11MB3666namp_" --_000_BN8PR11MB3666214D66E8EF96887B2D81CACC9BN8PR11MB3666namp_ Content-Type: text/plain; charset="iso-8859-2" Content-Transfer-Encoding: quoted-printable Really sorry, Could you help to provide more information on the below statement? "undefined parent register accesses" Thanks in advance. Best Regards, Hao Wu From: devel@edk2.groups.io On Behalf Of Bassa, Damia= n Sent: Tuesday, August 24, 2021 11:15 PM To: devel@edk2.groups.io Subject: [edk2-devel] [PATCH] MdeModulePkg/PciBusDxe: Enumerator to check f= or RCiEP before looking for RP Before trying to access parent root port to check ARI capabilities, enumerator should see if Endpoint device is not Root Complex integrated to avoid undefined parent register accesses in these cases. Signed-off-by: Damian Bassa damian.bassa@intel.com --- .../Bus/Pci/PciBusDxe/PciEnumeratorSupport.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c b/MdeMod= ulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c index db1b35f8ef..6451fb8af9 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c @@ -2153,6 +2153,7 @@ CreatePciIoDevice ( PCI_IO_DEVICE *PciIoDevice; EFI_PCI_IO_PROTOCOL *PciIo; EFI_STATUS Status; + PCI_REG_PCIE_CAPABILITY Capability; PciIoDevice =3D AllocateZeroPool (sizeof (PCI_IO_DEVICE)); if (PciIoDevice =3D=3D NULL) { @@ -2229,7 +2230,16 @@ CreatePciIoDevice ( return NULL; } - if (PcdGetBool (PcdAriSupport)) { + PciIo->Pci.Read ( + PciIo, + EfiPciIoWidthUint16, + PciIoDevice->PciExpressCapabilityOffset + OFFSET_OF (PCI_C= APABILITY_PCIEXP, Capability), + 1, + &Capability.Uint16 + ); + + if (PcdGetBool (PcdAriSupport) && + Capability.Bits.DevicePortType !=3D PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX= _INTEGRATED_ENDPOINT) { // // Check if the device is an ARI device. // -- 2.27.0.windows.1 ________________________________ Intel Technology Poland sp. z o.o. ul. S=B3owackiego 173 | 80-298 Gda=F1sk | S=B1d Rejonowy Gda=F1sk P=F3=B3no= c | VII Wydzia=B3 Gospodarczy Krajowego Rejestru S=B1dowego - KRS 101882 | = NIP 957-07-52-316 | Kapita=B3 zak=B3adowy 200.000 PLN. Ta wiadomo=B6=E6 wraz z za=B3=B1cznikami jest przeznaczona dla okre=B6loneg= o adresata i mo=BFe zawiera=E6 informacje poufne. W razie przypadkowego otr= zymania tej wiadomo=B6ci, prosimy o powiadomienie nadawcy oraz trwa=B3e jej= usuni=EAcie; jakiekolwiek przegl=B1danie lub rozpowszechnianie jest zabron= ione. This e-mail and any attachments may contain confidential material for the s= ole use of the intended recipient(s). If you are not the intended recipient= , please contact the sender and delete all copies; any review or distributi= on by others is strictly prohibited. --_000_BN8PR11MB3666214D66E8EF96887B2D81CACC9BN8PR11MB3666namp_ Content-Type: text/html; charset="iso-8859-2" Content-Transfer-Encoding: quoted-printable

Really sorry,

 

Could you help to provide more information on the be= low statement?

“undefined parent register accesses”

 

Thanks in advance.

 

Best Regards,

Hao Wu

 

From: devel@edk2.groups.io <devel@edk2.gro= ups.io> On Behalf Of Bassa, Damian
Sent: Tuesday, August 24, 2021 11:15 PM
To: devel@edk2.groups.io
Subject: [edk2-devel] [PATCH] MdeModulePkg/PciBusDxe: Enumerator to = check for RCiEP before looking for RP

 

Before trying to access parent root port to check AR= I capabilities,

enumerator should see if Endpoint device is not Root= Complex integrated

to avoid undefined parent register accesses in these= cases.

 

Signed-off-by: Damian Bassa damian.bassa@intel.com

 

---

.../Bus/Pci/PciBusDxe/PciEnumeratorSupport.c &n= bsp;       | 12 +++++++++++-

1 file changed, 11 insertions(+), 1 deletion(-)=

 

diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnume= ratorSupport.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c=

index db1b35f8ef..6451fb8af9 100644

--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSu= pport.c

+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSu= pport.c

@@ -2153,6 +2153,7 @@ CreatePciIoDevice (=

   PCI_IO_DEVICE    &n= bsp;   *PciIoDevice;

   EFI_PCI_IO_PROTOCOL  *PciIo;<= /o:p>

   EFI_STATUS     &nbs= p;     Status;

+  PCI_REG_PCIE_CAPABILITY Capability;

 

   PciIoDevice =3D AllocateZeroPool (= sizeof (PCI_IO_DEVICE));

   if (PciIoDevice =3D=3D NULL) {

@@ -2229,7 +2230,16 @@ CreatePciIoDevice (

     return NULL;

   }

 

-  if (PcdGetBool (PcdAriSupport)) {=

+  PciIo->Pci.Read (

+        &nb= sp;       PciIo,

+        &nb= sp;       EfiPciIoWidthUint16,

+        &nb= sp;       PciIoDevice->PciExpressCapabilit= yOffset + OFFSET_OF (PCI_CAPABILITY_PCIEXP, Capability),

+        &nb= sp;       1,

+        &nb= sp;       &Capability.Uint16

+        &nb= sp;       );

+

+  if (PcdGetBool (PcdAriSupport) &&

+    Capability.Bits.DevicePortType != =3D PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_INTEGRATED_ENDPOINT) {

     //

     // Check if the device is a= n ARI device.

     //

--

2.27.0.windows.1

 

Intel Technology Poland s= p. z o.o.
ul. S=B3owackiego 173 | 80-298 Gda=F1sk | S= =B1d Rejonowy Gda=F1sk P=F3=B3noc | VII Wydzia=B3 Gospodarczy Krajowego Rej= estru S=B1dowego - KRS 101882 | NIP 957-07-52-316 | Kapita=B3 zak=B3adowy 200.000 PLN.

Ta wiadomo=B6=E6 wraz z za= =B3=B1cznikami jest przeznaczona dla okre=B6lonego adresata i mo=BFe zawier= a=E6 informacje poufne. W razie przypadkowego otrzymania tej wiadomo=B6ci, prosimy o powiadomienie nadawcy oraz trwa=B3e jej usuni=EAci= e; jakiekolwiek przegl=B1danie lub rozpowszechnianie jest zabronione.
This e-mail and any attachments may contain confidential material for the s= ole use of the intended recipient(s). If you are not the intended recipient= , please contact the sender and delete all copies; any review or distributi= on by others is strictly prohibited.

 

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