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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: KGQOy8yMraLJysgb1nt96bkJx7686176AA= Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=Xcdmw3lI; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=intel.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io; arc=reject ("signature check failed: fail, {[1] = sig:microsoft.com:reject}") Hi Gerd, Could you help to review this V3 patch? The related code and comments has b= een modified based on your previous comments. Please ignore the V2 patch set. There was a typo error in the V2 patch and = was corrected in V3 patch. Thanks, Dun -----Original Message----- From: devel@edk2.groups.io On Behalf Of duntan Sent: Thursday, January 11, 2024 5:00 PM To: devel@edk2.groups.io Cc: Ni, Ray ; Laszlo Ersek ; Kumar, Ra= hul R ; Gerd Hoffmann Subject: [edk2-devel] [Patch V3] UefiCpuPkg:Limit PhysicalAddressBits in sp= ecial case When creating smm page table, limit maximum supported physical address bits= returned by CalculateMaximumSupportAddress() to 47 if 5-Level Paging is disabled. When 5-Level Paging is disabled and the PhysicalAddressBits retrived from CPU HOB or CpuId is bigger than 47, and s= ince virtual addresses are sign-extended, only [0, 2^47-1] range in 52-bit = physical address is mapped in page table. Signed-off-by: Dun Tan Reviewed-by: Ray Ni Cc: Laszlo Ersek Cc: Rahul Kumar Cc: Gerd Hoffmann --- UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c b/UefiCpuPkg/PiSmmCpuD= xeSmm/X64/PageTbl.c index ddd9be66b5..35c282a771 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c @@ -137,11 +137,13 @@ GetSubEntriesNum ( /** Calculate the maximum support address. =20 + @param[in] Is5LevelPagingNeeded If 5-level paging enabling is needed. + @return the maximum support address. **/ UINT8 CalculateMaximumSupportAddress ( - VOID + BOOLEAN Is5LevelPagingNeeded ) { UINT32 RegEax; @@ -164,6 +166,15 @@ CalculateMaximumSupportAddress ( } } =20 + // + // Only [0, 2^47 -1] in 52-bit physical addresses is mapped in page=20 + table // when 5-Level Paging is disabled. + // + ASSERT (PhysicalAddressBits <=3D 52); + if (!Is5LevelPagingNeeded && (PhysicalAddressBits > 47)) { + PhysicalAddressBits =3D 47; + } + return PhysicalAddressBits; } =20 @@ -197,7 +208,7 @@ SmmInitPageTable ( mCpuSmmRestrictedMemoryAccess =3D PcdGetBool (PcdCpuSmmRestrictedMemoryA= ccess); m1GPageTableSupport =3D Is1GPageSupport (); m5LevelPagingNeeded =3D Is5LevelPagingNeeded (); - mPhysicalAddressBits =3D CalculateMaximumSupportAddress (); + mPhysicalAddressBits =3D CalculateMaximumSupportAddress (m5Leve= lPagingNeeded); PatchInstructionX86 (gPatch5LevelPagingNeeded, m5LevelPagingNeeded, 1); if (m5LevelPagingNeeded) { mPagingMode =3D m1GPageTableSupport ? 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