From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by mx.groups.io with SMTP id smtpd.web10.7198.1685691217662191755 for ; Fri, 02 Jun 2023 00:33:38 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=PNthwMAK; spf=pass (domain: intel.com, ip: 134.134.136.31, mailfrom: dun.tan@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1685691217; x=1717227217; h=from:to:cc:subject:date:message-id:references: in-reply-to:content-transfer-encoding:mime-version; bh=4do81gifEoR5gvSjfhMysL5xqlbNgGgobEXtQYzRsV0=; b=PNthwMAKMjrgec5nzh1qiy6/mkEbnk9Kk/akimWbrx8MlxlgV1yNumL2 fu3NPPtMTt7jDd1+hqmBJplV2fYugTv/m+2qVkPEgn91HwEcywQ/s0LQ6 C53i1T1lW7k8Fkel/NCz51XVUO53DRVW5BJquqwHtVxPMBmIvexnnx/0P HLiCf5MowOFo8uzoIBEy3yBn6E3ze5D2CPmsuYeH/EIIXqqDeXhyXDQeR xFUsd8SqGS+4vHaS2jwmWU3GcKPzGxzmd4pE0narFouh4NBmb67Enbq1n imGjpgztSZJjwi+QCgv0zFs7AwVZYexEOeEi5Fx0d3Z2avUGd6OGEJASw Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10728"; a="419329662" X-IronPort-AV: E=Sophos;i="6.00,212,1681196400"; d="scan'208";a="419329662" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Jun 2023 00:33:14 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10728"; a="797495155" X-IronPort-AV: E=Sophos;i="6.00,212,1681196400"; d="scan'208";a="797495155" Received: from orsmsx601.amr.corp.intel.com ([10.22.229.14]) by FMSMGA003.fm.intel.com with ESMTP; 02 Jun 2023 00:33:14 -0700 Received: from orsmsx611.amr.corp.intel.com (10.22.229.24) by ORSMSX601.amr.corp.intel.com (10.22.229.14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.23; Fri, 2 Jun 2023 00:33:13 -0700 Received: from ORSEDG601.ED.cps.intel.com (10.7.248.6) by orsmsx611.amr.corp.intel.com (10.22.229.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.23 via Frontend Transport; Fri, 2 Jun 2023 00:33:13 -0700 Received: from NAM11-CO1-obe.outbound.protection.outlook.com (104.47.56.176) by edgegateway.intel.com (134.134.137.102) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.23; Fri, 2 Jun 2023 00:33:13 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=CbqlUua6YLVtHDyM7tg2A/dAl4oRQdOhE+/dfqMi17LvXOrFgM55rrh8wsbdqklEcQah8/Ewf4bc72vq3eDUyXQE6Sr6g+InPvGNP9aifDu4LANEsEhsBI0tp8fKOat7dxNxFRt4hpPvC5yQAi7a2K7/wKfWeqa3q8uzlY4ftUD5hcIvvIF8IW7zuq1GNs74SF5MNMfzlIDRe8LJFQhzKuswcrJU1sIkDCzjUQtIYahvd7s0JIWdVhuuTsAjm9gdDFrrrmwhm+pNvgEr20teee2t2pV+7fuE3r9agKzBIyv2TgG0yW6QmdrI5Jr/vgC/fpph+gPE3n3DGbA+zzub2g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=lFlk2yIc/dChR94WMUgDJuI8dj4Ud2elPGB9iWMfHBM=; b=hK4EGDNBSHOYw7Z/M4Uv8ptjSOAgoD7zaqCFCvY5HCDPnyZ5BCt4uF3yhpu9mVBJj1dQTJ48FB3RmlxwohNul+logBjGHubt4MxIsdpna1MacF8IlJswKBybnSboyP/fE8VC2sIscBfSeuE6hfdt6na69iMrldIjNSwxdI+wvzMJAO+aeYwKLaFvXMgrl/wjyg3dZy7i5kneTYqWBRsJltGnPx8aG1G7P/bP47NlhGz2JJoR/siY8mwDnJYa6XdpuTykyIIWQnVyBOI51rNUfQo/m0JG64UcG/1UGlqspL3qiU8VkuiVdRXfuWRWFnhndbxR9xdRssAmz1/GrS1UXw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none Received: from BN9PR11MB5483.namprd11.prod.outlook.com (2603:10b6:408:104::10) by SJ1PR11MB6298.namprd11.prod.outlook.com (2603:10b6:a03:457::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6455.22; Fri, 2 Jun 2023 07:33:05 +0000 Received: from BN9PR11MB5483.namprd11.prod.outlook.com ([fe80::3023:34d3:bd4e:7901]) by BN9PR11MB5483.namprd11.prod.outlook.com ([fe80::3023:34d3:bd4e:7901%3]) with mapi id 15.20.6455.024; Fri, 2 Jun 2023 07:33:05 +0000 From: "duntan" To: "Ni, Ray" , "devel@edk2.groups.io" CC: "Dong, Eric" , "Kumar, Rahul R" , Gerd Hoffmann Subject: Re: [edk2-devel] [Patch V4 10/15] UefiCpuPkg: Add GenSmmPageTable() to create smm page table Thread-Topic: [edk2-devel] [Patch V4 10/15] UefiCpuPkg: Add GenSmmPageTable() to create smm page table Thread-Index: AQHZlQGXoP12ZGXSlESw3n09GrnBb6922ZOQgAAFHMCAABfjgIAADyOQ Date: Fri, 2 Jun 2023 07:33:04 +0000 Message-ID: References: <20230516095932.1525-1-dun.tan@intel.com> <20230516095932.1525-11-dun.tan@intel.com> In-Reply-To: Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: BN9PR11MB5483:EE_|SJ1PR11MB6298:EE_ x-ms-office365-filtering-correlation-id: ba58fce9-ec9c-4cd8-48e7-08db633b9a71 x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: F2PC+btJXl9vO/lPv7OZua/M06nRxlMbYS7Z97rQE0NVxXJPthzr9NoazkGP77Fg6h2VcBfBjZhAfB9Gfh/XXXBph/KHaz9ao6nBxercFarW0I6K2Deo3XPeg8sdUQFoDScNvUbiTy+D0/r3qyyLEVXzRk3hxiWlwFo0khdaFgcmQ0MMUBpC//rWHlLcDS/I8i+P3SHWqFPr+BjvPKMz+bFHlFz5JWlYTB94B9Kee4FHcJQ9mj+7rB1TkVPeCcdYVU4M2SSq3nntxltroZvc6p9d90z3UBfaLMG1CLtWCumH27O0sVEZM8+TDiAdS/+glRdOJJbfVQmdobWUtWAxE07wZD1IddaU8N8KQ4oTClAwliSX6oiWO6zczkSerc00eX61hCq8iAETpbBeLuYhOk8NgVIRrzgxHyHXFKzhlc+O7tCSYPoPqJ5fCYYaEIXP/W8hZ/7E4AcdQHZmHy7rlqTjakFQLVUxU1y5lcdLh6QdH48vm43nlqTkVClSCKnM0nNFlROsEPMFPSxv3sl0kXXp5RnDf8POWn953KuWg5nJe6DAOo9rGpkfiqUPI/9NurdvAee2rF9OTyuuJA914iLcZ9uN4UhE8W4pG3Ss2iUnxQwtuqEkh8WWHIiJxIJn2XFVJKW5UMDCOaLPG4tRow== x-forefront-antispam-report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:BN9PR11MB5483.namprd11.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230028)(346002)(136003)(366004)(376002)(39860400002)(396003)(451199021)(82960400001)(38100700002)(122000001)(86362001)(38070700005)(33656002)(66899021)(66476007)(110136005)(52536014)(41300700001)(8676002)(30864003)(966005)(55016003)(5660300002)(53546011)(9686003)(26005)(6506007)(8936002)(186003)(83380400001)(316002)(7696005)(66556008)(66446008)(66946007)(478600001)(76116006)(71200400001)(54906003)(19627235002)(4326008)(64756008)(2906002)(579004);DIR:OUT;SFP:1102; x-ms-exchange-antispam-messagedata-chunkcount: 1 x-ms-exchange-antispam-messagedata-0: =?us-ascii?Q?BA8PfKuJpt1/9JxjgDNyXKcbpEmjyMaxizihcVqXzVVrYqF9VmUxgyUTIiFb?= =?us-ascii?Q?GsFABfhTFz/LoejxBMRywUAkvR7aJQ8I3H2QiHxh9Ky5kXR8kyhfDD0lUNEv?= =?us-ascii?Q?XLgfzvNZc+z9qxBIoTH+1Hu9YJ+QK0vdsgdJSQKqDWo3BpEJdALd8b4+8Tf4?= =?us-ascii?Q?gVxE6t11xhmImRCdzo/CE0vBfzusCm4f33PIhjtr19NEJPg/jGBU33b1p3la?= =?us-ascii?Q?24YNaSzTn7OGMMiwKVhWebgzAqN9t7S9CZxfHM/BJQ/byKT91GVVu4/G1sk4?= =?us-ascii?Q?z1PB+1s7wfvoliaZK3spEict0H8Vo1n4Ik0odICJGNk/UXOVxdLDJa4cnwx8?= =?us-ascii?Q?v5embGfqQgIxxVgpCIS8R5HhWI1qEmdeu6jaUPQETqzSPPLtbd7UtdgdbUIB?= =?us-ascii?Q?7etFvlWzzYVIOR1dcMpz+uUNAmT2673v9as9JsUDi9Xhua78NEqBR09AtKYh?= =?us-ascii?Q?bzE/97Rdb3CUKg+hdNFRb0sJaksF6L627RkTUnlChWn6gJBiUMZCKB1p/Zj6?= =?us-ascii?Q?ivFBOvTbXAwr7SkXNARNCQXZODSSJSB+5Wv9FNnourX6NLhabzBPDqVSWJ3H?= =?us-ascii?Q?6RUkdAQJhERibAsgNkSIZf06Z0NVthzfQsA5Gs8uvhTmy4bk0c57KJ4+5Ejn?= =?us-ascii?Q?iXpMYslnWha8pT93QzXoQq/n5uvs//CrHTAmyXdAOhAwY7xJT16WpuTEMAcH?= =?us-ascii?Q?eOsI1OJ0gkU/sVkf/p/QnGbkm5/XbbEqn6XvAodH3321UNwoP2X2ZW6415Sg?= =?us-ascii?Q?2ck55/4QEc+l7AjsBaZWct7C9Laa65rUttyPjohOaD2gkYu9dkiK/CU/CTzR?= =?us-ascii?Q?omg0kvSA/qRhAwnooqMcH2Yi6f9NJay88eKznNYIPnZg++xdLnmXSqXPgrTd?= =?us-ascii?Q?lLjAjsbmwI3sx1/TdZaEhcYuMxovtCWhARsj1cg1B6R2z2df1y5KBIHSe0SI?= =?us-ascii?Q?BM2fCMh+700mG7ZxFthYk3z6Ki6nS4QOLRuHnZNZQhzxqlDmHJfTRtkwtmkq?= =?us-ascii?Q?01qcD5NruL+VinJuGmQPu/sVpYLj/s0y3ftipZwewfi9OfCRKJkAUhn/6cSP?= =?us-ascii?Q?3UVgaM1XOYR7FXHN71RqdvwH9kL9+OC0rJFnBKsYV55ijPYC1VVg1umW4lCA?= =?us-ascii?Q?hjKuZKZ92G6kWCoe8adnZv3Bhozj5vSfsLHYqpcTJn+IrmZvdqTsjcSjFeMu?= =?us-ascii?Q?qLQcvqdJppzMc3JnyKAqU+Z/a+taUSzGsrbClTpWkNlog/ypgJSPoPx6aGWV?= =?us-ascii?Q?uRisOscGxrRWvx1b0tzzq3sYdWURMszaUPCbOPed1oU5TcwbRokuKn3pjWOb?= =?us-ascii?Q?kLw3YYBDBy4rAzNEvE8oWL3/A4ihLAY/k1u36SBuTOCvkb0EE6m6BCFIGR/W?= =?us-ascii?Q?MCNNoLAnqxEBHav0J6aAcXYM9bzMnBi6sCz2r1Wptvg0WW3ZLioBP/YFVa+p?= =?us-ascii?Q?BFtPRhu7hUuFq0k+SAbryTKEknsbwLvUNOzAb0nv3MC+1EojrQNRsAQ10Rl1?= =?us-ascii?Q?Z8yvBG0V9HBqaoY4rL/eVpPXNiYeen0qYd+vKf8Lp+pxwcUuWOMlTlPp7XqY?= =?us-ascii?Q?kcrV8LdbvPpn9wWKmw8=3D?= MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BN9PR11MB5483.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: ba58fce9-ec9c-4cd8-48e7-08db633b9a71 X-MS-Exchange-CrossTenant-originalarrivaltime: 02 Jun 2023 07:33:04.8105 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: gPFKQhlf5jvq+Y16ITVCRZjDW/YVe4O91iENli6Uu8l8fAz18+QFW+31f91YYwNQJvNGs65n36kmzdz1RP8kkg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ1PR11MB6298 Return-Path: dun.tan@intel.com X-OriginatorOrg: intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable In original code logic, SmmS3 page table set GuardPage in smm normal stack = as not-present instead of Smm S3 Stack. A bugzila has been submitted to track this issue: https://bugzilla.tianocor= e.org/show_bug.cgi?id=3D4476 . Will fix the issue in future patches. So now remain the code status that the GuardPage in normal stack and the Gu= ardPage in shadow stack are protected at different place.=20 Thanks, Dun -----Original Message----- From: Ni, Ray =20 Sent: Friday, June 2, 2023 1:09 PM To: Tan, Dun ; devel@edk2.groups.io Cc: Dong, Eric ; Kumar, Rahul R ; Gerd Hoffmann Subject: RE: [edk2-devel] [Patch V4 10/15] UefiCpuPkg: Add GenSmmPageTable(= ) to create smm page table I see. The GuardPage in normal stack is marked as not-present inside GenSmmPageTab= le. The GuardPage in shadow stack is marked as not-present after calling Initia= lizeMpServiceData(). Do you think it would be clearer to group them together? Thanks, Ray > -----Original Message----- > From: Tan, Dun > Sent: Friday, June 2, 2023 11:47 AM > To: Ni, Ray ; devel@edk2.groups.io > Cc: Dong, Eric ; Kumar, Rahul R=20 > ; Gerd Hoffmann > Subject: RE: [edk2-devel] [Patch V4 10/15] UefiCpuPkg: Add=20 > GenSmmPageTable() to create smm page table >=20 > Edited the reply to make it clearer. >=20 > -----Original Message----- > From: Tan, Dun > Sent: Friday, June 2, 2023 11:36 AM > To: Ni, Ray ; devel@edk2.groups.io > Cc: Dong, Eric ; Kumar, Rahul R=20 > ; Gerd Hoffmann > Subject: RE: [edk2-devel] [Patch V4 10/15] UefiCpuPkg: Add=20 > GenSmmPageTable() to create smm page table >=20 > GenSmmPageTable() doesn't mark the "Guard page" in=20 > "mSmmShadowStackSize range" is to align with old behavior. > GenSmmPageTable() is also used to create SmmS3Cr3 and the "Guard page"=20 > in "mSmmShadowStackSize range" is not marked as non-present in SmmS3Cr3. > In the code logic, the "Guard page" in "mSmmShadowStackSize range" is=20 > marked as not-present after InitializeMpServiceData() creates the initial= smm page table. > This process is only done for smm runtime page table. >=20 > Thanks, > Dun > -----Original Message----- > From: Ni, Ray > Sent: Friday, June 2, 2023 11:23 AM > To: devel@edk2.groups.io; Tan, Dun > Cc: Dong, Eric ; Kumar, Rahul R=20 > ; Gerd Hoffmann > Subject: RE: [edk2-devel] [Patch V4 10/15] UefiCpuPkg: Add=20 > GenSmmPageTable() to create smm page table >=20 >=20 > // > // SMM Stack Guard Enabled > // Append Shadow Stack after normal stack > // 2 more pages is allocated for each processor, one is guard pag= e and the > other is known good shadow stack. > // > // |=3D Stacks > //=20 > +--------------------------------------------------+------------------ > -------------------- > -------------------------+ > // | Known Good Stack | Guard Page | SMM Stack | Known Good = Shadow > Stack | Guard Page | SMM Shadow Stack | > //=20 > +--------------------------------------------------+------------------ > -------------------- > -------------------------+ > // | 4K | 4K |PcdCpuSmmStackSize| = 4K | 4K > |PcdCpuSmmShadowStackSize| > // |<---------------- mSmmStackSize=20 > ----------------->|<--------------------- > mSmmShadowStackSize ------------------->| > // | = | > // |<-------------------------------------------- Processor N=20 > ---------------------------- > --------------------------->| > // >=20 > GenSmmPageTable() only sets the "Guard page" in "mSmmStackSize range"=20 > as not-present. > But the "Guard page" in "mSmmShadowStackSize range" is not marked as=20 > not- present. > Why? >=20 > Thanks, > Ray >=20 > > -----Original Message----- > > From: devel@edk2.groups.io On Behalf Of=20 > > duntan > > Sent: Tuesday, May 16, 2023 5:59 PM > > To: devel@edk2.groups.io > > Cc: Dong, Eric ; Ni, Ray ;=20 > > Kumar, Rahul R ; Gerd Hoffmann=20 > > > > Subject: [edk2-devel] [Patch V4 10/15] UefiCpuPkg: Add > > GenSmmPageTable() to create smm page table > > > > This commit is code refinement to current smm pagetable generation=20 > > code. Add a new GenSmmPageTable() API to create smm page table based=20 > > on the PageTableMap() API in CpuPageTableLib. Caller only needs to=20 > > specify the paging mode and the PhysicalAddressBits to map. > > This function can be used to create both IA32 pae paging and X64=20 > > 5level, 4level paging. > > > > Signed-off-by: Dun Tan > > Cc: Eric Dong > > Cc: Ray Ni > > Cc: Rahul Kumar > > Cc: Gerd Hoffmann > > --- > > UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c | 2 +- > > UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 15 > > +++++++++++++++ > > UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | 65 > > > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > > UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c | 220 > > ++++++++++++++++++++++++++------------------------------------------ > > ++++++++++++++++++++++++++-- > > ++++++++++++++++++++++++++--------------- > > -------------------------------------------------------------------- > > -- > > ---------------------------- > > ------------------------------------- > > 4 files changed, 107 insertions(+), 195 deletions(-) > > > > diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c > > b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c > > index 9c8107080a..b11264ce4a 100644 > > --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c > > +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c > > @@ -63,7 +63,7 @@ SmmInitPageTable ( > > InitializeIDTSmmStackGuard (); > > } > > > > - return Gen4GPageTable (TRUE); > > + return GenSmmPageTable (PagingPae, mPhysicalAddressBits); > > } > > > > /** > > diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h > > b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h > > index a7da9673a5..5399659bc0 100644 > > --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h > > +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h > > @@ -553,6 +553,21 @@ Gen4GPageTable ( > > IN BOOLEAN Is32BitPageTable > > ); > > > > +/** > > + Create page table based on input PagingMode and=20 > > +PhysicalAddressBits in > smm. > > + > > + @param[in] PagingMode The paging mode. > > + @param[in] PhysicalAddressBits The bits of physical address to= map. > > + > > + @retval PageTable Address > > + > > +**/ > > +UINTN > > +GenSmmPageTable ( > > + IN PAGING_MODE PagingMode, > > + IN UINT8 PhysicalAddressBits > > + ); > > + > > /** > > Initialize global data for MP synchronization. > > > > diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c > > b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c > > index ef0ba9a355..138ff43c9d 100644 > > --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c > > +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c > > @@ -1642,6 +1642,71 @@ EdkiiSmmClearMemoryAttributes ( > > return SmmClearMemoryAttributes (BaseAddress, Length,=20 > > Attributes); } > > > > +/** > > + Create page table based on input PagingMode and=20 > > +PhysicalAddressBits in > smm. > > + > > + @param[in] PagingMode The paging mode. > > + @param[in] PhysicalAddressBits The bits of physical address to= map. > > + > > + @retval PageTable Address > > + > > +**/ > > +UINTN > > +GenSmmPageTable ( > > + IN PAGING_MODE PagingMode, > > + IN UINT8 PhysicalAddressBits > > + ) > > +{ > > + UINTN PageTableBufferSize; > > + UINTN PageTable; > > + VOID *PageTableBuffer; > > + IA32_MAP_ATTRIBUTE MapAttribute; > > + IA32_MAP_ATTRIBUTE MapMask; > > + RETURN_STATUS Status; > > + UINTN GuardPage; > > + UINTN Index; > > + UINT64 Length; > > + > > + Length =3D LShiftU64 (1, PhysicalAddressBi= ts); > > + PageTable =3D 0; > > + PageTableBufferSize =3D 0; > > + MapMask.Uint64 =3D MAX_UINT64; > > + MapAttribute.Uint64 =3D mAddressEncMask; > > + MapAttribute.Bits.Present =3D 1; > > + MapAttribute.Bits.ReadWrite =3D 1; > > + MapAttribute.Bits.UserSupervisor =3D 1; > > + MapAttribute.Bits.Accessed =3D 1; > > + MapAttribute.Bits.Dirty =3D 1; > > + > > + Status =3D PageTableMap (&PageTable, PagingMode, NULL, > > &PageTableBufferSize, 0, Length, &MapAttribute, &MapMask, NULL); > > + ASSERT (Status =3D=3D RETURN_BUFFER_TOO_SMALL); DEBUG ((DEBUG_INFO, > > + "GenSMMPageTable: 0x%x bytes needed for initial > > SMM page table\n", PageTableBufferSize)); > > + PageTableBuffer =3D AllocatePageTableMemory (EFI_SIZE_TO_PAGES > > (PageTableBufferSize)); > > + ASSERT (PageTableBuffer !=3D NULL); Status =3D PageTableMap=20 > > + (&PageTable, PagingMode, PageTableBuffer, > > &PageTableBufferSize, 0, Length, &MapAttribute, &MapMask, NULL); > > + ASSERT (Status =3D=3D RETURN_SUCCESS); ASSERT (PageTableBufferSize= =20 > > + =3D=3D 0); > > + > > + if (FeaturePcdGet (PcdCpuSmmStackGuard)) { > > + // > > + // Mark the 4KB guard page between known good stack and smm=20 > > + stack as > > non-present > > + // > > + for (Index =3D 0; Index < gSmmCpuPrivate- > > >SmmCoreEntryContext.NumberOfCpus; Index++) { > > + GuardPage =3D mSmmStackArrayBase + EFI_PAGE_SIZE + Index * > > (mSmmStackSize + mSmmShadowStackSize); > > + Status =3D ConvertMemoryPageAttributes (PageTable, PagingMode= , > > GuardPage, SIZE_4KB, EFI_MEMORY_RP, TRUE, NULL); > > + } > > + } > > + > > + if ((PcdGet8 (PcdNullPointerDetectionPropertyMask) & BIT1) !=3D 0) { > > + // > > + // Mark [0, 4k] as non-present > > + // > > + Status =3D ConvertMemoryPageAttributes (PageTable, PagingMode, 0,= =20 > > + SIZE_4KB, > > EFI_MEMORY_RP, TRUE, NULL); > > + } > > + > > + return (UINTN)PageTable; > > +} > > + > > /** > > This function retrieves the attributes of the memory region specifie= d by > > BaseAddress and Length. If different attributes are got from=20 > > different part diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c > > b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c > > index 25ced50955..060e6dc147 100644 > > --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c > > +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c > > @@ -167,160 +167,6 @@ CalculateMaximumSupportAddress ( > > return PhysicalAddressBits; > > } > > > > -/** > > - Set static page table. > > - > > - @param[in] PageTable Address of page table. > > - @param[in] PhysicalAddressBits The maximum physical address bits > > supported. > > -**/ > > -VOID > > -SetStaticPageTable ( > > - IN UINTN PageTable, > > - IN UINT8 PhysicalAddressBits > > - ) > > -{ > > - UINT64 PageAddress; > > - UINTN NumberOfPml5EntriesNeeded; > > - UINTN NumberOfPml4EntriesNeeded; > > - UINTN NumberOfPdpEntriesNeeded; > > - UINTN IndexOfPml5Entries; > > - UINTN IndexOfPml4Entries; > > - UINTN IndexOfPdpEntries; > > - UINTN IndexOfPageDirectoryEntries; > > - UINT64 *PageMapLevel5Entry; > > - UINT64 *PageMapLevel4Entry; > > - UINT64 *PageMap; > > - UINT64 *PageDirectoryPointerEntry; > > - UINT64 *PageDirectory1GEntry; > > - UINT64 *PageDirectoryEntry; > > - > > - // > > - // IA-32e paging translates 48-bit linear addresses to 52-bit=20 > > physical addresses > > - // when 5-Level Paging is disabled. > > - // > > - ASSERT (PhysicalAddressBits <=3D 52); > > - if (!m5LevelPagingNeeded && (PhysicalAddressBits > 48)) { > > - PhysicalAddressBits =3D 48; > > - } > > - > > - NumberOfPml5EntriesNeeded =3D 1; > > - if (PhysicalAddressBits > 48) { > > - NumberOfPml5EntriesNeeded =3D (UINTN)LShiftU64 (1, PhysicalAddress= Bits - > > 48); > > - PhysicalAddressBits =3D 48; > > - } > > - > > - NumberOfPml4EntriesNeeded =3D 1; > > - if (PhysicalAddressBits > 39) { > > - NumberOfPml4EntriesNeeded =3D (UINTN)LShiftU64 (1, PhysicalAddress= Bits - > > 39); > > - PhysicalAddressBits =3D 39; > > - } > > - > > - NumberOfPdpEntriesNeeded =3D 1; > > - ASSERT (PhysicalAddressBits > 30); > > - NumberOfPdpEntriesNeeded =3D (UINTN)LShiftU64 (1,=20 > > PhysicalAddressBits > > - 30); > > - > > - // > > - // By architecture only one PageMapLevel4 exists - so lets=20 > > allocate storage for it. > > - // > > - PageMap =3D (VOID *)PageTable; > > - > > - PageMapLevel4Entry =3D PageMap; > > - PageMapLevel5Entry =3D NULL; > > - if (m5LevelPagingNeeded) { > > - // > > - // By architecture only one PageMapLevel5 exists - so lets allocat= e storage > for > > it. > > - // > > - PageMapLevel5Entry =3D PageMap; > > - } > > - > > - PageAddress =3D 0; > > - > > - for ( IndexOfPml5Entries =3D 0 > > - ; IndexOfPml5Entries < NumberOfPml5EntriesNeeded > > - ; IndexOfPml5Entries++, PageMapLevel5Entry++) > > - { > > - // > > - // Each PML5 entry points to a page of PML4 entires. > > - // So lets allocate space for them and fill them in in the IndexOf= Pml4Entries > > loop. > > - // When 5-Level Paging is disabled, below allocation happens only = once. > > - // > > - if (m5LevelPagingNeeded) { > > - PageMapLevel4Entry =3D (UINT64 *)((*PageMapLevel5Entry) & > > ~mAddressEncMask & gPhyMask); > > - if (PageMapLevel4Entry =3D=3D NULL) { > > - PageMapLevel4Entry =3D AllocatePageTableMemory (1); > > - ASSERT (PageMapLevel4Entry !=3D NULL); > > - ZeroMem (PageMapLevel4Entry, EFI_PAGES_TO_SIZE (1)); > > - > > - *PageMapLevel5Entry =3D (UINT64)(UINTN)PageMapLevel4Entry | > > mAddressEncMask | PAGE_ATTRIBUTE_BITS; > > - } > > - } > > - > > - for (IndexOfPml4Entries =3D 0; IndexOfPml4Entries < > > (NumberOfPml5EntriesNeeded =3D=3D 1 ? NumberOfPml4EntriesNeeded : 512); > > IndexOfPml4Entries++, PageMapLevel4Entry++) { > > - // > > - // Each PML4 entry points to a page of Page Directory Pointer en= tries. > > - // > > - PageDirectoryPointerEntry =3D (UINT64 *)((*PageMapLevel4Entry) & > > ~mAddressEncMask & gPhyMask); > > - if (PageDirectoryPointerEntry =3D=3D NULL) { > > - PageDirectoryPointerEntry =3D AllocatePageTableMemory (1); > > - ASSERT (PageDirectoryPointerEntry !=3D NULL); > > - ZeroMem (PageDirectoryPointerEntry, EFI_PAGES_TO_SIZE (1)); > > - > > - *PageMapLevel4Entry =3D (UINT64)(UINTN)PageDirectoryPointerEnt= ry | > > mAddressEncMask | PAGE_ATTRIBUTE_BITS; > > - } > > - > > - if (m1GPageTableSupport) { > > - PageDirectory1GEntry =3D PageDirectoryPointerEntry; > > - for (IndexOfPageDirectoryEntries =3D 0; IndexOfPageDirectoryEn= tries < 512; > > IndexOfPageDirectoryEntries++, PageDirectory1GEntry++, PageAddress=20 > > IndexOfPageDirectoryEntries+++=3D > > SIZE_1GB) { > > - if ((IndexOfPml4Entries =3D=3D 0) && (IndexOfPageDirectoryEn= tries < 4)) { > > - // > > - // Skip the < 4G entries > > - // > > - continue; > > - } > > - > > - // > > - // Fill in the Page Directory entries > > - // > > - *PageDirectory1GEntry =3D PageAddress | mAddressEncMask | > IA32_PG_PS > > | PAGE_ATTRIBUTE_BITS; > > - } > > - } else { > > - PageAddress =3D BASE_4GB; > > - for (IndexOfPdpEntries =3D 0; IndexOfPdpEntries < > > (NumberOfPml4EntriesNeeded =3D=3D 1 ? NumberOfPdpEntriesNeeded : 512); > > IndexOfPdpEntries++, PageDirectoryPointerEntry++) { > > - if ((IndexOfPml4Entries =3D=3D 0) && (IndexOfPdpEntries < 4)= ) { > > - // > > - // Skip the < 4G entries > > - // > > - continue; > > - } > > - > > - // > > - // Each Directory Pointer entries points to a page of Page D= irectory > entires. > > - // So allocate space for them and fill them in in the > > IndexOfPageDirectoryEntries loop. > > - // > > - PageDirectoryEntry =3D (UINT64 *)((*PageDirectoryPointerEntr= y) & > > ~mAddressEncMask & gPhyMask); > > - if (PageDirectoryEntry =3D=3D NULL) { > > - PageDirectoryEntry =3D AllocatePageTableMemory (1); > > - ASSERT (PageDirectoryEntry !=3D NULL); > > - ZeroMem (PageDirectoryEntry, EFI_PAGES_TO_SIZE (1)); > > - > > - // > > - // Fill in a Page Directory Pointer Entries > > - // > > - *PageDirectoryPointerEntry =3D (UINT64)(UINTN)PageDirector= yEntry | > > mAddressEncMask | PAGE_ATTRIBUTE_BITS; > > - } > > - > > - for (IndexOfPageDirectoryEntries =3D 0; IndexOfPageDirectory= Entries < > 512; > > IndexOfPageDirectoryEntries++, PageDirectoryEntry++, PageAddress +=3D > > SIZE_2MB) { > > - // > > - // Fill in the Page Directory entries > > - // > > - *PageDirectoryEntry =3D PageAddress | mAddressEncMask | IA= 32_PG_PS > | > > PAGE_ATTRIBUTE_BITS; > > - } > > - } > > - } > > - } > > - } > > -} > > - > > /** > > Create PageTable for SMM use. > > > > @@ -332,15 +178,16 @@ SmmInitPageTable ( > > VOID > > ) > > { > > - EFI_PHYSICAL_ADDRESS Pages; > > - UINT64 *PTEntry; > > + UINTN PageTable; > > LIST_ENTRY *FreePage; > > UINTN Index; > > UINTN PageFaultHandlerHookAddress; > > IA32_IDT_GATE_DESCRIPTOR *IdtEntry; > > EFI_STATUS Status; > > + UINT64 *PdptEntry; > > UINT64 *Pml4Entry; > > UINT64 *Pml5Entry; > > + UINT8 PhysicalAddressBits; > > > > // > > // Initialize spin lock > > @@ -357,59 +204,44 @@ SmmInitPageTable ( > > } else { > > mPagingMode =3D m1GPageTableSupport ? Paging4Level1GB : Paging4Lev= el; > > } > > + > > DEBUG ((DEBUG_INFO, "5LevelPaging Needed - %d\n", > > m5LevelPagingNeeded)); > > DEBUG ((DEBUG_INFO, "1GPageTable Support - %d\n", > > m1GPageTableSupport)); > > DEBUG ((DEBUG_INFO, "PcdCpuSmmRestrictedMemoryAccess - %d\n",=20 > > mCpuSmmRestrictedMemoryAccess)); > > DEBUG ((DEBUG_INFO, "PhysicalAddressBits - %d\n", > > mPhysicalAddressBits)); > > - // > > - // Generate PAE page table for the first 4GB memory space > > - // > > - Pages =3D Gen4GPageTable (FALSE); > > > > // > > - // Set IA32_PG_PMNT bit to mask this entry > > + // Generate initial SMM page table. > > + // Only map [0, 4G] when PcdCpuSmmRestrictedMemoryAccess is FALSE. > > // > > - PTEntry =3D (UINT64 *)(UINTN)Pages; > > - for (Index =3D 0; Index < 4; Index++) { > > - PTEntry[Index] |=3D IA32_PG_PMNT; > > - } > > - > > - // > > - // Fill Page-Table-Level4 (PML4) entry > > - // > > - Pml4Entry =3D (UINT64 *)AllocatePageTableMemory (1); > > - ASSERT (Pml4Entry !=3D NULL); > > - *Pml4Entry =3D Pages | mAddressEncMask | PAGE_ATTRIBUTE_BITS; > > - ZeroMem (Pml4Entry + 1, EFI_PAGE_SIZE - sizeof (*Pml4Entry)); > > - > > - // > > - // Set sub-entries number > > - // > > - SetSubEntriesNum (Pml4Entry, 3); > > - PTEntry =3D Pml4Entry; > > + PhysicalAddressBits =3D mCpuSmmRestrictedMemoryAccess ? > > mPhysicalAddressBits : 32; > > + PageTable =3D GenSmmPageTable (mPagingMode, PhysicalAddres= sBits); > > > > if (m5LevelPagingNeeded) { > > + Pml5Entry =3D (UINT64 *)PageTable; > > // > > - // Fill PML5 entry > > - // > > - Pml5Entry =3D (UINT64 *)AllocatePageTableMemory (1); > > - ASSERT (Pml5Entry !=3D NULL); > > - *Pml5Entry =3D (UINTN)Pml4Entry | mAddressEncMask | > > PAGE_ATTRIBUTE_BITS; > > - ZeroMem (Pml5Entry + 1, EFI_PAGE_SIZE - sizeof (*Pml5Entry)); > > - // > > - // Set sub-entries number > > + // Set Pml5Entry sub-entries number for smm PF handler usage. > > // > > SetSubEntriesNum (Pml5Entry, 1); > > - PTEntry =3D Pml5Entry; > > + Pml4Entry =3D (UINT64 *)((*Pml5Entry) & ~mAddressEncMask &=20 > > + gPhyMask); } else { > > + Pml4Entry =3D (UINT64 *)PageTable; } > > + > > + // > > + // Set IA32_PG_PMNT bit to mask first 4 PdptEntry. > > + // > > + PdptEntry =3D (UINT64 *)((*Pml4Entry) & ~mAddressEncMask &=20 > > + gPhyMask); for (Index =3D 0; Index < 4; Index++) { > > + PdptEntry[Index] |=3D IA32_PG_PMNT; > > } > > > > - if (mCpuSmmRestrictedMemoryAccess) { > > + if (!mCpuSmmRestrictedMemoryAccess) { > > // > > - // When access to non-SMRAM memory is restricted, create page tabl= e > > - // that covers all memory space. > > + // Set Pml4Entry sub-entries number for smm PF handler usage. > > // > > - SetStaticPageTable ((UINTN)PTEntry, mPhysicalAddressBits); > > - } else { > > + SetSubEntriesNum (Pml4Entry, 3); > > + > > // > > // Add pages to page pool > > // > > @@ -466,7 +298,7 @@ SmmInitPageTable ( > > // > > // Return the address of PML4/PML5 (to set CR3) > > // > > - return (UINT32)(UINTN)PTEntry; > > + return (UINT32)PageTable; > > } > > > > /** > > -- > > 2.31.1.windows.1 > > > > > > > >=20 > >