From: "Chiu, Chasel" <chasel.chiu@intel.com>
To: "Loo, Tung Lun" <tung.lun.loo@intel.com>,
"devel@edk2.groups.io" <devel@edk2.groups.io>
Cc: "Desimone, Nathaniel L" <nathaniel.l.desimone@intel.com>,
"Zeng, Star" <star.zeng@intel.com>
Subject: Re: [PATCH] IntelFsp2Pkg: Add FSP 2.3 header support
Date: Tue, 31 May 2022 02:16:08 +0000 [thread overview]
Message-ID: <BN9PR11MB5483129F65BB25021986053EE6DC9@BN9PR11MB5483.namprd11.prod.outlook.com> (raw)
In-Reply-To: <20220511232629.1941-1-tung.lun.loo@intel.com>
Patch pushed: https://github.com/tianocore/edk2/commit/fa2b212d61dfeb9c00a174280a73a4f573ef617d
Thanks,
Chasel
> -----Original Message-----
> From: Loo, Tung Lun <tung.lun.loo@intel.com>
> Sent: Thursday, May 12, 2022 7:26 AM
> To: devel@edk2.groups.io
> Cc: Loo, Tung Lun <tung.lun.loo@intel.com>; Desimone, Nathaniel L
> <nathaniel.l.desimone@intel.com>; Zeng, Star <star.zeng@intel.com>; Chiu,
> Chasel <chasel.chiu@intel.com>
> Subject: [PATCH] IntelFsp2Pkg: Add FSP 2.3 header support
>
> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3921
>
> This patch adds a couple of fields supported in FSP 2.3 header from both header
> generation and tool support perspective.
>
> Signed-off-by: Loo Tung Lun <tung.lun.loo@intel.com>
> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
> Cc: Star Zeng <star.zeng@intel.com>
> Cc: Chasel Chiu <chasel.chiu@intel.com>
> ---
> IntelFsp2Pkg/Tools/ConfigEditor/ConfigEditor.py | 63
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-----
> IntelFsp2Pkg/Tools/ConfigEditor/GenYamlCfg.py | 14 +++++++++++---
> 2 files changed, 69 insertions(+), 8 deletions(-)
>
> diff --git a/IntelFsp2Pkg/Tools/ConfigEditor/ConfigEditor.py
> b/IntelFsp2Pkg/Tools/ConfigEditor/ConfigEditor.py
> index 680b90e09d..5271504282 100644
> --- a/IntelFsp2Pkg/Tools/ConfigEditor/ConfigEditor.py
> +++ b/IntelFsp2Pkg/Tools/ConfigEditor/ConfigEditor.py
> @@ -13,6 +13,7 @@ import tkinter.ttk as ttk
> import tkinter.messagebox as messagebox import tkinter.filedialog as filedialog
> +from pickle import FALSE, TRUE from pathlib import Path from GenYamlCfg
> import CGenYamlCfg, bytes_to_value, \ bytes_to_bracket_str,
> value_to_bytes, array_str_to_value@@ -458,7 +459,10 @@ class
> FSP_INFORMATION_HEADER(Structure):
> ('NotifyPhaseEntryOffset', c_uint32), ('FspMemoryInitEntryOffset',
> c_uint32), ('TempRamExitEntryOffset', c_uint32),-
> ('FspSiliconInitEntryOffset', c_uint32)+ ('FspSiliconInitEntryOffset',
> c_uint32),+ ('FspMultiPhaseSiInitEntryOffset', c_uint32),+
> ('ExtendedImageRevision', c_uint16),+ ('Reserved4', c_uint16) ] @@ -
> 700,6 +704,34 @@ class FirmwareDevice:
> raise Exception("ERROR: Incorrect FV size in image !")
> self.CheckFsp() + def IsIntegerType(self, val):+ if sys.version_info[0] < 3:+
> if type(val) in (int, long):+ return True+ else:+ if type(val) is
> int:+ return True+ return False++ def ConvertRevisionString(self,
> obj):+ for field in obj._fields_:+ key = field[0]+ val = getattr(obj,
> key)+ rep = ''++ if self.IsIntegerType(val):+ if (key ==
> 'ImageRevision'):+ FspImageRevisionMajor = ((val >> 24) & 0xFF)+
> FspImageRevisionMinor = ((val >> 16) & 0xFF)+
> FspImageRevisionRevision = ((val >> 8) & 0xFF)+
> FspImageRevisionBuildNumber = (val & 0xFF)+ rep = '0x%08X' % val+
> elif (key == 'ExtendedImageRevision'):+ FspImageRevisionRevision |=
> (val & 0xFF00)+ FspImageRevisionBuildNumber |= ((val << 8) &
> 0xFF00)+ rep = "0x%04X ('%02X.%02X.%04X.%04X')" % (val,
> FspImageRevisionMajor, FspImageRevisionMinor, FspImageRevisionRevision,
> FspImageRevisionBuildNumber)+ return rep+ def OutputFsp(self):
> def copy_text_to_clipboard(): window.clipboard_clear()@@ -721,7
> +753,8 @@ class FirmwareDevice:
> self.OutputText = self.OutputText + "Fsp Header Details \n\n" while i <
> len(self.FihList): try:- self.OutputText +=
> str(self.BuildList[i].decode()) + "\n"+ # self.OutputText +=
> str(self.BuildList[i].decode()) + "\n"+ self.OutputText +=
> str(self.BuildList[i]) + "\n" except Exception: self.OutputText +=
> "No description found\n" self.OutputText += "FSP Header :\n "@@ -729,6
> +762,8 @@ class FirmwareDevice:
> str(self.FihList[i].Signature.decode('utf-8')) + "\n "
> self.OutputText += "Header Length : " + \
> str(hex(self.FihList[i].HeaderLength)) + "\n "+ self.OutputText +=
> "Reserved1 : " + \+ str(hex(self.FihList[i].Reserved1)) + "\n "
> self.OutputText += "Header Revision : " + \
> str(hex(self.FihList[i].HeaderRevision)) + "\n " self.OutputText += "Spec
> Version : " + \@@ -743,15 +778,17 @@ class FirmwareDevice:
> str(hex(self.FihList[i].ImageBase)) + "\n " self.OutputText +=
> "Image Attribute : " + \ str(hex(self.FihList[i].ImageAttribute)) + "\n "+
> self.OutputText += "Component Attribute : " + \+
> str(hex(self.FihList[i].ComponentAttribute)) + "\n " self.OutputText +=
> "Cfg Region Offset : " + \ str(hex(self.FihList[i].CfgRegionOffset)) + "\n "
> self.OutputText += "Cfg Region Size : " + \
> str(hex(self.FihList[i].CfgRegionSize)) + "\n "- self.OutputText += "API Entry
> Num : " + \+ self.OutputText += "Reserved2 : " + \
> str(hex(self.FihList[i].Reserved2)) + "\n " self.OutputText += "Temp Ram
> Init Entry : " + \ str(hex(self.FihList[i].TempRamInitEntryOffset)) + "\n "-
> self.OutputText += "FSP Init Entry : " + \+ self.OutputText += "Reserved3 : "
> + \ str(hex(self.FihList[i].Reserved3)) + "\n " self.OutputText +=
> "Notify Phase Entry : " + \ str(hex(self.FihList[i].NotifyPhaseEntryOffset))
> + "\n "@@ -760,7 +797,23 @@ class FirmwareDevice:
> self.OutputText += "Temp Ram Exit Entry : " + \
> str(hex(self.FihList[i].TempRamExitEntryOffset)) + "\n " self.OutputText +=
> "Fsp Silicon Init Entry : " + \-
> str(hex(self.FihList[i].FspSiliconInitEntryOffset)) + "\n\n"+
> str(hex(self.FihList[i].FspSiliconInitEntryOffset)) + "\n "+ self.OutputText +=
> "Fsp Multi Phase Si Init Entry : " + \+
> str(hex(self.FihList[i].FspMultiPhaseSiInitEntryOffset)) + "\n "++ # display
> ExtendedImageRevision & Reserved4 if HeaderRevision >= 6+ for fsp in
> self.FihList:+ if fsp.HeaderRevision >= 6:+
> Display_ExtndImgRev = TRUE+ else:+ Display_ExtndImgRev =
> FALSE+ self.OutputText += "\n"+ if Display_ExtndImgRev ==
> TRUE:+ self.OutputText += "ExtendedImageRevision : " + \+
> str(self.ConvertRevisionString(self.FihList[i])) + "\n "+ self.OutputText +=
> "Reserved4 : " + \+ str(hex(self.FihList[i].Reserved4)) + "\n\n"+
> self.OutputText += "FSP Extended Header:\n " self.OutputText +=
> "Signature : " + \ str(self.FspExtList[i].Signature.decode('utf-8')) + "\n
> "diff --git a/IntelFsp2Pkg/Tools/ConfigEditor/GenYamlCfg.py
> b/IntelFsp2Pkg/Tools/ConfigEditor/GenYamlCfg.py
> index b593885807..90d7a11184 100644
> --- a/IntelFsp2Pkg/Tools/ConfigEditor/GenYamlCfg.py
> +++ b/IntelFsp2Pkg/Tools/ConfigEditor/GenYamlCfg.py
> @@ -929,17 +929,25 @@ into %d bytes !" % (value_str, length))
> ]]: tmp_list.append((op_val,
> op_str)) else:- opt_list = item['option'].split(',')+ if
> item['option'].find(';') != -1:+ opt_list = item['option'].split(';')+
> else:+ opt_list = re.split(', ', item['option']) for option in
> opt_list: option = option.strip() try:- (op_val,
> op_str) = option.split(':')+ if option.find(':') != -1:+
> (op_val, op_str) = option.split(':')+ else:+ op_val =
> option+ op_str = option except Exception:-
> raise SystemExit("Exception: Invalide \+ raise SystemExit("Exception:
> Invalid \ option format '%s' !" % option) tmp_list.append((op_val,
> op_str)) return tmp_list + def get_page_title(self, page_id, top=None):
> if top is None: top = self.get_cfg_page()['root']--
> 2.28.0.windows.1
prev parent reply other threads:[~2022-05-31 2:16 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-11 23:26 [PATCH] IntelFsp2Pkg: Add FSP 2.3 header support Tung Lun
2022-05-30 3:56 ` Chiu, Chasel
2022-05-31 2:16 ` Chiu, Chasel [this message]
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