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BN9PR11MB5483.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: d244a74d-eeed-498b-c8b8-08da42ab8627 X-MS-Exchange-CrossTenant-originalarrivaltime: 31 May 2022 02:16:08.3473 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: jkJWyu05bXvsPBcDMcix4AuBvbRZas9rHAqNbql8Rb0tL+EkrEdd+jn8SWFshRP6A4uT8WRr5QOjZyW2GcHrHQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR11MB6041 Return-Path: chasel.chiu@intel.com X-OriginatorOrg: intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Patch pushed: https://github.com/tianocore/edk2/commit/fa2b212d61dfeb9c00a1= 74280a73a4f573ef617d Thanks, Chasel > -----Original Message----- > From: Loo, Tung Lun > Sent: Thursday, May 12, 2022 7:26 AM > To: devel@edk2.groups.io > Cc: Loo, Tung Lun ; Desimone, Nathaniel L > ; Zeng, Star ; Chiu, > Chasel > Subject: [PATCH] IntelFsp2Pkg: Add FSP 2.3 header support >=20 > BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3921 >=20 > This patch adds a couple of fields supported in FSP 2.3 header from both = header > generation and tool support perspective. >=20 > Signed-off-by: Loo Tung Lun > Cc: Nate DeSimone > Cc: Star Zeng > Cc: Chasel Chiu > --- > IntelFsp2Pkg/Tools/ConfigEditor/ConfigEditor.py | 63 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++----- > IntelFsp2Pkg/Tools/ConfigEditor/GenYamlCfg.py | 14 +++++++++++--- > 2 files changed, 69 insertions(+), 8 deletions(-) >=20 > diff --git a/IntelFsp2Pkg/Tools/ConfigEditor/ConfigEditor.py > b/IntelFsp2Pkg/Tools/ConfigEditor/ConfigEditor.py > index 680b90e09d..5271504282 100644 > --- a/IntelFsp2Pkg/Tools/ConfigEditor/ConfigEditor.py > +++ b/IntelFsp2Pkg/Tools/ConfigEditor/ConfigEditor.py > @@ -13,6 +13,7 @@ import tkinter.ttk as ttk > import tkinter.messagebox as messagebox import tkinter.filedialog as fil= edialog > +from pickle import FALSE, TRUE from pathlib import Path from GenYamlCfg > import CGenYamlCfg, bytes_to_value, \ bytes_to_bracket_str, > value_to_bytes, array_str_to_value@@ -458,7 +459,10 @@ class > FSP_INFORMATION_HEADER(Structure): > ('NotifyPhaseEntryOffset', c_uint32), ('FspMemoryIni= tEntryOffset', > c_uint32), ('TempRamExitEntryOffset', c_uint32),- > ('FspSiliconInitEntryOffset', c_uint32)+ ('FspSiliconInitEntryOff= set', > c_uint32),+ ('FspMultiPhaseSiInitEntryOffset', c_uint32),+ > ('ExtendedImageRevision', c_uint16),+ ('Reserved4', c_uint16) = ] @@ - > 700,6 +704,34 @@ class FirmwareDevice: > raise Exception("ERROR: Incorrect FV size in image != ") > self.CheckFsp() + def IsIntegerType(self, val):+ if sys.version= _info[0] < 3:+ > if type(val) in (int, long):+ return True+ else:+ = if type(val) is > int:+ return True+ return False++ def ConvertRev= isionString(self, > obj):+ for field in obj._fields_:+ key =3D field[0]+ = val =3D getattr(obj, > key)+ rep =3D ''++ if self.IsIntegerType(val):+ = if (key =3D=3D > 'ImageRevision'):+ FspImageRevisionMajor =3D ((val >> = 24) & 0xFF)+ > FspImageRevisionMinor =3D ((val >> 16) & 0xFF)+ > FspImageRevisionRevision =3D ((val >> 8) & 0xFF)+ > FspImageRevisionBuildNumber =3D (val & 0xFF)+ rep =3D = '0x%08X' % val+ > elif (key =3D=3D 'ExtendedImageRevision'):+ FspImageRe= visionRevision |=3D > (val & 0xFF00)+ FspImageRevisionBuildNumber |=3D ((val= << 8) & > 0xFF00)+ rep =3D "0x%04X ('%02X.%02X.%04X.%04X')" % (v= al, > FspImageRevisionMajor, FspImageRevisionMinor, FspImageRevisionRevision, > FspImageRevisionBuildNumber)+ return rep+ def Outp= utFsp(self): > def copy_text_to_clipboard(): window.clipboard_clear()@@ -721= ,7 > +753,8 @@ class FirmwareDevice: > self.OutputText =3D self.OutputText + "Fsp Header Details \n\n" = while i < > len(self.FihList): try:- self.OutputText +=3D > str(self.BuildList[i].decode()) + "\n"+ # self.OutputText = +=3D > str(self.BuildList[i].decode()) + "\n"+ self.OutputText += =3D > str(self.BuildList[i]) + "\n" except Exception: = self.OutputText +=3D > "No description found\n" self.OutputText +=3D "FSP Header :\n= "@@ -729,6 > +762,8 @@ class FirmwareDevice: > str(self.FihList[i].Signature.decode('utf-8')) + "\n " > self.OutputText +=3D "Header Length : " + \ > str(hex(self.FihList[i].HeaderLength)) + "\n "+ self.OutputTex= t +=3D > "Reserved1 : " + \+ str(hex(self.FihList[i].Reserved1)) + = "\n " > self.OutputText +=3D "Header Revision : " + \ > str(hex(self.FihList[i].HeaderRevision)) + "\n " self.OutputT= ext +=3D "Spec > Version : " + \@@ -743,15 +778,17 @@ class FirmwareDevice: > str(hex(self.FihList[i].ImageBase)) + "\n " = self.OutputText +=3D > "Image Attribute : " + \ str(hex(self.FihList[i].ImageAtt= ribute)) + "\n "+ > self.OutputText +=3D "Component Attribute : " + \+ > str(hex(self.FihList[i].ComponentAttribute)) + "\n " self.Out= putText +=3D > "Cfg Region Offset : " + \ str(hex(self.FihList[i].CfgReg= ionOffset)) + "\n " > self.OutputText +=3D "Cfg Region Size : " + \ > str(hex(self.FihList[i].CfgRegionSize)) + "\n "- self.OutputTe= xt +=3D "API Entry > Num : " + \+ self.OutputText +=3D "Reserved2 : " + \ > str(hex(self.FihList[i].Reserved2)) + "\n " self.OutputText += =3D "Temp Ram > Init Entry : " + \ str(hex(self.FihList[i].TempRamInitEnt= ryOffset)) + "\n "- > self.OutputText +=3D "FSP Init Entry : " + \+ self.OutputText = +=3D "Reserved3 : " > + \ str(hex(self.FihList[i].Reserved3)) + "\n " = self.OutputText +=3D > "Notify Phase Entry : " + \ str(hex(self.FihList[i].Notif= yPhaseEntryOffset)) > + "\n "@@ -760,7 +797,23 @@ class FirmwareDevice: > self.OutputText +=3D "Temp Ram Exit Entry : " + \ > str(hex(self.FihList[i].TempRamExitEntryOffset)) + "\n " self= .OutputText +=3D > "Fsp Silicon Init Entry : " + \- > str(hex(self.FihList[i].FspSiliconInitEntryOffset)) + "\n\n"+ > str(hex(self.FihList[i].FspSiliconInitEntryOffset)) + "\n "+ s= elf.OutputText +=3D > "Fsp Multi Phase Si Init Entry : " + \+ > str(hex(self.FihList[i].FspMultiPhaseSiInitEntryOffset)) + "\n "++ = # display > ExtendedImageRevision & Reserved4 if HeaderRevision >=3D 6+ fo= r fsp in > self.FihList:+ if fsp.HeaderRevision >=3D 6:+ > Display_ExtndImgRev =3D TRUE+ else:+ Di= splay_ExtndImgRev =3D > FALSE+ self.OutputText +=3D "\n"+ if Displ= ay_ExtndImgRev =3D=3D > TRUE:+ self.OutputText +=3D "ExtendedImageRevision : " + \= + > str(self.ConvertRevisionString(self.FihList[i])) + "\n "+ = self.OutputText +=3D > "Reserved4 : " + \+ str(hex(self.FihList[i].Reserved4)= ) + "\n\n"+ > self.OutputText +=3D "FSP Extended Header:\n " self.OutputTex= t +=3D > "Signature : " + \ str(self.FspExtList[i].Signature.decod= e('utf-8')) + "\n > "diff --git a/IntelFsp2Pkg/Tools/ConfigEditor/GenYamlCfg.py > b/IntelFsp2Pkg/Tools/ConfigEditor/GenYamlCfg.py > index b593885807..90d7a11184 100644 > --- a/IntelFsp2Pkg/Tools/ConfigEditor/GenYamlCfg.py > +++ b/IntelFsp2Pkg/Tools/ConfigEditor/GenYamlCfg.py > @@ -929,17 +929,25 @@ into %d bytes !" % (value_str, length)) > ]]= : tmp_list.append((op_val, > op_str)) else:- opt_list =3D item['option'].sp= lit(',')+ if > item['option'].find(';') !=3D -1:+ opt_list =3D item['= option'].split(';')+ > else:+ opt_list =3D re.split(', ', item['option']) = for option in > opt_list: option =3D option.strip() = try:- (op_val, > op_str) =3D option.split(':')+ if option.find(':')= !=3D -1:+ > (op_val, op_str) =3D option.split(':')+ else:+ = op_val =3D > option+ op_str =3D option = except Exception:- > raise SystemExit("Exception: Invalide \+ raise Sys= temExit("Exception: > Invalid \ option format '%s' !" % option) tmp_list.ap= pend((op_val, > op_str)) return tmp_list + def get_page_title(self, page_id, = top=3DNone): > if top is None: top =3D self.get_cfg_page()['root']-- > 2.28.0.windows.1