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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Thanks for fixing this issue! Reviewed-by: Chasel Chiu > -----Original Message----- > From: Benjamin Doron > Sent: Friday, July 23, 2021 10:27 AM > To: devel@edk2.groups.io > Cc: Chiu, Chasel ; Desimone, Nathaniel L > ; Liming Gao > ; Dong, Eric > Subject: [PATCH v2] MinPlatformPkg/PciHostBridgeLibSimple: Fix Mem.Limit > assignment >=20 > In the case where the root bridge's Mem.Limit is the base address of PCIe > MMIO, subtract one to make a valid end address. >=20 > This fixes an issue where CpuDxe returns "Length(0x50000001) is not > aligned!" when PciHostBridgeDxe attempts to make this range uncacheable. >=20 > Cc: Chasel Chiu > Cc: Nate DeSimone > Cc: Liming Gao > Cc: Eric Dong > Signed-off-by: Benjamin Doron > --- >=20 > Platform/Intel/MinPlatformPkg/Pci/Library/PciHostBridgeLibSimple/PciHostB > ridgeLibSimple.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) >=20 > diff --git > a/Platform/Intel/MinPlatformPkg/Pci/Library/PciHostBridgeLibSimple/PciHos > tBridgeLibSimple.c > b/Platform/Intel/MinPlatformPkg/Pci/Library/PciHostBridgeLibSimple/PciHos > tBridgeLibSimple.c > index e231f747019e..0e3fee28b5d1 100644 > --- > a/Platform/Intel/MinPlatformPkg/Pci/Library/PciHostBridgeLibSimple/PciHos > tBridgeLibSimple.c > +++ b/Platform/Intel/MinPlatformPkg/Pci/Library/PciHostBridgeLibSimple/P > +++ ciHostBridgeLibSimple.c > @@ -90,7 +90,7 @@ PciHostBridgeGetRootBridges ( > if (PcdGet32(PcdPciReservedMemLimit) !=3D 0) > { mRootBridgeTemplate.Mem.Limit =3D PcdGet32 > (PcdPciReservedMemLimit); } else {- mRootBridgeTemplate.Mem.Limit = =3D > (UINT32) PcdGet64 (PcdPciExpressBaseAddress);+ > mRootBridgeTemplate.Mem.Limit =3D (UINT32) PcdGet64 > (PcdPciExpressBaseAddress) - 1; } > mRootBridgeTemplate.MemAbove4G.Base =3D PcdGet64 > (PcdPciReservedMemAbove4GBBase);-- > 2.31.1