From: "Chiu, Chasel" <chasel.chiu@intel.com>
To: "devel@edk2.groups.io" <devel@edk2.groups.io>,
"mikuback@linux.microsoft.com" <mikuback@linux.microsoft.com>
Cc: "Desimone, Nathaniel L" <nathaniel.l.desimone@intel.com>,
Jeremy Soller <jeremy@system76.com>
Subject: Re: [edk2-devel] [edk2-platforms][PATCH v4 12/41] KabylakeOpenBoardPkg: Use IntelSiliconPkg BIOS area and ucode PCDs
Date: Mon, 28 Jun 2021 01:36:42 +0000 [thread overview]
Message-ID: <BN9PR11MB54832185F05D086F5D46B8EDE6039@BN9PR11MB5483.namprd11.prod.outlook.com> (raw)
In-Reply-To: <20210625212120.235-13-mikuback@linux.microsoft.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
> -----Original Message-----
> From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Michael
> Kubacki
> Sent: Saturday, June 26, 2021 5:21 AM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel <chasel.chiu@intel.com>; Desimone, Nathaniel L
> <nathaniel.l.desimone@intel.com>; Jeremy Soller <jeremy@system76.com>
> Subject: [edk2-devel] [edk2-platforms][PATCH v4 12/41]
> KabylakeOpenBoardPkg: Use IntelSiliconPkg BIOS area and ucode PCDs
>
> From: Michael Kubacki <michael.kubacki@microsoft.com>
>
> REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3307
>
> Updates PCDs to use the IntelSiliconPkg PCD tokenspace now that the PCDs are
> declared in IntelSiliconPkg.dec.
>
> Cc: Chasel Chiu <chasel.chiu@intel.com>
> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
> Cc: Jeremy Soller <jeremy@system76.com>
> Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
> ---
> Platform/Intel/KabylakeOpenBoardPkg/BiosInfo/BiosInfo.inf
> | 4 +--
>
> Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Include/Fdf/FlashMapInclu
> de.fdf | 4 +--
> Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.fdf
> | 38 ++++++++++----------
>
> Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Include/Fdf/FlashMapIncl
> ude.fdf | 4 +--
> Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf
> | 38 ++++++++++----------
>
> Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSiliconP
> olicyUpdateLib/PeiSiliconPolicyUpdateLib.inf | 4 +--
> 6 files changed, 46 insertions(+), 46 deletions(-)
>
> diff --git a/Platform/Intel/KabylakeOpenBoardPkg/BiosInfo/BiosInfo.inf
> b/Platform/Intel/KabylakeOpenBoardPkg/BiosInfo/BiosInfo.inf
> index e5e40144a68a..6607ea6edfc3 100644
> --- a/Platform/Intel/KabylakeOpenBoardPkg/BiosInfo/BiosInfo.inf
> +++ b/Platform/Intel/KabylakeOpenBoardPkg/BiosInfo/BiosInfo.inf
> @@ -36,8 +36,8 @@ [Packages]
> MinPlatformPkg/MinPlatformPkg.dec
>
> [Pcd]
> - gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase ## CONSUMES
> - gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize ## CONSUMES
> + gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase ##
> CONSUMES
> + gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize ##
> CONSUMES
>
> [Sources]
> BiosInfo.c
> diff --git
> a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Include/Fdf/FlashMapIncl
> ude.fdf
> b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Include/Fdf/FlashMapIncl
> ude.fdf
> index 6cb6d54f558f..ce809a277b6e 100644
> ---
> a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Include/Fdf/FlashMapIncl
> ude.fdf
> +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Include/Fdf/FlashMa
> +++ pInclude.fdf
> @@ -36,8 +36,8 @@
> SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize =
> 0x00140000 #
> SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset =
> 0x002E0000 # Flash addr (0xFFD00000)
> SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize =
> 0x000B0000 #
> -SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset = 0x00390000
> # Flash addr (0xFFDB0000)
> -SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize = 0x000A0000
> #
> +SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset =
> 0x00390000 # Flash addr (0xFFDB0000)
> +SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =
> 0x000A0000 #
> SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset =
> 0x00430000 # Flash addr (0xFFE50000)
> SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize =
> 0x00060000 #
> SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset =
> 0x00490000 # Flash addr (0xFFEB0000)
> diff --git
> a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.fdf
> b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.fdf
> index bcd1ade72ba5..39432d21b8b5 100644
> --- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.fdf
> +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.fdf
> @@ -29,8 +29,8 @@ [FD.GalagoPro3]
> # assigned with PCD values. Instead, it uses the definitions for its variety, which
> # are FLASH_BASE, FLASH_SIZE, FLASH_BLOCK_SIZE and FLASH_NUM_BLOCKS.
> #
> -BaseAddress = $(FLASH_BASE) |
> gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress #The base address of the
> FLASH Device.
> -Size = $(FLASH_SIZE) | gSiPkgTokenSpaceGuid.PcdFlashAreaSize
> #The size in bytes of the FLASH Device
> +BaseAddress = $(FLASH_BASE) |
> gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress #The base address
> of the FLASH Device.
> +Size = $(FLASH_SIZE) | gIntelSiliconPkgTokenSpaceGuid.PcdBiosSize
> #The size in bytes of the FLASH Device
> ErasePolarity = 1
> BlockSize = $(FLASH_BLOCK_SIZE)
> NumBlocks = $(FLASH_NUM_BLOCKS)
> @@ -39,23 +39,23 @@ [FD.GalagoPro3]
> DEFINE SIPKG_PEI_BIN = INF
>
> # Set FLASH_REGION_FV_RECOVERY_OFFSET to PcdNemCodeCacheBase,
> because macro expression is not supported.
> -# So, PlatformSecLib uses PcdFlashAreaBaseAddress + PcdNemCodeCacheBase
> to get the real CodeCache base address.
> +# So, PlatformSecLib uses PcdBiosAreaBaseAddress + PcdNemCodeCacheBase
> to get the real CodeCache base address.
> SET gSiPkgTokenSpaceGuid.PcdNemCodeCacheBase =
> $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset)
> -SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase =
> $(gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress) +
> $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset)
> -SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =
> $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize)
> -SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress =
> $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase) + 0x60 -SET
> gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =
> $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) - 0x60
> +SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase =
> +$(gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) +
> +$(gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset)
> +SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =
> +$(gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize)
> +SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress =
> +$(gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase) + 0x60 SET
> +gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =
> +$(gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) - 0x60
> SET gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv = 0x60
> -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase =
> gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase
> -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize =
> gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize
> -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset =
> gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset
> -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress =
> gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress
> -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize =
> gSiPkgTokenSpaceGuid.PcdFlashAreaSize
> -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress =
> $(gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress) +
> $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset)
> -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress =
> $(gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress) +
> $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset)
> -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress =
> $(gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress) +
> $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset)
> -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress =
> gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress
> -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize =
> gSiPkgTokenSpaceGuid.PcdFlashAreaSize
> +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase =
> gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase
> +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize =
> gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize
> +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset =
> +gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset
> +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress =
> gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress
> +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize =
> gIntelSiliconPkgTokenSpaceGuid.PcdBiosSize
> +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress =
> $(gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) +
> $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset)
> +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress =
> $(gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) +
> $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset)
> +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress =
> $(gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) +
> $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset)
> +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress =
> gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress
> +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize =
> gIntelSiliconPkgTokenSpaceGuid.PcdBiosSize
>
> #################################################################
> ###############
> #
> # Following are lists of FD Region layout which correspond to the locations of
> different @@ -155,8 +155,8 @@ [FD.GalagoPro3]
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase|gMinPlatformPk
> gTokenSpaceGuid.PcdFlashFvPostMemorySize
> FV = FvPostMemory
>
> -
> gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset|gSiPkgTokenSpaceGuid.Pcd
> FlashMicrocodeFvSize
> -
> gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase|gSiPkgTokenSpaceGuid.PcdFl
> ashMicrocodeFvSize
> +gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset|gIntelSiliconP
> +kgTokenSpaceGuid.PcdFlashMicrocodeFvSize
> +gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase|gIntelSiliconPkg
> +TokenSpaceGuid.PcdFlashMicrocodeFvSize
> #Microcode
> FV = FvMicrocode
>
> diff --git
> a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Include/Fdf/FlashMapI
> nclude.fdf
> b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Include/Fdf/FlashMapI
> nclude.fdf
> index b5e3f66ceafc..67649e867616 100644
> ---
> a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Include/Fdf/FlashMapI
> nclude.fdf
> +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Include/Fdf/Flash
> +++ MapInclude.fdf
> @@ -34,8 +34,8 @@
> SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize =
> 0x001E0000 #
> SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset =
> 0x00370000 # Flash addr (0xFFB70000)
> SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize =
> 0x00180000 #
> -SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset = 0x004F0000
> # Flash addr (0xFFCF0000)
> -SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize = 0x000A0000
> #
> +SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset =
> 0x004F0000 # Flash addr (0xFFCF0000)
> +SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =
> 0x000A0000 #
> SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset =
> 0x00590000 # Flash addr (0xFFD90000)
> SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize =
> 0x00060000 #
> SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset =
> 0x005F0000 # Flash addr (0xFFDF0000)
> diff --git
> a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf
> b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf
> index 6cdf4e2f9f1f..f003dda0ddfc 100644
> --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf
> +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf
> @@ -29,8 +29,8 @@ [FD.KabylakeRvp3]
> # assigned with PCD values. Instead, it uses the definitions for its variety, which
> # are FLASH_BASE, FLASH_SIZE, FLASH_BLOCK_SIZE and FLASH_NUM_BLOCKS.
> #
> -BaseAddress = $(FLASH_BASE) |
> gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress #The base address of the
> FLASH Device.
> -Size = $(FLASH_SIZE) | gSiPkgTokenSpaceGuid.PcdFlashAreaSize
> #The size in bytes of the FLASH Device
> +BaseAddress = $(FLASH_BASE) |
> gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress #The base address of
> the FLASH Device.
> +Size = $(FLASH_SIZE) | gIntelSiliconPkgTokenSpaceGuid.PcdBiosSize
> #The size in bytes of the FLASH Device
> ErasePolarity = 1
> BlockSize = $(FLASH_BLOCK_SIZE)
> NumBlocks = $(FLASH_NUM_BLOCKS)
> @@ -39,23 +39,23 @@ [FD.KabylakeRvp3]
> DEFINE SIPKG_PEI_BIN = INF
>
> # Set FLASH_REGION_FV_RECOVERY_OFFSET to PcdNemCodeCacheBase,
> because macro expression is not supported.
> -# So, PlatformSecLib uses PcdFlashAreaBaseAddress + PcdNemCodeCacheBase
> to get the real CodeCache base address.
> +# So, PlatformSecLib uses PcdBiosAreaBaseAddress + PcdNemCodeCacheBase
> to get the real CodeCache base address.
> SET gSiPkgTokenSpaceGuid.PcdNemCodeCacheBase =
> $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset)
> -SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase =
> $(gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress) +
> $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset)
> -SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =
> $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize)
> -SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress =
> $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase) + 0x60 -SET
> gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =
> $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) - 0x60
> +SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase =
> +$(gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) +
> +$(gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset)
> +SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =
> +$(gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize)
> +SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress =
> +$(gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase) + 0x60 SET
> +gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =
> +$(gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) - 0x60
> SET gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv = 0x60
> -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase =
> gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase
> -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize =
> gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize
> -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset =
> gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset
> -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress =
> gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress
> -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize =
> gSiPkgTokenSpaceGuid.PcdFlashAreaSize
> -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress =
> $(gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress) +
> $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset)
> -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress =
> $(gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress) +
> $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset)
> -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress =
> $(gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress) +
> $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset)
> -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress =
> gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress
> -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize =
> gSiPkgTokenSpaceGuid.PcdFlashAreaSize
> +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase =
> gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase
> +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize =
> gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize
> +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset =
> +gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset
> +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress =
> gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress
> +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize =
> gIntelSiliconPkgTokenSpaceGuid.PcdBiosSize
> +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress =
> $(gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) +
> $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset)
> +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress =
> $(gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) +
> $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset)
> +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress =
> $(gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) +
> $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset)
> +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress =
> gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress
> +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize =
> gIntelSiliconPkgTokenSpaceGuid.PcdBiosSize
>
> #################################################################
> ###############
> #
> # Following are lists of FD Region layout which correspond to the locations of
> different @@ -151,8 +151,8 @@ [FD.KabylakeRvp3]
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase|gMinPlatformPk
> gTokenSpaceGuid.PcdFlashFvPostMemorySize
> FV = FvPostMemory
>
> -
> gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset|gSiPkgTokenSpaceGuid.Pcd
> FlashMicrocodeFvSize
> -
> gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase|gSiPkgTokenSpaceGuid.PcdFl
> ashMicrocodeFvSize
> +gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset|gIntelSiliconP
> +kgTokenSpaceGuid.PcdFlashMicrocodeFvSize
> +gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase|gIntelSiliconPkg
> +TokenSpaceGuid.PcdFlashMicrocodeFvSize
> #Microcode
> FV = FvMicrocode
>
> diff --git
> a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSilico
> nPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf
> b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSilico
> nPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf
> index 97ec70f611b1..8a99f7c59a49 100644
> ---
> a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSilico
> nPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf
> +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/Pe
> +++ iSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf
> @@ -52,8 +52,8 @@ [Guids]
>
> [Pcd]
> gSiPkgTokenSpaceGuid.PcdPeiMinMemorySize
> - gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase
> - gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize
> + gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase
> + gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize
> gKabylakeOpenBoardPkgTokenSpaceGuid.PcdGraphicsVbtGuid
> gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompResistor ##
> CONSUMES
> gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompTarget ##
> CONSUMES
> --
> 2.28.0.windows.1
>
>
>
> -=-=-=-=-=-=
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>
next prev parent reply other threads:[~2021-06-28 1:37 UTC|newest]
Thread overview: 83+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-25 21:20 [edk2-platforms][PATCH v4 00/41] Consolidate SpiFlashCommonLib instances Michael Kubacki
2021-06-25 21:20 ` [edk2-platforms][PATCH v4 01/41] CometlakeOpenBoardPkg: Remove redundant IntelSiliconPkg.dec entry Michael Kubacki
2021-06-28 1:36 ` [edk2-devel] " Chiu, Chasel
2021-06-28 23:05 ` Chaganty, Rangasai V
2021-06-25 21:20 ` [edk2-platforms][PATCH v4 02/41] WhiskeylakeOpenBoardPkg: " Michael Kubacki
2021-06-28 23:05 ` Chaganty, Rangasai V
2021-06-25 21:20 ` [edk2-platforms][PATCH v4 03/41] CometlakeOpenBoardPkg/PeiPolicyUpdateLib: Add missing GUID to INF Michael Kubacki
2021-06-28 1:36 ` [edk2-devel] " Chiu, Chasel
2021-06-28 23:08 ` Chaganty, Rangasai V
2021-06-25 21:20 ` [edk2-platforms][PATCH v4 04/41] IntelSiliconPkg: Add BIOS area base address and size PCDs Michael Kubacki
2021-06-28 23:10 ` Chaganty, Rangasai V
2021-06-25 21:20 ` [edk2-platforms][PATCH v4 05/41] IntelSiliconPkg: Add microcode FV PCDs Michael Kubacki
2021-06-28 23:50 ` Chaganty, Rangasai V
[not found] ` <MW3PR11MB4602324E354DB86D21B3171FB6039@MW3PR11MB4602.namprd11.prod.outlook.com>
2021-06-29 5:09 ` Ni, Ray
2021-06-30 2:26 ` Michael Kubacki
2021-06-30 6:45 ` Ni, Ray
2021-06-30 15:18 ` [edk2-devel] " Michael Kubacki
2021-06-25 21:20 ` [edk2-platforms][PATCH v4 06/41] IntelSiliconPkg: Add PCH SPI PPI Michael Kubacki
2021-06-28 23:16 ` Chaganty, Rangasai V
2021-06-25 21:20 ` [edk2-platforms][PATCH v4 07/41] IntelSiliconPkg: Add PCH SPI Protocol Michael Kubacki
2021-06-25 21:20 ` [edk2-platforms][PATCH v4 08/41] IntelSiliconPkg: Add SpiFlashCommonLib Michael Kubacki
2021-06-28 23:26 ` Chaganty, Rangasai V
2021-06-25 21:20 ` [edk2-platforms][PATCH v4 09/41] IntelSiliconPkg: Add SmmSpiFlashCommonLib Michael Kubacki
2021-06-28 23:32 ` Chaganty, Rangasai V
2021-06-25 21:20 ` [edk2-platforms][PATCH v4 10/41] IntelSiliconPkg: Add MM SPI FVB services Michael Kubacki
2021-06-25 21:20 ` [edk2-platforms][PATCH v4 11/41] CometlakeOpenBoardPkg: Use IntelSiliconPkg BIOS area and ucode PCDs Michael Kubacki
2021-06-28 1:34 ` Chiu, Chasel
2021-06-25 21:20 ` [edk2-platforms][PATCH v4 12/41] KabylakeOpenBoardPkg: " Michael Kubacki
2021-06-28 1:36 ` Chiu, Chasel [this message]
2021-06-25 21:20 ` [edk2-platforms][PATCH v4 13/41] SimicsOpenBoardPkg: " Michael Kubacki
2021-06-25 21:20 ` [edk2-platforms][PATCH v4 14/41] TigerlakeOpenBoardPkg: " Michael Kubacki
2021-06-25 21:20 ` [edk2-platforms][PATCH v4 15/41] WhiskeylakeOpenBoardPkg: " Michael Kubacki
2021-06-28 1:38 ` [edk2-devel] " Chiu, Chasel
2021-06-25 21:20 ` [edk2-platforms][PATCH v4 16/41] CoffeelakeSiliconPkg: " Michael Kubacki
2021-06-28 1:36 ` [edk2-devel] " Chiu, Chasel
2021-06-25 21:20 ` [edk2-platforms][PATCH v4 17/41] KabylakeSiliconPkg: " Michael Kubacki
2021-06-28 1:37 ` [edk2-devel] " Chiu, Chasel
2021-06-25 21:20 ` [edk2-platforms][PATCH v4 18/41] SimicsIch10Pkg: " Michael Kubacki
2021-06-25 21:20 ` [edk2-platforms][PATCH v4 19/41] TigerlakeSiliconPkg: " Michael Kubacki
2021-06-25 21:20 ` [edk2-platforms][PATCH v4 20/41] CometlakeOpenBoardPkg: Update SpiFvbService & SpiFlashCommonLib Michael Kubacki
2021-06-28 1:33 ` Chiu, Chasel
2021-06-29 0:10 ` Chaganty, Rangasai V
2021-06-25 21:21 ` [edk2-platforms][PATCH v4 21/41] KabylakeOpenBoardPkg: " Michael Kubacki
2021-06-28 1:33 ` Chiu, Chasel
2021-06-25 21:21 ` [edk2-platforms][PATCH v4 22/41] SimicsOpenBoardPkg: " Michael Kubacki
2021-06-25 21:21 ` [edk2-platforms][PATCH v4 23/41] TigerlakeOpenBoardPkg: " Michael Kubacki
2021-06-25 21:21 ` [edk2-platforms][PATCH v4 24/41] WhiskeylakeOpenBoardPkg: " Michael Kubacki
2021-06-28 1:37 ` [edk2-devel] " Chiu, Chasel
2021-06-25 21:21 ` [edk2-platforms][PATCH v4 25/41] MinPlatformPkg: Remove SpiFvbService modules Michael Kubacki
2021-06-28 1:37 ` [edk2-devel] " Chiu, Chasel
2021-06-25 21:21 ` [edk2-platforms][PATCH v4 26/41] CoffeelakeSiliconPkg: Remove SmmSpiFlashCommonLib Michael Kubacki
2021-06-28 1:34 ` Chiu, Chasel
2021-06-29 0:08 ` Chaganty, Rangasai V
2021-06-25 21:21 ` [edk2-platforms][PATCH v4 27/41] KabylakeSiliconPkg: " Michael Kubacki
2021-06-28 1:34 ` Chiu, Chasel
2021-06-25 21:21 ` [edk2-platforms][PATCH v4 28/41] SimicsIch10Pkg: " Michael Kubacki
2021-06-25 21:21 ` [edk2-platforms][PATCH v4 29/41] TigerlakeOpenBoardPkg: " Michael Kubacki
2021-06-25 21:21 ` [edk2-platforms][PATCH v4 30/41] MinPlatformPkg: Remove SpiFlashCommonLibNull Michael Kubacki
2021-06-28 1:38 ` [edk2-devel] " Chiu, Chasel
2021-06-25 21:21 ` [edk2-platforms][PATCH v4 31/41] KabylakeOpenBoardPkg/PeiSerialPortLibSpiFlash: Add IntelSiliconPkg.dec Michael Kubacki
2021-06-28 1:37 ` [edk2-devel] " Chiu, Chasel
2021-06-25 21:21 ` [edk2-platforms][PATCH v4 32/41] CoffeelakeSiliconPkg: Remove PCH SPI PPI and Protocol from package Michael Kubacki
2021-06-28 1:34 ` Chiu, Chasel
2021-06-25 21:21 ` [edk2-platforms][PATCH v4 33/41] KabylakeSiliconPkg: " Michael Kubacki
2021-06-28 1:35 ` Chiu, Chasel
2021-06-25 21:21 ` [edk2-platforms][PATCH v4 34/41] SimicsIch10Pkg: Remove PCH SPI SMM " Michael Kubacki
2021-06-25 21:21 ` [edk2-platforms][PATCH v4 35/41] TigerlakeSiliconPkg: Remove PCH SPI PPI and " Michael Kubacki
2021-06-25 21:21 ` [edk2-platforms][PATCH v4 36/41] IntelSiliconPkg: Add flash region GUIDs Michael Kubacki
2021-06-29 0:07 ` Chaganty, Rangasai V
2021-07-29 0:46 ` Nate DeSimone
2021-06-25 21:21 ` [edk2-platforms][PATCH v4 37/41] IntelSiliconPkg: Identify flash regions by GUID Michael Kubacki
2021-06-29 0:07 ` Chaganty, Rangasai V
2021-07-29 0:47 ` Nate DeSimone
2021-06-25 21:21 ` [edk2-platforms][PATCH v4 38/41] CoffeelakeSiliconPkg/BasePchSpiCommonLib: " Michael Kubacki
2021-06-28 1:35 ` Chiu, Chasel
2021-06-25 21:21 ` [edk2-platforms][PATCH v4 39/41] KabylakeSiliconPkg: " Michael Kubacki
2021-06-28 1:38 ` [edk2-devel] " Chiu, Chasel
2021-07-28 23:58 ` [edk2-devel] [edk2-platforms][PATCH v4 00/41] Consolidate SpiFlashCommonLib instances Nate DeSimone
2021-07-29 0:08 ` Michael Kubacki
2021-08-02 18:24 ` Michael Kubacki
2021-08-05 23:31 ` Nate DeSimone
[not found] ` <20210625212120.235-41-mikuback@linux.microsoft.com>
2021-07-29 0:47 ` [edk2-platforms][PATCH v4 40/41] SimicsIch10Pkg/BasePchSpiCommonLib: Identify flash regions by GUID Nate DeSimone
[not found] ` <20210625212120.235-42-mikuback@linux.microsoft.com>
2021-07-29 0:48 ` [edk2-platforms][PATCH v4 41/41] TigerlakeSiliconPkg/BasePchSpiCommonLib: " Nate DeSimone
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