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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Chasel Chiu > -----Original Message----- > From: devel@edk2.groups.io On Behalf Of Michael > Kubacki > Sent: Saturday, June 26, 2021 5:21 AM > To: devel@edk2.groups.io > Cc: Chiu, Chasel ; Desimone, Nathaniel L > ; Jeremy Soller > Subject: [edk2-devel] [edk2-platforms][PATCH v4 12/41] > KabylakeOpenBoardPkg: Use IntelSiliconPkg BIOS area and ucode PCDs >=20 > From: Michael Kubacki >=20 > REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D3307 >=20 > Updates PCDs to use the IntelSiliconPkg PCD tokenspace now that the PCDs = are > declared in IntelSiliconPkg.dec. >=20 > Cc: Chasel Chiu > Cc: Nate DeSimone > Cc: Jeremy Soller > Signed-off-by: Michael Kubacki > Reviewed-by: Nate DeSimone > --- > Platform/Intel/KabylakeOpenBoardPkg/BiosInfo/BiosInfo.inf > | 4 +-- >=20 > Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Include/Fdf/FlashMapInclu > de.fdf | 4 +-- > Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.fdf > | 38 ++++++++++---------- >=20 > Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Include/Fdf/FlashMapIncl > ude.fdf | 4 +-- > Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf > | 38 ++++++++++---------- >=20 > Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSilico= nP > olicyUpdateLib/PeiSiliconPolicyUpdateLib.inf | 4 +-- > 6 files changed, 46 insertions(+), 46 deletions(-) >=20 > diff --git a/Platform/Intel/KabylakeOpenBoardPkg/BiosInfo/BiosInfo.inf > b/Platform/Intel/KabylakeOpenBoardPkg/BiosInfo/BiosInfo.inf > index e5e40144a68a..6607ea6edfc3 100644 > --- a/Platform/Intel/KabylakeOpenBoardPkg/BiosInfo/BiosInfo.inf > +++ b/Platform/Intel/KabylakeOpenBoardPkg/BiosInfo/BiosInfo.inf > @@ -36,8 +36,8 @@ [Packages] > MinPlatformPkg/MinPlatformPkg.dec >=20 > [Pcd] > - gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase ## CON= SUMES > - gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize ## CON= SUMES > + gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase = ## > CONSUMES > + gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize = ## > CONSUMES >=20 > [Sources] > BiosInfo.c > diff --git > a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Include/Fdf/FlashMapIncl > ude.fdf > b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Include/Fdf/FlashMapIncl > ude.fdf > index 6cb6d54f558f..ce809a277b6e 100644 > --- > a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Include/Fdf/FlashMapIncl > ude.fdf > +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Include/Fdf/FlashMa > +++ pInclude.fdf > @@ -36,8 +36,8 @@ > SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize =3D > 0x00140000 # > SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset =3D > 0x002E0000 # Flash addr (0xFFD00000) > SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize =3D > 0x000B0000 # > -SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset =3D = 0x00390000 > # Flash addr (0xFFDB0000) > -SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =3D = 0x000A0000 > # > +SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset =3D > 0x00390000 # Flash addr (0xFFDB0000) > +SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =3D > 0x000A0000 # > SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset =3D > 0x00430000 # Flash addr (0xFFE50000) > SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize =3D > 0x00060000 # > SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset =3D > 0x00490000 # Flash addr (0xFFEB0000) > diff --git > a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.fdf > b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.fdf > index bcd1ade72ba5..39432d21b8b5 100644 > --- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.fdf > +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.fdf > @@ -29,8 +29,8 @@ [FD.GalagoPro3] > # assigned with PCD values. Instead, it uses the definitions for its var= iety, which > # are FLASH_BASE, FLASH_SIZE, FLASH_BLOCK_SIZE and FLASH_NUM_BLOCKS. > # > -BaseAddress =3D $(FLASH_BASE) | > gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress #The base address of th= e > FLASH Device. > -Size =3D $(FLASH_SIZE) | gSiPkgTokenSpaceGuid.PcdFlashAreaSize > #The size in bytes of the FLASH Device > +BaseAddress =3D $(FLASH_BASE) | > gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress #The base addr= ess > of the FLASH Device. > +Size =3D $(FLASH_SIZE) | gIntelSiliconPkgTokenSpaceGuid.PcdBios= Size > #The size in bytes of the FLASH Device > ErasePolarity =3D 1 > BlockSize =3D $(FLASH_BLOCK_SIZE) > NumBlocks =3D $(FLASH_NUM_BLOCKS) > @@ -39,23 +39,23 @@ [FD.GalagoPro3] > DEFINE SIPKG_PEI_BIN =3D INF >=20 > # Set FLASH_REGION_FV_RECOVERY_OFFSET to PcdNemCodeCacheBase, > because macro expression is not supported. > -# So, PlatformSecLib uses PcdFlashAreaBaseAddress + PcdNemCodeCacheBase > to get the real CodeCache base address. > +# So, PlatformSecLib uses PcdBiosAreaBaseAddress + PcdNemCodeCacheBase > to get the real CodeCache base address. > SET gSiPkgTokenSpaceGuid.PcdNemCodeCacheBase =3D > $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset) > -SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase =3D > $(gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress) + > $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset) > -SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =3D > $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) > -SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress =3D > $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase) + 0x60 -SET > gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =3D > $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) - 0x60 > +SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase =3D > +$(gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + > +$(gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset) > +SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =3D > +$(gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) > +SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress =3D > +$(gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase) + 0x60 SET > +gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =3D > +$(gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) - 0x60 > SET gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv =3D 0x60 > -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase =3D > gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase > -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize =3D > gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize > -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset =3D > gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset > -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress =3D > gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress > -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize =3D > gSiPkgTokenSpaceGuid.PcdFlashAreaSize > -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress =3D > $(gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress) + > $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset) > -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress =3D > $(gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress) + > $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset) > -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress =3D > $(gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress) + > $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset) > -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress =3D > gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress > -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize =3D > gSiPkgTokenSpaceGuid.PcdFlashAreaSize > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase =3D > gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize =3D > gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset =3D > +gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset > +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress =3D > gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress > +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize =3D > gIntelSiliconPkgTokenSpaceGuid.PcdBiosSize > +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress =3D > $(gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + > $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset) > +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress =3D > $(gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + > $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset) > +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress =3D > $(gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + > $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset) > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress =3D > gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize =3D > gIntelSiliconPkgTokenSpaceGuid.PcdBiosSize >=20 > ################################################################# > ############### > # > # Following are lists of FD Region layout which correspond to the locati= ons of > different @@ -155,8 +155,8 @@ [FD.GalagoPro3] > gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase|gMinPlatformPk > gTokenSpaceGuid.PcdFlashFvPostMemorySize > FV =3D FvPostMemory >=20 > - > gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset|gSiPkgTokenSpaceGuid.Pcd > FlashMicrocodeFvSize > - > gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase|gSiPkgTokenSpaceGuid.PcdFl > ashMicrocodeFvSize > +gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset|gIntelSiliconP > +kgTokenSpaceGuid.PcdFlashMicrocodeFvSize > +gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase|gIntelSiliconPkg > +TokenSpaceGuid.PcdFlashMicrocodeFvSize > #Microcode > FV =3D FvMicrocode >=20 > diff --git > a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Include/Fdf/FlashMapI > nclude.fdf > b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Include/Fdf/FlashMapI > nclude.fdf > index b5e3f66ceafc..67649e867616 100644 > --- > a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Include/Fdf/FlashMapI > nclude.fdf > +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Include/Fdf/Flash > +++ MapInclude.fdf > @@ -34,8 +34,8 @@ > SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize =3D > 0x001E0000 # > SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset =3D > 0x00370000 # Flash addr (0xFFB70000) > SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize =3D > 0x00180000 # > -SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset =3D = 0x004F0000 > # Flash addr (0xFFCF0000) > -SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =3D = 0x000A0000 > # > +SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset =3D > 0x004F0000 # Flash addr (0xFFCF0000) > +SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =3D > 0x000A0000 # > SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset =3D > 0x00590000 # Flash addr (0xFFD90000) > SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize =3D > 0x00060000 # > SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset =3D > 0x005F0000 # Flash addr (0xFFDF0000) > diff --git > a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf > b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf > index 6cdf4e2f9f1f..f003dda0ddfc 100644 > --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf > +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf > @@ -29,8 +29,8 @@ [FD.KabylakeRvp3] > # assigned with PCD values. Instead, it uses the definitions for its var= iety, which > # are FLASH_BASE, FLASH_SIZE, FLASH_BLOCK_SIZE and FLASH_NUM_BLOCKS. > # > -BaseAddress =3D $(FLASH_BASE) | > gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress #The base address of th= e > FLASH Device. > -Size =3D $(FLASH_SIZE) | gSiPkgTokenSpaceGuid.PcdFlashAreaSize > #The size in bytes of the FLASH Device > +BaseAddress =3D $(FLASH_BASE) | > gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress #The base address = of > the FLASH Device. > +Size =3D $(FLASH_SIZE) | gIntelSiliconPkgTokenSpaceGuid.PcdBios= Size > #The size in bytes of the FLASH Device > ErasePolarity =3D 1 > BlockSize =3D $(FLASH_BLOCK_SIZE) > NumBlocks =3D $(FLASH_NUM_BLOCKS) > @@ -39,23 +39,23 @@ [FD.KabylakeRvp3] > DEFINE SIPKG_PEI_BIN =3D INF >=20 > # Set FLASH_REGION_FV_RECOVERY_OFFSET to PcdNemCodeCacheBase, > because macro expression is not supported. > -# So, PlatformSecLib uses PcdFlashAreaBaseAddress + PcdNemCodeCacheBase > to get the real CodeCache base address. > +# So, PlatformSecLib uses PcdBiosAreaBaseAddress + PcdNemCodeCacheBase > to get the real CodeCache base address. > SET gSiPkgTokenSpaceGuid.PcdNemCodeCacheBase =3D > $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset) > -SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase =3D > $(gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress) + > $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset) > -SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =3D > $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) > -SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress =3D > $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase) + 0x60 -SET > gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =3D > $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) - 0x60 > +SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase =3D > +$(gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + > +$(gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset) > +SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =3D > +$(gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) > +SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress =3D > +$(gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase) + 0x60 SET > +gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =3D > +$(gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) - 0x60 > SET gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv =3D 0x60 > -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase =3D > gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase > -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize =3D > gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize > -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset =3D > gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset > -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress =3D > gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress > -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize =3D > gSiPkgTokenSpaceGuid.PcdFlashAreaSize > -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress =3D > $(gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress) + > $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset) > -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress =3D > $(gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress) + > $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset) > -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress =3D > $(gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress) + > $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset) > -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress =3D > gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress > -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize =3D > gSiPkgTokenSpaceGuid.PcdFlashAreaSize > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase =3D > gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize =3D > gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset =3D > +gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset > +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress =3D > gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress > +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize =3D > gIntelSiliconPkgTokenSpaceGuid.PcdBiosSize > +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress =3D > $(gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + > $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset) > +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress =3D > $(gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + > $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset) > +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress =3D > $(gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + > $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset) > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress =3D > gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize =3D > gIntelSiliconPkgTokenSpaceGuid.PcdBiosSize >=20 > ################################################################# > ############### > # > # Following are lists of FD Region layout which correspond to the locati= ons of > different @@ -151,8 +151,8 @@ [FD.KabylakeRvp3] > gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase|gMinPlatformPk > gTokenSpaceGuid.PcdFlashFvPostMemorySize > FV =3D FvPostMemory >=20 > - > gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset|gSiPkgTokenSpaceGuid.Pcd > FlashMicrocodeFvSize > - > gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase|gSiPkgTokenSpaceGuid.PcdFl > ashMicrocodeFvSize > +gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset|gIntelSiliconP > +kgTokenSpaceGuid.PcdFlashMicrocodeFvSize > +gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase|gIntelSiliconPkg > +TokenSpaceGuid.PcdFlashMicrocodeFvSize > #Microcode > FV =3D FvMicrocode >=20 > diff --git > a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSili= co > nPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf > b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSili= co > nPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf > index 97ec70f611b1..8a99f7c59a49 100644 > --- > a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSili= co > nPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf > +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/Pe > +++ iSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf > @@ -52,8 +52,8 @@ [Guids] >=20 > [Pcd] > gSiPkgTokenSpaceGuid.PcdPeiMinMemorySize > - gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase > - gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize > + gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase > + gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize > gKabylakeOpenBoardPkgTokenSpaceGuid.PcdGraphicsVbtGuid > gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompResistor ## > CONSUMES > gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompTarget ## > CONSUMES > -- > 2.28.0.windows.1 >=20 >=20 >=20 > -=3D-=3D-=3D-=3D-=3D-=3D > Groups.io Links: You receive all messages sent to this group. > View/Reply Online (#77109): https://edk2.groups.io/g/devel/message/77109 > Mute This Topic: https://groups.io/mt/83794793/1777047 > Group Owner: devel+owner@edk2.groups.io > Unsubscribe: https://edk2.groups.io/g/devel/unsub [chasel.chiu@intel.com] > -=3D-=3D-=3D-=3D-=3D-=3D >=20