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contact devel+owner@edk2.groups.io Resent-Date: Mon, 01 Apr 2024 23:50:01 -0700 Resent-From: chasel.chiu@intel.com Reply-To: devel@edk2.groups.io,chasel.chiu@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: I8kYXHGlbhMvp7QFdfYVX2TMx7686176AA= Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20240206 header.b=2eKBiO9+; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=intel.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io Reviewed-by: Chasel Chiu Thanks, Chasel > -----Original Message----- > From: Tan, Dun > Sent: Sunday, March 31, 2024 11:04 PM > To: devel@edk2.groups.io > Cc: Ni, Ray ; Lou, Yun ; Chiu, Chase= l > ; Desimone, Nathaniel L > ; Liming Gao ; > Dong, Eric > Subject: [edk2-platforms V2 3/3] MinPlatformPkg: Sort ApicIdOrderTable by > special rules >=20 > Sort ApicIdOrderTable by following special rules: > 1. Make sure BSP is the first entry. > 2. For APs, big core first, then small core. >=20 > With this implementation, BIOS can present cores in order of relative > performance in MADT. Linux OS would schedule cores by the order that they= are > presented in the MADT LocalX2ApicStruct entries.Then Linux OS would think= of > this as relative performance order. This implementation can benefit the l= inux os > usage case. >=20 > Signed-off-by: Dun Tan > Cc: Ray Ni > Cc: Jason Lou > Cc: Chasel Chiu > Cc: Nate DeSimone > Cc: Liming Gao > Cc: Eric Dong > --- > Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c | 63 > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 63 insertions(+) >=20 > diff --git a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c > b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c > index 1fa70e3df9..389df48824 100644 > --- a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c > +++ b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c > @@ -132,6 +132,62 @@ AppendCpuMapTableEntry ( >=20 > } >=20 > +/** > + Sort CpuApicIdOrderTable based on the following rules: > + 1.Make sure BSP is the first entry. > + 2.Big core first, then small core. > + > + @param[in] CpuApicIdOrderTable Pointer to EFI_CPU_ID_ORDER_MAP > + @param[in] Count Number to EFI_CPU_ID_ORDER_MAP > + @param[in] BspIndex BSP index > +**/ > +VOID > +SortApicIdOrderTable ( > + IN EFI_CPU_ID_ORDER_MAP *CpuApicIdOrderTable, > + IN UINTN Count, > + IN UINTN BspIndex > + ) > +{ > + UINTN Index; > + UINTN SubIndex; > + EFI_CPU_ID_ORDER_MAP SortBuffer; > + > + // > + // Put BSP at the first entry. > + // > + if (BspIndex !=3D 0) { > + CopyMem (&SortBuffer, &CpuApicIdOrderTable[BspIndex], sizeof > (EFI_CPU_ID_ORDER_MAP)); > + CopyMem (&CpuApicIdOrderTable[1], CpuApicIdOrderTable, (BspIndex) * > sizeof (EFI_CPU_ID_ORDER_MAP)); > + CopyMem (CpuApicIdOrderTable, &SortBuffer, sizeof > + (EFI_CPU_ID_ORDER_MAP)); } > + > + // > + // If there are more than 2 cores, perform insertion sort for rest > + cores except the bsp in first entry // to move big cores in front of s= mall cores. > + // Also the original order based on the MpService index inside big cor= es and > small cores are retained. > + // > + for (Index =3D 2; Index < Count; Index++) { > + if (CpuApicIdOrderTable[Index].CoreType =3D=3D > CPUID_CORE_TYPE_INTEL_ATOM) { > + continue; > + } > + > + CopyMem (&SortBuffer, &CpuApicIdOrderTable[Index], sizeof > + (EFI_CPU_ID_ORDER_MAP)); > + > + for (SubIndex =3D Index - 1; SubIndex >=3D 1; SubIndex--) { > + if (CpuApicIdOrderTable[SubIndex].CoreType =3D=3D > CPUID_CORE_TYPE_INTEL_ATOM) { > + CopyMem (&CpuApicIdOrderTable[SubIndex + 1], > &CpuApicIdOrderTable[SubIndex], sizeof (EFI_CPU_ID_ORDER_MAP)); > + } else { > + // > + // Except the BSP, all cores in front of SubIndex must be big co= res. > + // > + break; > + } > + } > + > + CopyMem (&CpuApicIdOrderTable[SubIndex + 1], &SortBuffer, sizeof > +(EFI_CPU_ID_ORDER_MAP)); > + } > +} > + > /** > Get CPU core type. >=20 > @@ -174,6 +230,7 @@ CreateCpuLocalApicInTable ( > EFI_CPU_ID_ORDER_MAP *CpuIdMapPtr; > UINT32 Socket; > UINT32 CpuidMaxInput; > + UINTN BspIndex; >=20 > Status =3D EFI_SUCCESS; >=20 > @@ -198,6 +255,10 @@ CreateCpuLocalApicInTable ( > &ProcessorInfoBuffer > ); >=20 > + if ((ProcessorInfoBuffer.StatusFlag & PROCESSOR_AS_BSP_BIT) !=3D 0) = { > + BspIndex =3D Index; > + } > + > CpuIdMapPtr =3D (EFI_CPU_ID_ORDER_MAP *) &CpuApicIdOrderTable[Index]= ; > if ((ProcessorInfoBuffer.StatusFlag & PROCESSOR_ENABLED_BIT) !=3D 0)= { > CpuIdMapPtr->ApicId =3D (UINT32)ProcessorInfoBuffer.ProcessorId; > @@ -230,6 +291,8 @@ CreateCpuLocalApicInTable ( > } > } >=20 > + SortApicIdOrderTable (CpuApicIdOrderTable, mNumberOfCpus, BspIndex); > + > DEBUG ((DEBUG_INFO, "::ACPI:: APIC ID Order Table Init. mNumOfBitSh= ift =3D > %x\n", mNumOfBitShift)); > DebugDisplayReOrderTable (CpuApicIdOrderTable); >=20 > -- > 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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