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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Chasel Chiu > -----Original Message----- > From: Desimone, Nathaniel L > Sent: Tuesday, August 10, 2021 12:37 PM > To: devel@edk2.groups.io > Cc: Chiu, Chasel ; Michael Kubacki > ; Benjamin Doron > > Subject: [edk2-platforms] [PATCH V1] KabylakeSiliconPkg: Update > SA_MISC_PEI_PREMEM_CONFIG >=20 > Updates SA_MISC_PEI_PREMEM_CONFIG from revision 1 to revision 3. Add > initialization of the policy values. >=20 > Cc: Chasel Chiu > Cc: Michael Kubacki > Cc: Benjamin Doron > Signed-off-by: Nate DeSimone > --- > .../KabylakeRvp3/OpenBoardPkg.dsc | 24 +++--- > .../PeiSiliconPolicyUpdateLib.c | 39 +++++++++- > .../PeiSiliconPolicyUpdateLib.inf | 9 ++- > .../ConfigBlock/SaMiscPeiPreMemConfig.h | 77 ++++++++++++++++++- > .../Library/PeiSaPolicyLib/PeiSaPolicyLib.c | 37 ++++++++- > 5 files changed, 169 insertions(+), 17 deletions(-) >=20 > diff --git > a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc > b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc > index 8523ab3f4f..f64555e391 100644 > --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc > +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc > @@ -182,17 +182,6 @@ > # Board-specific > ####################################### >=20 > PlatformHookLib|$(PROJECT)/Library/BasePlatformHookLib/BasePlatformHook > Lib.inf > -!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection =3D=3D 1 > - # > - # FSP API mode > - # > - > SiliconPolicyUpdateLib|$(PROJECT)/FspWrapper/Library/PeiSiliconPolicyUpda= te > LibFsp/PeiSiliconPolicyUpdateLibFsp.inf > -!else > - # > - # FSP Dispatch mode and non-FSP build (EDK2 build) > - # > - > SiliconPolicyUpdateLib|$(PROJECT)/Policy/Library/PeiSiliconPolicyUpdateLi= b/Pei > SiliconPolicyUpdateLib.inf > -!endif >=20 > [LibraryClasses.IA32.SEC] > ####################################### > @@ -200,6 +189,7 @@ > ####################################### >=20 > TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/Sec > TestPointCheckLib.inf >=20 > SecBoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/SecBoardInitLibN > ull/SecBoardInitLibNull.inf > + > + SiliconPolicyUpdateLib|MinPlatformPkg/PlatformInit/Library/SiliconPoli > + cyUpdateLibNull/SiliconPolicyUpdateLibNull.inf >=20 > [LibraryClasses.common.PEIM] > ####################################### > @@ -222,6 +212,18 @@ > ####################################### > # Board Package > ####################################### > +!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection =3D=3D 1 > + # > + # FSP API mode > + # > + > +SiliconPolicyUpdateLib|$(PROJECT)/FspWrapper/Library/PeiSiliconPolicyUp > +dateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf > +!else > + # > + # FSP Dispatch mode and non-FSP build (EDK2 build) > + # > + > +SiliconPolicyUpdateLib|$(PROJECT)/Policy/Library/PeiSiliconPolicyUpdate > +Lib/PeiSiliconPolicyUpdateLib.inf > +!endif > + > # Thunderbolt > !if gKabylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE >=20 > PeiDTbtInitLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/Private/P > eiDTbtInitLib/PeiDTbtInitLib.inf > diff --git > a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSili= co > nPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c > b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSili= co > nPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c > index 5cc7c03c61..2dce9be63c 100644 > --- > a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSili= co > nPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c > +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/Pe > +++ iSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c > @@ -1,7 +1,7 @@ > /** @file > Provides silicon policy update library functions. >=20 > -Copyright (c) 2019, Intel Corporation. All rights reserved.
> +Copyright (c) 2019 - 2021, Intel Corporation. All rights reserved.
> SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > **/ > @@ -398,6 +398,8 @@ SiliconPolicyUpdatePreMem ( > SA_MISC_PEI_PREMEM_CONFIG *MiscPeiPreMemConfig; > MEMORY_CONFIG_NO_CRC *MemConfigNoCrc; > VOID *Buffer; > + UINTN VariableSize; > + VOID *MemorySavedData; > UINT8 SpdAddressTable[4]; >=20 > DEBUG((DEBUG_INFO, "\nUpdating Policy in Pre-Mem\n")); @@ -417,6 > +419,41 @@ SiliconPolicyUpdatePreMem ( > // Pass board specific SpdAddressTable to policy > // > CopyMem ((VOID *) MiscPeiPreMemConfig->SpdAddressTable, (VOID *) > SpdAddressTable, (sizeof (UINT8) * 4)); > + > + // > + // Set size of SMRAM > + // > + MiscPeiPreMemConfig->TsegSize =3D PcdGet32 (PcdTsegSize); > + > + // > + // Initialize S3 Data variable (S3DataPtr). It may be used for war= m and fast > boot paths. > + // Note: AmberLake FSP does not implement the FSPM_ARCH_CONFIG_PPI > added in FSP 2.1, hence > + // the platform specific S3DataPtr must be used instead. > + // > + VariableSize =3D 0; > + MemorySavedData =3D NULL; > + Status =3D PeiGetVariable ( > + L"MemoryConfig", > + &gFspNonVolatileStorageHobGuid, > + &MemorySavedData, > + &VariableSize > + ); > + DEBUG ((DEBUG_INFO, "Get L\"MemoryConfig\" > gFspNonVolatileStorageHobGuid - %r\n", Status)); > + DEBUG ((DEBUG_INFO, "MemoryConfig Size - 0x%x\n", VariableSize)); > + if (!EFI_ERROR (Status)) { > + MiscPeiPreMemConfig->S3DataPtr =3D MemorySavedData; > + } > + > + // > + // In FSP Dispatch Mode these BAR values are initialized by > SiliconPolicyInitPreMem() in > + // KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyIni= tPreMem.c; > this function calls > + // PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI->PeiPreMemPolicyInit() to > initialize all Config Blocks > + // with default policy values (including these BAR values.) > PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI > + // is implemented in the FSP. Make sure the value that FSP is usin= g matches > the value we are using. > + // > + ASSERT (PcdGet64 (PcdMchBaseAddress) <=3D 0xFFFFFFFF); > + ASSERT (MiscPeiPreMemConfig->MchBar =3D=3D (UINT32) PcdGet64 > (PcdMchBaseAddress)); > + ASSERT (MiscPeiPreMemConfig->SmbusBar =3D=3D PcdGet16 > + (PcdSmbusBaseAddress)); > } > MemConfigNoCrc =3D NULL; > Status =3D GetConfigBlock (Policy, &gMemoryConfigNoCrcGuid, (VOID *) > &MemConfigNoCrc); diff --git > a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSili= co > nPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf > b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSili= co > nPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf > index 97ec70f611..5c2da68bf9 100644 > --- > a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSili= co > nPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf > +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/Pe > +++ iSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf > @@ -1,7 +1,7 @@ > ### @file > # Component information file for silicon policy update library # -# Cop= yright (c) > 2019 - 2020 Intel Corporation. All rights reserved.
> +# Copyright (c) 2019 - 2021 Intel Corporation. All rights reserved.
> # > # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -11,7 +11,7 @@ > INF_VERSION =3D 0x00010005 > BASE_NAME =3D PeiSiliconPolicyUpdateLib > FILE_GUID =3D 14F5D83D-76A5-4241-BEC5-987E70E233D= 5 > - MODULE_TYPE =3D BASE > + MODULE_TYPE =3D PEIM > VERSION_STRING =3D 1.0 > LIBRARY_CLASS =3D SiliconPolicyUpdateLib >=20 > @@ -33,6 +33,7 @@ > [Packages] > MinPlatformPkg/MinPlatformPkg.dec > MdePkg/MdePkg.dec > + IntelFsp2Pkg/IntelFsp2Pkg.dec > UefiCpuPkg/UefiCpuPkg.dec > KabylakeSiliconPkg/SiPkg.dec > KabylakeOpenBoardPkg/OpenBoardPkg.dec > @@ -49,11 +50,15 @@ > gHsioPciePreMemConfigGuid ## CONSUMES > gHsioSataPreMemConfigGuid ## CONSUMES > gSaMiscPeiPreMemConfigGuid ## CONSUMES > + gFspNonVolatileStorageHobGuid ## CONSUMES >=20 > [Pcd] > gSiPkgTokenSpaceGuid.PcdPeiMinMemorySize > gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase > gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize > + gSiPkgTokenSpaceGuid.PcdMchBaseAddress > + gSiPkgTokenSpaceGuid.PcdSmbusBaseAddress > + gSiPkgTokenSpaceGuid.PcdTsegSize > gKabylakeOpenBoardPkgTokenSpaceGuid.PcdGraphicsVbtGuid > gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompResistor ## > CONSUMES > gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompTarget ## > CONSUMES > diff --git > a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/ConfigBlock/SaMisc= Pei > PreMemConfig.h > b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/ConfigBlock/SaMisc= Pei > PreMemConfig.h > index 4aa02e3142..2ed587f425 100644 > --- > a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/ConfigBlock/SaMisc= Pei > PreMemConfig.h > +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/ConfigBlock/S > +++ aMiscPeiPreMemConfig.h > @@ -1,7 +1,7 @@ > /** @file > Policy details for miscellaneous configuration in System Agent >=20 > -Copyright (c) 2017, Intel Corporation. All rights reserved.
> +Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.
> SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > **/ > @@ -14,18 +14,91 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #define > SA_MC_MAX_SOCKETS 4 #endif >=20 > -#define SA_MISC_PEI_PREMEM_CONFIG_REVISION 1 > +#define SA_MISC_PEI_PREMEM_CONFIG_REVISION 3 >=20 > /** > This configuration block is to configure SA Miscellaneous variables du= ring PEI > Pre-Mem phase like programming > different System Agent BARs, TsegSize, IedSize, MmioSize required etc. > Revision 1: > - Initial version. > + Revision 2: > + - Added SgDelayAfterOffMethod, SgDelayAfterLinkEnable and > SgGenSpeedChangeEnable. > + Revision 3: > + - Added BdatTestType and BdatSchema. > **/ > typedef struct { > CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Blo= ck > Header > UINT8 SpdAddressTable[SA_MC_MAX_SOCKETS];///< Offset 28 Memory > DIMMs' SPD address for reading SPD data. example: > SpdAddressTable[0]=3D0xA2(C0D0), SpdAddressTable[1]=3D0xA0(C0D1), > SpdAddressTable[2]=3D0xA2(C1D0), SpdAddressTable[3]=3D0xA0(C1D1) > + VOID *S3DataPtr; ///< Offset 32 Memory data = save pointer for > S3 resume. The memory space should be allocated and filled with proper S3 > resume data on a resume path > UINT32 MchBar; ///< Offset 36 Address of S= ystem Agent > MCHBAR: 0xFED10000 > + UINT32 DmiBar; ///< Offset 40 Address of S= ystem Agent > DMIBAR: 0xFED18000 > + UINT32 EpBar; ///< Offset 44 Address of S= ystem Agent EPBAR: > 0xFED19000 > + UINT32 SmbusBar; ///< Offset 48 Address of S= ystem Agent > SMBUS BAR: 0xEFA0 > + UINT32 GdxcBar; ///< Offset 52 Address of S= ystem Agent > GDXCBAR: 0xFED84000 > + /** > + Offset 56 Size of TSEG in bytes. (Must be power of 2) > + 0x400000: 4MB for Release build (When IED enabled, it will be= 8MB) > + 0x1000000 : 16MB for Debug build (Regardless IED enabled or dis= abled) > + **/ > + UINT32 TsegSize; > + UINT32 EdramBar; ///< Offset 60 Address of S= ystem Agent > EDRAMBAR: 0xFED80000 > + /** > + Offset 64 > + (Test) Size of IED region in bytes. > + 0 : IED Disabled (no memory occupied) > + 0x400000 : 4MB SMM memory occupied by IED (Part of TSEG) > + Note: Enabling IED may also enlarge TsegSize together. **/ > + UINT32 IedSize; > + UINT8 UserBd; ///< Offset 68 0=3DMobil= e/Mobile Halo, > 1=3DDesktop/DT Halo, 5=3DULT/ULX/Mobile Halo, 7=3DUP Server > + UINT8 SgMode; ///< Offset 69 SgMode: 0= =3DDisabled, > 1=3DSG Muxed, 2=3DSG Muxless, 3=3DPEG > + UINT16 SgSubSystemId; ///< Offset 70 Switchable G= raphics > Subsystem ID: 2212 > + UINT16 SgDelayAfterPwrEn; ///< Offset 72 Dgpu Delay a= fter Power > enable using Setup option: 0=3DMinimal, 1000=3DMaximum, 300=3D300 > microseconds > + UINT16 SgDelayAfterHoldReset; ///< Offset 74 Dgpu Delay a= fter Hold > Reset using Setup option: 0=3DMinimal, 1000=3DMaximum, 100=3D100 > microseconds > + UINT32 SkipExtGfxScan:1; ///< (Test) OFfset 7= 6:0 :1=3DSkip > External Gfx Device Scan; 0=3DScan for external graphics devices. = Set this > policy to skip External Graphics card scanning if the platform uses Inter= nal > Graphics only. > + UINT32 BdatEnable:1; ///< (Test) OFfset 7= 6:1 :This field > enables the generation of the BIOS DATA ACPI Tables: 0=3DFALSE, > 1=3DTRUE\n Please refer to the MRC documentation for more details > + UINT32 TxtImplemented:1; ///< OFfset 76:2 :This fiel= d currently is > used to tell MRC if it should run after TXT initializatoin completed: = 0=3DRun > without waiting for TXT, 1=3DRun after TXT initialization by callback > + /** > + Offset 76:3 : > + (Test) Scan External Discrete Graphics Devices for Legacy > + Only VGA OpROMs > + > + When enabled, if the primary graphics device is an external discrete = graphics > device, Si will scan the > + graphics device for legacy only VGA OpROMs. If the primary graphics = device > only implements legacy VBIOS, then the > + LegacyOnlyVgaOpRomDetected field in the SA_DATA_HOB will be set to 1. > + > + This is intended to ease the implementation of a BIOS feature to > automatically enable CSM if the Primary Gfx device > + only supports Legacy VBIOS (No UEFI GOP Present). Otherwise disablin= g CSM > won't result in no video being displayed. > + This is useful for platforms that implement PCIe slots that allow the= end user > to install an arbitrary Gfx device. > + > + This setting will only take effect if SkipExtGfxScan =3D=3D 0. It is= ignored > otherwise. > + > + - Disabled (0x0) : Don't Scan for Legacy Only VGA OpROMs (Defa= ult) > + - Enabled (0x1) : Scan External Gfx for Legacy Only VGA > + OpROM **/ > + UINT32 ScanExtGfxForLegacyOpRom:1; > + UINT32 RsvdBits0 :28; ///< OFfset 76:4 :Reserved = for future use > + UINT8 LockPTMregs; ///< (Test) Offset 8= 0 Lock PCU > Thermal Management registers: 0=3DFALSE, 1=3DTRUE > + UINT8 BdatTestType; ///< Offset 81 When BdatEna= ble is set to > TRUE, this option selects the type of data which will be populated in the= BIOS > Data ACPI Tables: 0=3DRMT, 1=3DRMT Per Bit, 2=3DMargin 2D. > + UINT8 BdatSchema; ///< Offset 82 When BdatEna= ble is set to > TRUE, this option selects the BDAT Schema version which will be used to f= ormat > BDAT Test results: 0=3DSchema 2, 1=3DSchema 6B > + UINT8 Rsvd1; ///< Offset 83 Reserved for= future use > + /** > + Offset 84 : > + Size of reserved MMIO space for PCI devices\n > + 0=3DAUTO, 512=3D512MB, 768=3D768MB, 1024=3D1024MB, 1280=3D128= 0MB, > 1536=3D1536MB, 1792=3D1792MB, > + 2048=3D2048MB, 2304=3D2304MB, 2560=3D2560MB, 2816=3D2816MB, > 3072=3D3072MB\n > + When AUTO mode selected, the MMIO size will be calculated by require= d > MMIO size from PCIe devices detected. > + **/ > + UINT16 MmioSize; > + INT16 MmioSizeAdjustment; ///< Offset 86 Increase (gi= ven positive > value) or Decrease (given negative value) the Reserved MMIO size when > Dynamic Tolud/AUTO mode enabled (in MBs): 0=3Dno adjustment > + UINT64 AcpiReservedMemoryBase; ///< Offset 88 The Base add= ress of > a Reserved memory buffer allocated in previous boot for S3 resume used. > Originally it is retrieved from AcpiVariableCompatibility variable. > + UINT64 SystemMemoryLength; ///< Offset 96 Total system= memory > length from previous boot, this is required for S3 resume. Originally it = is retrieved > from AcpiVariableCompatibility variable. > + UINT32 AcpiReservedMemorySize; ///< Offset 104 The Size of= a > Reserved memory buffer allocated in previous boot for S3 resume used. > Originally it is retrieved from AcpiVariableCompatibility variable. > + UINT32 OpRomScanTempMmioBar; ///< (Test) Offset 1= 08 > Temporary address to MMIO map OpROMs during VGA scanning. Used for > ScanExtGfxForLegacyOpRom feature. MUST BE 16MB ALIGNED! > + UINT32 OpRomScanTempMmioLimit; ///< (Test) Offset 1= 12 > Limit address for OpROM MMIO range. Used for ScanExtGfxForLegacyOpRom > feature. (OpROMScanTempMmioLimit - OpRomScanTempMmioBar) MUST BE > >=3D 16MB! > + UINT16 SgDelayAfterOffMethod; ///< Offset 128 Dgpu Delay = after off > method is called using Setup option: 0=3DMinimal, 1000=3DMaximum, 300= =3D300 > microseconds > + UINT16 SgDelayAfterLinkEnable; ///< Offset 130 Delay after= link enable > method is called using Setup option: 0=3DMinimal, 1000=3DMaximum, 100= =3D100 > microseconds > + UINT8 SgGenSpeedChangeEnable; ///< Offset 132 Enable/Disa= ble Gen > speed changes using Setup option: 0=3DDisable, 1=3DEnable > + UINT8 Rsvd3[3]; ///< Offset 133 Reserved fo= r future use > } SA_MISC_PEI_PREMEM_CONFIG; > #pragma pack(pop) >=20 > diff --git > a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/Pei= SaPol > icyLib.c > b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/Pei= SaPol > icyLib.c > index eb18d993e7..5210856346 100644 > --- > a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/Pei= SaPol > icyLib.c > +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLi > +++ b/PeiSaPolicyLib.c > @@ -1,7 +1,7 @@ > /** @file > This file provides services for PEI policy default initialization >=20 > -Copyright (c) 2017, Intel Corporation. All rights reserved.
> +Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.
> SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > **/ > @@ -19,6 +19,9 @@ extern EFI_GUID gMemoryConfigNoCrcGuid; extern > EFI_GUID gGraphicsPeiConfigGuid; extern EFI_GUID gVtdConfigGuid; >=20 > +#define DEFAULT_OPTION_ROM_TEMP_BAR 0x80000000 > +#define DEFAULT_OPTION_ROM_TEMP_MEM_LIMIT 0xC0000000 > + > // > // Function call to Load defaults for Individial IP Blocks // @@ -33,6 = +36,38 > @@ LoadSaMiscPeiPreMemDefault ( >=20 > DEBUG ((DEBUG_INFO, "MiscPeiPreMemConfig->Header.GuidHob.Name =3D > %g\n", &MiscPeiPreMemConfig->Header.GuidHob.Name)); > DEBUG ((DEBUG_INFO, "MiscPeiPreMemConfig- > >Header.GuidHob.Header.HobLength =3D 0x%x\n", MiscPeiPreMemConfig- > >Header.GuidHob.Header.HobLength)); > + > + // > + // Policy initialization commented out here is because it's the same w= ith > default 0 and no need to re-do again. > + // > + MiscPeiPreMemConfig->LockPTMregs =3D 1; > + > + // > + // Initialize the Platform Configuration // > + MiscPeiPreMemConfig->MchBar =3D (UINT32) PcdGet64 > (PcdMchBaseAddress); > + MiscPeiPreMemConfig->DmiBar =3D 0xFED18000; > + MiscPeiPreMemConfig->EpBar =3D 0xFED19000; > + MiscPeiPreMemConfig->EdramBar =3D 0xFED80000; > + MiscPeiPreMemConfig->SmbusBar =3D PcdGet16 (PcdSmbusBaseAdd= ress); > + MiscPeiPreMemConfig->TsegSize =3D PcdGet32 (PcdTsegSize); > + MiscPeiPreMemConfig->GdxcBar =3D 0xFED84000; > + > + // > + // Initialize the Switchable Graphics Default Configuration // > + MiscPeiPreMemConfig->SgDelayAfterHoldReset =3D 100; //100ms > + MiscPeiPreMemConfig->SgDelayAfterPwrEn =3D 300; //300ms > + MiscPeiPreMemConfig->SgDelayAfterOffMethod =3D 0; > + MiscPeiPreMemConfig->SgDelayAfterLinkEnable =3D 0; > + MiscPeiPreMemConfig->SgGenSpeedChangeEnable =3D 0; > + > + /// > + /// Initialize the DataPtr for S3 resume /// > + MiscPeiPreMemConfig->S3DataPtr =3D NULL; > + MiscPeiPreMemConfig->OpRomScanTempMmioBar =3D > DEFAULT_OPTION_ROM_TEMP_BAR; > + MiscPeiPreMemConfig->OpRomScanTempMmioLimit =3D > DEFAULT_OPTION_ROM_TEMP_MEM_LIMIT; > } >=20 > VOID > -- > 2.27.0.windows.1