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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Chasel Chiu Thanks, Chasel > -----Original Message----- > From: Desimone, Nathaniel L > Sent: Tuesday, June 7, 2022 7:17 AM > To: devel@edk2.groups.io > Cc: Chiu, Chasel ; Kubacki, Michael > ; Benjamin Doron > ; Soller, Jeremy > Subject: [edk2-platforms] [PATCH V2 1/4] KabylakeOpenBoardPkg: Indicate > width of CLK duty cycle in FADT >=20 > Set the location of the DUTY_CYCLE field in the P_CNT register and indica= te the > width of the clock duty cycle to OS power management >=20 > Cc: Chasel Chiu > Cc: Michael Kubacki > Cc: Benjamin Doron > Cc: Jeremy Soller > Signed-off-by: Nate DeSimone > --- > .../AspireVn7Dash572G/OpenBoardPkgPcd.dsc | 9 ++++++++- > .../GalagoPro3/OpenBoardPkgPcd.dsc | 8 +++++++- > .../KabylakeRvp3/OpenBoardPkgPcd.dsc | 11 +++++++++-- > 3 files changed, 24 insertions(+), 4 deletions(-) >=20 > diff --git > a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPc > d.dsc > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPc > d.dsc > index 21ee86403d..02080aa864 100644 > --- > a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPc > d.dsc > +++ > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkg > +++ Pcd.dsc > @@ -1,7 +1,7 @@ > ## @file > # PCD configuration build description file for the Aspire VN7-572G boar= d. > # > -# Copyright (c) 2017 - 2020, Intel Corporation. All rights reserved.
> +# Copyright (c) 2017 - 2022, Intel Corporation. All rights > +reserved.
> # > # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -346,6 +346,13 @@ > gSiPkgTokenSpaceGuid.PcdHstiIhvFeature1|0xF2 # FIXME: Boot Guard and > BIOS Guard not present, measured boot enforcement checking code not prese= nt > gSiPkgTokenSpaceGuid.PcdHstiIhvFeature2|0x07 >=20 > + # > + # Set the location of the DUTY_CYCLE field in the P_CNT register # > + and indicate the width of the clock duty cycle to OS power management > + # > + gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1 > + gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3 > + > ###################################### > # Platform Configuration > ###################################### > diff --git > a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc > b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc > index 44dacdf082..dce4db17c2 100644 > --- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc > +++ > b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc > @@ -1,7 +1,7 @@ > ## @file > # PCD configuration build description file for the GalagoPro3 board. > # > -# Copyright (c) 2019 - 2020, Intel Corporation. All rights reserved.
> +# Copyright (c) 2019 - 2022, Intel Corporation. All rights > +reserved.
> # > # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -251,6 +251,12 @@ > gSiPkgTokenSpaceGuid.PcdHstiIhvFeature1|0xF2 > gSiPkgTokenSpaceGuid.PcdHstiIhvFeature2|0x07 >=20 > + # > + # Set the location of the DUTY_CYCLE field in the P_CNT register # > + and indicate the width of the clock duty cycle to OS power management > + # > + gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1 > + gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3 >=20 > gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress|gEfiMdePkgTokenSpaceGui > d.PcdPciExpressBaseAddress >=20 > gSiPkgTokenSpaceGuid.PcdSiPciExpressRegionLength|gMinPlatformPkgTokenSp > aceGuid.PcdPciExpressRegionLength >=20 > diff --git > a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc > b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc > index 725596cbf7..ccf757e202 100644 > --- > a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc > +++ > b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.d > +++ sc > @@ -1,7 +1,7 @@ > ## @file > # PCD configuration build description file for the KabylakeRvp3 board. > # > -# Copyright (c) 2017 - 2020, Intel Corporation. All rights reserved.
> +# Copyright (c) 2017 - 2022, Intel Corporation. All rights > +reserved.
> # > # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -78,6 +78,7 @@ > # so FSP needs more temporary memory for FSP heap + stack size. > # > gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize|0x26000 > + > # > # FSP API mode does not need to enlarge the boot loader stack size > # since the stacks are separate. > @@ -290,6 +291,13 @@ > gSiPkgTokenSpaceGuid.PcdHstiIhvFeature1|0xF2 > gSiPkgTokenSpaceGuid.PcdHstiIhvFeature2|0x07 >=20 > + # > + # Set the location of the DUTY_CYCLE field in the P_CNT register # > + and indicate the width of the clock duty cycle to OS power management > + # > + gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1 > + gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3 > + > ###################################### > # Platform Configuration > ###################################### > @@ -346,7 +354,6 @@ > gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, > 0x0F, 0x07, 0x1F, 0x1F, 0x0F, 0x0F, 0x07, 0x03, 0x00, 0x00, 0x00, 0x00, 0= x00, > 0x00, 0x00} !endif >=20 > - > ###################################### > # Board Configuration > ###################################### > -- > 2.27.0.windows.1