From: "Chiu, Chasel" <chasel.chiu@intel.com>
To: "Desimone, Nathaniel L" <nathaniel.l.desimone@intel.com>,
"devel@edk2.groups.io" <devel@edk2.groups.io>
Cc: "Sinha, Ankit" <ankit.sinha@intel.com>,
"Kubacki, Michael" <michael.kubacki@microsoft.com>,
"Soller, Jeremy" <jeremy@system76.com>
Subject: Re: [edk2-platforms] [PATCH V1] KabylakeOpenBoardPkg/GalagoPro3: Add FSP Dispatch Mode PCDs
Date: Wed, 8 Jun 2022 01:28:37 +0000 [thread overview]
Message-ID: <BN9PR11MB548352526B24BF18F8A9F2D5E6A49@BN9PR11MB5483.namprd11.prod.outlook.com> (raw)
In-Reply-To: <20220606230925.3706-1-nathaniel.l.desimone@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
Thanks,
Chasel
> -----Original Message-----
> From: Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>
> Sent: Tuesday, June 7, 2022 7:09 AM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel <chasel.chiu@intel.com>; Sinha, Ankit <ankit.sinha@intel.com>;
> Kubacki, Michael <michael.kubacki@microsoft.com>; Soller, Jeremy
> <jeremy@system76.com>
> Subject: [edk2-platforms] [PATCH V1] KabylakeOpenBoardPkg/GalagoPro3: Add
> FSP Dispatch Mode PCDs
>
> Adds missing FSP dispatch mode PCDs to the Galago Pro 3.
>
> Cc: Chasel Chiu <chasel.chiu@intel.com>
> Cc: Ankit Sinha <ankit.sinha@intel.com>
> Cc: Michael Kubacki <michael.kubacki@microsoft.com>
> Cc: Jeremy Soller <jeremy@system76.com>
> Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
> ---
> .../GalagoPro3/OpenBoardPkgPcd.dsc | 46 +++++++++++++++++--
> 1 file changed, 42 insertions(+), 4 deletions(-)
>
> diff --git
> a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc
> b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc
> index 44dacdf082..28f044df5e 100644
> --- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc
> +++
> b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc
> @@ -1,7 +1,7 @@
> ## @file
> # PCD configuration build description file for the GalagoPro3 board.
> #
> -# Copyright (c) 2019 - 2020, Intel Corporation. All rights reserved.<BR>
> +# Copyright (c) 2019 - 2022, Intel Corporation. All rights
> +reserved.<BR>
> #
> # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -40,6 +40,26 @@
> #
> gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode|TRUE
>
> + #
> + # FALSE: The PEI Main included in FvPreMemory is used to dispatch all PEIMs
> + # (both inside FSP and outside FSP).
> + # Pros:
> + # * PEI Main is re-built from source and is always the latest version
> + # * Platform code can link any desired LibraryClass to PEI Main
> + # (Ex: Custom DebugLib instance, SerialPortLib, etc.)
> + # Cons:
> + # * The PEI Main being used to execute FSP PEIMs is not the PEI Main
> + # that the FSP PEIMs were tested with, adding risk of breakage.
> + # * Two copies of PEI Main will exist in the final binary,
> + # #1 in FSP-M, #2 in FvPreMemory. The copy in FSP-M is never
> + # executed, wasting space.
> + #
> + # <b>TRUE</b>: The PEI Main included in FSP is used to dispatch all PEIMs
> + # (both inside FSP and outside FSP). PEI Main will not be included in
> + # FvPreMemory. This is the default and is the recommended choice.
> + #
> + gMinPlatformPkgTokenSpaceGuid.PcdFspDispatchModeUseFspPeiMain|TRUE
> +
> #
> # FSP Base address PCD will be updated in FDF basing on flash map.
> #
> @@ -52,6 +72,7 @@
> gSiPkgTokenSpaceGuid.PcdTemporaryRamSize|0x00040000
> gSiPkgTokenSpaceGuid.PcdTsegSize|0x1000000
>
> +!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1
> #
> # FSP API mode does not share stack with the boot loader,
> # so FSP needs more temporary memory for FSP heap + stack size.
> @@ -63,6 +84,24 @@
> # since the stacks are separate.
> #
> gSiPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x20000
> +!else
> + #
> + # In FSP Dispatch mode boot loader stack size must be large
> + # enough for executing both boot loader and FSP.
> + #
> + gSiPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x40000
> +!endif
> +
> +!if (gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode == FALSE) ||
> +(gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1)
> +
> +gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress|gEfiMdePkgTokenSpaceG
> ui
> +d.PcdPciExpressBaseAddress
> +
> +gSiPkgTokenSpaceGuid.PcdSiPciExpressRegionLength|gMinPlatformPkgTokenS
> p
> +aceGuid.PcdPciExpressRegionLength
> +!else
> + #
> + # FSP Dispatch mode requires more platform memory as boot loader and
> +FSP sharing the same
> + # platform memory.
> + #
> + gSiPkgTokenSpaceGuid.PcdPeiMinMemorySize|0x5500000
> +!endif
>
> [PcdsFeatureFlag.common]
> ######################################
> @@ -222,7 +261,7 @@
> gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|1000
> gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|10000
> gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x20000
> -
> +!if (gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode == FALSE) ||
> +(gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1)
> #
> # In non-FSP build (EDK2 build) or FSP API mode below PCD are FixedAtBuild
> # (They will be DynamicEx in FSP Dispatch mode) @@ -242,6 +281,7 @@
> # 3: Place AP in the Run-Loop state.
> # @Prompt The AP wait loop state.
> gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode|2
> +!endif
>
> ######################################
> # Silicon Configuration
> @@ -251,8 +291,6 @@
> gSiPkgTokenSpaceGuid.PcdHstiIhvFeature1|0xF2
> gSiPkgTokenSpaceGuid.PcdHstiIhvFeature2|0x07
>
> -
> gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress|gEfiMdePkgTokenSpaceGui
> d.PcdPciExpressBaseAddress
> -
> gSiPkgTokenSpaceGuid.PcdSiPciExpressRegionLength|gMinPlatformPkgTokenSp
> aceGuid.PcdPciExpressRegionLength
>
> ######################################
> # Platform Configuration
> --
> 2.27.0.windows.1
prev parent reply other threads:[~2022-06-08 1:28 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-06 23:09 [edk2-platforms] [PATCH V1] KabylakeOpenBoardPkg/GalagoPro3: Add FSP Dispatch Mode PCDs Nate DeSimone
2022-06-06 23:15 ` Sinha, Ankit
2022-06-08 1:28 ` Chiu, Chasel [this message]
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